xref: /linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.c (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1 /*
2  * Copyright 2018 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  */
22 #include "nv50.h"
23 
24 #include <subdev/bios.h>
25 #include <subdev/bios/pll.h>
26 #include <subdev/clk/pll.h>
27 #include <subdev/gsp.h>
28 
29 static int
tu102_devinit_pll_set(struct nvkm_devinit * init,u32 type,u32 freq)30 tu102_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 freq)
31 {
32 	struct nvkm_subdev *subdev = &init->subdev;
33 	struct nvkm_device *device = subdev->device;
34 	struct nvbios_pll info;
35 	int head = type - PLL_VPLL0;
36 	int N, fN, M, P;
37 	int ret;
38 
39 	ret = nvbios_pll_parse(device->bios, type, &info);
40 	if (ret)
41 		return ret;
42 
43 	ret = gt215_pll_calc(subdev, &info, freq, &N, &fN, &M, &P);
44 	if (ret < 0)
45 		return ret;
46 
47 	switch (info.type) {
48 	case PLL_VPLL0:
49 	case PLL_VPLL1:
50 	case PLL_VPLL2:
51 	case PLL_VPLL3:
52 		nvkm_wr32(device, 0x00ef10 + (head * 0x40), fN << 16);
53 		nvkm_wr32(device, 0x00ef04 + (head * 0x40), (P << 16) |
54 							    (N <<  8) |
55 							    (M <<  0));
56 		/*XXX*/
57 		nvkm_wr32(device, 0x00ef0c + (head * 0x40), 0x00000900);
58 		nvkm_wr32(device, 0x00ef00 + (head * 0x40), 0x02000014);
59 		break;
60 	default:
61 		nvkm_warn(subdev, "%08x/%dKhz unimplemented\n", type, freq);
62 		ret = -EINVAL;
63 		break;
64 	}
65 
66 	return ret;
67 }
68 
69 static int
tu102_devinit_wait(struct nvkm_device * device)70 tu102_devinit_wait(struct nvkm_device *device)
71 {
72 	unsigned timeout = 50 + 2000;
73 
74 	do {
75 		if (nvkm_rd32(device, 0x118128) & 0x00000001) {
76 			if ((nvkm_rd32(device, 0x118234) & 0x000000ff) == 0xff)
77 				return 0;
78 		}
79 
80 		usleep_range(1000, 2000);
81 	} while (timeout--);
82 
83 	return -ETIMEDOUT;
84 }
85 
86 int
tu102_devinit_post(struct nvkm_devinit * init,bool post)87 tu102_devinit_post(struct nvkm_devinit *init, bool post)
88 {
89 	return tu102_devinit_wait(init->subdev.device);
90 }
91 
92 static const struct nvkm_devinit_func
93 tu102_devinit = {
94 	.init = nv50_devinit_init,
95 	.post = tu102_devinit_post,
96 	.pll_set = tu102_devinit_pll_set,
97 	.disable = gm107_devinit_disable,
98 };
99 
100 int
tu102_devinit_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_devinit ** pinit)101 tu102_devinit_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
102 		  struct nvkm_devinit **pinit)
103 {
104 	if (nvkm_gsp_rm(device->gsp))
105 		return r535_devinit_new(&tu102_devinit, device, type, inst, pinit);
106 
107 	return nv50_devinit_new_(&tu102_devinit, device, type, inst, pinit);
108 }
109