1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
3
4 #ifndef _ICE_TYPE_H_
5 #define _ICE_TYPE_H_
6
7 #define ICE_BYTES_PER_WORD 2
8 #define ICE_BYTES_PER_DWORD 4
9 #define ICE_CHNL_MAX_TC 16
10
11 #include "ice_hw_autogen.h"
12 #include "ice_devids.h"
13 #include "ice_osdep.h"
14 #include "ice_controlq.h"
15 #include "ice_lan_tx_rx.h"
16 #include "ice_flex_type.h"
17 #include "ice_protocol_type.h"
18 #include "ice_sbq_cmd.h"
19 #include "ice_vlan_mode.h"
20 #include "ice_fwlog.h"
21
ice_is_tc_ena(unsigned long bitmap,u8 tc)22 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
23 {
24 return test_bit(tc, &bitmap);
25 }
26
round_up_64bit(u64 a,u32 b)27 static inline u64 round_up_64bit(u64 a, u32 b)
28 {
29 return div64_long(((a) + (b) / 2), (b));
30 }
31
ice_round_to_num(u32 N,u32 R)32 static inline u32 ice_round_to_num(u32 N, u32 R)
33 {
34 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
35 ((((N) + (R) - 1) / (R)) * (R)));
36 }
37
38 /* Driver always calls main vsi_handle first */
39 #define ICE_MAIN_VSI_HANDLE 0
40
41 /* debug masks - set these bits in hw->debug_mask to control output */
42 #define ICE_DBG_INIT BIT_ULL(1)
43 #define ICE_DBG_FW_LOG BIT_ULL(3)
44 #define ICE_DBG_LINK BIT_ULL(4)
45 #define ICE_DBG_PHY BIT_ULL(5)
46 #define ICE_DBG_QCTX BIT_ULL(6)
47 #define ICE_DBG_NVM BIT_ULL(7)
48 #define ICE_DBG_LAN BIT_ULL(8)
49 #define ICE_DBG_FLOW BIT_ULL(9)
50 #define ICE_DBG_SW BIT_ULL(13)
51 #define ICE_DBG_SCHED BIT_ULL(14)
52 #define ICE_DBG_RDMA BIT_ULL(15)
53 #define ICE_DBG_PKG BIT_ULL(16)
54 #define ICE_DBG_RES BIT_ULL(17)
55 #define ICE_DBG_PTP BIT_ULL(19)
56 #define ICE_DBG_AQ_MSG BIT_ULL(24)
57 #define ICE_DBG_AQ_DESC BIT_ULL(25)
58 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
59 #define ICE_DBG_AQ_CMD BIT_ULL(27)
60 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
61 ICE_DBG_AQ_DESC | \
62 ICE_DBG_AQ_DESC_BUF | \
63 ICE_DBG_AQ_CMD)
64 #define ICE_DBG_PARSER BIT_ULL(28)
65
66 #define ICE_DBG_USER BIT_ULL(31)
67
68 enum ice_aq_res_ids {
69 ICE_NVM_RES_ID = 1,
70 ICE_SPD_RES_ID,
71 ICE_CHANGE_LOCK_RES_ID,
72 ICE_GLOBAL_CFG_LOCK_RES_ID
73 };
74
75 enum ice_fec_stats_types {
76 ICE_FEC_CORR_LOW,
77 ICE_FEC_CORR_HIGH,
78 ICE_FEC_UNCORR_LOW,
79 ICE_FEC_UNCORR_HIGH,
80 ICE_FEC_MAX
81 };
82
83 /* FW update timeout definitions are in milliseconds */
84 #define ICE_NVM_TIMEOUT 180000
85 #define ICE_CHANGE_LOCK_TIMEOUT 1000
86 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000
87
88 enum ice_aq_res_access_type {
89 ICE_RES_READ = 1,
90 ICE_RES_WRITE
91 };
92
93 struct ice_driver_ver {
94 u8 major_ver;
95 u8 minor_ver;
96 u8 build_ver;
97 u8 subbuild_ver;
98 u8 driver_string[32];
99 };
100
101 enum ice_fc_mode {
102 ICE_FC_NONE = 0,
103 ICE_FC_RX_PAUSE,
104 ICE_FC_TX_PAUSE,
105 ICE_FC_FULL,
106 ICE_FC_PFC,
107 ICE_FC_DFLT
108 };
109
110 enum ice_phy_cache_mode {
111 ICE_FC_MODE = 0,
112 ICE_SPEED_MODE,
113 ICE_FEC_MODE
114 };
115
116 enum ice_fec_mode {
117 ICE_FEC_NONE = 0,
118 ICE_FEC_RS,
119 ICE_FEC_BASER,
120 ICE_FEC_AUTO
121 };
122
123 struct ice_phy_cache_mode_data {
124 union {
125 enum ice_fec_mode curr_user_fec_req;
126 enum ice_fc_mode curr_user_fc_req;
127 u16 curr_user_speed_req;
128 } data;
129 };
130
131 enum ice_set_fc_aq_failures {
132 ICE_SET_FC_AQ_FAIL_NONE = 0,
133 ICE_SET_FC_AQ_FAIL_GET,
134 ICE_SET_FC_AQ_FAIL_SET,
135 ICE_SET_FC_AQ_FAIL_UPDATE
136 };
137
138 /* Various MAC types */
139 enum ice_mac_type {
140 ICE_MAC_UNKNOWN = 0,
141 ICE_MAC_E810,
142 ICE_MAC_E830,
143 ICE_MAC_GENERIC,
144 ICE_MAC_GENERIC_3K_E825,
145 };
146
147 /* Media Types */
148 enum ice_media_type {
149 ICE_MEDIA_UNKNOWN = 0,
150 ICE_MEDIA_FIBER,
151 ICE_MEDIA_BASET,
152 ICE_MEDIA_BACKPLANE,
153 ICE_MEDIA_DA,
154 };
155
156 enum ice_vsi_type {
157 ICE_VSI_PF = 0,
158 ICE_VSI_VF = 1,
159 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
160 ICE_VSI_CHNL = 4,
161 ICE_VSI_LB = 6,
162 ICE_VSI_SF = 9,
163 };
164
165 struct ice_link_status {
166 /* Refer to ice_aq_phy_type for bits definition */
167 u64 phy_type_low;
168 u64 phy_type_high;
169 u8 topo_media_conflict;
170 u16 max_frame_size;
171 u16 link_speed;
172 u16 req_speeds;
173 u8 link_cfg_err;
174 u8 lse_ena; /* Link Status Event notification */
175 u8 link_info;
176 u8 an_info;
177 u8 ext_info;
178 u8 fec_info;
179 u8 pacing;
180 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
181 * ice_aqc_get_phy_caps structure
182 */
183 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
184 };
185
186 /* Different reset sources for which a disable queue AQ call has to be made in
187 * order to clean the Tx scheduler as a part of the reset
188 */
189 enum ice_disq_rst_src {
190 ICE_NO_RESET = 0,
191 ICE_VM_RESET,
192 ICE_VF_RESET,
193 };
194
195 /* PHY info such as phy_type, etc... */
196 struct ice_phy_info {
197 struct ice_link_status link_info;
198 struct ice_link_status link_info_old;
199 u64 phy_type_low;
200 u64 phy_type_high;
201 enum ice_media_type media_type;
202 u8 get_link_info;
203 /* Please refer to struct ice_aqc_get_link_status_data to get
204 * detail of enable bit in curr_user_speed_req
205 */
206 u16 curr_user_speed_req;
207 enum ice_fec_mode curr_user_fec_req;
208 enum ice_fc_mode curr_user_fc_req;
209 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
210 };
211
212 /* protocol enumeration for filters */
213 enum ice_fltr_ptype {
214 /* NONE - used for undef/error */
215 ICE_FLTR_PTYPE_NONF_NONE = 0,
216 ICE_FLTR_PTYPE_NONF_ETH,
217 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
218 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
219 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
220 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
221 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
222 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
223 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
224 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
225 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
226 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
227 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
228 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
229 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
230 ICE_FLTR_PTYPE_NONF_IPV4_AH,
231 ICE_FLTR_PTYPE_NONF_IPV6_AH,
232 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
233 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
234 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
235 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
236 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
237 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
238 ICE_FLTR_PTYPE_NON_IP_L2,
239 ICE_FLTR_PTYPE_FRAG_IPV4,
240 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
241 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
242 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
243 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
244 ICE_FLTR_PTYPE_MAX,
245 };
246
247 enum ice_fd_hw_seg {
248 ICE_FD_HW_SEG_NON_TUN = 0,
249 ICE_FD_HW_SEG_TUN,
250 ICE_FD_HW_SEG_MAX,
251 };
252
253 /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */
254 #define ICE_MAX_FDIR_VSI_PER_FILTER (2 + ICE_CHNL_MAX_TC)
255
256 struct ice_fd_hw_prof {
257 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
258 int cnt;
259 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
260 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
261 u64 prof_id[ICE_FD_HW_SEG_MAX];
262 };
263
264 /* Common HW capabilities for SW use */
265 struct ice_hw_common_caps {
266 u32 valid_functions;
267 /* DCB capabilities */
268 u32 active_tc_bitmap;
269 u32 maxtc;
270
271 /* Tx/Rx queues */
272 u16 num_rxq; /* Number/Total Rx queues */
273 u16 rxq_first_id; /* First queue ID for Rx queues */
274 u16 num_txq; /* Number/Total Tx queues */
275 u16 txq_first_id; /* First queue ID for Tx queues */
276
277 /* MSI-X vectors */
278 u16 num_msix_vectors;
279 u16 msix_vector_first_id;
280
281 /* Max MTU for function or device */
282 u16 max_mtu;
283
284 /* Virtualization support */
285 u8 sr_iov_1_1; /* SR-IOV enabled */
286
287 /* RSS related capabilities */
288 u16 rss_table_size; /* 512 for PFs and 64 for VFs */
289 u8 rss_table_entry_width; /* RSS Entry width in bits */
290
291 u8 dcb;
292 u8 ieee_1588;
293 u8 rdma;
294 u8 roce_lag;
295 u8 sriov_lag;
296
297 bool nvm_update_pending_nvm;
298 bool nvm_update_pending_orom;
299 bool nvm_update_pending_netlist;
300 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0)
301 #define ICE_NVM_PENDING_OROM BIT(1)
302 #define ICE_NVM_PENDING_NETLIST BIT(2)
303 bool nvm_unified_update;
304 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
305 /* PCIe reset avoidance */
306 bool pcie_reset_avoidance;
307 /* Post update reset restriction */
308 bool reset_restrict_support;
309 bool tx_sched_topo_comp_mode_en;
310 };
311
312 /* IEEE 1588 TIME_SYNC specific info */
313 /* Function specific definitions */
314 #define ICE_TS_FUNC_ENA_M BIT(0)
315 #define ICE_TS_SRC_TMR_OWND_M BIT(1)
316 #define ICE_TS_TMR_ENA_M BIT(2)
317 #define ICE_TS_TMR_IDX_OWND_S 4
318 #define ICE_TS_TMR_IDX_OWND_M BIT(4)
319 #define ICE_TS_CLK_FREQ_S 16
320 #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S)
321 #define ICE_TS_CLK_SRC_S 20
322 #define ICE_TS_CLK_SRC_M BIT(20)
323 #define ICE_TS_TMR_IDX_ASSOC_S 24
324 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
325
326 /* TIME_REF clock rate specification */
327 enum ice_time_ref_freq {
328 ICE_TIME_REF_FREQ_25_000 = 0,
329 ICE_TIME_REF_FREQ_122_880 = 1,
330 ICE_TIME_REF_FREQ_125_000 = 2,
331 ICE_TIME_REF_FREQ_153_600 = 3,
332 ICE_TIME_REF_FREQ_156_250 = 4,
333 ICE_TIME_REF_FREQ_245_760 = 5,
334
335 NUM_ICE_TIME_REF_FREQ,
336
337 ICE_TIME_REF_FREQ_INVALID = -1,
338 };
339
340 /* Clock source specification */
341 enum ice_clk_src {
342 ICE_CLK_SRC_TCXO = 0, /* Temperature compensated oscillator */
343 ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */
344
345 NUM_ICE_CLK_SRC
346 };
347
348 struct ice_ts_func_info {
349 /* Function specific info */
350 enum ice_time_ref_freq time_ref;
351 u8 clk_freq;
352 u8 clk_src;
353 u8 tmr_index_assoc;
354 u8 ena;
355 u8 tmr_index_owned;
356 u8 src_tmr_owned;
357 u8 tmr_ena;
358 };
359
360 /* Device specific definitions */
361 #define ICE_TS_TMR0_OWNR_M 0x7
362 #define ICE_TS_TMR0_OWND_M BIT(3)
363 #define ICE_TS_TMR1_OWNR_S 4
364 #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
365 #define ICE_TS_TMR1_OWND_M BIT(7)
366 #define ICE_TS_DEV_ENA_M BIT(24)
367 #define ICE_TS_TMR0_ENA_M BIT(25)
368 #define ICE_TS_TMR1_ENA_M BIT(26)
369 #define ICE_TS_LL_TX_TS_READ_M BIT(28)
370 #define ICE_TS_LL_TX_TS_INT_READ_M BIT(29)
371
372 struct ice_ts_dev_info {
373 /* Device specific info */
374 u32 ena_ports;
375 u32 tmr_own_map;
376 u32 tmr0_owner;
377 u32 tmr1_owner;
378 u8 tmr0_owned;
379 u8 tmr1_owned;
380 u8 ena;
381 u8 tmr0_ena;
382 u8 tmr1_ena;
383 u8 ts_ll_read;
384 u8 ts_ll_int_read;
385 };
386
387 #define ICE_NAC_TOPO_PRIMARY_M BIT(0)
388 #define ICE_NAC_TOPO_DUAL_M BIT(1)
389 #define ICE_NAC_TOPO_ID_M GENMASK(0xF, 0)
390
391 struct ice_nac_topology {
392 u32 mode;
393 u8 id;
394 };
395
396 /* Function specific capabilities */
397 struct ice_hw_func_caps {
398 struct ice_hw_common_caps common_cap;
399 u32 num_allocd_vfs; /* Number of allocated VFs */
400 u32 vf_base_id; /* Logical ID of the first VF */
401 u32 guar_num_vsi;
402 u32 fd_fltr_guar; /* Number of filters guaranteed */
403 u32 fd_fltr_best_effort; /* Number of best effort filters */
404 struct ice_ts_func_info ts_func_info;
405 };
406
407 #define ICE_SENSOR_SUPPORT_E810_INT_TEMP_BIT 0
408
409 /* Device wide capabilities */
410 struct ice_hw_dev_caps {
411 struct ice_hw_common_caps common_cap;
412 u32 num_vfs_exposed; /* Total number of VFs exposed */
413 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
414 u32 num_flow_director_fltr; /* Number of FD filters available */
415 struct ice_ts_dev_info ts_dev_info;
416 u32 num_funcs;
417 struct ice_nac_topology nac_topo;
418 /* bitmap of supported sensors
419 * bit 0 - internal temperature sensor
420 * bit 31:1 - Reserved
421 */
422 u32 supported_sensors;
423 };
424
425 /* MAC info */
426 struct ice_mac_info {
427 u8 lan_addr[ETH_ALEN];
428 u8 perm_addr[ETH_ALEN];
429 };
430
431 /* Reset types used to determine which kind of reset was requested. These
432 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
433 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
434 * because its reset source is different than the other types listed.
435 */
436 enum ice_reset_req {
437 ICE_RESET_POR = 0,
438 ICE_RESET_INVAL = 0,
439 ICE_RESET_CORER = 1,
440 ICE_RESET_GLOBR = 2,
441 ICE_RESET_EMPR = 3,
442 ICE_RESET_PFR = 4,
443 };
444
445 /* Bus parameters */
446 struct ice_bus_info {
447 u16 device;
448 u8 func;
449 };
450
451 /* Flow control (FC) parameters */
452 struct ice_fc_info {
453 enum ice_fc_mode current_mode; /* FC mode in effect */
454 enum ice_fc_mode req_mode; /* FC mode requested by caller */
455 };
456
457 /* Option ROM version information */
458 struct ice_orom_info {
459 u8 major; /* Major version of OROM */
460 u8 patch; /* Patch version of OROM */
461 u16 build; /* Build version of OROM */
462 };
463
464 /* NVM version information */
465 struct ice_nvm_info {
466 u32 eetrack;
467 u8 major;
468 u8 minor;
469 };
470
471 /* netlist version information */
472 struct ice_netlist_info {
473 u32 major; /* major high/low */
474 u32 minor; /* minor high/low */
475 u32 type; /* type high/low */
476 u32 rev; /* revision high/low */
477 u32 hash; /* SHA-1 hash word */
478 u16 cust_ver; /* customer version */
479 };
480
481 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
482 * of the flash image.
483 */
484 enum ice_flash_bank {
485 ICE_INVALID_FLASH_BANK,
486 ICE_1ST_FLASH_BANK,
487 ICE_2ND_FLASH_BANK,
488 };
489
490 /* Enumeration of which flash bank is desired to read from, either the active
491 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
492 * code which just wants to read the active or inactive flash bank.
493 */
494 enum ice_bank_select {
495 ICE_ACTIVE_FLASH_BANK,
496 ICE_INACTIVE_FLASH_BANK,
497 };
498
499 /* information for accessing NVM, OROM, and Netlist flash banks */
500 struct ice_bank_info {
501 u32 nvm_ptr; /* Pointer to 1st NVM bank */
502 u32 nvm_size; /* Size of NVM bank */
503 u32 orom_ptr; /* Pointer to 1st OROM bank */
504 u32 orom_size; /* Size of OROM bank */
505 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
506 u32 netlist_size; /* Size of Netlist bank */
507 u32 active_css_hdr_len; /* Active CSS header length */
508 u32 inactive_css_hdr_len; /* Inactive CSS header length */
509 enum ice_flash_bank nvm_bank; /* Active NVM bank */
510 enum ice_flash_bank orom_bank; /* Active OROM bank */
511 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
512 };
513
514 /* Flash Chip Information */
515 struct ice_flash_info {
516 struct ice_orom_info orom; /* Option ROM version info */
517 struct ice_nvm_info nvm; /* NVM version information */
518 struct ice_netlist_info netlist;/* Netlist version info */
519 struct ice_bank_info banks; /* Flash Bank information */
520 u16 sr_words; /* Shadow RAM size in words */
521 u32 flash_size; /* Size of available flash in bytes */
522 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
523 };
524
525 struct ice_link_default_override_tlv {
526 u8 options;
527 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
528 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
529 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
530 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
531 #define ICE_LINK_OVERRIDE_EN BIT(3)
532 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
533 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
534 u8 phy_config;
535 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
536 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
537 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
538 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
539 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
540 u8 fec_options;
541 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
542 u8 rsvd1;
543 u64 phy_type_low;
544 u64 phy_type_high;
545 };
546
547 #define ICE_NVM_VER_LEN 32
548
549 /* Max number of port to queue branches w.r.t topology */
550 #define ICE_MAX_TRAFFIC_CLASS 8
551 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
552
553 #define ice_for_each_traffic_class(_i) \
554 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
555
556 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
557 * to driver defined policy for default aggregator
558 */
559 #define ICE_INVAL_TEID 0xFFFFFFFF
560 #define ICE_DFLT_AGG_ID 0
561
562 struct ice_sched_node {
563 struct ice_sched_node *parent;
564 struct ice_sched_node *sibling; /* next sibling in the same layer */
565 struct ice_sched_node **children;
566 struct ice_aqc_txsched_elem_data info;
567 char *name;
568 struct devlink_rate *rate_node;
569 u64 tx_max;
570 u64 tx_share;
571 u32 agg_id; /* aggregator group ID */
572 u32 id;
573 u32 tx_priority;
574 u32 tx_weight;
575 u16 vsi_handle;
576 u8 in_use; /* suspended or in use */
577 u8 tx_sched_layer; /* Logical Layer (1-9) */
578 u8 num_children;
579 u8 tc_num;
580 u8 owner;
581 #define ICE_SCHED_NODE_OWNER_LAN 0
582 #define ICE_SCHED_NODE_OWNER_RDMA 2
583 };
584
585 /* Access Macros for Tx Sched Elements data */
586 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
587
588 /* The aggregator type determines if identifier is for a VSI group,
589 * aggregator group, aggregator of queues, or queue group.
590 */
591 enum ice_agg_type {
592 ICE_AGG_TYPE_UNKNOWN = 0,
593 ICE_AGG_TYPE_VSI,
594 ICE_AGG_TYPE_AGG, /* aggregator */
595 ICE_AGG_TYPE_Q,
596 ICE_AGG_TYPE_QG
597 };
598
599 /* Rate limit types */
600 enum ice_rl_type {
601 ICE_UNKNOWN_BW = 0,
602 ICE_MIN_BW, /* for CIR profile */
603 ICE_MAX_BW, /* for EIR profile */
604 ICE_SHARED_BW /* for shared profile */
605 };
606
607 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
608 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
609 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
610 #define ICE_SCHED_DFLT_RL_PROF_ID 0
611 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
612 #define ICE_SCHED_DFLT_BW_WT 4
613 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
614 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
615
616 #define ICE_MAX_PORT_PER_PCI_DEV 8
617
618 /* Data structure for saving BW information */
619 enum ice_bw_type {
620 ICE_BW_TYPE_PRIO,
621 ICE_BW_TYPE_CIR,
622 ICE_BW_TYPE_CIR_WT,
623 ICE_BW_TYPE_EIR,
624 ICE_BW_TYPE_EIR_WT,
625 ICE_BW_TYPE_SHARED,
626 ICE_BW_TYPE_CNT /* This must be last */
627 };
628
629 struct ice_bw {
630 u32 bw;
631 u16 bw_alloc;
632 };
633
634 struct ice_bw_type_info {
635 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
636 u8 generic;
637 struct ice_bw cir_bw;
638 struct ice_bw eir_bw;
639 u32 shared_bw;
640 };
641
642 /* VSI queue context structure for given TC */
643 struct ice_q_ctx {
644 u16 q_handle;
645 u32 q_teid;
646 /* bw_t_info saves queue BW information */
647 struct ice_bw_type_info bw_t_info;
648 };
649
650 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
651 struct ice_sched_vsi_info {
652 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
653 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
654 struct list_head list_entry;
655 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
656 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS];
657 /* bw_t_info saves VSI BW information */
658 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
659 };
660
661 /* driver defines the policy */
662 struct ice_sched_tx_policy {
663 u16 max_num_vsis;
664 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
665 u8 rdma_ena;
666 };
667
668 /* CEE or IEEE 802.1Qaz ETS Configuration data */
669 struct ice_dcb_ets_cfg {
670 u8 willing;
671 u8 cbs;
672 u8 maxtcs;
673 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
674 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
675 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
676 };
677
678 /* CEE or IEEE 802.1Qaz PFC Configuration data */
679 struct ice_dcb_pfc_cfg {
680 u8 willing;
681 u8 mbc;
682 u8 pfccap;
683 u8 pfcena;
684 };
685
686 /* CEE or IEEE 802.1Qaz Application Priority data */
687 struct ice_dcb_app_priority_table {
688 u16 prot_id;
689 u8 priority;
690 u8 selector;
691 };
692
693 #define ICE_MAX_USER_PRIORITY 8
694 #define ICE_DCBX_MAX_APPS 64
695 #define ICE_DSCP_NUM_VAL 64
696 #define ICE_LLDPDU_SIZE 1500
697 #define ICE_TLV_STATUS_OPER 0x1
698 #define ICE_TLV_STATUS_SYNC 0x2
699 #define ICE_TLV_STATUS_ERR 0x4
700 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
701 #define ICE_APP_SEL_ETHTYPE 0x1
702 #define ICE_APP_SEL_TCPIP 0x2
703 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
704 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
705 #define ICE_CEE_APP_SEL_TCPIP 0x1
706
707 struct ice_dcbx_cfg {
708 u32 numapps;
709 u32 tlv_status; /* CEE mode TLV status */
710 struct ice_dcb_ets_cfg etscfg;
711 struct ice_dcb_ets_cfg etsrec;
712 struct ice_dcb_pfc_cfg pfc;
713 #define ICE_QOS_MODE_VLAN 0x0
714 #define ICE_QOS_MODE_DSCP 0x1
715 u8 pfc_mode;
716 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
717 /* when DSCP mapping defined by user set its bit to 1 */
718 DECLARE_BITMAP(dscp_mapped, ICE_DSCP_NUM_VAL);
719 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
720 u8 dscp_map[ICE_DSCP_NUM_VAL];
721 u8 dcbx_mode;
722 #define ICE_DCBX_MODE_CEE 0x1
723 #define ICE_DCBX_MODE_IEEE 0x2
724 u8 app_mode;
725 #define ICE_DCBX_APPS_NON_WILLING 0x1
726 };
727
728 struct ice_qos_cfg {
729 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
730 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
731 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
732 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
733 u8 is_sw_lldp : 1;
734 };
735
736 struct ice_port_info {
737 struct ice_sched_node *root; /* Root Node per Port */
738 struct ice_hw *hw; /* back pointer to HW instance */
739 u32 last_node_teid; /* scheduler last node info */
740 u16 sw_id; /* Initial switch ID belongs to port */
741 u16 pf_vf_num;
742 u8 port_state;
743 u8 local_fwd_mode;
744 #define ICE_SCHED_PORT_STATE_INIT 0x0
745 #define ICE_SCHED_PORT_STATE_READY 0x1
746 u8 lport;
747 #define ICE_LPORT_MASK 0xff
748 struct ice_fc_info fc;
749 struct ice_mac_info mac;
750 struct ice_phy_info phy;
751 struct mutex sched_lock; /* protect access to TXSched tree */
752 struct ice_sched_node *
753 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
754 /* List contain profile ID(s) and other params per layer */
755 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
756 struct ice_qos_cfg qos_cfg;
757 struct xarray sched_node_ids;
758 u8 is_vf:1;
759 u8 is_custom_tx_enabled:1;
760 };
761
762 struct ice_switch_info {
763 struct list_head vsi_list_map_head;
764 struct ice_sw_recipe *recp_list;
765 u16 prof_res_bm_init;
766 u16 max_used_prof_index;
767 u16 rule_cnt;
768 u8 recp_cnt;
769
770 DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
771 };
772
773 /* Enum defining the different states of the mailbox snapshot in the
774 * PF-VF mailbox overflow detection algorithm. The snapshot can be in
775 * states:
776 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot
777 * within the mailbox buffer.
778 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot
779 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the
780 * mailbox and mark any VFs sending more messages than the threshold limit set.
781 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF.
782 */
783 enum ice_mbx_snapshot_state {
784 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0,
785 ICE_MAL_VF_DETECT_STATE_TRAVERSE,
786 ICE_MAL_VF_DETECT_STATE_DETECT,
787 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF,
788 };
789
790 /* Structure to hold information of the static snapshot and the mailbox
791 * buffer data used to generate and track the snapshot.
792 * 1. state: the state of the mailbox snapshot in the malicious VF
793 * detection state handler ice_mbx_vf_state_handler()
794 * 2. head: head of the mailbox snapshot in a circular mailbox buffer
795 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer
796 * 4. num_iterations: number of messages traversed in circular mailbox buffer
797 * 5. num_msg_proc: number of messages processed in mailbox
798 * 6. num_pending_arq: number of pending asynchronous messages
799 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently
800 * serviced work item or interrupt.
801 */
802 struct ice_mbx_snap_buffer_data {
803 enum ice_mbx_snapshot_state state;
804 u32 head;
805 u32 tail;
806 u32 num_iterations;
807 u16 num_msg_proc;
808 u16 num_pending_arq;
809 u16 max_num_msgs_mbx;
810 };
811
812 /* Structure used to track a single VF's messages on the mailbox:
813 * 1. list_entry: linked list entry node
814 * 2. msg_count: the number of asynchronous messages sent by this VF
815 * 3. malicious: whether this VF has been detected as malicious before
816 */
817 struct ice_mbx_vf_info {
818 struct list_head list_entry;
819 u32 msg_count;
820 u8 malicious : 1;
821 };
822
823 /* Structure to hold data relevant to the captured static snapshot
824 * of the PF-VF mailbox.
825 */
826 struct ice_mbx_snapshot {
827 struct ice_mbx_snap_buffer_data mbx_buf;
828 struct list_head mbx_vf;
829 };
830
831 /* Structure to hold data to be used for capturing or updating a
832 * static snapshot.
833 * 1. num_msg_proc: number of messages processed in mailbox
834 * 2. num_pending_arq: number of pending asynchronous messages
835 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently
836 * serviced work item or interrupt.
837 * 4. async_watermark_val: An upper threshold set by caller to determine
838 * if the pending arq count is large enough to assume that there is
839 * the possibility of a mailicious VF.
840 */
841 struct ice_mbx_data {
842 u16 num_msg_proc;
843 u16 num_pending_arq;
844 u16 max_num_msgs_mbx;
845 u16 async_watermark_val;
846 };
847
848 #define ICE_PORTS_PER_QUAD 4
849 #define ICE_GET_QUAD_NUM(port) ((port) / ICE_PORTS_PER_QUAD)
850
851 struct ice_eth56g_params {
852 u8 num_phys;
853 u8 phy_addr[2];
854 bool onestep_ena;
855 bool sfd_ena;
856 u32 peer_delay;
857 };
858
859 union ice_phy_params {
860 struct ice_eth56g_params eth56g;
861 };
862
863 /* PHY model */
864 enum ice_phy_model {
865 ICE_PHY_UNSUP = -1,
866 ICE_PHY_E810 = 1,
867 ICE_PHY_E82X,
868 ICE_PHY_ETH56G,
869 };
870
871 /* Global Link Topology */
872 enum ice_global_link_topo {
873 ICE_LINK_TOPO_UP_TO_2_LINKS,
874 ICE_LINK_TOPO_UP_TO_4_LINKS,
875 ICE_LINK_TOPO_UP_TO_8_LINKS,
876 ICE_LINK_TOPO_RESERVED,
877 };
878
879 struct ice_ptp_hw {
880 enum ice_phy_model phy_model;
881 union ice_phy_params phy;
882 u8 num_lports;
883 u8 ports_per_phy;
884 bool is_2x50g_muxed_topo;
885 };
886
887 /* Port hardware description */
888 struct ice_hw {
889 u8 __iomem *hw_addr;
890 void *back;
891 struct ice_aqc_layer_props *layer_info;
892 struct ice_port_info *port_info;
893 /* PSM clock frequency for calculating RL profile params */
894 u32 psm_clk_freq;
895 u64 debug_mask; /* bitmap for debug mask */
896 enum ice_mac_type mac_type;
897
898 u16 fd_ctr_base; /* FD counter base index */
899
900 /* pci info */
901 u16 device_id;
902 u16 vendor_id;
903 u16 subsystem_device_id;
904 u16 subsystem_vendor_id;
905 u8 revision_id;
906
907 u8 pf_id; /* device profile info */
908
909 u16 max_burst_size; /* driver sets this value */
910
911 u8 recp_reuse:1; /* indicates whether FW supports recipe reuse */
912
913 /* Tx Scheduler values */
914 u8 num_tx_sched_layers;
915 u8 num_tx_sched_phys_layers;
916 u8 flattened_layers;
917 u8 max_cgds;
918 u8 sw_entry_point_layer;
919 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
920 struct list_head agg_list; /* lists all aggregator */
921
922 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
923 u8 evb_veb; /* true for VEB, false for VEPA */
924 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
925 struct ice_bus_info bus;
926 struct ice_flash_info flash;
927 struct ice_hw_dev_caps dev_caps; /* device capabilities */
928 struct ice_hw_func_caps func_caps; /* function capabilities */
929
930 struct ice_switch_info *switch_info; /* switch filter lists */
931
932 /* Control Queue info */
933 struct ice_ctl_q_info adminq;
934 struct ice_ctl_q_info sbq;
935 struct ice_ctl_q_info mailboxq;
936
937 u8 api_branch; /* API branch version */
938 u8 api_maj_ver; /* API major version */
939 u8 api_min_ver; /* API minor version */
940 u8 api_patch; /* API patch version */
941 u8 fw_branch; /* firmware branch version */
942 u8 fw_maj_ver; /* firmware major version */
943 u8 fw_min_ver; /* firmware minor version */
944 u8 fw_patch; /* firmware patch version */
945 u32 fw_build; /* firmware build number */
946
947 struct ice_fwlog_cfg fwlog_cfg;
948 bool fwlog_supported; /* does hardware support FW logging? */
949 struct ice_fwlog_ring fwlog_ring;
950
951 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
952 * register. Used for determining the ITR/INTRL granularity during
953 * initialization.
954 */
955 #define ICE_MAX_AGG_BW_200G 0x0
956 #define ICE_MAX_AGG_BW_100G 0X1
957 #define ICE_MAX_AGG_BW_50G 0x2
958 #define ICE_MAX_AGG_BW_25G 0x3
959 /* ITR granularity for different speeds */
960 #define ICE_ITR_GRAN_ABOVE_25 2
961 #define ICE_ITR_GRAN_MAX_25 4
962 /* ITR granularity in 1 us */
963 u8 itr_gran;
964 /* INTRL granularity for different speeds */
965 #define ICE_INTRL_GRAN_ABOVE_25 4
966 #define ICE_INTRL_GRAN_MAX_25 8
967 /* INTRL granularity in 1 us */
968 u8 intrl_gran;
969
970 struct ice_ptp_hw ptp;
971
972 /* Active package version (currently active) */
973 struct ice_pkg_ver active_pkg_ver;
974 u32 pkg_seg_id;
975 u32 pkg_sign_type;
976 u32 active_track_id;
977 u8 pkg_has_signing_seg:1;
978 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
979 u8 active_pkg_in_nvm;
980
981 /* Driver's package ver - (from the Ice Metadata section) */
982 struct ice_pkg_ver pkg_ver;
983 u8 pkg_name[ICE_PKG_NAME_SIZE];
984
985 /* Driver's Ice segment format version and ID (from the Ice seg) */
986 struct ice_pkg_ver ice_seg_fmt_ver;
987 u8 ice_seg_id[ICE_SEG_ID_SIZE];
988
989 /* Pointer to the ice segment */
990 struct ice_seg *seg;
991
992 /* Pointer to allocated copy of pkg memory */
993 u8 *pkg_copy;
994 u32 pkg_size;
995
996 /* tunneling info */
997 struct mutex tnl_lock;
998 struct ice_tunnel_table tnl;
999
1000 struct udp_tunnel_nic_shared udp_tunnel_shared;
1001 struct udp_tunnel_nic_info udp_tunnel_nic;
1002
1003 /* dvm boost update information */
1004 struct ice_dvm_table dvm_upd;
1005
1006 /* HW block tables */
1007 struct ice_blk_info blk[ICE_BLK_COUNT];
1008 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
1009 struct list_head fl_profs[ICE_BLK_COUNT];
1010
1011 /* Flow Director filter info */
1012 int fdir_active_fltr;
1013
1014 struct mutex fdir_fltr_lock; /* protect Flow Director */
1015 struct list_head fdir_list_head;
1016
1017 /* Book-keeping of side-band filter count per flow-type.
1018 * This is used to detect and handle input set changes for
1019 * respective flow-type.
1020 */
1021 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
1022
1023 struct ice_fd_hw_prof **fdir_prof;
1024 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
1025 struct mutex rss_locks; /* protect RSS configuration */
1026 struct list_head rss_list_head;
1027 struct ice_mbx_snapshot mbx_snapshot;
1028 DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX);
1029 u8 dvm_ena;
1030 u16 io_expander_handle;
1031 u8 cgu_part_number;
1032 };
1033
1034 /* Statistics collected by each port, VSI, VEB, and S-channel */
1035 struct ice_eth_stats {
1036 u64 rx_bytes; /* gorc */
1037 u64 rx_unicast; /* uprc */
1038 u64 rx_multicast; /* mprc */
1039 u64 rx_broadcast; /* bprc */
1040 u64 rx_discards; /* rdpc */
1041 u64 rx_unknown_protocol; /* rupp */
1042 u64 tx_bytes; /* gotc */
1043 u64 tx_unicast; /* uptc */
1044 u64 tx_multicast; /* mptc */
1045 u64 tx_broadcast; /* bptc */
1046 u64 tx_discards; /* tdpc */
1047 u64 tx_errors; /* tepc */
1048 };
1049
1050 #define ICE_MAX_UP 8
1051
1052 /* Statistics collected by the MAC */
1053 struct ice_hw_port_stats {
1054 /* eth stats collected by the port */
1055 struct ice_eth_stats eth;
1056 /* additional port specific stats */
1057 u64 tx_dropped_link_down; /* tdold */
1058 u64 crc_errors; /* crcerrs */
1059 u64 illegal_bytes; /* illerrc */
1060 u64 error_bytes; /* errbc */
1061 u64 mac_local_faults; /* mlfc */
1062 u64 mac_remote_faults; /* mrfc */
1063 u64 link_xon_rx; /* lxonrxc */
1064 u64 link_xoff_rx; /* lxoffrxc */
1065 u64 link_xon_tx; /* lxontxc */
1066 u64 link_xoff_tx; /* lxofftxc */
1067 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1068 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1069 u64 priority_xon_tx[8]; /* pxontxc[8] */
1070 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1071 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1072 u64 rx_size_64; /* prc64 */
1073 u64 rx_size_127; /* prc127 */
1074 u64 rx_size_255; /* prc255 */
1075 u64 rx_size_511; /* prc511 */
1076 u64 rx_size_1023; /* prc1023 */
1077 u64 rx_size_1522; /* prc1522 */
1078 u64 rx_size_big; /* prc9522 */
1079 u64 rx_undersize; /* ruc */
1080 u64 rx_fragments; /* rfc */
1081 u64 rx_oversize; /* roc */
1082 u64 rx_jabber; /* rjc */
1083 u64 tx_size_64; /* ptc64 */
1084 u64 tx_size_127; /* ptc127 */
1085 u64 tx_size_255; /* ptc255 */
1086 u64 tx_size_511; /* ptc511 */
1087 u64 tx_size_1023; /* ptc1023 */
1088 u64 tx_size_1522; /* ptc1522 */
1089 u64 tx_size_big; /* ptc9522 */
1090 /* flow director stats */
1091 u32 fd_sb_status;
1092 u64 fd_sb_match;
1093 };
1094
1095 enum ice_sw_fwd_act_type {
1096 ICE_FWD_TO_VSI = 0,
1097 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1098 ICE_FWD_TO_Q,
1099 ICE_FWD_TO_QGRP,
1100 ICE_DROP_PACKET,
1101 ICE_MIRROR_PACKET,
1102 ICE_NOP,
1103 ICE_INVAL_ACT
1104 };
1105
1106 struct ice_aq_get_set_rss_lut_params {
1107 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1108 enum ice_lut_size lut_size; /* size of the LUT buffer */
1109 enum ice_lut_type lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1110 u16 vsi_handle; /* software VSI handle */
1111 u8 global_lut_id; /* only valid when lut_type is global */
1112 };
1113
1114 /* Checksum and Shadow RAM pointers */
1115 #define ICE_SR_NVM_CTRL_WORD 0x00
1116 #define ICE_SR_BOOT_CFG_PTR 0x132
1117 #define ICE_SR_NVM_WOL_CFG 0x19
1118 #define ICE_NVM_OROM_VER_OFF 0x02
1119 #define ICE_SR_PBA_BLOCK_PTR 0x16
1120 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1121 #define ICE_SR_NVM_EETRACK_LO 0x2D
1122 #define ICE_SR_NVM_EETRACK_HI 0x2E
1123 #define ICE_NVM_VER_LO_SHIFT 0
1124 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1125 #define ICE_NVM_VER_HI_SHIFT 12
1126 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1127 #define ICE_OROM_VER_PATCH_SHIFT 0
1128 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1129 #define ICE_OROM_VER_BUILD_SHIFT 8
1130 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1131 #define ICE_OROM_VER_SHIFT 24
1132 #define ICE_OROM_VER_MASK (0xffU << ICE_OROM_VER_SHIFT)
1133 #define ICE_SR_PFA_PTR 0x40
1134 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1135 #define ICE_SR_NVM_BANK_SIZE 0x43
1136 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1137 #define ICE_SR_OROM_BANK_SIZE 0x45
1138 #define ICE_SR_NETLIST_BANK_PTR 0x46
1139 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1140 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1141
1142 /* CSS Header words */
1143 #define ICE_NVM_CSS_HDR_LEN_L 0x02
1144 #define ICE_NVM_CSS_HDR_LEN_H 0x03
1145 #define ICE_NVM_CSS_SREV_L 0x14
1146 #define ICE_NVM_CSS_SREV_H 0x15
1147
1148 /* Length of Authentication header section in words */
1149 #define ICE_NVM_AUTH_HEADER_LEN 0x08
1150
1151 /* The Link Topology Netlist section is stored as a series of words. It is
1152 * stored in the NVM as a TLV, with the first two words containing the type
1153 * and length.
1154 */
1155 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1156 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1157 #define ICE_NETLIST_LEN_OFFSET 0x0001
1158
1159 /* The Link Topology section follows the TLV header. When reading the netlist
1160 * using ice_read_netlist_module, we need to account for the 2-word TLV
1161 * header.
1162 */
1163 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1164
1165 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1166 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1167
1168 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0)
1169
1170 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1171 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1172 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1173
1174 /* netlist ID block field offsets (word offsets) */
1175 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1176 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1177 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1178 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1179 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1180 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1181 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1182 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1183 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1184 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1185
1186 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */
1187 #define ICE_SR_CTRL_WORD_1_S 0x06
1188 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1189 #define ICE_SR_CTRL_WORD_VALID 0x1
1190 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1191 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1192 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1193
1194 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1195
1196 /* Link override related */
1197 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1198 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1199 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1200 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1201 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1202 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1203 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1204 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1205
1206 #define ICE_SR_WORDS_IN_1KB 512
1207
1208 /* AQ API version for LLDP_FILTER_CONTROL */
1209 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1210 #define ICE_FW_API_LLDP_FLTR_MIN 7
1211 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1212
1213 /* AQ API version for report default configuration */
1214 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1215 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1216 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1217
1218 #endif /* _ICE_TYPE_H_ */
1219