1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Contains CPU feature definitions 4 * 5 * Copyright (C) 2015 ARM Ltd. 6 * 7 * A note for the weary kernel hacker: the code here is confusing and hard to 8 * follow! That's partly because it's solving a nasty problem, but also because 9 * there's a little bit of over-abstraction that tends to obscure what's going 10 * on behind a maze of helper functions and macros. 11 * 12 * The basic problem is that hardware folks have started gluing together CPUs 13 * with distinct architectural features; in some cases even creating SoCs where 14 * user-visible instructions are available only on a subset of the available 15 * cores. We try to address this by snapshotting the feature registers of the 16 * boot CPU and comparing these with the feature registers of each secondary 17 * CPU when bringing them up. If there is a mismatch, then we update the 18 * snapshot state to indicate the lowest-common denominator of the feature, 19 * known as the "safe" value. This snapshot state can be queried to view the 20 * "sanitised" value of a feature register. 21 * 22 * The sanitised register values are used to decide which capabilities we 23 * have in the system. These may be in the form of traditional "hwcaps" 24 * advertised to userspace or internal "cpucaps" which are used to configure 25 * things like alternative patching and static keys. While a feature mismatch 26 * may result in a TAINT_CPU_OUT_OF_SPEC kernel taint, a capability mismatch 27 * may prevent a CPU from being onlined at all. 28 * 29 * Some implementation details worth remembering: 30 * 31 * - Mismatched features are *always* sanitised to a "safe" value, which 32 * usually indicates that the feature is not supported. 33 * 34 * - A mismatched feature marked with FTR_STRICT will cause a "SANITY CHECK" 35 * warning when onlining an offending CPU and the kernel will be tainted 36 * with TAINT_CPU_OUT_OF_SPEC. 37 * 38 * - Features marked as FTR_VISIBLE have their sanitised value visible to 39 * userspace. FTR_VISIBLE features in registers that are only visible 40 * to EL0 by trapping *must* have a corresponding HWCAP so that late 41 * onlining of CPUs cannot lead to features disappearing at runtime. 42 * 43 * - A "feature" is typically a 4-bit register field. A "capability" is the 44 * high-level description derived from the sanitised field value. 45 * 46 * - Read the Arm ARM (DDI 0487F.a) section D13.1.3 ("Principles of the ID 47 * scheme for fields in ID registers") to understand when feature fields 48 * may be signed or unsigned (FTR_SIGNED and FTR_UNSIGNED accordingly). 49 * 50 * - KVM exposes its own view of the feature registers to guest operating 51 * systems regardless of FTR_VISIBLE. This is typically driven from the 52 * sanitised register values to allow virtual CPUs to be migrated between 53 * arbitrary physical CPUs, but some features not present on the host are 54 * also advertised and emulated. Look at sys_reg_descs[] for the gory 55 * details. 56 * 57 * - If the arm64_ftr_bits[] for a register has a missing field, then this 58 * field is treated as STRICT RES0, including for read_sanitised_ftr_reg(). 59 * This is stronger than FTR_HIDDEN and can be used to hide features from 60 * KVM guests. 61 */ 62 63 #define pr_fmt(fmt) "CPU features: " fmt 64 65 #include <linux/bsearch.h> 66 #include <linux/cpumask.h> 67 #include <linux/crash_dump.h> 68 #include <linux/kstrtox.h> 69 #include <linux/sort.h> 70 #include <linux/stop_machine.h> 71 #include <linux/sysfs.h> 72 #include <linux/types.h> 73 #include <linux/minmax.h> 74 #include <linux/mm.h> 75 #include <linux/cpu.h> 76 #include <linux/kasan.h> 77 #include <linux/percpu.h> 78 #include <linux/sched/isolation.h> 79 80 #include <asm/arm_pmuv3.h> 81 #include <asm/cpu.h> 82 #include <asm/cpufeature.h> 83 #include <asm/cpu_ops.h> 84 #include <asm/fpsimd.h> 85 #include <asm/hwcap.h> 86 #include <asm/insn.h> 87 #include <asm/kvm_host.h> 88 #include <asm/mmu.h> 89 #include <asm/mmu_context.h> 90 #include <asm/mpam.h> 91 #include <asm/mte.h> 92 #include <asm/hypervisor.h> 93 #include <asm/processor.h> 94 #include <asm/smp.h> 95 #include <asm/sysreg.h> 96 #include <asm/traps.h> 97 #include <asm/vectors.h> 98 #include <asm/virt.h> 99 100 #include <asm/spectre.h> 101 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ 102 static DECLARE_BITMAP(elf_hwcap, MAX_CPU_FEATURES) __read_mostly; 103 104 #ifdef CONFIG_COMPAT 105 #define COMPAT_ELF_HWCAP_DEFAULT \ 106 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\ 107 COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\ 108 COMPAT_HWCAP_TLS|COMPAT_HWCAP_IDIV|\ 109 COMPAT_HWCAP_LPAE) 110 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT; 111 unsigned int compat_elf_hwcap2 __read_mostly; 112 unsigned int compat_elf_hwcap3 __read_mostly; 113 #endif 114 115 DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 116 EXPORT_SYMBOL(system_cpucaps); 117 static struct arm64_cpu_capabilities const __ro_after_init *cpucap_ptrs[ARM64_NCAPS]; 118 119 DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 120 121 /* 122 * arm64_use_ng_mappings must be placed in the .data section, otherwise it 123 * ends up in the .bss section where it is initialized in early_map_kernel() 124 * after the MMU (with the idmap) was enabled. create_init_idmap() - which 125 * runs before early_map_kernel() and reads the variable via PTE_MAYBE_NG - 126 * may end up generating an incorrect idmap page table attributes. 127 */ 128 bool arm64_use_ng_mappings __read_mostly = false; 129 EXPORT_SYMBOL(arm64_use_ng_mappings); 130 131 DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; 132 133 /* 134 * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs 135 * support it? 136 */ 137 static bool __read_mostly allow_mismatched_32bit_el0; 138 139 /* 140 * Static branch enabled only if allow_mismatched_32bit_el0 is set and we have 141 * seen at least one CPU capable of 32-bit EL0. 142 */ 143 DEFINE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 144 145 /* 146 * Mask of CPUs supporting 32-bit EL0. 147 * Only valid if arm64_mismatched_32bit_el0 is enabled. 148 */ 149 static cpumask_var_t cpu_32bit_el0_mask __cpumask_var_read_mostly; 150 151 void dump_cpu_features(void) 152 { 153 /* file-wide pr_fmt adds "CPU features: " prefix */ 154 pr_emerg("0x%*pb\n", ARM64_NCAPS, &system_cpucaps); 155 } 156 157 #define __ARM64_MAX_POSITIVE(reg, field) \ 158 ((reg##_##field##_SIGNED ? \ 159 BIT(reg##_##field##_WIDTH - 1) : \ 160 BIT(reg##_##field##_WIDTH)) - 1) 161 162 #define __ARM64_MIN_NEGATIVE(reg, field) BIT(reg##_##field##_WIDTH - 1) 163 164 #define __ARM64_CPUID_FIELDS(reg, field, min_value, max_value) \ 165 .sys_reg = SYS_##reg, \ 166 .field_pos = reg##_##field##_SHIFT, \ 167 .field_width = reg##_##field##_WIDTH, \ 168 .sign = reg##_##field##_SIGNED, \ 169 .min_field_value = min_value, \ 170 .max_field_value = max_value, 171 172 /* 173 * ARM64_CPUID_FIELDS() encodes a field with a range from min_value to 174 * an implicit maximum that depends on the sign-ess of the field. 175 * 176 * An unsigned field will be capped at all ones, while a signed field 177 * will be limited to the positive half only. 178 */ 179 #define ARM64_CPUID_FIELDS(reg, field, min_value) \ 180 __ARM64_CPUID_FIELDS(reg, field, \ 181 SYS_FIELD_VALUE(reg, field, min_value), \ 182 __ARM64_MAX_POSITIVE(reg, field)) 183 184 /* 185 * ARM64_CPUID_FIELDS_NEG() encodes a field with a range from an 186 * implicit minimal value to max_value. This should be used when 187 * matching a non-implemented property. 188 */ 189 #define ARM64_CPUID_FIELDS_NEG(reg, field, max_value) \ 190 __ARM64_CPUID_FIELDS(reg, field, \ 191 __ARM64_MIN_NEGATIVE(reg, field), \ 192 SYS_FIELD_VALUE(reg, field, max_value)) 193 194 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 195 { \ 196 .sign = SIGNED, \ 197 .visible = VISIBLE, \ 198 .strict = STRICT, \ 199 .type = TYPE, \ 200 .shift = SHIFT, \ 201 .width = WIDTH, \ 202 .safe_val = SAFE_VAL, \ 203 } 204 205 /* Define a feature with unsigned values */ 206 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 207 __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 208 209 /* Define a feature with a signed value */ 210 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \ 211 __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) 212 213 #define ARM64_FTR_END \ 214 { \ 215 .width = 0, \ 216 } 217 218 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap); 219 220 static bool __system_matches_cap(unsigned int n); 221 222 /* 223 * NOTE: Any changes to the visibility of features should be kept in 224 * sync with the documentation of the CPU feature register ABI. 225 */ 226 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { 227 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), 228 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), 229 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), 230 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), 231 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), 232 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), 233 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), 234 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), 235 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), 236 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMIC_SHIFT, 4, 0), 237 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), 238 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), 239 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), 240 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), 241 ARM64_FTR_END, 242 }; 243 244 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { 245 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LS64_SHIFT, 4, 0), 246 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_XS_SHIFT, 4, 0), 247 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_I8MM_SHIFT, 4, 0), 248 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DGH_SHIFT, 4, 0), 249 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_BF16_SHIFT, 4, 0), 250 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SPECRES_SHIFT, 4, 0), 251 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_SB_SHIFT, 4, 0), 252 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FRINTTS_SHIFT, 4, 0), 253 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 254 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPI_SHIFT, 4, 0), 255 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 256 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_GPA_SHIFT, 4, 0), 257 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_LRCPC_SHIFT, 4, 0), 258 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_FCMA_SHIFT, 4, 0), 259 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_JSCVT_SHIFT, 4, 0), 260 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 261 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_API_SHIFT, 4, 0), 262 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 263 FTR_STRICT, FTR_EXACT, ID_AA64ISAR1_EL1_APA_SHIFT, 4, 0), 264 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_EL1_DPB_SHIFT, 4, 0), 265 ARM64_FTR_END, 266 }; 267 268 static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { 269 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_LUT_SHIFT, 4, 0), 270 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CSSC_SHIFT, 4, 0), 271 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRFM_SHIFT, 4, 0), 272 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_CLRBHB_SHIFT, 4, 0), 273 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_BC_SHIFT, 4, 0), 274 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_MOPS_SHIFT, 4, 0), 275 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 276 FTR_STRICT, FTR_EXACT, ID_AA64ISAR2_EL1_APA3_SHIFT, 4, 0), 277 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH), 278 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_GPA3_SHIFT, 4, 0), 279 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, 0), 280 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, 0), 281 ARM64_FTR_END, 282 }; 283 284 static const struct arm64_ftr_bits ftr_id_aa64isar3[] = { 285 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FPRCVT_SHIFT, 4, 0), 286 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSUI_SHIFT, 4, ID_AA64ISAR3_EL1_LSUI_NI), 287 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_LSFE_SHIFT, 4, 0), 288 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64ISAR3_EL1_FAMINMAX_SHIFT, 4, 0), 289 ARM64_FTR_END, 290 }; 291 292 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { 293 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV3_SHIFT, 4, 0), 294 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_CSV2_SHIFT, 4, 0), 295 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_DIT_SHIFT, 4, 0), 296 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AMU_SHIFT, 4, 0), 297 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_MPAM_SHIFT, 4, 0), 298 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SEL2_SHIFT, 4, 0), 299 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 300 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SVE_SHIFT, 4, 0), 301 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_RAS_SHIFT, 4, 0), 302 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_GIC_SHIFT, 4, 0), 303 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_AdvSIMD_SHIFT, 4, ID_AA64PFR0_EL1_AdvSIMD_NI), 304 S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_FP_SHIFT, 4, ID_AA64PFR0_EL1_FP_NI), 305 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL3_SHIFT, 4, 0), 306 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL2_SHIFT, 4, 0), 307 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL1_SHIFT, 4, ID_AA64PFR0_EL1_EL1_IMP), 308 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_EL0_SHIFT, 4, ID_AA64PFR0_EL1_EL0_IMP), 309 ARM64_FTR_END, 310 }; 311 312 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = { 313 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_DF2_SHIFT, 4, 0), 314 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_GCS), 315 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_GCS_SHIFT, 4, 0), 316 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_frac_SHIFT, 4, 0), 317 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 318 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SME_SHIFT, 4, 0), 319 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MPAM_frac_SHIFT, 4, 0), 320 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_RAS_frac_SHIFT, 4, 0), 321 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_MTE), 322 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_MTE_SHIFT, 4, ID_AA64PFR1_EL1_MTE_NI), 323 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_SSBS_SHIFT, 4, ID_AA64PFR1_EL1_SSBS_NI), 324 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_BTI), 325 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_EL1_BT_SHIFT, 4, 0), 326 ARM64_FTR_END, 327 }; 328 329 static const struct arm64_ftr_bits ftr_id_aa64pfr2[] = { 330 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_FPMR_SHIFT, 4, 0), 331 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_GCIE_SHIFT, 4, ID_AA64PFR2_EL1_GCIE_NI), 332 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTEFAR_SHIFT, 4, ID_AA64PFR2_EL1_MTEFAR_NI), 333 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR2_EL1_MTESTOREONLY_SHIFT, 4, ID_AA64PFR2_EL1_MTESTOREONLY_NI), 334 ARM64_FTR_END, 335 }; 336 337 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = { 338 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 339 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F64MM_SHIFT, 4, 0), 340 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 341 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F32MM_SHIFT, 4, 0), 342 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 343 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_F16MM_SHIFT, 4, 0), 344 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 345 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_I8MM_SHIFT, 4, 0), 346 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 347 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SM4_SHIFT, 4, 0), 348 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 349 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SHA3_SHIFT, 4, 0), 350 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 351 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_B16B16_SHIFT, 4, 0), 352 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 353 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BF16_SHIFT, 4, 0), 354 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 355 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_BitPerm_SHIFT, 4, 0), 356 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 357 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_EltPerm_SHIFT, 4, 0), 358 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 359 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_AES_SHIFT, 4, 0), 360 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE), 361 FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_EL1_SVEver_SHIFT, 4, 0), 362 ARM64_FTR_END, 363 }; 364 365 static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = { 366 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 367 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, 0), 368 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 369 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUT6_SHIFT, 1, 0), 370 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 371 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_LUTv2_SHIFT, 1, 0), 372 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 373 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, 0), 374 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 375 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I64_SHIFT, 4, 0), 376 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 377 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F64F64_SHIFT, 1, 0), 378 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 379 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I16I32_SHIFT, 4, 0), 380 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 381 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16B16_SHIFT, 1, 0), 382 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 383 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F16_SHIFT, 1, 0), 384 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 385 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F16_SHIFT, 1, 0), 386 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 387 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F8F32_SHIFT, 1, 0), 388 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 389 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_I8I32_SHIFT, 4, 0), 390 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 391 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F16F32_SHIFT, 1, 0), 392 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 393 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_B16F32_SHIFT, 1, 0), 394 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 395 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_BI32I32_SHIFT, 1, 0), 396 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 397 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_F32F32_SHIFT, 1, 0), 398 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 399 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8FMA_SHIFT, 1, 0), 400 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 401 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP4_SHIFT, 1, 0), 402 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 403 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SF8DP2_SHIFT, 1, 0), 404 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 405 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SBitPerm_SHIFT, 1, 0), 406 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 407 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_AES_SHIFT, 1, 0), 408 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 409 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SFEXPA_SHIFT, 1, 0), 410 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 411 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_STMOP_SHIFT, 1, 0), 412 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SME), 413 FTR_STRICT, FTR_EXACT, ID_AA64SMFR0_EL1_SMOP4_SHIFT, 1, 0), 414 ARM64_FTR_END, 415 }; 416 417 static const struct arm64_ftr_bits ftr_id_aa64fpfr0[] = { 418 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8CVT_SHIFT, 1, 0), 419 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8FMA_SHIFT, 1, 0), 420 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP4_SHIFT, 1, 0), 421 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8DP2_SHIFT, 1, 0), 422 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM8_SHIFT, 1, 0), 423 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8MM4_SHIFT, 1, 0), 424 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F16MM2_SHIFT, 1, 0), 425 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E4M3_SHIFT, 1, 0), 426 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, ID_AA64FPFR0_EL1_F8E5M2_SHIFT, 1, 0), 427 ARM64_FTR_END, 428 }; 429 430 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = { 431 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0), 432 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0), 433 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0), 434 /* 435 * Page size not being supported at Stage-2 is not fatal. You 436 * just give up KVM if PAGE_SIZE isn't supported there. Go fix 437 * your favourite nesting hypervisor. 438 * 439 * There is a small corner case where the hypervisor explicitly 440 * advertises a given granule size at Stage-2 (value 2) on some 441 * vCPUs, and uses the fallback to Stage-1 (value 0) for other 442 * vCPUs. Although this is not forbidden by the architecture, it 443 * indicates that the hypervisor is being silly (or buggy). 444 * 445 * We make no effort to cope with this and pretend that if these 446 * fields are inconsistent across vCPUs, then it isn't worth 447 * trying to bring KVM up. 448 */ 449 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1), 450 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1), 451 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1), 452 /* 453 * We already refuse to boot CPUs that don't support our configured 454 * page size, so we can only detect mismatches for a page size other 455 * than the one we're currently using. Unfortunately, SoCs like this 456 * exist in the wild so, even though we don't like it, we'll have to go 457 * along with it and treat them as non-strict. 458 */ 459 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI), 460 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI), 461 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI), 462 463 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0), 464 /* Linux shouldn't care about secure memory */ 465 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0), 466 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGEND_SHIFT, 4, 0), 467 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASIDBITS_SHIFT, 4, 0), 468 /* 469 * Differing PARange is fine as long as all peripherals and memory are mapped 470 * within the minimum PARange of all CPUs 471 */ 472 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0), 473 ARM64_FTR_END, 474 }; 475 476 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { 477 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ECBHB_SHIFT, 4, 0), 478 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TIDCP1_SHIFT, 4, 0), 479 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_AFP_SHIFT, 4, 0), 480 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HCX_SHIFT, 4, 0), 481 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_ETS_SHIFT, 4, 0), 482 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_TWED_SHIFT, 4, 0), 483 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_XNX_SHIFT, 4, 0), 484 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1_SpecSEI_SHIFT, 4, 0), 485 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_PAN_SHIFT, 4, 0), 486 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_LO_SHIFT, 4, 0), 487 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HPDS_SHIFT, 4, 0), 488 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VH_SHIFT, 4, 0), 489 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_VMIDBits_SHIFT, 4, 0), 490 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_EL1_HAFDBS_SHIFT, 4, 0), 491 ARM64_FTR_END, 492 }; 493 494 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { 495 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_E0PD_SHIFT, 4, 0), 496 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_EVT_SHIFT, 4, 0), 497 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_BBM_SHIFT, 4, 0), 498 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_TTL_SHIFT, 4, 0), 499 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_FWB_SHIFT, 4, 0), 500 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IDS_SHIFT, 4, 0), 501 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_AT_SHIFT, 4, 0), 502 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_ST_SHIFT, 4, 0), 503 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_NV_SHIFT, 4, 0), 504 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CCIDX_SHIFT, 4, 0), 505 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_VARange_SHIFT, 4, 0), 506 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_IESB_SHIFT, 4, 0), 507 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_LSM_SHIFT, 4, 0), 508 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_UAO_SHIFT, 4, 0), 509 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_EL1_CnP_SHIFT, 4, 0), 510 ARM64_FTR_END, 511 }; 512 513 static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { 514 ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), 515 FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), 516 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), 517 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_SCTLRX_SHIFT, 4, 0), 518 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), 519 ARM64_FTR_END, 520 }; 521 522 static const struct arm64_ftr_bits ftr_id_aa64mmfr4[] = { 523 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_E2H0_SHIFT, 4, 0), 524 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR4_EL1_NV_frac_SHIFT, 4, 0), 525 ARM64_FTR_END, 526 }; 527 528 static const struct arm64_ftr_bits ftr_ctr[] = { 529 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */ 530 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DIC_SHIFT, 1, 1), 531 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IDC_SHIFT, 1, 1), 532 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_CWG_SHIFT, 4, 0), 533 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_OR_ZERO_SAFE, CTR_EL0_ERG_SHIFT, 4, 0), 534 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_DminLine_SHIFT, 4, 1), 535 /* 536 * Linux can handle differing I-cache policies. Userspace JITs will 537 * make use of *minLine. 538 * If we have differing I-cache policies, report it as the weakest - VIPT. 539 */ 540 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, CTR_EL0_L1Ip_SHIFT, 2, CTR_EL0_L1Ip_VIPT), /* L1Ip */ 541 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_EL0_IminLine_SHIFT, 4, 0), 542 ARM64_FTR_END, 543 }; 544 545 static struct arm64_ftr_override __ro_after_init no_override = { }; 546 547 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = { 548 .name = "SYS_CTR_EL0", 549 .ftr_bits = ftr_ctr, 550 .override = &no_override, 551 }; 552 553 static const struct arm64_ftr_bits ftr_id_mmfr0[] = { 554 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_InnerShr_SHIFT, 4, 0xf), 555 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_FCSE_SHIFT, 4, 0), 556 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_AuxReg_SHIFT, 4, 0), 557 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_TCM_SHIFT, 4, 0), 558 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_ShareLvl_SHIFT, 4, 0), 559 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_OuterShr_SHIFT, 4, 0xf), 560 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_PMSA_SHIFT, 4, 0), 561 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR0_EL1_VMSA_SHIFT, 4, 0), 562 ARM64_FTR_END, 563 }; 564 565 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = { 566 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_DoubleLock_SHIFT, 4, 0), 567 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_PMSVer_SHIFT, 4, 0), 568 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_CTX_CMPs_SHIFT, 4, 0), 569 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_WRPs_SHIFT, 4, 0), 570 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_EL1_BRPs_SHIFT, 4, 0), 571 /* 572 * We can instantiate multiple PMU instances with different levels 573 * of support. 574 */ 575 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_EL1_PMUVer_SHIFT, 4, 0), 576 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_EL1_DebugVer_SHIFT, 4, 0x6), 577 ARM64_FTR_END, 578 }; 579 580 static const struct arm64_ftr_bits ftr_mvfr0[] = { 581 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPRound_SHIFT, 4, 0), 582 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPShVec_SHIFT, 4, 0), 583 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSqrt_SHIFT, 4, 0), 584 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDivide_SHIFT, 4, 0), 585 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPTrap_SHIFT, 4, 0), 586 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPDP_SHIFT, 4, 0), 587 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_FPSP_SHIFT, 4, 0), 588 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR0_EL1_SIMDReg_SHIFT, 4, 0), 589 ARM64_FTR_END, 590 }; 591 592 static const struct arm64_ftr_bits ftr_mvfr1[] = { 593 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0), 594 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0), 595 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0), 596 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0), 597 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0), 598 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0), 599 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPDNaN_SHIFT, 4, 0), 600 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPFtZ_SHIFT, 4, 0), 601 ARM64_FTR_END, 602 }; 603 604 static const struct arm64_ftr_bits ftr_mvfr2[] = { 605 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_FPMisc_SHIFT, 4, 0), 606 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR2_EL1_SIMDMisc_SHIFT, 4, 0), 607 ARM64_FTR_END, 608 }; 609 610 static const struct arm64_ftr_bits ftr_dczid[] = { 611 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_EL0_DZP_SHIFT, 1, 1), 612 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_EL0_BS_SHIFT, 4, 0), 613 ARM64_FTR_END, 614 }; 615 616 static const struct arm64_ftr_bits ftr_gmid[] = { 617 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, GMID_EL1_BS_SHIFT, 4, 0), 618 ARM64_FTR_END, 619 }; 620 621 static const struct arm64_ftr_bits ftr_id_isar0[] = { 622 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Divide_SHIFT, 4, 0), 623 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Debug_SHIFT, 4, 0), 624 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Coproc_SHIFT, 4, 0), 625 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_CmpBranch_SHIFT, 4, 0), 626 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitField_SHIFT, 4, 0), 627 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_BitCount_SHIFT, 4, 0), 628 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR0_EL1_Swap_SHIFT, 4, 0), 629 ARM64_FTR_END, 630 }; 631 632 static const struct arm64_ftr_bits ftr_id_isar5[] = { 633 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_RDM_SHIFT, 4, 0), 634 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_CRC32_SHIFT, 4, 0), 635 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA2_SHIFT, 4, 0), 636 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SHA1_SHIFT, 4, 0), 637 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_AES_SHIFT, 4, 0), 638 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_EL1_SEVL_SHIFT, 4, 0), 639 ARM64_FTR_END, 640 }; 641 642 static const struct arm64_ftr_bits ftr_id_mmfr4[] = { 643 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_EVT_SHIFT, 4, 0), 644 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CCIDX_SHIFT, 4, 0), 645 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_LSM_SHIFT, 4, 0), 646 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_HPDS_SHIFT, 4, 0), 647 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_CnP_SHIFT, 4, 0), 648 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_XNX_SHIFT, 4, 0), 649 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR4_EL1_AC2_SHIFT, 4, 0), 650 651 /* 652 * SpecSEI = 1 indicates that the PE might generate an SError on an 653 * external abort on speculative read. It is safe to assume that an 654 * SError might be generated than it will not be. Hence it has been 655 * classified as FTR_HIGHER_SAFE. 656 */ 657 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_MMFR4_EL1_SpecSEI_SHIFT, 4, 0), 658 ARM64_FTR_END, 659 }; 660 661 static const struct arm64_ftr_bits ftr_id_isar4[] = { 662 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SWP_frac_SHIFT, 4, 0), 663 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_PSR_M_SHIFT, 4, 0), 664 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SynchPrim_frac_SHIFT, 4, 0), 665 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Barrier_SHIFT, 4, 0), 666 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_SMC_SHIFT, 4, 0), 667 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Writeback_SHIFT, 4, 0), 668 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_WithShifts_SHIFT, 4, 0), 669 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR4_EL1_Unpriv_SHIFT, 4, 0), 670 ARM64_FTR_END, 671 }; 672 673 static const struct arm64_ftr_bits ftr_id_mmfr5[] = { 674 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_MMFR5_EL1_ETS_SHIFT, 4, 0), 675 ARM64_FTR_END, 676 }; 677 678 static const struct arm64_ftr_bits ftr_id_isar6[] = { 679 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_I8MM_SHIFT, 4, 0), 680 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_BF16_SHIFT, 4, 0), 681 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SPECRES_SHIFT, 4, 0), 682 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_SB_SHIFT, 4, 0), 683 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_FHM_SHIFT, 4, 0), 684 ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_DP_SHIFT, 4, 0), 685 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR6_EL1_JSCVT_SHIFT, 4, 0), 686 ARM64_FTR_END, 687 }; 688 689 static const struct arm64_ftr_bits ftr_id_pfr0[] = { 690 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_DIT_SHIFT, 4, 0), 691 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_CSV2_SHIFT, 4, 0), 692 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State3_SHIFT, 4, 0), 693 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State2_SHIFT, 4, 0), 694 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State1_SHIFT, 4, 0), 695 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR0_EL1_State0_SHIFT, 4, 0), 696 ARM64_FTR_END, 697 }; 698 699 static const struct arm64_ftr_bits ftr_id_pfr1[] = { 700 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GIC_SHIFT, 4, 0), 701 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virt_frac_SHIFT, 4, 0), 702 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Sec_frac_SHIFT, 4, 0), 703 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_GenTimer_SHIFT, 4, 0), 704 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Virtualization_SHIFT, 4, 0), 705 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_MProgMod_SHIFT, 4, 0), 706 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_Security_SHIFT, 4, 0), 707 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_PFR1_EL1_ProgMod_SHIFT, 4, 0), 708 ARM64_FTR_END, 709 }; 710 711 static const struct arm64_ftr_bits ftr_id_pfr2[] = { 712 ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_SSBS_SHIFT, 4, 0), 713 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_PFR2_EL1_CSV3_SHIFT, 4, 0), 714 ARM64_FTR_END, 715 }; 716 717 static const struct arm64_ftr_bits ftr_id_dfr0[] = { 718 /* [31:28] TraceFilt */ 719 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_DFR0_EL1_PerfMon_SHIFT, 4, 0), 720 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MProfDbg_SHIFT, 4, 0), 721 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapTrc_SHIFT, 4, 0), 722 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopTrc_SHIFT, 4, 0), 723 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_MMapDbg_SHIFT, 4, 0), 724 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopSDbg_SHIFT, 4, 0), 725 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR0_EL1_CopDbg_SHIFT, 4, 0), 726 ARM64_FTR_END, 727 }; 728 729 static const struct arm64_ftr_bits ftr_id_dfr1[] = { 730 S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_EL1_MTPMU_SHIFT, 4, 0), 731 ARM64_FTR_END, 732 }; 733 734 static const struct arm64_ftr_bits ftr_mpamidr[] = { 735 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PMG_MAX_SHIFT, MPAMIDR_EL1_PMG_MAX_WIDTH, 0), 736 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_VPMR_MAX_SHIFT, MPAMIDR_EL1_VPMR_MAX_WIDTH, 0), 737 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_HAS_HCR_SHIFT, 1, 0), 738 ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, MPAMIDR_EL1_PARTID_MAX_SHIFT, MPAMIDR_EL1_PARTID_MAX_WIDTH, 0), 739 ARM64_FTR_END, 740 }; 741 742 /* 743 * Common ftr bits for a 32bit register with all hidden, strict 744 * attributes, with 4bit feature fields and a default safe value of 745 * 0. Covers the following 32bit registers: 746 * id_isar[1-3], id_mmfr[1-3] 747 */ 748 static const struct arm64_ftr_bits ftr_generic_32bits[] = { 749 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0), 750 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0), 751 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0), 752 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0), 753 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0), 754 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0), 755 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0), 756 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0), 757 ARM64_FTR_END, 758 }; 759 760 /* Table for a single 32bit feature value */ 761 static const struct arm64_ftr_bits ftr_single32[] = { 762 ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0), 763 ARM64_FTR_END, 764 }; 765 766 static const struct arm64_ftr_bits ftr_raz[] = { 767 ARM64_FTR_END, 768 }; 769 770 #define __ARM64_FTR_REG_OVERRIDE(id_str, id, table, ovr) { \ 771 .sys_id = id, \ 772 .reg = &(struct arm64_ftr_reg){ \ 773 .name = id_str, \ 774 .override = (ovr), \ 775 .ftr_bits = &((table)[0]), \ 776 }} 777 778 #define ARM64_FTR_REG_OVERRIDE(id, table, ovr) \ 779 __ARM64_FTR_REG_OVERRIDE(#id, id, table, ovr) 780 781 #define ARM64_FTR_REG(id, table) \ 782 __ARM64_FTR_REG_OVERRIDE(#id, id, table, &no_override) 783 784 struct arm64_ftr_override __read_mostly id_aa64mmfr0_override; 785 struct arm64_ftr_override __read_mostly id_aa64mmfr1_override; 786 struct arm64_ftr_override __read_mostly id_aa64mmfr2_override; 787 struct arm64_ftr_override __read_mostly id_aa64pfr0_override; 788 struct arm64_ftr_override __read_mostly id_aa64pfr1_override; 789 struct arm64_ftr_override __read_mostly id_aa64zfr0_override; 790 struct arm64_ftr_override __read_mostly id_aa64smfr0_override; 791 struct arm64_ftr_override __read_mostly id_aa64isar1_override; 792 struct arm64_ftr_override __read_mostly id_aa64isar2_override; 793 794 struct arm64_ftr_override __read_mostly arm64_sw_feature_override; 795 796 static const struct __ftr_reg_entry { 797 u32 sys_id; 798 struct arm64_ftr_reg *reg; 799 } arm64_ftr_regs[] = { 800 801 /* Op1 = 0, CRn = 0, CRm = 1 */ 802 ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0), 803 ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_id_pfr1), 804 ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0), 805 ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0), 806 ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits), 807 ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits), 808 ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits), 809 810 /* Op1 = 0, CRn = 0, CRm = 2 */ 811 ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_id_isar0), 812 ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits), 813 ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits), 814 ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits), 815 ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_id_isar4), 816 ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5), 817 ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4), 818 ARM64_FTR_REG(SYS_ID_ISAR6_EL1, ftr_id_isar6), 819 820 /* Op1 = 0, CRn = 0, CRm = 3 */ 821 ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_mvfr0), 822 ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_mvfr1), 823 ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2), 824 ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2), 825 ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1), 826 ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5), 827 828 /* Op1 = 0, CRn = 0, CRm = 4 */ 829 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0, 830 &id_aa64pfr0_override), 831 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1, 832 &id_aa64pfr1_override), 833 ARM64_FTR_REG(SYS_ID_AA64PFR2_EL1, ftr_id_aa64pfr2), 834 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0, 835 &id_aa64zfr0_override), 836 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64SMFR0_EL1, ftr_id_aa64smfr0, 837 &id_aa64smfr0_override), 838 ARM64_FTR_REG(SYS_ID_AA64FPFR0_EL1, ftr_id_aa64fpfr0), 839 840 /* Op1 = 0, CRn = 0, CRm = 5 */ 841 ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0), 842 ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz), 843 844 /* Op1 = 0, CRn = 0, CRm = 6 */ 845 ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), 846 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1, 847 &id_aa64isar1_override), 848 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2, 849 &id_aa64isar2_override), 850 ARM64_FTR_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3), 851 852 /* Op1 = 0, CRn = 0, CRm = 7 */ 853 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0, 854 &id_aa64mmfr0_override), 855 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1, 856 &id_aa64mmfr1_override), 857 ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2, 858 &id_aa64mmfr2_override), 859 ARM64_FTR_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3), 860 ARM64_FTR_REG(SYS_ID_AA64MMFR4_EL1, ftr_id_aa64mmfr4), 861 862 /* Op1 = 0, CRn = 10, CRm = 4 */ 863 ARM64_FTR_REG(SYS_MPAMIDR_EL1, ftr_mpamidr), 864 865 /* Op1 = 1, CRn = 0, CRm = 0 */ 866 ARM64_FTR_REG(SYS_GMID_EL1, ftr_gmid), 867 868 /* Op1 = 3, CRn = 0, CRm = 0 */ 869 { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 }, 870 ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid), 871 872 /* Op1 = 3, CRn = 14, CRm = 0 */ 873 ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32), 874 }; 875 876 static int search_cmp_ftr_reg(const void *id, const void *regp) 877 { 878 return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id; 879 } 880 881 /* 882 * get_arm64_ftr_reg_nowarn - Looks up a feature register entry using 883 * its sys_reg() encoding. With the array arm64_ftr_regs sorted in the 884 * ascending order of sys_id, we use binary search to find a matching 885 * entry. 886 * 887 * returns - Upon success, matching ftr_reg entry for id. 888 * - NULL on failure. It is upto the caller to decide 889 * the impact of a failure. 890 */ 891 static struct arm64_ftr_reg *get_arm64_ftr_reg_nowarn(u32 sys_id) 892 { 893 const struct __ftr_reg_entry *ret; 894 895 ret = bsearch((const void *)(unsigned long)sys_id, 896 arm64_ftr_regs, 897 ARRAY_SIZE(arm64_ftr_regs), 898 sizeof(arm64_ftr_regs[0]), 899 search_cmp_ftr_reg); 900 if (ret) 901 return ret->reg; 902 return NULL; 903 } 904 905 /* 906 * get_arm64_ftr_reg - Looks up a feature register entry using 907 * its sys_reg() encoding. This calls get_arm64_ftr_reg_nowarn(). 908 * 909 * returns - Upon success, matching ftr_reg entry for id. 910 * - NULL on failure but with an WARN_ON(). 911 */ 912 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id) 913 { 914 struct arm64_ftr_reg *reg; 915 916 reg = get_arm64_ftr_reg_nowarn(sys_id); 917 918 /* 919 * Requesting a non-existent register search is an error. Warn 920 * and let the caller handle it. 921 */ 922 WARN_ON(!reg); 923 return reg; 924 } 925 926 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg, 927 s64 ftr_val) 928 { 929 u64 mask = arm64_ftr_mask(ftrp); 930 931 reg &= ~mask; 932 reg |= (ftr_val << ftrp->shift) & mask; 933 return reg; 934 } 935 936 s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new, 937 s64 cur) 938 { 939 s64 ret = 0; 940 941 switch (ftrp->type) { 942 case FTR_EXACT: 943 ret = ftrp->safe_val; 944 break; 945 case FTR_LOWER_SAFE: 946 ret = min(new, cur); 947 break; 948 case FTR_HIGHER_OR_ZERO_SAFE: 949 if (!cur || !new) 950 break; 951 fallthrough; 952 case FTR_HIGHER_SAFE: 953 ret = max(new, cur); 954 break; 955 default: 956 BUG(); 957 } 958 959 return ret; 960 } 961 962 static void __init sort_ftr_regs(void) 963 { 964 unsigned int i; 965 966 for (i = 0; i < ARRAY_SIZE(arm64_ftr_regs); i++) { 967 const struct arm64_ftr_reg *ftr_reg = arm64_ftr_regs[i].reg; 968 const struct arm64_ftr_bits *ftr_bits = ftr_reg->ftr_bits; 969 unsigned int j = 0; 970 971 /* 972 * Features here must be sorted in descending order with respect 973 * to their shift values and should not overlap with each other. 974 */ 975 for (; ftr_bits->width != 0; ftr_bits++, j++) { 976 unsigned int width = ftr_reg->ftr_bits[j].width; 977 unsigned int shift = ftr_reg->ftr_bits[j].shift; 978 unsigned int prev_shift; 979 980 WARN((shift + width) > 64, 981 "%s has invalid feature at shift %d\n", 982 ftr_reg->name, shift); 983 984 /* 985 * Skip the first feature. There is nothing to 986 * compare against for now. 987 */ 988 if (j == 0) 989 continue; 990 991 prev_shift = ftr_reg->ftr_bits[j - 1].shift; 992 WARN((shift + width) > prev_shift, 993 "%s has feature overlap at shift %d\n", 994 ftr_reg->name, shift); 995 } 996 997 /* 998 * Skip the first register. There is nothing to 999 * compare against for now. 1000 */ 1001 if (i == 0) 1002 continue; 1003 /* 1004 * Registers here must be sorted in ascending order with respect 1005 * to sys_id for subsequent binary search in get_arm64_ftr_reg() 1006 * to work correctly. 1007 */ 1008 BUG_ON(arm64_ftr_regs[i].sys_id <= arm64_ftr_regs[i - 1].sys_id); 1009 } 1010 } 1011 1012 /* 1013 * Initialise the CPU feature register from Boot CPU values. 1014 * Also initialises the strict_mask for the register. 1015 * Any bits that are not covered by an arm64_ftr_bits entry are considered 1016 * RES0 for the system-wide value, and must strictly match. 1017 */ 1018 static void init_cpu_ftr_reg(u32 sys_reg, u64 new) 1019 { 1020 u64 val = 0; 1021 u64 strict_mask = ~0x0ULL; 1022 u64 user_mask = 0; 1023 u64 valid_mask = 0; 1024 1025 const struct arm64_ftr_bits *ftrp; 1026 struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg); 1027 1028 if (!reg) 1029 return; 1030 1031 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1032 u64 ftr_mask = arm64_ftr_mask(ftrp); 1033 s64 ftr_new = arm64_ftr_value(ftrp, new); 1034 s64 ftr_ovr = arm64_ftr_value(ftrp, reg->override->val); 1035 1036 if ((ftr_mask & reg->override->mask) == ftr_mask) { 1037 s64 tmp = arm64_ftr_safe_value(ftrp, ftr_ovr, ftr_new); 1038 char *str = NULL; 1039 1040 if (ftr_ovr != tmp) { 1041 /* Unsafe, remove the override */ 1042 reg->override->mask &= ~ftr_mask; 1043 reg->override->val &= ~ftr_mask; 1044 tmp = ftr_ovr; 1045 str = "ignoring override"; 1046 } else if (ftr_new != tmp) { 1047 /* Override was valid */ 1048 ftr_new = tmp; 1049 str = "forced"; 1050 } else { 1051 /* Override was the safe value */ 1052 str = "already set"; 1053 } 1054 1055 pr_warn("%s[%d:%d]: %s to %llx\n", 1056 reg->name, 1057 ftrp->shift + ftrp->width - 1, 1058 ftrp->shift, str, 1059 tmp & (BIT(ftrp->width) - 1)); 1060 } else if ((ftr_mask & reg->override->val) == ftr_mask) { 1061 reg->override->val &= ~ftr_mask; 1062 pr_warn("%s[%d:%d]: impossible override, ignored\n", 1063 reg->name, 1064 ftrp->shift + ftrp->width - 1, 1065 ftrp->shift); 1066 } 1067 1068 val = arm64_ftr_set_value(ftrp, val, ftr_new); 1069 1070 valid_mask |= ftr_mask; 1071 if (!ftrp->strict) 1072 strict_mask &= ~ftr_mask; 1073 if (ftrp->visible) 1074 user_mask |= ftr_mask; 1075 else 1076 reg->user_val = arm64_ftr_set_value(ftrp, 1077 reg->user_val, 1078 ftrp->safe_val); 1079 } 1080 1081 val &= valid_mask; 1082 1083 reg->sys_val = val; 1084 reg->strict_mask = strict_mask; 1085 reg->user_mask = user_mask; 1086 } 1087 1088 extern const struct arm64_cpu_capabilities arm64_errata[]; 1089 static const struct arm64_cpu_capabilities arm64_features[]; 1090 1091 static void __init 1092 init_cpucap_indirect_list_from_array(const struct arm64_cpu_capabilities *caps) 1093 { 1094 for (; caps->matches; caps++) { 1095 if (WARN(caps->capability >= ARM64_NCAPS, 1096 "Invalid capability %d\n", caps->capability)) 1097 continue; 1098 if (WARN(cpucap_ptrs[caps->capability], 1099 "Duplicate entry for capability %d\n", 1100 caps->capability)) 1101 continue; 1102 cpucap_ptrs[caps->capability] = caps; 1103 } 1104 } 1105 1106 static void __init init_cpucap_indirect_list(void) 1107 { 1108 init_cpucap_indirect_list_from_array(arm64_features); 1109 init_cpucap_indirect_list_from_array(arm64_errata); 1110 } 1111 1112 static void __init setup_boot_cpu_capabilities(void); 1113 1114 static void init_32bit_cpu_features(struct cpuinfo_32bit *info) 1115 { 1116 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0); 1117 init_cpu_ftr_reg(SYS_ID_DFR1_EL1, info->reg_id_dfr1); 1118 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0); 1119 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1); 1120 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2); 1121 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3); 1122 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4); 1123 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5); 1124 init_cpu_ftr_reg(SYS_ID_ISAR6_EL1, info->reg_id_isar6); 1125 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0); 1126 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1); 1127 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2); 1128 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3); 1129 init_cpu_ftr_reg(SYS_ID_MMFR4_EL1, info->reg_id_mmfr4); 1130 init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5); 1131 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0); 1132 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1); 1133 init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2); 1134 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0); 1135 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1); 1136 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); 1137 } 1138 1139 #ifdef CONFIG_ARM64_PSEUDO_NMI 1140 static bool enable_pseudo_nmi; 1141 1142 static int __init early_enable_pseudo_nmi(char *p) 1143 { 1144 return kstrtobool(p, &enable_pseudo_nmi); 1145 } 1146 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); 1147 1148 static __init void detect_system_supports_pseudo_nmi(void) 1149 { 1150 struct device_node *np; 1151 1152 if (!enable_pseudo_nmi) 1153 return; 1154 1155 /* 1156 * Detect broken MediaTek firmware that doesn't properly save and 1157 * restore GIC priorities. 1158 */ 1159 np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); 1160 if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { 1161 pr_info("Pseudo-NMI disabled due to MediaTek Chromebook GICR save problem\n"); 1162 enable_pseudo_nmi = false; 1163 } 1164 of_node_put(np); 1165 } 1166 #else /* CONFIG_ARM64_PSEUDO_NMI */ 1167 static inline void detect_system_supports_pseudo_nmi(void) { } 1168 #endif 1169 1170 static bool detect_ftr_has_mpam(void) 1171 { 1172 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1173 u64 pfr1 = read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1); 1174 1175 return id_aa64pfr0_mpam(pfr0) || id_aa64pfr1_mpamfrac(pfr1); 1176 } 1177 1178 void __init init_cpu_features(struct cpuinfo_arm64 *info) 1179 { 1180 /* Before we start using the tables, make sure it is sorted */ 1181 sort_ftr_regs(); 1182 1183 init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr); 1184 init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid); 1185 init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq); 1186 init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0); 1187 init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); 1188 init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); 1189 init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); 1190 init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); 1191 init_cpu_ftr_reg(SYS_ID_AA64ISAR3_EL1, info->reg_id_aa64isar3); 1192 init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); 1193 init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); 1194 init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); 1195 init_cpu_ftr_reg(SYS_ID_AA64MMFR3_EL1, info->reg_id_aa64mmfr3); 1196 init_cpu_ftr_reg(SYS_ID_AA64MMFR4_EL1, info->reg_id_aa64mmfr4); 1197 init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0); 1198 init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1); 1199 init_cpu_ftr_reg(SYS_ID_AA64PFR2_EL1, info->reg_id_aa64pfr2); 1200 init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0); 1201 init_cpu_ftr_reg(SYS_ID_AA64SMFR0_EL1, info->reg_id_aa64smfr0); 1202 init_cpu_ftr_reg(SYS_ID_AA64FPFR0_EL1, info->reg_id_aa64fpfr0); 1203 1204 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) 1205 init_32bit_cpu_features(&info->aarch32); 1206 1207 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1208 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1209 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1210 1211 vec_init_vq_map(ARM64_VEC_SVE); 1212 1213 cpacr_restore(cpacr); 1214 } 1215 1216 if (IS_ENABLED(CONFIG_ARM64_SME) && 1217 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1218 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1219 1220 vec_init_vq_map(ARM64_VEC_SME); 1221 1222 cpacr_restore(cpacr); 1223 } 1224 1225 if (detect_ftr_has_mpam()) { 1226 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1227 init_cpu_ftr_reg(SYS_MPAMIDR_EL1, info->reg_mpamidr); 1228 } 1229 1230 if (id_aa64pfr1_mte(info->reg_id_aa64pfr1)) 1231 init_cpu_ftr_reg(SYS_GMID_EL1, info->reg_gmid); 1232 } 1233 1234 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new) 1235 { 1236 const struct arm64_ftr_bits *ftrp; 1237 1238 for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) { 1239 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val); 1240 s64 ftr_new = arm64_ftr_value(ftrp, new); 1241 1242 if (ftr_cur == ftr_new) 1243 continue; 1244 /* Find a safe value */ 1245 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur); 1246 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new); 1247 } 1248 1249 } 1250 1251 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot) 1252 { 1253 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1254 1255 if (!regp) 1256 return 0; 1257 1258 update_cpu_ftr_reg(regp, val); 1259 if ((boot & regp->strict_mask) == (val & regp->strict_mask)) 1260 return 0; 1261 pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n", 1262 regp->name, boot, cpu, val); 1263 return 1; 1264 } 1265 1266 static void relax_cpu_ftr_reg(u32 sys_id, int field) 1267 { 1268 const struct arm64_ftr_bits *ftrp; 1269 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id); 1270 1271 if (!regp) 1272 return; 1273 1274 for (ftrp = regp->ftr_bits; ftrp->width; ftrp++) { 1275 if (ftrp->shift == field) { 1276 regp->strict_mask &= ~arm64_ftr_mask(ftrp); 1277 break; 1278 } 1279 } 1280 1281 /* Bogus field? */ 1282 WARN_ON(!ftrp->width); 1283 } 1284 1285 static void lazy_init_32bit_cpu_features(struct cpuinfo_arm64 *info, 1286 struct cpuinfo_arm64 *boot) 1287 { 1288 static bool boot_cpu_32bit_regs_overridden = false; 1289 1290 if (!allow_mismatched_32bit_el0 || boot_cpu_32bit_regs_overridden) 1291 return; 1292 1293 if (id_aa64pfr0_32bit_el0(boot->reg_id_aa64pfr0)) 1294 return; 1295 1296 boot->aarch32 = info->aarch32; 1297 init_32bit_cpu_features(&boot->aarch32); 1298 boot_cpu_32bit_regs_overridden = true; 1299 } 1300 1301 static int update_32bit_cpu_features(int cpu, struct cpuinfo_32bit *info, 1302 struct cpuinfo_32bit *boot) 1303 { 1304 int taint = 0; 1305 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 1306 1307 /* 1308 * If we don't have AArch32 at EL1, then relax the strictness of 1309 * EL1-dependent register fields to avoid spurious sanity check fails. 1310 */ 1311 if (!id_aa64pfr0_32bit_el1(pfr0)) { 1312 relax_cpu_ftr_reg(SYS_ID_ISAR4_EL1, ID_ISAR4_EL1_SMC_SHIFT); 1313 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virt_frac_SHIFT); 1314 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Sec_frac_SHIFT); 1315 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Virtualization_SHIFT); 1316 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_Security_SHIFT); 1317 relax_cpu_ftr_reg(SYS_ID_PFR1_EL1, ID_PFR1_EL1_ProgMod_SHIFT); 1318 } 1319 1320 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu, 1321 info->reg_id_dfr0, boot->reg_id_dfr0); 1322 taint |= check_update_ftr_reg(SYS_ID_DFR1_EL1, cpu, 1323 info->reg_id_dfr1, boot->reg_id_dfr1); 1324 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu, 1325 info->reg_id_isar0, boot->reg_id_isar0); 1326 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu, 1327 info->reg_id_isar1, boot->reg_id_isar1); 1328 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu, 1329 info->reg_id_isar2, boot->reg_id_isar2); 1330 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu, 1331 info->reg_id_isar3, boot->reg_id_isar3); 1332 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu, 1333 info->reg_id_isar4, boot->reg_id_isar4); 1334 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu, 1335 info->reg_id_isar5, boot->reg_id_isar5); 1336 taint |= check_update_ftr_reg(SYS_ID_ISAR6_EL1, cpu, 1337 info->reg_id_isar6, boot->reg_id_isar6); 1338 1339 /* 1340 * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and 1341 * ACTLR formats could differ across CPUs and therefore would have to 1342 * be trapped for virtualization anyway. 1343 */ 1344 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu, 1345 info->reg_id_mmfr0, boot->reg_id_mmfr0); 1346 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu, 1347 info->reg_id_mmfr1, boot->reg_id_mmfr1); 1348 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu, 1349 info->reg_id_mmfr2, boot->reg_id_mmfr2); 1350 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu, 1351 info->reg_id_mmfr3, boot->reg_id_mmfr3); 1352 taint |= check_update_ftr_reg(SYS_ID_MMFR4_EL1, cpu, 1353 info->reg_id_mmfr4, boot->reg_id_mmfr4); 1354 taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu, 1355 info->reg_id_mmfr5, boot->reg_id_mmfr5); 1356 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu, 1357 info->reg_id_pfr0, boot->reg_id_pfr0); 1358 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu, 1359 info->reg_id_pfr1, boot->reg_id_pfr1); 1360 taint |= check_update_ftr_reg(SYS_ID_PFR2_EL1, cpu, 1361 info->reg_id_pfr2, boot->reg_id_pfr2); 1362 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu, 1363 info->reg_mvfr0, boot->reg_mvfr0); 1364 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu, 1365 info->reg_mvfr1, boot->reg_mvfr1); 1366 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu, 1367 info->reg_mvfr2, boot->reg_mvfr2); 1368 1369 return taint; 1370 } 1371 1372 /* 1373 * Update system wide CPU feature registers with the values from a 1374 * non-boot CPU. Also performs SANITY checks to make sure that there 1375 * aren't any insane variations from that of the boot CPU. 1376 */ 1377 void update_cpu_features(int cpu, 1378 struct cpuinfo_arm64 *info, 1379 struct cpuinfo_arm64 *boot) 1380 { 1381 int taint = 0; 1382 1383 /* 1384 * The kernel can handle differing I-cache policies, but otherwise 1385 * caches should look identical. Userspace JITs will make use of 1386 * *minLine. 1387 */ 1388 taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu, 1389 info->reg_ctr, boot->reg_ctr); 1390 1391 /* 1392 * Userspace may perform DC ZVA instructions. Mismatched block sizes 1393 * could result in too much or too little memory being zeroed if a 1394 * process is preempted and migrated between CPUs. 1395 */ 1396 taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu, 1397 info->reg_dczid, boot->reg_dczid); 1398 1399 /* If different, timekeeping will be broken (especially with KVM) */ 1400 taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu, 1401 info->reg_cntfrq, boot->reg_cntfrq); 1402 1403 /* 1404 * The kernel uses self-hosted debug features and expects CPUs to 1405 * support identical debug features. We presently need CTX_CMPs, WRPs, 1406 * and BRPs to be identical. 1407 * ID_AA64DFR1 is currently RES0. 1408 */ 1409 taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu, 1410 info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0); 1411 taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu, 1412 info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1); 1413 /* 1414 * Even in big.LITTLE, processors should be identical instruction-set 1415 * wise. 1416 */ 1417 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu, 1418 info->reg_id_aa64isar0, boot->reg_id_aa64isar0); 1419 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, 1420 info->reg_id_aa64isar1, boot->reg_id_aa64isar1); 1421 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, 1422 info->reg_id_aa64isar2, boot->reg_id_aa64isar2); 1423 taint |= check_update_ftr_reg(SYS_ID_AA64ISAR3_EL1, cpu, 1424 info->reg_id_aa64isar3, boot->reg_id_aa64isar3); 1425 1426 /* 1427 * Differing PARange support is fine as long as all peripherals and 1428 * memory are mapped within the minimum PARange of all CPUs. 1429 * Linux should not care about secure memory. 1430 */ 1431 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu, 1432 info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0); 1433 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu, 1434 info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1); 1435 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu, 1436 info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2); 1437 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR3_EL1, cpu, 1438 info->reg_id_aa64mmfr3, boot->reg_id_aa64mmfr3); 1439 taint |= check_update_ftr_reg(SYS_ID_AA64MMFR4_EL1, cpu, 1440 info->reg_id_aa64mmfr4, boot->reg_id_aa64mmfr4); 1441 1442 taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu, 1443 info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0); 1444 taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu, 1445 info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1); 1446 taint |= check_update_ftr_reg(SYS_ID_AA64PFR2_EL1, cpu, 1447 info->reg_id_aa64pfr2, boot->reg_id_aa64pfr2); 1448 1449 taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu, 1450 info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0); 1451 1452 taint |= check_update_ftr_reg(SYS_ID_AA64SMFR0_EL1, cpu, 1453 info->reg_id_aa64smfr0, boot->reg_id_aa64smfr0); 1454 1455 taint |= check_update_ftr_reg(SYS_ID_AA64FPFR0_EL1, cpu, 1456 info->reg_id_aa64fpfr0, boot->reg_id_aa64fpfr0); 1457 1458 /* Probe vector lengths */ 1459 if (IS_ENABLED(CONFIG_ARM64_SVE) && 1460 id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1))) { 1461 if (!system_capabilities_finalized()) { 1462 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 1463 1464 vec_update_vq_map(ARM64_VEC_SVE); 1465 1466 cpacr_restore(cpacr); 1467 } 1468 } 1469 1470 if (IS_ENABLED(CONFIG_ARM64_SME) && 1471 id_aa64pfr1_sme(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) { 1472 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 1473 1474 /* Probe vector lengths */ 1475 if (!system_capabilities_finalized()) 1476 vec_update_vq_map(ARM64_VEC_SME); 1477 1478 cpacr_restore(cpacr); 1479 } 1480 1481 if (detect_ftr_has_mpam()) { 1482 info->reg_mpamidr = read_cpuid(MPAMIDR_EL1); 1483 taint |= check_update_ftr_reg(SYS_MPAMIDR_EL1, cpu, 1484 info->reg_mpamidr, boot->reg_mpamidr); 1485 } 1486 1487 /* 1488 * The kernel uses the LDGM/STGM instructions and the number of tags 1489 * they read/write depends on the GMID_EL1.BS field. Check that the 1490 * value is the same on all CPUs. 1491 */ 1492 if (IS_ENABLED(CONFIG_ARM64_MTE) && 1493 id_aa64pfr1_mte(info->reg_id_aa64pfr1)) { 1494 taint |= check_update_ftr_reg(SYS_GMID_EL1, cpu, 1495 info->reg_gmid, boot->reg_gmid); 1496 } 1497 1498 /* 1499 * If we don't have AArch32 at all then skip the checks entirely 1500 * as the register values may be UNKNOWN and we're not going to be 1501 * using them for anything. 1502 * 1503 * This relies on a sanitised view of the AArch64 ID registers 1504 * (e.g. SYS_ID_AA64PFR0_EL1), so we call it last. 1505 */ 1506 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 1507 lazy_init_32bit_cpu_features(info, boot); 1508 taint |= update_32bit_cpu_features(cpu, &info->aarch32, 1509 &boot->aarch32); 1510 } 1511 1512 /* 1513 * Mismatched CPU features are a recipe for disaster. Don't even 1514 * pretend to support them. 1515 */ 1516 if (taint) { 1517 pr_warn_once("Unsupported CPU feature variation detected.\n"); 1518 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); 1519 } 1520 } 1521 1522 u64 read_sanitised_ftr_reg(u32 id) 1523 { 1524 struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id); 1525 1526 if (!regp) 1527 return 0; 1528 return regp->sys_val; 1529 } 1530 EXPORT_SYMBOL_GPL(read_sanitised_ftr_reg); 1531 1532 #define read_sysreg_case(r) \ 1533 case r: val = read_sysreg_s(r); break; 1534 1535 /* 1536 * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated. 1537 * Read the system register on the current CPU 1538 */ 1539 u64 __read_sysreg_by_encoding(u32 sys_id) 1540 { 1541 struct arm64_ftr_reg *regp; 1542 u64 val; 1543 1544 switch (sys_id) { 1545 read_sysreg_case(SYS_ID_PFR0_EL1); 1546 read_sysreg_case(SYS_ID_PFR1_EL1); 1547 read_sysreg_case(SYS_ID_PFR2_EL1); 1548 read_sysreg_case(SYS_ID_DFR0_EL1); 1549 read_sysreg_case(SYS_ID_DFR1_EL1); 1550 read_sysreg_case(SYS_ID_MMFR0_EL1); 1551 read_sysreg_case(SYS_ID_MMFR1_EL1); 1552 read_sysreg_case(SYS_ID_MMFR2_EL1); 1553 read_sysreg_case(SYS_ID_MMFR3_EL1); 1554 read_sysreg_case(SYS_ID_MMFR4_EL1); 1555 read_sysreg_case(SYS_ID_MMFR5_EL1); 1556 read_sysreg_case(SYS_ID_ISAR0_EL1); 1557 read_sysreg_case(SYS_ID_ISAR1_EL1); 1558 read_sysreg_case(SYS_ID_ISAR2_EL1); 1559 read_sysreg_case(SYS_ID_ISAR3_EL1); 1560 read_sysreg_case(SYS_ID_ISAR4_EL1); 1561 read_sysreg_case(SYS_ID_ISAR5_EL1); 1562 read_sysreg_case(SYS_ID_ISAR6_EL1); 1563 read_sysreg_case(SYS_MVFR0_EL1); 1564 read_sysreg_case(SYS_MVFR1_EL1); 1565 read_sysreg_case(SYS_MVFR2_EL1); 1566 1567 read_sysreg_case(SYS_ID_AA64PFR0_EL1); 1568 read_sysreg_case(SYS_ID_AA64PFR1_EL1); 1569 read_sysreg_case(SYS_ID_AA64PFR2_EL1); 1570 read_sysreg_case(SYS_ID_AA64ZFR0_EL1); 1571 read_sysreg_case(SYS_ID_AA64SMFR0_EL1); 1572 read_sysreg_case(SYS_ID_AA64FPFR0_EL1); 1573 read_sysreg_case(SYS_ID_AA64DFR0_EL1); 1574 read_sysreg_case(SYS_ID_AA64DFR1_EL1); 1575 read_sysreg_case(SYS_ID_AA64MMFR0_EL1); 1576 read_sysreg_case(SYS_ID_AA64MMFR1_EL1); 1577 read_sysreg_case(SYS_ID_AA64MMFR2_EL1); 1578 read_sysreg_case(SYS_ID_AA64MMFR3_EL1); 1579 read_sysreg_case(SYS_ID_AA64MMFR4_EL1); 1580 read_sysreg_case(SYS_ID_AA64ISAR0_EL1); 1581 read_sysreg_case(SYS_ID_AA64ISAR1_EL1); 1582 read_sysreg_case(SYS_ID_AA64ISAR2_EL1); 1583 read_sysreg_case(SYS_ID_AA64ISAR3_EL1); 1584 1585 read_sysreg_case(SYS_CNTFRQ_EL0); 1586 read_sysreg_case(SYS_CTR_EL0); 1587 read_sysreg_case(SYS_DCZID_EL0); 1588 1589 default: 1590 BUG(); 1591 return 0; 1592 } 1593 1594 regp = get_arm64_ftr_reg(sys_id); 1595 if (regp) { 1596 val &= ~regp->override->mask; 1597 val |= (regp->override->val & regp->override->mask); 1598 } 1599 1600 return val; 1601 } 1602 1603 #include <linux/irqchip/arm-gic-v3.h> 1604 1605 static bool 1606 has_always(const struct arm64_cpu_capabilities *entry, int scope) 1607 { 1608 return true; 1609 } 1610 1611 static bool 1612 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) 1613 { 1614 int val, min, max; 1615 u64 tmp; 1616 1617 val = cpuid_feature_extract_field_width(reg, entry->field_pos, 1618 entry->field_width, 1619 entry->sign); 1620 1621 tmp = entry->min_field_value; 1622 tmp <<= entry->field_pos; 1623 1624 min = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1625 entry->field_width, 1626 entry->sign); 1627 1628 tmp = entry->max_field_value; 1629 tmp <<= entry->field_pos; 1630 1631 max = cpuid_feature_extract_field_width(tmp, entry->field_pos, 1632 entry->field_width, 1633 entry->sign); 1634 1635 return val >= min && val <= max; 1636 } 1637 1638 static u64 1639 read_scoped_sysreg(const struct arm64_cpu_capabilities *entry, int scope) 1640 { 1641 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 1642 if (scope == SCOPE_SYSTEM) 1643 return read_sanitised_ftr_reg(entry->sys_reg); 1644 else 1645 return __read_sysreg_by_encoding(entry->sys_reg); 1646 } 1647 1648 static bool 1649 has_user_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1650 { 1651 int mask; 1652 struct arm64_ftr_reg *regp; 1653 u64 val = read_scoped_sysreg(entry, scope); 1654 1655 regp = get_arm64_ftr_reg(entry->sys_reg); 1656 if (!regp) 1657 return false; 1658 1659 mask = cpuid_feature_extract_unsigned_field_width(regp->user_mask, 1660 entry->field_pos, 1661 entry->field_width); 1662 if (!mask) 1663 return false; 1664 1665 return feature_matches(val, entry); 1666 } 1667 1668 static bool 1669 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) 1670 { 1671 u64 val = read_scoped_sysreg(entry, scope); 1672 return feature_matches(val, entry); 1673 } 1674 1675 const struct cpumask *system_32bit_el0_cpumask(void) 1676 { 1677 if (!system_supports_32bit_el0()) 1678 return cpu_none_mask; 1679 1680 if (static_branch_unlikely(&arm64_mismatched_32bit_el0)) 1681 return cpu_32bit_el0_mask; 1682 1683 return cpu_possible_mask; 1684 } 1685 1686 const struct cpumask *task_cpu_fallback_mask(struct task_struct *p) 1687 { 1688 return __task_cpu_possible_mask(p, housekeeping_cpumask(HK_TYPE_DOMAIN)); 1689 } 1690 1691 static int __init parse_32bit_el0_param(char *str) 1692 { 1693 allow_mismatched_32bit_el0 = true; 1694 return 0; 1695 } 1696 early_param("allow_mismatched_32bit_el0", parse_32bit_el0_param); 1697 1698 static ssize_t aarch32_el0_show(struct device *dev, 1699 struct device_attribute *attr, char *buf) 1700 { 1701 const struct cpumask *mask = system_32bit_el0_cpumask(); 1702 1703 return sysfs_emit(buf, "%*pbl\n", cpumask_pr_args(mask)); 1704 } 1705 static const DEVICE_ATTR_RO(aarch32_el0); 1706 1707 static int __init aarch32_el0_sysfs_init(void) 1708 { 1709 struct device *dev_root; 1710 int ret = 0; 1711 1712 if (!allow_mismatched_32bit_el0) 1713 return 0; 1714 1715 dev_root = bus_get_dev_root(&cpu_subsys); 1716 if (dev_root) { 1717 ret = device_create_file(dev_root, &dev_attr_aarch32_el0); 1718 put_device(dev_root); 1719 } 1720 return ret; 1721 } 1722 device_initcall(aarch32_el0_sysfs_init); 1723 1724 static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) 1725 { 1726 if (!has_cpuid_feature(entry, scope)) 1727 return allow_mismatched_32bit_el0; 1728 1729 if (scope == SCOPE_SYSTEM) 1730 pr_info("detected: 32-bit EL0 Support\n"); 1731 1732 return true; 1733 } 1734 1735 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) 1736 { 1737 bool has_sre; 1738 1739 if (!has_cpuid_feature(entry, scope)) 1740 return false; 1741 1742 has_sre = gic_enable_sre(); 1743 if (!has_sre) 1744 pr_warn_once("%s present but disabled by higher exception level\n", 1745 entry->desc); 1746 1747 return has_sre; 1748 } 1749 1750 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry, 1751 int scope) 1752 { 1753 u64 ctr; 1754 1755 if (scope == SCOPE_SYSTEM) 1756 ctr = arm64_ftr_reg_ctrel0.sys_val; 1757 else 1758 ctr = read_cpuid_effective_cachetype(); 1759 1760 return ctr & BIT(CTR_EL0_IDC_SHIFT); 1761 } 1762 1763 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused) 1764 { 1765 /* 1766 * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively 1767 * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses 1768 * to the CTR_EL0 on this CPU and emulate it with the real/safe 1769 * value. 1770 */ 1771 if (!(read_cpuid_cachetype() & BIT(CTR_EL0_IDC_SHIFT))) 1772 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0); 1773 } 1774 1775 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry, 1776 int scope) 1777 { 1778 u64 ctr; 1779 1780 if (scope == SCOPE_SYSTEM) 1781 ctr = arm64_ftr_reg_ctrel0.sys_val; 1782 else 1783 ctr = read_cpuid_cachetype(); 1784 1785 return ctr & BIT(CTR_EL0_DIC_SHIFT); 1786 } 1787 1788 static bool __maybe_unused 1789 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope) 1790 { 1791 /* 1792 * Kdump isn't guaranteed to power-off all secondary CPUs, CNP 1793 * may share TLB entries with a CPU stuck in the crashed 1794 * kernel. 1795 */ 1796 if (is_kdump_kernel()) 1797 return false; 1798 1799 if (cpus_have_cap(ARM64_WORKAROUND_DISABLE_CNP)) 1800 return false; 1801 1802 return has_cpuid_feature(entry, scope); 1803 } 1804 1805 static bool __meltdown_safe = true; 1806 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */ 1807 1808 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry, 1809 int scope) 1810 { 1811 /* List of CPUs that are not vulnerable and don't need KPTI */ 1812 static const struct midr_range kpti_safe_list[] = { 1813 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2), 1814 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN), 1815 MIDR_ALL_VERSIONS(MIDR_BRAHMA_B53), 1816 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35), 1817 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53), 1818 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1819 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), 1820 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), 1821 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), 1822 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110), 1823 MIDR_ALL_VERSIONS(MIDR_NVIDIA_CARMEL), 1824 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_GOLD), 1825 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_2XX_SILVER), 1826 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_3XX_SILVER), 1827 MIDR_ALL_VERSIONS(MIDR_QCOM_KRYO_4XX_SILVER), 1828 { /* sentinel */ } 1829 }; 1830 char const *str = "kpti command line option"; 1831 bool meltdown_safe; 1832 1833 meltdown_safe = is_midr_in_range_list(kpti_safe_list); 1834 1835 /* Defer to CPU feature registers */ 1836 if (has_cpuid_feature(entry, scope)) 1837 meltdown_safe = true; 1838 1839 if (!meltdown_safe) 1840 __meltdown_safe = false; 1841 1842 /* 1843 * For reasons that aren't entirely clear, enabling KPTI on Cavium 1844 * ThunderX leads to apparent I-cache corruption of kernel text, which 1845 * ends as well as you might imagine. Don't even try. We cannot rely 1846 * on the cpus_have_*cap() helpers here to detect the CPU erratum 1847 * because cpucap detection order may change. However, since we know 1848 * affected CPUs are always in a homogeneous configuration, it is 1849 * safe to rely on this_cpu_has_cap() here. 1850 */ 1851 if (this_cpu_has_cap(ARM64_WORKAROUND_CAVIUM_27456)) { 1852 str = "ARM64_WORKAROUND_CAVIUM_27456"; 1853 __kpti_forced = -1; 1854 } 1855 1856 /* Useful for KASLR robustness */ 1857 if (kaslr_enabled() && kaslr_requires_kpti()) { 1858 if (!__kpti_forced) { 1859 str = "KASLR"; 1860 __kpti_forced = 1; 1861 } 1862 } 1863 1864 if (cpu_mitigations_off() && !__kpti_forced) { 1865 str = "mitigations=off"; 1866 __kpti_forced = -1; 1867 } 1868 1869 if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) { 1870 pr_info_once("kernel page table isolation disabled by kernel configuration\n"); 1871 return false; 1872 } 1873 1874 /* Forced? */ 1875 if (__kpti_forced) { 1876 pr_info_once("kernel page table isolation forced %s by %s\n", 1877 __kpti_forced > 0 ? "ON" : "OFF", str); 1878 return __kpti_forced > 0; 1879 } 1880 1881 return !meltdown_safe; 1882 } 1883 1884 static bool has_nv1(const struct arm64_cpu_capabilities *entry, int scope) 1885 { 1886 /* 1887 * Although the Apple M2 family appears to support NV1, the 1888 * PTW barfs on the nVHE EL2 S1 page table format. Pretend 1889 * that it doesn't support NV1 at all. 1890 */ 1891 static const struct midr_range nv1_ni_list[] = { 1892 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 1893 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 1894 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 1895 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 1896 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 1897 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 1898 {} 1899 }; 1900 1901 return (__system_matches_cap(ARM64_HAS_NESTED_VIRT) && 1902 !(has_cpuid_feature(entry, scope) || 1903 is_midr_in_range_list(nv1_ni_list))); 1904 } 1905 1906 #if defined(ID_AA64MMFR0_EL1_TGRAN_LPA2) && defined(ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2) 1907 static bool has_lpa2_at_stage1(u64 mmfr0) 1908 { 1909 unsigned int tgran; 1910 1911 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1912 ID_AA64MMFR0_EL1_TGRAN_SHIFT); 1913 return tgran == ID_AA64MMFR0_EL1_TGRAN_LPA2; 1914 } 1915 1916 static bool has_lpa2_at_stage2(u64 mmfr0) 1917 { 1918 unsigned int tgran; 1919 1920 tgran = cpuid_feature_extract_unsigned_field(mmfr0, 1921 ID_AA64MMFR0_EL1_TGRAN_2_SHIFT); 1922 return tgran == ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2; 1923 } 1924 1925 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1926 { 1927 u64 mmfr0; 1928 1929 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 1930 return has_lpa2_at_stage1(mmfr0) && has_lpa2_at_stage2(mmfr0); 1931 } 1932 #else 1933 static bool has_lpa2(const struct arm64_cpu_capabilities *entry, int scope) 1934 { 1935 return false; 1936 } 1937 #endif 1938 1939 #ifdef CONFIG_HW_PERF_EVENTS 1940 static bool has_pmuv3(const struct arm64_cpu_capabilities *entry, int scope) 1941 { 1942 u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); 1943 unsigned int pmuver; 1944 1945 pmuver = cpuid_feature_extract_unsigned_field(dfr0, 1946 ID_AA64DFR0_EL1_PMUVer_SHIFT); 1947 1948 return pmuv3_implemented(pmuver); 1949 } 1950 #endif 1951 1952 static void cpu_enable_kpti(struct arm64_cpu_capabilities const *cap) 1953 { 1954 if (__this_cpu_read(this_cpu_vector) == vectors) { 1955 const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); 1956 1957 __this_cpu_write(this_cpu_vector, v); 1958 } 1959 1960 } 1961 1962 static int __init parse_kpti(char *str) 1963 { 1964 bool enabled; 1965 int ret = kstrtobool(str, &enabled); 1966 1967 if (ret) 1968 return ret; 1969 1970 __kpti_forced = enabled ? 1 : -1; 1971 return 0; 1972 } 1973 early_param("kpti", parse_kpti); 1974 1975 #ifdef CONFIG_ARM64_HW_AFDBM 1976 static struct cpumask dbm_cpus __read_mostly; 1977 1978 static inline void __cpu_enable_hw_dbm(void) 1979 { 1980 u64 tcr = read_sysreg(tcr_el1) | TCR_EL1_HD; 1981 1982 write_sysreg(tcr, tcr_el1); 1983 isb(); 1984 local_flush_tlb_all(); 1985 } 1986 1987 static bool cpu_has_broken_dbm(void) 1988 { 1989 /* List of CPUs which have broken DBM support. */ 1990 static const struct midr_range cpus[] = { 1991 #ifdef CONFIG_ARM64_ERRATUM_1024718 1992 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55), 1993 /* Kryo4xx Silver (rdpe => r1p0) */ 1994 MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe), 1995 #endif 1996 #ifdef CONFIG_ARM64_ERRATUM_2051678 1997 MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2), 1998 #endif 1999 {}, 2000 }; 2001 2002 return is_midr_in_range_list(cpus); 2003 } 2004 2005 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) 2006 { 2007 return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) && 2008 !cpu_has_broken_dbm(); 2009 } 2010 2011 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) 2012 { 2013 if (cpu_can_use_dbm(cap)) { 2014 __cpu_enable_hw_dbm(); 2015 cpumask_set_cpu(smp_processor_id(), &dbm_cpus); 2016 } 2017 } 2018 2019 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, 2020 int __unused) 2021 { 2022 /* 2023 * DBM is a non-conflicting feature. i.e, the kernel can safely 2024 * run a mix of CPUs with and without the feature. So, we 2025 * unconditionally enable the capability to allow any late CPU 2026 * to use the feature. We only enable the control bits on the 2027 * CPU, if it is supported. 2028 */ 2029 2030 return true; 2031 } 2032 2033 #endif 2034 2035 #ifdef CONFIG_ARM64_AMU_EXTN 2036 2037 /* 2038 * The "amu_cpus" cpumask only signals that the CPU implementation for the 2039 * flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide 2040 * information regarding all the events that it supports. When a CPU bit is 2041 * set in the cpumask, the user of this feature can only rely on the presence 2042 * of the 4 fixed counters for that CPU. But this does not guarantee that the 2043 * counters are enabled or access to these counters is enabled by code 2044 * executed at higher exception levels (firmware). 2045 */ 2046 static struct cpumask amu_cpus __read_mostly; 2047 2048 bool cpu_has_amu_feat(int cpu) 2049 { 2050 return cpumask_test_cpu(cpu, &amu_cpus); 2051 } 2052 2053 int get_cpu_with_amu_feat(void) 2054 { 2055 return cpumask_any(&amu_cpus); 2056 } 2057 2058 static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) 2059 { 2060 if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { 2061 cpumask_set_cpu(smp_processor_id(), &amu_cpus); 2062 2063 /* 0 reference values signal broken/disabled counters */ 2064 if (!this_cpu_has_cap(ARM64_WORKAROUND_2457168)) 2065 update_freq_counters_refs(); 2066 } 2067 } 2068 2069 static bool has_amu(const struct arm64_cpu_capabilities *cap, 2070 int __unused) 2071 { 2072 /* 2073 * The AMU extension is a non-conflicting feature: the kernel can 2074 * safely run a mix of CPUs with and without support for the 2075 * activity monitors extension. Therefore, unconditionally enable 2076 * the capability to allow any late CPU to use the feature. 2077 * 2078 * With this feature unconditionally enabled, the cpu_enable 2079 * function will be called for all CPUs that match the criteria, 2080 * including secondary and hotplugged, marking this feature as 2081 * present on that respective CPU. The enable function will also 2082 * print a detection message. 2083 */ 2084 2085 return true; 2086 } 2087 #else 2088 int get_cpu_with_amu_feat(void) 2089 { 2090 return nr_cpu_ids; 2091 } 2092 #endif 2093 2094 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused) 2095 { 2096 return is_kernel_in_hyp_mode(); 2097 } 2098 2099 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused) 2100 { 2101 /* 2102 * Copy register values that aren't redirected by hardware. 2103 * 2104 * Before code patching, we only set tpidr_el1, all CPUs need to copy 2105 * this value to tpidr_el2 before we patch the code. Once we've done 2106 * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to 2107 * do anything here. 2108 */ 2109 if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN)) 2110 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2); 2111 } 2112 2113 static bool has_nested_virt_support(const struct arm64_cpu_capabilities *cap, 2114 int scope) 2115 { 2116 if (kvm_get_mode() != KVM_MODE_NV) 2117 return false; 2118 2119 if (!cpucap_multi_entry_cap_matches(cap, scope)) { 2120 pr_warn("unavailable: %s\n", cap->desc); 2121 return false; 2122 } 2123 2124 return true; 2125 } 2126 2127 static bool hvhe_possible(const struct arm64_cpu_capabilities *entry, 2128 int __unused) 2129 { 2130 return arm64_test_sw_feature_override(ARM64_SW_FEATURE_OVERRIDE_HVHE); 2131 } 2132 2133 bool cpu_supports_bbml2_noabort(void) 2134 { 2135 /* 2136 * We want to allow usage of BBML2 in as wide a range of kernel contexts 2137 * as possible. This list is therefore an allow-list of known-good 2138 * implementations that both support BBML2 and additionally, fulfill the 2139 * extra constraint of never generating TLB conflict aborts when using 2140 * the relaxed BBML2 semantics (such aborts make use of BBML2 in certain 2141 * kernel contexts difficult to prove safe against recursive aborts). 2142 * 2143 * Note that implementations can only be considered "known-good" if their 2144 * implementors attest to the fact that the implementation never raises 2145 * TLB conflict aborts for BBML2 mapping granularity changes. 2146 */ 2147 static const struct midr_range supports_bbml2_noabort_list[] = { 2148 MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf), 2149 MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf), 2150 MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf), 2151 MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS), 2152 MIDR_ALL_VERSIONS(MIDR_AMPERE1), 2153 MIDR_ALL_VERSIONS(MIDR_AMPERE1A), 2154 {} 2155 }; 2156 2157 /* Does our cpu guarantee to never raise TLB conflict aborts? */ 2158 if (!is_midr_in_range_list(supports_bbml2_noabort_list)) 2159 return false; 2160 2161 /* 2162 * We currently ignore the ID_AA64MMFR2_EL1 register, and only care 2163 * about whether the MIDR check passes. 2164 */ 2165 2166 return true; 2167 } 2168 2169 static bool has_bbml2_noabort(const struct arm64_cpu_capabilities *caps, int scope) 2170 { 2171 return cpu_supports_bbml2_noabort(); 2172 } 2173 2174 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) 2175 { 2176 /* 2177 * We modify PSTATE. This won't work from irq context as the PSTATE 2178 * is discarded once we return from the exception. 2179 */ 2180 WARN_ON_ONCE(in_interrupt()); 2181 2182 sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0); 2183 set_pstate_pan(1); 2184 } 2185 2186 #ifdef CONFIG_ARM64_RAS_EXTN 2187 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused) 2188 { 2189 /* Firmware may have left a deferred SError in this register. */ 2190 write_sysreg_s(0, SYS_DISR_EL1); 2191 } 2192 static bool has_rasv1p1(const struct arm64_cpu_capabilities *__unused, int scope) 2193 { 2194 const struct arm64_cpu_capabilities rasv1p1_caps[] = { 2195 { 2196 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, V1P1) 2197 }, 2198 { 2199 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2200 }, 2201 { 2202 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, RAS_frac, RASv1p1) 2203 }, 2204 }; 2205 2206 return (has_cpuid_feature(&rasv1p1_caps[0], scope) || 2207 (has_cpuid_feature(&rasv1p1_caps[1], scope) && 2208 has_cpuid_feature(&rasv1p1_caps[2], scope))); 2209 } 2210 #endif /* CONFIG_ARM64_RAS_EXTN */ 2211 2212 #ifdef CONFIG_ARM64_PTR_AUTH 2213 static bool has_address_auth_cpucap(const struct arm64_cpu_capabilities *entry, int scope) 2214 { 2215 int boot_val, sec_val; 2216 2217 /* We don't expect to be called with SCOPE_SYSTEM */ 2218 WARN_ON(scope == SCOPE_SYSTEM); 2219 /* 2220 * The ptr-auth feature levels are not intercompatible with lower 2221 * levels. Hence we must match ptr-auth feature level of the secondary 2222 * CPUs with that of the boot CPU. The level of boot cpu is fetched 2223 * from the sanitised register whereas direct register read is done for 2224 * the secondary CPUs. 2225 * The sanitised feature state is guaranteed to match that of the 2226 * boot CPU as a mismatched secondary CPU is parked before it gets 2227 * a chance to update the state, with the capability. 2228 */ 2229 boot_val = cpuid_feature_extract_field(read_sanitised_ftr_reg(entry->sys_reg), 2230 entry->field_pos, entry->sign); 2231 if (scope & SCOPE_BOOT_CPU) 2232 return boot_val >= entry->min_field_value; 2233 /* Now check for the secondary CPUs with SCOPE_LOCAL_CPU scope */ 2234 sec_val = cpuid_feature_extract_field(__read_sysreg_by_encoding(entry->sys_reg), 2235 entry->field_pos, entry->sign); 2236 return (sec_val >= entry->min_field_value) && (sec_val == boot_val); 2237 } 2238 2239 static bool has_address_auth_metacap(const struct arm64_cpu_capabilities *entry, 2240 int scope) 2241 { 2242 bool api = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_IMP_DEF], scope); 2243 bool apa = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5], scope); 2244 bool apa3 = has_address_auth_cpucap(cpucap_ptrs[ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3], scope); 2245 2246 return apa || apa3 || api; 2247 } 2248 2249 static bool has_generic_auth(const struct arm64_cpu_capabilities *entry, 2250 int __unused) 2251 { 2252 bool gpi = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF); 2253 bool gpa = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5); 2254 bool gpa3 = __system_matches_cap(ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3); 2255 2256 return gpa || gpa3 || gpi; 2257 } 2258 #endif /* CONFIG_ARM64_PTR_AUTH */ 2259 2260 #ifdef CONFIG_ARM64_E0PD 2261 static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) 2262 { 2263 if (this_cpu_has_cap(ARM64_HAS_E0PD)) 2264 sysreg_clear_set(tcr_el1, 0, TCR_EL1_E0PD1); 2265 } 2266 #endif /* CONFIG_ARM64_E0PD */ 2267 2268 static void cpu_enable_ls64(struct arm64_cpu_capabilities const *cap) 2269 { 2270 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnALS, SCTLR_EL1_EnALS); 2271 } 2272 2273 static void cpu_enable_ls64_v(struct arm64_cpu_capabilities const *cap) 2274 { 2275 sysreg_clear_set(sctlr_el1, SCTLR_EL1_EnASR, 0); 2276 } 2277 2278 #ifdef CONFIG_ARM64_PSEUDO_NMI 2279 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, 2280 int scope) 2281 { 2282 /* 2283 * ARM64_HAS_GICV3_CPUIF has a lower index, and is a boot CPU 2284 * feature, so will be detected earlier. 2285 */ 2286 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_MASKING <= ARM64_HAS_GICV3_CPUIF); 2287 if (!cpus_have_cap(ARM64_HAS_GICV3_CPUIF)) 2288 return false; 2289 2290 return enable_pseudo_nmi; 2291 } 2292 2293 static bool has_gic_prio_relaxed_sync(const struct arm64_cpu_capabilities *entry, 2294 int scope) 2295 { 2296 /* 2297 * If we're not using priority masking then we won't be poking PMR_EL1, 2298 * and there's no need to relax synchronization of writes to it, and 2299 * ICC_CTLR_EL1 might not be accessible and we must avoid reads from 2300 * that. 2301 * 2302 * ARM64_HAS_GIC_PRIO_MASKING has a lower index, and is a boot CPU 2303 * feature, so will be detected earlier. 2304 */ 2305 BUILD_BUG_ON(ARM64_HAS_GIC_PRIO_RELAXED_SYNC <= ARM64_HAS_GIC_PRIO_MASKING); 2306 if (!cpus_have_cap(ARM64_HAS_GIC_PRIO_MASKING)) 2307 return false; 2308 2309 /* 2310 * When Priority Mask Hint Enable (PMHE) == 0b0, PMR is not used as a 2311 * hint for interrupt distribution, a DSB is not necessary when 2312 * unmasking IRQs via PMR, and we can relax the barrier to a NOP. 2313 * 2314 * Linux itself doesn't use 1:N distribution, so has no need to 2315 * set PMHE. The only reason to have it set is if EL3 requires it 2316 * (and we can't change it). 2317 */ 2318 return (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK) == 0; 2319 } 2320 #endif 2321 2322 static bool can_trap_icv_dir_el1(const struct arm64_cpu_capabilities *entry, 2323 int scope) 2324 { 2325 static const struct midr_range has_vgic_v3[] = { 2326 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM), 2327 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM), 2328 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_PRO), 2329 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_PRO), 2330 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_ICESTORM_MAX), 2331 MIDR_ALL_VERSIONS(MIDR_APPLE_M1_FIRESTORM_MAX), 2332 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD), 2333 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE), 2334 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_PRO), 2335 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_PRO), 2336 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_BLIZZARD_MAX), 2337 MIDR_ALL_VERSIONS(MIDR_APPLE_M2_AVALANCHE_MAX), 2338 {}, 2339 }; 2340 struct arm_smccc_res res = {}; 2341 2342 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV3_CPUIF); 2343 BUILD_BUG_ON(ARM64_HAS_ICH_HCR_EL2_TDIR <= ARM64_HAS_GICV5_LEGACY); 2344 if (!is_hyp_mode_available()) 2345 return false; 2346 2347 if (this_cpu_has_cap(ARM64_HAS_GICV5_LEGACY)) 2348 return true; 2349 2350 if (!this_cpu_has_cap(ARM64_HAS_GICV3_CPUIF) && 2351 !is_midr_in_range_list(has_vgic_v3)) 2352 return false; 2353 2354 /* 2355 * pKVM prevents late onlining of CPUs. This means that whatever 2356 * state the capability is in after deprivilege cannot be affected 2357 * by a new CPU booting -- this is garanteed to be a CPU we have 2358 * already seen, and the cap is therefore unchanged. 2359 */ 2360 if (system_capabilities_finalized() && is_protected_kvm_enabled()) 2361 return cpus_have_final_cap(ARM64_HAS_ICH_HCR_EL2_TDIR); 2362 2363 if (is_kernel_in_hyp_mode()) 2364 res.a1 = read_sysreg_s(SYS_ICH_VTR_EL2); 2365 else 2366 arm_smccc_1_1_hvc(HVC_GET_ICH_VTR_EL2, &res); 2367 2368 if (res.a0 == HVC_STUB_ERR) 2369 return false; 2370 2371 return res.a1 & ICH_VTR_EL2_TDS; 2372 } 2373 2374 #ifdef CONFIG_ARM64_BTI 2375 static void bti_enable(const struct arm64_cpu_capabilities *__unused) 2376 { 2377 /* 2378 * Use of X16/X17 for tail-calls and trampolines that jump to 2379 * function entry points using BR is a requirement for 2380 * marking binaries with GNU_PROPERTY_AARCH64_FEATURE_1_BTI. 2381 * So, be strict and forbid other BRs using other registers to 2382 * jump onto a PACIxSP instruction: 2383 */ 2384 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_BT0 | SCTLR_EL1_BT1); 2385 isb(); 2386 } 2387 #endif /* CONFIG_ARM64_BTI */ 2388 2389 #ifdef CONFIG_ARM64_MTE 2390 static void cpu_enable_mte(struct arm64_cpu_capabilities const *cap) 2391 { 2392 static bool cleared_zero_page = false; 2393 2394 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ATA | SCTLR_EL1_ATA0); 2395 2396 mte_cpu_setup(); 2397 2398 /* 2399 * Clear the tags in the zero page. This needs to be done via the 2400 * linear map which has the Tagged attribute. Since this page is 2401 * always mapped as pte_special(), set_pte_at() will not attempt to 2402 * clear the tags or set PG_mte_tagged. 2403 */ 2404 if (!cleared_zero_page) { 2405 cleared_zero_page = true; 2406 mte_clear_page_tags(lm_alias(empty_zero_page)); 2407 } 2408 2409 kasan_init_hw_tags_cpu(); 2410 } 2411 #endif /* CONFIG_ARM64_MTE */ 2412 2413 static void user_feature_fixup(void) 2414 { 2415 if (cpus_have_cap(ARM64_WORKAROUND_2658417)) { 2416 struct arm64_ftr_reg *regp; 2417 2418 regp = get_arm64_ftr_reg(SYS_ID_AA64ISAR1_EL1); 2419 if (regp) 2420 regp->user_mask &= ~ID_AA64ISAR1_EL1_BF16_MASK; 2421 } 2422 2423 if (cpus_have_cap(ARM64_WORKAROUND_SPECULATIVE_SSBS)) { 2424 struct arm64_ftr_reg *regp; 2425 2426 regp = get_arm64_ftr_reg(SYS_ID_AA64PFR1_EL1); 2427 if (regp) 2428 regp->user_mask &= ~ID_AA64PFR1_EL1_SSBS_MASK; 2429 } 2430 } 2431 2432 static void elf_hwcap_fixup(void) 2433 { 2434 #ifdef CONFIG_COMPAT 2435 if (cpus_have_cap(ARM64_WORKAROUND_1742098)) 2436 compat_elf_hwcap2 &= ~COMPAT_HWCAP2_AES; 2437 #endif /* CONFIG_COMPAT */ 2438 } 2439 2440 #ifdef CONFIG_KVM 2441 static bool is_kvm_protected_mode(const struct arm64_cpu_capabilities *entry, int __unused) 2442 { 2443 return kvm_get_mode() == KVM_MODE_PROTECTED; 2444 } 2445 #endif /* CONFIG_KVM */ 2446 2447 static void cpu_trap_el0_impdef(const struct arm64_cpu_capabilities *__unused) 2448 { 2449 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_TIDCP); 2450 } 2451 2452 static void cpu_enable_dit(const struct arm64_cpu_capabilities *__unused) 2453 { 2454 set_pstate_dit(1); 2455 } 2456 2457 static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) 2458 { 2459 sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); 2460 } 2461 2462 #ifdef CONFIG_ARM64_POE 2463 static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) 2464 { 2465 sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1_E0POE); 2466 sysreg_clear_set(CPACR_EL1, 0, CPACR_EL1_E0POE); 2467 } 2468 #endif 2469 2470 #ifdef CONFIG_ARM64_GCS 2471 static void cpu_enable_gcs(const struct arm64_cpu_capabilities *__unused) 2472 { 2473 /* GCSPR_EL0 is always readable */ 2474 write_sysreg_s(GCSCRE0_EL1_nTR, SYS_GCSCRE0_EL1); 2475 } 2476 #endif 2477 2478 /* Internal helper functions to match cpu capability type */ 2479 static bool 2480 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 2481 { 2482 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 2483 } 2484 2485 static bool 2486 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 2487 { 2488 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 2489 } 2490 2491 static bool 2492 cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) 2493 { 2494 return !!(cap->type & ARM64_CPUCAP_PANIC_ON_CONFLICT); 2495 } 2496 2497 static bool 2498 test_has_mpam(const struct arm64_cpu_capabilities *entry, int scope) 2499 { 2500 if (!detect_ftr_has_mpam()) 2501 return false; 2502 2503 /* Check firmware actually enabled MPAM on this cpu. */ 2504 return (read_sysreg_s(SYS_MPAM1_EL1) & MPAM1_EL1_MPAMEN); 2505 } 2506 2507 static void 2508 cpu_enable_mpam(const struct arm64_cpu_capabilities *entry) 2509 { 2510 int cpu = smp_processor_id(); 2511 u64 regval = 0; 2512 2513 if (IS_ENABLED(CONFIG_ARM64_MPAM) && static_branch_likely(&mpam_enabled)) 2514 regval = READ_ONCE(per_cpu(arm64_mpam_current, cpu)); 2515 2516 write_sysreg_s(regval | MPAM1_EL1_MPAMEN, SYS_MPAM1_EL1); 2517 if (cpus_have_cap(ARM64_SME)) 2518 write_sysreg_s(regval & (MPAMSM_EL1_PARTID_D | MPAMSM_EL1_PMG_D), SYS_MPAMSM_EL1); 2519 isb(); 2520 2521 /* Synchronising the EL0 write is left until the ERET to EL0 */ 2522 write_sysreg_s(regval, SYS_MPAM0_EL1); 2523 } 2524 2525 static bool 2526 test_has_mpam_hcr(const struct arm64_cpu_capabilities *entry, int scope) 2527 { 2528 u64 idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 2529 2530 return idr & MPAMIDR_EL1_HAS_HCR; 2531 } 2532 2533 static bool 2534 test_has_gicv5_legacy(const struct arm64_cpu_capabilities *entry, int scope) 2535 { 2536 if (!this_cpu_has_cap(ARM64_HAS_GICV5_CPUIF)) 2537 return false; 2538 2539 return !!(read_sysreg_s(SYS_ICC_IDR0_EL1) & ICC_IDR0_EL1_GCIE_LEGACY); 2540 } 2541 2542 static const struct arm64_cpu_capabilities arm64_features[] = { 2543 { 2544 .capability = ARM64_ALWAYS_BOOT, 2545 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2546 .matches = has_always, 2547 }, 2548 { 2549 .capability = ARM64_ALWAYS_SYSTEM, 2550 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2551 .matches = has_always, 2552 }, 2553 { 2554 .desc = "GICv3 CPU interface", 2555 .capability = ARM64_HAS_GICV3_CPUIF, 2556 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2557 .matches = has_useable_gicv3_cpuif, 2558 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, GIC, IMP) 2559 }, 2560 { 2561 .desc = "Enhanced Counter Virtualization", 2562 .capability = ARM64_HAS_ECV, 2563 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2564 .matches = has_cpuid_feature, 2565 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, IMP) 2566 }, 2567 { 2568 .desc = "Enhanced Counter Virtualization (CNTPOFF)", 2569 .capability = ARM64_HAS_ECV_CNTPOFF, 2570 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2571 .matches = has_cpuid_feature, 2572 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, ECV, CNTPOFF) 2573 }, 2574 { 2575 .desc = "Privileged Access Never", 2576 .capability = ARM64_HAS_PAN, 2577 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2578 .matches = has_cpuid_feature, 2579 .cpu_enable = cpu_enable_pan, 2580 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, IMP) 2581 }, 2582 #ifdef CONFIG_ARM64_EPAN 2583 { 2584 .desc = "Enhanced Privileged Access Never", 2585 .capability = ARM64_HAS_EPAN, 2586 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2587 .matches = has_cpuid_feature, 2588 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, PAN, PAN3) 2589 }, 2590 #endif /* CONFIG_ARM64_EPAN */ 2591 { 2592 .desc = "LSE atomic instructions", 2593 .capability = ARM64_HAS_LSE_ATOMICS, 2594 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2595 .matches = has_cpuid_feature, 2596 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, ATOMIC, IMP) 2597 }, 2598 { 2599 .desc = "Virtualization Host Extensions", 2600 .capability = ARM64_HAS_VIRT_HOST_EXTN, 2601 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2602 .matches = runs_at_el2, 2603 .cpu_enable = cpu_copy_el2regs, 2604 }, 2605 { 2606 .desc = "Nested Virtualization Support", 2607 .capability = ARM64_HAS_NESTED_VIRT, 2608 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2609 .matches = has_nested_virt_support, 2610 .match_list = (const struct arm64_cpu_capabilities []){ 2611 { 2612 .matches = has_cpuid_feature, 2613 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, NV2) 2614 }, 2615 { 2616 .matches = has_cpuid_feature, 2617 ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2_ONLY) 2618 }, 2619 { /* Sentinel */ } 2620 }, 2621 }, 2622 { 2623 .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, 2624 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2625 .matches = has_32bit_el0, 2626 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) 2627 }, 2628 #ifdef CONFIG_KVM 2629 { 2630 .desc = "32-bit EL1 Support", 2631 .capability = ARM64_HAS_32BIT_EL1, 2632 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2633 .matches = has_cpuid_feature, 2634 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL1, AARCH32) 2635 }, 2636 { 2637 .desc = "Protected KVM", 2638 .capability = ARM64_KVM_PROTECTED_MODE, 2639 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2640 .matches = is_kvm_protected_mode, 2641 }, 2642 { 2643 .desc = "HCRX_EL2 register", 2644 .capability = ARM64_HAS_HCX, 2645 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2646 .matches = has_cpuid_feature, 2647 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HCX, IMP) 2648 }, 2649 #endif 2650 { 2651 .desc = "Kernel page table isolation (KPTI)", 2652 .capability = ARM64_UNMAP_KERNEL_AT_EL0, 2653 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE, 2654 .cpu_enable = cpu_enable_kpti, 2655 .matches = unmap_kernel_at_el0, 2656 /* 2657 * The ID feature fields below are used to indicate that 2658 * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for 2659 * more details. 2660 */ 2661 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, CSV3, IMP) 2662 }, 2663 { 2664 .capability = ARM64_HAS_FPSIMD, 2665 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2666 .matches = has_cpuid_feature, 2667 .cpu_enable = cpu_enable_fpsimd, 2668 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, FP, IMP) 2669 }, 2670 #ifdef CONFIG_ARM64_PMEM 2671 { 2672 .desc = "Data cache clean to Point of Persistence", 2673 .capability = ARM64_HAS_DCPOP, 2674 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2675 .matches = has_cpuid_feature, 2676 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, IMP) 2677 }, 2678 { 2679 .desc = "Data cache clean to Point of Deep Persistence", 2680 .capability = ARM64_HAS_DCPODP, 2681 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2682 .matches = has_cpuid_feature, 2683 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, DPB, DPB2) 2684 }, 2685 #endif 2686 #ifdef CONFIG_ARM64_SVE 2687 { 2688 .desc = "Scalable Vector Extension", 2689 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2690 .capability = ARM64_SVE, 2691 .cpu_enable = cpu_enable_sve, 2692 .matches = has_cpuid_feature, 2693 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, SVE, IMP) 2694 }, 2695 #endif /* CONFIG_ARM64_SVE */ 2696 #ifdef CONFIG_ARM64_RAS_EXTN 2697 { 2698 .desc = "RAS Extension Support", 2699 .capability = ARM64_HAS_RAS_EXTN, 2700 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2701 .matches = has_cpuid_feature, 2702 .cpu_enable = cpu_clear_disr, 2703 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, RAS, IMP) 2704 }, 2705 { 2706 .desc = "RASv1p1 Extension Support", 2707 .capability = ARM64_HAS_RASV1P1_EXTN, 2708 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2709 .matches = has_rasv1p1, 2710 }, 2711 #endif /* CONFIG_ARM64_RAS_EXTN */ 2712 #ifdef CONFIG_ARM64_AMU_EXTN 2713 { 2714 .desc = "Activity Monitors Unit (AMU)", 2715 .capability = ARM64_HAS_AMU_EXTN, 2716 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2717 .matches = has_amu, 2718 .cpu_enable = cpu_amu_enable, 2719 .cpus = &amu_cpus, 2720 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) 2721 }, 2722 #endif /* CONFIG_ARM64_AMU_EXTN */ 2723 { 2724 .desc = "Data cache clean to the PoU not required for I/D coherence", 2725 .capability = ARM64_HAS_CACHE_IDC, 2726 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2727 .matches = has_cache_idc, 2728 .cpu_enable = cpu_emulate_effective_ctr, 2729 }, 2730 { 2731 .desc = "Instruction cache invalidation not required for I/D coherence", 2732 .capability = ARM64_HAS_CACHE_DIC, 2733 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2734 .matches = has_cache_dic, 2735 }, 2736 { 2737 .desc = "Stage-2 Force Write-Back", 2738 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2739 .capability = ARM64_HAS_STAGE2_FWB, 2740 .matches = has_cpuid_feature, 2741 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, FWB, IMP) 2742 }, 2743 { 2744 .desc = "ARMv8.4 Translation Table Level", 2745 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2746 .capability = ARM64_HAS_ARMv8_4_TTL, 2747 .matches = has_cpuid_feature, 2748 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, TTL, IMP) 2749 }, 2750 { 2751 .desc = "TLB range maintenance instructions", 2752 .capability = ARM64_HAS_TLB_RANGE, 2753 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2754 .matches = has_cpuid_feature, 2755 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, TLB, RANGE) 2756 }, 2757 #ifdef CONFIG_ARM64_HW_AFDBM 2758 { 2759 .desc = "Hardware dirty bit management", 2760 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, 2761 .capability = ARM64_HW_DBM, 2762 .matches = has_hw_dbm, 2763 .cpu_enable = cpu_enable_hw_dbm, 2764 .cpus = &dbm_cpus, 2765 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) 2766 }, 2767 #endif 2768 #ifdef CONFIG_ARM64_HAFT 2769 { 2770 .desc = "Hardware managed Access Flag for Table Descriptors", 2771 /* 2772 * Contrary to the page/block access flag, the table access flag 2773 * cannot be emulated in software (no access fault will occur). 2774 * Therefore this should be used only if it's supported system 2775 * wide. 2776 */ 2777 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2778 .capability = ARM64_HAFT, 2779 .matches = has_cpuid_feature, 2780 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, HAFT) 2781 }, 2782 #endif 2783 { 2784 .desc = "CRC32 instructions", 2785 .capability = ARM64_HAS_CRC32, 2786 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2787 .matches = has_cpuid_feature, 2788 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, CRC32, IMP) 2789 }, 2790 { 2791 .desc = "Speculative Store Bypassing Safe (SSBS)", 2792 .capability = ARM64_SSBS, 2793 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2794 .matches = has_cpuid_feature, 2795 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SSBS, IMP) 2796 }, 2797 #ifdef CONFIG_ARM64_CNP 2798 { 2799 .desc = "Common not Private translations", 2800 .capability = ARM64_HAS_CNP, 2801 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2802 .matches = has_useable_cnp, 2803 .cpu_enable = cpu_enable_cnp, 2804 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, CnP, IMP) 2805 }, 2806 #endif 2807 { 2808 .desc = "Speculation barrier (SB)", 2809 .capability = ARM64_HAS_SB, 2810 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2811 .matches = has_cpuid_feature, 2812 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, SB, IMP) 2813 }, 2814 #ifdef CONFIG_ARM64_PTR_AUTH 2815 { 2816 .desc = "Address authentication (architected QARMA5 algorithm)", 2817 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA5, 2818 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2819 .matches = has_address_auth_cpucap, 2820 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, APA, PAuth) 2821 }, 2822 { 2823 .desc = "Address authentication (architected QARMA3 algorithm)", 2824 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH_QARMA3, 2825 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2826 .matches = has_address_auth_cpucap, 2827 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, APA3, PAuth) 2828 }, 2829 { 2830 .desc = "Address authentication (IMP DEF algorithm)", 2831 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF, 2832 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2833 .matches = has_address_auth_cpucap, 2834 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, API, PAuth) 2835 }, 2836 { 2837 .capability = ARM64_HAS_ADDRESS_AUTH, 2838 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2839 .matches = has_address_auth_metacap, 2840 }, 2841 { 2842 .desc = "Generic authentication (architected QARMA5 algorithm)", 2843 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA5, 2844 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2845 .matches = has_cpuid_feature, 2846 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPA, IMP) 2847 }, 2848 { 2849 .desc = "Generic authentication (architected QARMA3 algorithm)", 2850 .capability = ARM64_HAS_GENERIC_AUTH_ARCH_QARMA3, 2851 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2852 .matches = has_cpuid_feature, 2853 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, GPA3, IMP) 2854 }, 2855 { 2856 .desc = "Generic authentication (IMP DEF algorithm)", 2857 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF, 2858 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2859 .matches = has_cpuid_feature, 2860 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, GPI, IMP) 2861 }, 2862 { 2863 .capability = ARM64_HAS_GENERIC_AUTH, 2864 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2865 .matches = has_generic_auth, 2866 }, 2867 #endif /* CONFIG_ARM64_PTR_AUTH */ 2868 #ifdef CONFIG_ARM64_PSEUDO_NMI 2869 { 2870 /* 2871 * Depends on having GICv3 2872 */ 2873 .desc = "IRQ priority masking", 2874 .capability = ARM64_HAS_GIC_PRIO_MASKING, 2875 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2876 .matches = can_use_gic_priorities, 2877 }, 2878 { 2879 /* 2880 * Depends on ARM64_HAS_GIC_PRIO_MASKING 2881 */ 2882 .capability = ARM64_HAS_GIC_PRIO_RELAXED_SYNC, 2883 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2884 .matches = has_gic_prio_relaxed_sync, 2885 }, 2886 #endif 2887 { 2888 /* 2889 * Depends on having GICv3 2890 */ 2891 .desc = "ICV_DIR_EL1 trapping", 2892 .capability = ARM64_HAS_ICH_HCR_EL2_TDIR, 2893 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 2894 .matches = can_trap_icv_dir_el1, 2895 }, 2896 #ifdef CONFIG_ARM64_E0PD 2897 { 2898 .desc = "E0PD", 2899 .capability = ARM64_HAS_E0PD, 2900 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2901 .cpu_enable = cpu_enable_e0pd, 2902 .matches = has_cpuid_feature, 2903 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, E0PD, IMP) 2904 }, 2905 #endif 2906 { 2907 .desc = "Random Number Generator", 2908 .capability = ARM64_HAS_RNG, 2909 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2910 .matches = has_cpuid_feature, 2911 ARM64_CPUID_FIELDS(ID_AA64ISAR0_EL1, RNDR, IMP) 2912 }, 2913 #ifdef CONFIG_ARM64_BTI 2914 { 2915 .desc = "Branch Target Identification", 2916 .capability = ARM64_BTI, 2917 #ifdef CONFIG_ARM64_BTI_KERNEL 2918 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2919 #else 2920 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2921 #endif 2922 .matches = has_cpuid_feature, 2923 .cpu_enable = bti_enable, 2924 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, BT, IMP) 2925 }, 2926 #endif 2927 #ifdef CONFIG_ARM64_MTE 2928 { 2929 .desc = "Memory Tagging Extension", 2930 .capability = ARM64_MTE, 2931 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 2932 .matches = has_cpuid_feature, 2933 .cpu_enable = cpu_enable_mte, 2934 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE2) 2935 }, 2936 { 2937 .desc = "Asymmetric MTE Tag Check Fault", 2938 .capability = ARM64_MTE_ASYMM, 2939 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2940 .matches = has_cpuid_feature, 2941 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, MTE, MTE3) 2942 }, 2943 { 2944 .desc = "FAR on MTE Tag Check Fault", 2945 .capability = ARM64_MTE_FAR, 2946 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2947 .matches = has_cpuid_feature, 2948 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTEFAR, IMP) 2949 }, 2950 { 2951 .desc = "Store Only MTE Tag Check", 2952 .capability = ARM64_MTE_STORE_ONLY, 2953 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 2954 .matches = has_cpuid_feature, 2955 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, MTESTOREONLY, IMP) 2956 }, 2957 #endif /* CONFIG_ARM64_MTE */ 2958 { 2959 .desc = "RCpc load-acquire (LDAPR)", 2960 .capability = ARM64_HAS_LDAPR, 2961 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2962 .matches = has_cpuid_feature, 2963 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LRCPC, IMP) 2964 }, 2965 { 2966 .desc = "Fine Grained Traps", 2967 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2968 .capability = ARM64_HAS_FGT, 2969 .matches = has_cpuid_feature, 2970 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, IMP) 2971 }, 2972 { 2973 .desc = "Fine Grained Traps 2", 2974 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2975 .capability = ARM64_HAS_FGT2, 2976 .matches = has_cpuid_feature, 2977 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, FGT, FGT2) 2978 }, 2979 #ifdef CONFIG_ARM64_SME 2980 { 2981 .desc = "Scalable Matrix Extension", 2982 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2983 .capability = ARM64_SME, 2984 .matches = has_cpuid_feature, 2985 .cpu_enable = cpu_enable_sme, 2986 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, IMP) 2987 }, 2988 /* FA64 should be sorted after the base SME capability */ 2989 { 2990 .desc = "FA64", 2991 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 2992 .capability = ARM64_SME_FA64, 2993 .matches = has_cpuid_feature, 2994 .cpu_enable = cpu_enable_fa64, 2995 ARM64_CPUID_FIELDS(ID_AA64SMFR0_EL1, FA64, IMP) 2996 }, 2997 { 2998 .desc = "SME2", 2999 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3000 .capability = ARM64_SME2, 3001 .matches = has_cpuid_feature, 3002 .cpu_enable = cpu_enable_sme2, 3003 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, SME, SME2) 3004 }, 3005 #endif /* CONFIG_ARM64_SME */ 3006 { 3007 .desc = "WFx with timeout", 3008 .capability = ARM64_HAS_WFXT, 3009 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3010 .matches = has_cpuid_feature, 3011 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, WFxT, IMP) 3012 }, 3013 { 3014 .desc = "Trap EL0 IMPLEMENTATION DEFINED functionality", 3015 .capability = ARM64_HAS_TIDCP1, 3016 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3017 .matches = has_cpuid_feature, 3018 .cpu_enable = cpu_trap_el0_impdef, 3019 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, TIDCP1, IMP) 3020 }, 3021 { 3022 .desc = "Data independent timing control (DIT)", 3023 .capability = ARM64_HAS_DIT, 3024 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3025 .matches = has_cpuid_feature, 3026 .cpu_enable = cpu_enable_dit, 3027 ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, DIT, IMP) 3028 }, 3029 { 3030 .desc = "Memory Copy and Memory Set instructions", 3031 .capability = ARM64_HAS_MOPS, 3032 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3033 .matches = has_cpuid_feature, 3034 .cpu_enable = cpu_enable_mops, 3035 ARM64_CPUID_FIELDS(ID_AA64ISAR2_EL1, MOPS, IMP) 3036 }, 3037 { 3038 .capability = ARM64_HAS_TCR2, 3039 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3040 .matches = has_cpuid_feature, 3041 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, TCRX, IMP) 3042 }, 3043 { 3044 .desc = "Stage-1 Permission Indirection Extension (S1PIE)", 3045 .capability = ARM64_HAS_S1PIE, 3046 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3047 .matches = has_cpuid_feature, 3048 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1PIE, IMP) 3049 }, 3050 { 3051 .desc = "VHE for hypervisor only", 3052 .capability = ARM64_KVM_HVHE, 3053 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3054 .matches = hvhe_possible, 3055 }, 3056 { 3057 .desc = "Enhanced Virtualization Traps", 3058 .capability = ARM64_HAS_EVT, 3059 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3060 .matches = has_cpuid_feature, 3061 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, EVT, IMP) 3062 }, 3063 { 3064 .desc = "BBM Level 2 without TLB conflict abort", 3065 .capability = ARM64_HAS_BBML2_NOABORT, 3066 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3067 .matches = has_bbml2_noabort, 3068 }, 3069 { 3070 .desc = "52-bit Virtual Addressing for KVM (LPA2)", 3071 .capability = ARM64_HAS_LPA2, 3072 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3073 .matches = has_lpa2, 3074 }, 3075 { 3076 .desc = "FPMR", 3077 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3078 .capability = ARM64_HAS_FPMR, 3079 .matches = has_cpuid_feature, 3080 .cpu_enable = cpu_enable_fpmr, 3081 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, FPMR, IMP) 3082 }, 3083 #ifdef CONFIG_ARM64_VA_BITS_52 3084 { 3085 .capability = ARM64_HAS_VA52, 3086 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3087 .matches = has_cpuid_feature, 3088 #ifdef CONFIG_ARM64_64K_PAGES 3089 .desc = "52-bit Virtual Addressing (LVA)", 3090 ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, VARange, 52) 3091 #else 3092 .desc = "52-bit Virtual Addressing (LPA2)", 3093 #ifdef CONFIG_ARM64_4K_PAGES 3094 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN4, 52_BIT) 3095 #else 3096 ARM64_CPUID_FIELDS(ID_AA64MMFR0_EL1, TGRAN16, 52_BIT) 3097 #endif 3098 #endif 3099 }, 3100 #endif 3101 { 3102 .desc = "Memory Partitioning And Monitoring", 3103 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3104 .capability = ARM64_MPAM, 3105 .matches = test_has_mpam, 3106 .cpu_enable = cpu_enable_mpam, 3107 }, 3108 { 3109 .desc = "Memory Partitioning And Monitoring Virtualisation", 3110 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3111 .capability = ARM64_MPAM_HCR, 3112 .matches = test_has_mpam_hcr, 3113 }, 3114 { 3115 .desc = "NV1", 3116 .capability = ARM64_HAS_HCR_NV1, 3117 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3118 .matches = has_nv1, 3119 ARM64_CPUID_FIELDS_NEG(ID_AA64MMFR4_EL1, E2H0, NI_NV1) 3120 }, 3121 #ifdef CONFIG_ARM64_POE 3122 { 3123 .desc = "Stage-1 Permission Overlay Extension (S1POE)", 3124 .capability = ARM64_HAS_S1POE, 3125 .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, 3126 .matches = has_cpuid_feature, 3127 .cpu_enable = cpu_enable_poe, 3128 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) 3129 }, 3130 #endif 3131 #ifdef CONFIG_ARM64_GCS 3132 { 3133 .desc = "Guarded Control Stack (GCS)", 3134 .capability = ARM64_HAS_GCS, 3135 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3136 .cpu_enable = cpu_enable_gcs, 3137 .matches = has_cpuid_feature, 3138 ARM64_CPUID_FIELDS(ID_AA64PFR1_EL1, GCS, IMP) 3139 }, 3140 #endif 3141 #ifdef CONFIG_HW_PERF_EVENTS 3142 { 3143 .desc = "PMUv3", 3144 .capability = ARM64_HAS_PMUV3, 3145 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3146 .matches = has_pmuv3, 3147 }, 3148 #endif 3149 { 3150 .desc = "SCTLR2", 3151 .capability = ARM64_HAS_SCTLR2, 3152 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3153 .matches = has_cpuid_feature, 3154 ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, SCTLRX, IMP) 3155 }, 3156 { 3157 .desc = "GICv5 CPU interface", 3158 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE, 3159 .capability = ARM64_HAS_GICV5_CPUIF, 3160 .matches = has_cpuid_feature, 3161 ARM64_CPUID_FIELDS(ID_AA64PFR2_EL1, GCIE, IMP) 3162 }, 3163 { 3164 .desc = "GICv5 Legacy vCPU interface", 3165 .type = ARM64_CPUCAP_EARLY_LOCAL_CPU_FEATURE, 3166 .capability = ARM64_HAS_GICV5_LEGACY, 3167 .matches = test_has_gicv5_legacy, 3168 }, 3169 { 3170 .desc = "XNX", 3171 .capability = ARM64_HAS_XNX, 3172 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3173 .matches = has_cpuid_feature, 3174 ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, XNX, IMP) 3175 }, 3176 { 3177 .desc = "LS64", 3178 .capability = ARM64_HAS_LS64, 3179 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3180 .matches = has_cpuid_feature, 3181 .cpu_enable = cpu_enable_ls64, 3182 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64) 3183 }, 3184 { 3185 .desc = "LS64_V", 3186 .capability = ARM64_HAS_LS64_V, 3187 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3188 .matches = has_cpuid_feature, 3189 .cpu_enable = cpu_enable_ls64_v, 3190 ARM64_CPUID_FIELDS(ID_AA64ISAR1_EL1, LS64, LS64_V) 3191 }, 3192 #ifdef CONFIG_ARM64_LSUI 3193 { 3194 .desc = "Unprivileged Load Store Instructions (LSUI)", 3195 .capability = ARM64_HAS_LSUI, 3196 .type = ARM64_CPUCAP_SYSTEM_FEATURE, 3197 .matches = has_cpuid_feature, 3198 ARM64_CPUID_FIELDS(ID_AA64ISAR3_EL1, LSUI, IMP) 3199 }, 3200 #endif 3201 {}, 3202 }; 3203 3204 #define HWCAP_CPUID_MATCH(reg, field, min_value) \ 3205 .matches = has_user_cpuid_feature, \ 3206 ARM64_CPUID_FIELDS(reg, field, min_value) 3207 3208 #define __HWCAP_CAP(name, cap_type, cap) \ 3209 .desc = name, \ 3210 .type = ARM64_CPUCAP_SYSTEM_FEATURE, \ 3211 .hwcap_type = cap_type, \ 3212 .hwcap = cap, \ 3213 3214 #define HWCAP_CAP(reg, field, min_value, cap_type, cap) \ 3215 { \ 3216 __HWCAP_CAP(#cap, cap_type, cap) \ 3217 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3218 } 3219 3220 #define HWCAP_MULTI_CAP(list, cap_type, cap) \ 3221 { \ 3222 __HWCAP_CAP(#cap, cap_type, cap) \ 3223 .matches = cpucap_multi_entry_cap_matches, \ 3224 .match_list = list, \ 3225 } 3226 3227 #define HWCAP_CAP_MATCH(match, cap_type, cap) \ 3228 { \ 3229 __HWCAP_CAP(#cap, cap_type, cap) \ 3230 .matches = match, \ 3231 } 3232 3233 #define HWCAP_CAP_MATCH_ID(match, reg, field, min_value, cap_type, cap) \ 3234 { \ 3235 __HWCAP_CAP(#cap, cap_type, cap) \ 3236 HWCAP_CPUID_MATCH(reg, field, min_value) \ 3237 .matches = match, \ 3238 } 3239 3240 #ifdef CONFIG_ARM64_PTR_AUTH 3241 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = { 3242 { 3243 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, APA, PAuth) 3244 }, 3245 { 3246 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, APA3, PAuth) 3247 }, 3248 { 3249 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, API, PAuth) 3250 }, 3251 {}, 3252 }; 3253 3254 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { 3255 { 3256 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPA, IMP) 3257 }, 3258 { 3259 HWCAP_CPUID_MATCH(ID_AA64ISAR2_EL1, GPA3, IMP) 3260 }, 3261 { 3262 HWCAP_CPUID_MATCH(ID_AA64ISAR1_EL1, GPI, IMP) 3263 }, 3264 {}, 3265 }; 3266 #endif 3267 3268 #ifdef CONFIG_ARM64_SVE 3269 static bool has_sve_feature(const struct arm64_cpu_capabilities *cap, int scope) 3270 { 3271 return system_supports_sve() && has_user_cpuid_feature(cap, scope); 3272 } 3273 #endif 3274 3275 #ifdef CONFIG_ARM64_SME 3276 static bool has_sme_feature(const struct arm64_cpu_capabilities *cap, int scope) 3277 { 3278 return system_supports_sme() && has_user_cpuid_feature(cap, scope); 3279 } 3280 #endif 3281 3282 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { 3283 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, PMULL, CAP_HWCAP, KERNEL_HWCAP_PMULL), 3284 HWCAP_CAP(ID_AA64ISAR0_EL1, AES, AES, CAP_HWCAP, KERNEL_HWCAP_AES), 3285 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA1, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA1), 3286 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA256, CAP_HWCAP, KERNEL_HWCAP_SHA2), 3287 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA2, SHA512, CAP_HWCAP, KERNEL_HWCAP_SHA512), 3288 HWCAP_CAP(ID_AA64ISAR0_EL1, CRC32, IMP, CAP_HWCAP, KERNEL_HWCAP_CRC32), 3289 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, IMP, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), 3290 HWCAP_CAP(ID_AA64ISAR0_EL1, ATOMIC, FEAT_LSE128, CAP_HWCAP, KERNEL_HWCAP_LSE128), 3291 HWCAP_CAP(ID_AA64ISAR0_EL1, RDM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), 3292 HWCAP_CAP(ID_AA64ISAR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SHA3), 3293 HWCAP_CAP(ID_AA64ISAR0_EL1, SM3, IMP, CAP_HWCAP, KERNEL_HWCAP_SM3), 3294 HWCAP_CAP(ID_AA64ISAR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SM4), 3295 HWCAP_CAP(ID_AA64ISAR0_EL1, DP, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), 3296 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), 3297 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, F16F32DOT, CAP_HWCAP, KERNEL_HWCAP_F16F32DOT), 3298 HWCAP_CAP(ID_AA64ISAR0_EL1, FHM, F16F32MM, CAP_HWCAP, KERNEL_HWCAP_F16F32MM), 3299 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM, CAP_HWCAP, KERNEL_HWCAP_FLAGM), 3300 HWCAP_CAP(ID_AA64ISAR0_EL1, TS, FLAGM2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), 3301 HWCAP_CAP(ID_AA64ISAR0_EL1, RNDR, IMP, CAP_HWCAP, KERNEL_HWCAP_RNG), 3302 HWCAP_CAP(ID_AA64ISAR3_EL1, FPRCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_FPRCVT), 3303 HWCAP_CAP(ID_AA64PFR0_EL1, FP, IMP, CAP_HWCAP, KERNEL_HWCAP_FP), 3304 HWCAP_CAP(ID_AA64PFR0_EL1, FP, FP16, CAP_HWCAP, KERNEL_HWCAP_FPHP), 3305 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, IMP, CAP_HWCAP, KERNEL_HWCAP_ASIMD), 3306 HWCAP_CAP(ID_AA64PFR0_EL1, AdvSIMD, FP16, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP), 3307 HWCAP_CAP(ID_AA64PFR0_EL1, DIT, IMP, CAP_HWCAP, KERNEL_HWCAP_DIT), 3308 HWCAP_CAP(ID_AA64PFR2_EL1, FPMR, IMP, CAP_HWCAP, KERNEL_HWCAP_FPMR), 3309 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, IMP, CAP_HWCAP, KERNEL_HWCAP_DCPOP), 3310 HWCAP_CAP(ID_AA64ISAR1_EL1, DPB, DPB2, CAP_HWCAP, KERNEL_HWCAP_DCPODP), 3311 HWCAP_CAP(ID_AA64ISAR1_EL1, JSCVT, IMP, CAP_HWCAP, KERNEL_HWCAP_JSCVT), 3312 HWCAP_CAP(ID_AA64ISAR1_EL1, FCMA, IMP, CAP_HWCAP, KERNEL_HWCAP_FCMA), 3313 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, IMP, CAP_HWCAP, KERNEL_HWCAP_LRCPC), 3314 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC), 3315 HWCAP_CAP(ID_AA64ISAR1_EL1, LRCPC, LRCPC3, CAP_HWCAP, KERNEL_HWCAP_LRCPC3), 3316 HWCAP_CAP(ID_AA64ISAR1_EL1, FRINTTS, IMP, CAP_HWCAP, KERNEL_HWCAP_FRINT), 3317 HWCAP_CAP(ID_AA64ISAR1_EL1, SB, IMP, CAP_HWCAP, KERNEL_HWCAP_SB), 3318 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_BF16), 3319 HWCAP_CAP(ID_AA64ISAR1_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_EBF16), 3320 HWCAP_CAP(ID_AA64ISAR1_EL1, DGH, IMP, CAP_HWCAP, KERNEL_HWCAP_DGH), 3321 HWCAP_CAP(ID_AA64ISAR1_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_I8MM), 3322 HWCAP_CAP(ID_AA64ISAR1_EL1, LS64, LS64, CAP_HWCAP, KERNEL_HWCAP_LS64), 3323 HWCAP_CAP(ID_AA64ISAR2_EL1, LUT, IMP, CAP_HWCAP, KERNEL_HWCAP_LUT), 3324 HWCAP_CAP(ID_AA64ISAR3_EL1, FAMINMAX, IMP, CAP_HWCAP, KERNEL_HWCAP_FAMINMAX), 3325 HWCAP_CAP(ID_AA64ISAR3_EL1, LSFE, IMP, CAP_HWCAP, KERNEL_HWCAP_LSFE), 3326 HWCAP_CAP(ID_AA64MMFR2_EL1, AT, IMP, CAP_HWCAP, KERNEL_HWCAP_USCAT), 3327 #ifdef CONFIG_ARM64_SVE 3328 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ISAR2_EL1, LUT, LUT6, CAP_HWCAP, KERNEL_HWCAP_SVE_LUT6), 3329 HWCAP_CAP(ID_AA64PFR0_EL1, SVE, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE), 3330 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p3, CAP_HWCAP, KERNEL_HWCAP_SVE2P3), 3331 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p2, CAP_HWCAP, KERNEL_HWCAP_SVE2P2), 3332 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2p1, CAP_HWCAP, KERNEL_HWCAP_SVE2P1), 3333 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SVEver, SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2), 3334 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEAES), 3335 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, PMULL128, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL), 3336 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, AES, AES2, CAP_HWCAP, KERNEL_HWCAP_SVE_AES2), 3337 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM), 3338 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_B16B16), 3339 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, BFSCALE, CAP_HWCAP, KERNEL_HWCAP_SVE_BFSCALE), 3340 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, B16B16, B16MM, CAP_HWCAP, KERNEL_HWCAP_SVE_B16MM), 3341 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEBF16), 3342 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, BF16, EBF16, CAP_HWCAP, KERNEL_HWCAP_SVE_EBF16), 3343 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SHA3, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESHA3), 3344 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, SM4, IMP, CAP_HWCAP, KERNEL_HWCAP_SVESM4), 3345 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, I8MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEI8MM), 3346 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F32MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF32MM), 3347 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F64MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVEF64MM), 3348 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, F16MM, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_F16MM), 3349 HWCAP_CAP_MATCH_ID(has_sve_feature, ID_AA64ZFR0_EL1, EltPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SVE_ELTPERM), 3350 #endif 3351 #ifdef CONFIG_ARM64_GCS 3352 HWCAP_CAP(ID_AA64PFR1_EL1, GCS, IMP, CAP_HWCAP, KERNEL_HWCAP_GCS), 3353 #endif 3354 HWCAP_CAP(ID_AA64PFR1_EL1, SSBS, SSBS2, CAP_HWCAP, KERNEL_HWCAP_SSBS), 3355 #ifdef CONFIG_ARM64_BTI 3356 HWCAP_CAP(ID_AA64PFR1_EL1, BT, IMP, CAP_HWCAP, KERNEL_HWCAP_BTI), 3357 #endif 3358 #ifdef CONFIG_ARM64_PTR_AUTH 3359 HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA), 3360 HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG), 3361 #endif 3362 #ifdef CONFIG_ARM64_MTE 3363 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE2, CAP_HWCAP, KERNEL_HWCAP_MTE), 3364 HWCAP_CAP(ID_AA64PFR1_EL1, MTE, MTE3, CAP_HWCAP, KERNEL_HWCAP_MTE3), 3365 HWCAP_CAP(ID_AA64PFR2_EL1, MTEFAR, IMP, CAP_HWCAP, KERNEL_HWCAP_MTE_FAR), 3366 HWCAP_CAP(ID_AA64PFR2_EL1, MTESTOREONLY, IMP, CAP_HWCAP , KERNEL_HWCAP_MTE_STORE_ONLY), 3367 #endif /* CONFIG_ARM64_MTE */ 3368 HWCAP_CAP(ID_AA64MMFR0_EL1, ECV, IMP, CAP_HWCAP, KERNEL_HWCAP_ECV), 3369 HWCAP_CAP(ID_AA64MMFR1_EL1, AFP, IMP, CAP_HWCAP, KERNEL_HWCAP_AFP), 3370 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, IMP, CAP_HWCAP, KERNEL_HWCAP_CSSC), 3371 HWCAP_CAP(ID_AA64ISAR2_EL1, CSSC, CMPBR, CAP_HWCAP, KERNEL_HWCAP_CMPBR), 3372 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRFM, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRFM), 3373 HWCAP_CAP(ID_AA64ISAR2_EL1, RPRES, IMP, CAP_HWCAP, KERNEL_HWCAP_RPRES), 3374 HWCAP_CAP(ID_AA64ISAR2_EL1, WFxT, IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT), 3375 HWCAP_CAP(ID_AA64ISAR2_EL1, MOPS, IMP, CAP_HWCAP, KERNEL_HWCAP_MOPS), 3376 HWCAP_CAP(ID_AA64ISAR2_EL1, BC, IMP, CAP_HWCAP, KERNEL_HWCAP_HBC), 3377 #ifdef CONFIG_ARM64_SME 3378 HWCAP_CAP(ID_AA64PFR1_EL1, SME, IMP, CAP_HWCAP, KERNEL_HWCAP_SME), 3379 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, FA64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_FA64), 3380 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUT6, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUT6), 3381 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, LUTv2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_LUTV2), 3382 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p3, CAP_HWCAP, KERNEL_HWCAP_SME2P3), 3383 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p2, CAP_HWCAP, KERNEL_HWCAP_SME2P2), 3384 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2p1, CAP_HWCAP, KERNEL_HWCAP_SME2P1), 3385 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMEver, SME2, CAP_HWCAP, KERNEL_HWCAP_SME2), 3386 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I64), 3387 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F64F64, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F64F64), 3388 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I16I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I16I32), 3389 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16B16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16B16), 3390 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F16), 3391 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F16, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F16), 3392 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F8F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F8F32), 3393 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, I8I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_I8I32), 3394 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F16F32), 3395 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, B16F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_B16F32), 3396 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, BI32I32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_BI32I32), 3397 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, F32F32, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_F32F32), 3398 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8FMA), 3399 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP4), 3400 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SF8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SF8DP2), 3401 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SBitPerm, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SBITPERM), 3402 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, AES, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_AES), 3403 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SFEXPA, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SFEXPA), 3404 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, STMOP, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_STMOP), 3405 HWCAP_CAP_MATCH_ID(has_sme_feature, ID_AA64SMFR0_EL1, SMOP4, IMP, CAP_HWCAP, KERNEL_HWCAP_SME_SMOP4), 3406 #endif /* CONFIG_ARM64_SME */ 3407 HWCAP_CAP(ID_AA64FPFR0_EL1, F8CVT, IMP, CAP_HWCAP, KERNEL_HWCAP_F8CVT), 3408 HWCAP_CAP(ID_AA64FPFR0_EL1, F8FMA, IMP, CAP_HWCAP, KERNEL_HWCAP_F8FMA), 3409 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP4), 3410 HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), 3411 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM8, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM8), 3412 HWCAP_CAP(ID_AA64FPFR0_EL1, F8MM4, IMP, CAP_HWCAP, KERNEL_HWCAP_F8MM4), 3413 HWCAP_CAP(ID_AA64FPFR0_EL1, F16MM2, IMP, CAP_HWCAP, KERNEL_HWCAP_F16MM), 3414 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), 3415 HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), 3416 #ifdef CONFIG_ARM64_POE 3417 HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), 3418 #endif 3419 {}, 3420 }; 3421 3422 #ifdef CONFIG_COMPAT 3423 static bool compat_has_neon(const struct arm64_cpu_capabilities *cap, int scope) 3424 { 3425 /* 3426 * Check that all of MVFR1_EL1.{SIMDSP, SIMDInt, SIMDLS} are available, 3427 * in line with that of arm32 as in vfp_init(). We make sure that the 3428 * check is future proof, by making sure value is non-zero. 3429 */ 3430 u32 mvfr1; 3431 3432 WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible()); 3433 if (scope == SCOPE_SYSTEM) 3434 mvfr1 = read_sanitised_ftr_reg(SYS_MVFR1_EL1); 3435 else 3436 mvfr1 = read_sysreg_s(SYS_MVFR1_EL1); 3437 3438 return cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDSP_SHIFT) && 3439 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDInt_SHIFT) && 3440 cpuid_feature_extract_unsigned_field(mvfr1, MVFR1_EL1_SIMDLS_SHIFT); 3441 } 3442 #endif 3443 3444 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 3445 #ifdef CONFIG_COMPAT 3446 HWCAP_CAP_MATCH(compat_has_neon, CAP_COMPAT_HWCAP, COMPAT_HWCAP_NEON), 3447 HWCAP_CAP(MVFR1_EL1, SIMDFMAC, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv4), 3448 /* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */ 3449 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP), 3450 HWCAP_CAP(MVFR0_EL1, FPDP, VFPv3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3), 3451 HWCAP_CAP(MVFR1_EL1, FPHP, FP16, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP), 3452 HWCAP_CAP(MVFR1_EL1, SIMDHP, SIMDHP_FLOAT, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP), 3453 HWCAP_CAP(ID_ISAR5_EL1, AES, VMULL, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL), 3454 HWCAP_CAP(ID_ISAR5_EL1, AES, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES), 3455 HWCAP_CAP(ID_ISAR5_EL1, SHA1, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1), 3456 HWCAP_CAP(ID_ISAR5_EL1, SHA2, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2), 3457 HWCAP_CAP(ID_ISAR5_EL1, CRC32, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32), 3458 HWCAP_CAP(ID_ISAR6_EL1, DP, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDDP), 3459 HWCAP_CAP(ID_ISAR6_EL1, FHM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDFHM), 3460 HWCAP_CAP(ID_ISAR6_EL1, SB, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SB), 3461 HWCAP_CAP(ID_ISAR6_EL1, BF16, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDBF16), 3462 HWCAP_CAP(ID_ISAR6_EL1, I8MM, IMP, CAP_COMPAT_HWCAP, COMPAT_HWCAP_I8MM), 3463 HWCAP_CAP(ID_PFR2_EL1, SSBS, IMP, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SSBS), 3464 #endif 3465 {}, 3466 }; 3467 3468 static void cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3469 { 3470 switch (cap->hwcap_type) { 3471 case CAP_HWCAP: 3472 cpu_set_feature(cap->hwcap); 3473 break; 3474 #ifdef CONFIG_COMPAT 3475 case CAP_COMPAT_HWCAP: 3476 compat_elf_hwcap |= (u32)cap->hwcap; 3477 break; 3478 case CAP_COMPAT_HWCAP2: 3479 compat_elf_hwcap2 |= (u32)cap->hwcap; 3480 break; 3481 #endif 3482 default: 3483 WARN_ON(1); 3484 break; 3485 } 3486 } 3487 3488 /* Check if we have a particular HWCAP enabled */ 3489 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap) 3490 { 3491 bool rc; 3492 3493 switch (cap->hwcap_type) { 3494 case CAP_HWCAP: 3495 rc = cpu_have_feature(cap->hwcap); 3496 break; 3497 #ifdef CONFIG_COMPAT 3498 case CAP_COMPAT_HWCAP: 3499 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0; 3500 break; 3501 case CAP_COMPAT_HWCAP2: 3502 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0; 3503 break; 3504 #endif 3505 default: 3506 WARN_ON(1); 3507 rc = false; 3508 } 3509 3510 return rc; 3511 } 3512 3513 static void setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps) 3514 { 3515 /* We support emulation of accesses to CPU ID feature registers */ 3516 cpu_set_named_feature(CPUID); 3517 for (; hwcaps->matches; hwcaps++) 3518 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps))) 3519 cap_set_elf_hwcap(hwcaps); 3520 } 3521 3522 static void update_cpu_capabilities(u16 scope_mask) 3523 { 3524 int i; 3525 const struct arm64_cpu_capabilities *caps; 3526 3527 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3528 for (i = 0; i < ARM64_NCAPS; i++) { 3529 bool match_all = false; 3530 bool caps_set = false; 3531 bool boot_cpu = false; 3532 3533 caps = cpucap_ptrs[i]; 3534 if (!caps || !(caps->type & scope_mask)) 3535 continue; 3536 3537 match_all = cpucap_match_all_early_cpus(caps); 3538 caps_set = cpus_have_cap(caps->capability); 3539 boot_cpu = scope_mask & SCOPE_BOOT_CPU; 3540 3541 /* 3542 * Unless it's a match-all CPUs feature, avoid probing if 3543 * already detected. 3544 */ 3545 if (!match_all && caps_set) 3546 continue; 3547 3548 /* 3549 * A match-all CPUs capability is only set when probing the 3550 * boot CPU. It may be cleared subsequently if not detected on 3551 * secondary ones. 3552 */ 3553 if (match_all && !caps_set && !boot_cpu) 3554 continue; 3555 3556 if (!caps->matches(caps, cpucap_default_scope(caps))) { 3557 if (match_all) 3558 __clear_bit(caps->capability, system_cpucaps); 3559 continue; 3560 } 3561 3562 /* 3563 * Match-all CPUs capabilities are logged later when the 3564 * system capabilities are finalised. 3565 */ 3566 if (!match_all && caps->desc && !caps->cpus) 3567 pr_info("detected: %s\n", caps->desc); 3568 3569 __set_bit(caps->capability, system_cpucaps); 3570 3571 if (boot_cpu && (caps->type & SCOPE_BOOT_CPU)) 3572 set_bit(caps->capability, boot_cpucaps); 3573 } 3574 } 3575 3576 /* 3577 * Enable all the available capabilities on this CPU. The capabilities 3578 * with BOOT_CPU scope are handled separately and hence skipped here. 3579 */ 3580 static int cpu_enable_non_boot_scope_capabilities(void *__unused) 3581 { 3582 int i; 3583 u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU; 3584 3585 for_each_available_cap(i) { 3586 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[i]; 3587 3588 if (WARN_ON(!cap)) 3589 continue; 3590 3591 if (!(cap->type & non_boot_scope)) 3592 continue; 3593 3594 if (cap->cpu_enable) 3595 cap->cpu_enable(cap); 3596 } 3597 return 0; 3598 } 3599 3600 /* 3601 * Run through the enabled capabilities and enable() it on all active 3602 * CPUs 3603 */ 3604 static void __init enable_cpu_capabilities(u16 scope_mask) 3605 { 3606 int i; 3607 const struct arm64_cpu_capabilities *caps; 3608 bool boot_scope; 3609 3610 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3611 boot_scope = !!(scope_mask & SCOPE_BOOT_CPU); 3612 3613 for (i = 0; i < ARM64_NCAPS; i++) { 3614 caps = cpucap_ptrs[i]; 3615 if (!caps || !(caps->type & scope_mask) || 3616 !cpus_have_cap(caps->capability)) 3617 continue; 3618 3619 if (boot_scope && caps->cpu_enable) 3620 /* 3621 * Capabilities with SCOPE_BOOT_CPU scope are finalised 3622 * before any secondary CPU boots. Thus, each secondary 3623 * will enable the capability as appropriate via 3624 * check_local_cpu_capabilities(). The only exception is 3625 * the boot CPU, for which the capability must be 3626 * enabled here. This approach avoids costly 3627 * stop_machine() calls for this case. 3628 */ 3629 caps->cpu_enable(caps); 3630 } 3631 3632 /* 3633 * For all non-boot scope capabilities, use stop_machine() 3634 * as it schedules the work allowing us to modify PSTATE, 3635 * instead of on_each_cpu() which uses an IPI, giving us a 3636 * PSTATE that disappears when we return. 3637 */ 3638 if (!boot_scope) 3639 stop_machine(cpu_enable_non_boot_scope_capabilities, 3640 NULL, cpu_online_mask); 3641 } 3642 3643 /* 3644 * Run through the list of capabilities to check for conflicts. 3645 * If the system has already detected a capability, take necessary 3646 * action on this CPU. 3647 */ 3648 static void verify_local_cpu_caps(u16 scope_mask) 3649 { 3650 int i; 3651 bool cpu_has_cap, system_has_cap; 3652 const struct arm64_cpu_capabilities *caps; 3653 3654 scope_mask &= ARM64_CPUCAP_SCOPE_MASK; 3655 3656 for (i = 0; i < ARM64_NCAPS; i++) { 3657 caps = cpucap_ptrs[i]; 3658 if (!caps || !(caps->type & scope_mask)) 3659 continue; 3660 3661 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU); 3662 system_has_cap = cpus_have_cap(caps->capability); 3663 3664 if (system_has_cap) { 3665 /* 3666 * Check if the new CPU misses an advertised feature, 3667 * which is not safe to miss. 3668 */ 3669 if (!cpu_has_cap && !cpucap_late_cpu_optional(caps)) 3670 break; 3671 /* 3672 * We have to issue cpu_enable() irrespective of 3673 * whether the CPU has it or not, as it is enabeld 3674 * system wide. It is upto the call back to take 3675 * appropriate action on this CPU. 3676 */ 3677 if (caps->cpu_enable) 3678 caps->cpu_enable(caps); 3679 } else { 3680 /* 3681 * Check if the CPU has this capability if it isn't 3682 * safe to have when the system doesn't. 3683 */ 3684 if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) 3685 break; 3686 } 3687 } 3688 3689 if (i < ARM64_NCAPS) { 3690 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n", 3691 smp_processor_id(), caps->capability, 3692 caps->desc, system_has_cap, cpu_has_cap); 3693 3694 if (cpucap_panic_on_conflict(caps)) 3695 cpu_panic_kernel(); 3696 else 3697 cpu_die_early(); 3698 } 3699 } 3700 3701 /* 3702 * Check for CPU features that are used in early boot 3703 * based on the Boot CPU value. 3704 */ 3705 static void check_early_cpu_features(void) 3706 { 3707 verify_cpu_asid_bits(); 3708 3709 verify_local_cpu_caps(SCOPE_BOOT_CPU); 3710 } 3711 3712 static void 3713 __verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps) 3714 { 3715 3716 for (; caps->matches; caps++) 3717 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) { 3718 pr_crit("CPU%d: missing HWCAP: %s\n", 3719 smp_processor_id(), caps->desc); 3720 cpu_die_early(); 3721 } 3722 } 3723 3724 static void verify_local_elf_hwcaps(void) 3725 { 3726 __verify_local_elf_hwcaps(arm64_elf_hwcaps); 3727 3728 if (id_aa64pfr0_32bit_el0(read_cpuid(ID_AA64PFR0_EL1))) 3729 __verify_local_elf_hwcaps(compat_elf_hwcaps); 3730 } 3731 3732 static void verify_sve_features(void) 3733 { 3734 unsigned long cpacr = cpacr_save_enable_kernel_sve(); 3735 3736 if (vec_verify_vq_map(ARM64_VEC_SVE)) { 3737 pr_crit("CPU%d: SVE: vector length support mismatch\n", 3738 smp_processor_id()); 3739 cpu_die_early(); 3740 } 3741 3742 cpacr_restore(cpacr); 3743 } 3744 3745 static void verify_sme_features(void) 3746 { 3747 unsigned long cpacr = cpacr_save_enable_kernel_sme(); 3748 3749 if (vec_verify_vq_map(ARM64_VEC_SME)) { 3750 pr_crit("CPU%d: SME: vector length support mismatch\n", 3751 smp_processor_id()); 3752 cpu_die_early(); 3753 } 3754 3755 cpacr_restore(cpacr); 3756 } 3757 3758 static void verify_hyp_capabilities(void) 3759 { 3760 u64 safe_mmfr1, mmfr0, mmfr1; 3761 int parange, ipa_max; 3762 unsigned int safe_vmid_bits, vmid_bits; 3763 3764 if (!IS_ENABLED(CONFIG_KVM)) 3765 return; 3766 3767 safe_mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 3768 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 3769 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 3770 3771 /* Verify VMID bits */ 3772 safe_vmid_bits = get_vmid_bits(safe_mmfr1); 3773 vmid_bits = get_vmid_bits(mmfr1); 3774 if (vmid_bits < safe_vmid_bits) { 3775 pr_crit("CPU%d: VMID width mismatch\n", smp_processor_id()); 3776 cpu_die_early(); 3777 } 3778 3779 /* Verify IPA range */ 3780 parange = cpuid_feature_extract_unsigned_field(mmfr0, 3781 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 3782 ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange); 3783 if (ipa_max < get_kvm_ipa_limit()) { 3784 pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id()); 3785 cpu_die_early(); 3786 } 3787 } 3788 3789 static void verify_mpam_capabilities(void) 3790 { 3791 u64 cpu_idr = read_cpuid(ID_AA64PFR0_EL1); 3792 u64 sys_idr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 3793 u16 cpu_partid_max, cpu_pmg_max, sys_partid_max, sys_pmg_max; 3794 3795 if (FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, cpu_idr) != 3796 FIELD_GET(ID_AA64PFR0_EL1_MPAM_MASK, sys_idr)) { 3797 pr_crit("CPU%d: MPAM version mismatch\n", smp_processor_id()); 3798 cpu_die_early(); 3799 } 3800 3801 cpu_idr = read_cpuid(MPAMIDR_EL1); 3802 sys_idr = read_sanitised_ftr_reg(SYS_MPAMIDR_EL1); 3803 if (FIELD_GET(MPAMIDR_EL1_HAS_HCR, cpu_idr) != 3804 FIELD_GET(MPAMIDR_EL1_HAS_HCR, sys_idr)) { 3805 pr_crit("CPU%d: Missing MPAM HCR\n", smp_processor_id()); 3806 cpu_die_early(); 3807 } 3808 3809 cpu_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, cpu_idr); 3810 cpu_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, cpu_idr); 3811 sys_partid_max = FIELD_GET(MPAMIDR_EL1_PARTID_MAX, sys_idr); 3812 sys_pmg_max = FIELD_GET(MPAMIDR_EL1_PMG_MAX, sys_idr); 3813 if (cpu_partid_max < sys_partid_max || cpu_pmg_max < sys_pmg_max) { 3814 pr_crit("CPU%d: MPAM PARTID/PMG max values are mismatched\n", smp_processor_id()); 3815 cpu_die_early(); 3816 } 3817 } 3818 3819 /* 3820 * Run through the enabled system capabilities and enable() it on this CPU. 3821 * The capabilities were decided based on the available CPUs at the boot time. 3822 * Any new CPU should match the system wide status of the capability. If the 3823 * new CPU doesn't have a capability which the system now has enabled, we 3824 * cannot do anything to fix it up and could cause unexpected failures. So 3825 * we park the CPU. 3826 */ 3827 static void verify_local_cpu_capabilities(void) 3828 { 3829 /* 3830 * The capabilities with SCOPE_BOOT_CPU are checked from 3831 * check_early_cpu_features(), as they need to be verified 3832 * on all secondary CPUs. 3833 */ 3834 verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3835 verify_local_elf_hwcaps(); 3836 3837 if (system_supports_sve()) 3838 verify_sve_features(); 3839 3840 if (system_supports_sme()) 3841 verify_sme_features(); 3842 3843 if (is_hyp_mode_available()) 3844 verify_hyp_capabilities(); 3845 3846 if (system_supports_mpam()) 3847 verify_mpam_capabilities(); 3848 } 3849 3850 void check_local_cpu_capabilities(void) 3851 { 3852 /* 3853 * All secondary CPUs should conform to the early CPU features 3854 * in use by the kernel based on boot CPU. 3855 */ 3856 check_early_cpu_features(); 3857 3858 /* 3859 * If we haven't finalised the system capabilities, this CPU gets 3860 * a chance to update the errata work arounds and local features. 3861 * Otherwise, this CPU should verify that it has all the system 3862 * advertised capabilities. 3863 */ 3864 if (!system_capabilities_finalized()) 3865 update_cpu_capabilities(SCOPE_LOCAL_CPU); 3866 else 3867 verify_local_cpu_capabilities(); 3868 } 3869 3870 bool this_cpu_has_cap(unsigned int n) 3871 { 3872 if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) { 3873 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3874 3875 if (cap) 3876 return cap->matches(cap, SCOPE_LOCAL_CPU); 3877 } 3878 3879 return false; 3880 } 3881 EXPORT_SYMBOL_GPL(this_cpu_has_cap); 3882 3883 /* 3884 * This helper function is used in a narrow window when, 3885 * - The system wide safe registers are set with all the SMP CPUs and, 3886 * - The SYSTEM_FEATURE system_cpucaps may not have been set. 3887 */ 3888 static bool __maybe_unused __system_matches_cap(unsigned int n) 3889 { 3890 if (n < ARM64_NCAPS) { 3891 const struct arm64_cpu_capabilities *cap = cpucap_ptrs[n]; 3892 3893 if (cap) 3894 return cap->matches(cap, SCOPE_SYSTEM); 3895 } 3896 return false; 3897 } 3898 3899 void cpu_set_feature(unsigned int num) 3900 { 3901 set_bit(num, elf_hwcap); 3902 } 3903 3904 bool cpu_have_feature(unsigned int num) 3905 { 3906 return test_bit(num, elf_hwcap); 3907 } 3908 EXPORT_SYMBOL_GPL(cpu_have_feature); 3909 3910 unsigned long cpu_get_elf_hwcap(void) 3911 { 3912 /* 3913 * We currently only populate the first 32 bits of AT_HWCAP. Please 3914 * note that for userspace compatibility we guarantee that bits 62 3915 * and 63 will always be returned as 0. 3916 */ 3917 return elf_hwcap[0]; 3918 } 3919 3920 unsigned long cpu_get_elf_hwcap2(void) 3921 { 3922 return elf_hwcap[1]; 3923 } 3924 3925 unsigned long cpu_get_elf_hwcap3(void) 3926 { 3927 return elf_hwcap[2]; 3928 } 3929 3930 static void __init setup_boot_cpu_capabilities(void) 3931 { 3932 kvm_arm_target_impl_cpu_init(); 3933 /* 3934 * The boot CPU's feature register values have been recorded. Detect 3935 * boot cpucaps and local cpucaps for the boot CPU, then enable and 3936 * patch alternatives for the available boot cpucaps. 3937 */ 3938 update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU); 3939 enable_cpu_capabilities(SCOPE_BOOT_CPU); 3940 apply_boot_alternatives(); 3941 } 3942 3943 void __init setup_boot_cpu_features(void) 3944 { 3945 /* 3946 * Initialize the indirect array of CPU capabilities pointers before we 3947 * handle the boot CPU. 3948 */ 3949 init_cpucap_indirect_list(); 3950 3951 /* 3952 * Detect broken pseudo-NMI. Must be called _before_ the call to 3953 * setup_boot_cpu_capabilities() since it interacts with 3954 * can_use_gic_priorities(). 3955 */ 3956 detect_system_supports_pseudo_nmi(); 3957 3958 setup_boot_cpu_capabilities(); 3959 } 3960 3961 static void __init setup_system_capabilities(void) 3962 { 3963 /* 3964 * The system-wide safe feature register values have been finalized. 3965 * Detect, enable, and patch alternatives for the available system 3966 * cpucaps. 3967 */ 3968 update_cpu_capabilities(SCOPE_SYSTEM); 3969 enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); 3970 apply_alternatives_all(); 3971 3972 for (int i = 0; i < ARM64_NCAPS; i++) { 3973 const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; 3974 3975 if (!caps || !caps->desc) 3976 continue; 3977 3978 /* 3979 * Log any cpucaps with a cpumask as these aren't logged by 3980 * update_cpu_capabilities(). 3981 */ 3982 if (caps->cpus && cpumask_any(caps->cpus) < nr_cpu_ids) 3983 pr_info("detected: %s on CPU%*pbl\n", 3984 caps->desc, cpumask_pr_args(caps->cpus)); 3985 3986 /* Log match-all CPUs capabilities */ 3987 if (cpucap_match_all_early_cpus(caps) && 3988 cpus_have_cap(caps->capability)) 3989 pr_info("detected: %s\n", caps->desc); 3990 } 3991 3992 /* 3993 * TTBR0 PAN doesn't have its own cpucap, so log it manually. 3994 */ 3995 if (system_uses_ttbr0_pan()) 3996 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n"); 3997 3998 /* 3999 * Report Spectre mitigations status. 4000 */ 4001 spectre_print_disabled_mitigations(); 4002 } 4003 4004 void __init setup_system_features(void) 4005 { 4006 setup_system_capabilities(); 4007 4008 linear_map_maybe_split_to_ptes(); 4009 kpti_install_ng_mappings(); 4010 4011 sve_setup(); 4012 sme_setup(); 4013 4014 /* 4015 * Check for sane CTR_EL0.CWG value. 4016 */ 4017 if (!cache_type_cwg()) 4018 pr_warn("No Cache Writeback Granule information, assuming %d\n", 4019 ARCH_DMA_MINALIGN); 4020 } 4021 4022 void __init setup_user_features(void) 4023 { 4024 user_feature_fixup(); 4025 4026 setup_elf_hwcaps(arm64_elf_hwcaps); 4027 4028 if (system_supports_32bit_el0()) { 4029 setup_elf_hwcaps(compat_elf_hwcaps); 4030 elf_hwcap_fixup(); 4031 } 4032 4033 minsigstksz_setup(); 4034 } 4035 4036 static int enable_mismatched_32bit_el0(unsigned int cpu) 4037 { 4038 /* 4039 * The first 32-bit-capable CPU we detected and so can no longer 4040 * be offlined by userspace. -1 indicates we haven't yet onlined 4041 * a 32-bit-capable CPU. 4042 */ 4043 static int lucky_winner = -1; 4044 4045 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 4046 bool cpu_32bit = false; 4047 4048 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 4049 if (!housekeeping_cpu(cpu, HK_TYPE_DOMAIN)) 4050 pr_info("Treating domain isolated CPU %u as 64-bit only\n", cpu); 4051 else 4052 cpu_32bit = true; 4053 } 4054 4055 if (cpu_32bit) { 4056 cpumask_set_cpu(cpu, cpu_32bit_el0_mask); 4057 static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); 4058 } 4059 4060 if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) 4061 return 0; 4062 4063 if (lucky_winner >= 0) 4064 return 0; 4065 4066 /* 4067 * We've detected a mismatch. We need to keep one of our CPUs with 4068 * 32-bit EL0 online so that is_cpu_allowed() doesn't end up rejecting 4069 * every CPU in the system for a 32-bit task. 4070 */ 4071 lucky_winner = cpu_32bit ? cpu : cpumask_any_and(cpu_32bit_el0_mask, 4072 cpu_active_mask); 4073 dev_set_offline_disabled(get_cpu_device(lucky_winner)); 4074 setup_elf_hwcaps(compat_elf_hwcaps); 4075 elf_hwcap_fixup(); 4076 pr_info("Asymmetric 32-bit EL0 support detected on CPU %u; CPU hot-unplug disabled on CPU %u\n", 4077 cpu, lucky_winner); 4078 return 0; 4079 } 4080 4081 static int __init init_32bit_el0_mask(void) 4082 { 4083 if (!allow_mismatched_32bit_el0) 4084 return 0; 4085 4086 if (!zalloc_cpumask_var(&cpu_32bit_el0_mask, GFP_KERNEL)) 4087 return -ENOMEM; 4088 4089 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, 4090 "arm64/mismatched_32bit_el0:online", 4091 enable_mismatched_32bit_el0, NULL); 4092 } 4093 subsys_initcall_sync(init_32bit_el0_mask); 4094 4095 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap) 4096 { 4097 cpu_enable_swapper_cnp(); 4098 } 4099 4100 /* 4101 * We emulate only the following system register space. 4102 * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 2 - 7] 4103 * See Table C5-6 System instruction encodings for System register accesses, 4104 * ARMv8 ARM(ARM DDI 0487A.f) for more details. 4105 */ 4106 static inline bool __attribute_const__ is_emulated(u32 id) 4107 { 4108 return (sys_reg_Op0(id) == 0x3 && 4109 sys_reg_CRn(id) == 0x0 && 4110 sys_reg_Op1(id) == 0x0 && 4111 (sys_reg_CRm(id) == 0 || 4112 ((sys_reg_CRm(id) >= 2) && (sys_reg_CRm(id) <= 7)))); 4113 } 4114 4115 /* 4116 * With CRm == 0, reg should be one of : 4117 * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1. 4118 */ 4119 static inline int emulate_id_reg(u32 id, u64 *valp) 4120 { 4121 switch (id) { 4122 case SYS_MIDR_EL1: 4123 *valp = read_cpuid_id(); 4124 break; 4125 case SYS_MPIDR_EL1: 4126 *valp = SYS_MPIDR_SAFE_VAL; 4127 break; 4128 case SYS_REVIDR_EL1: 4129 /* IMPLEMENTATION DEFINED values are emulated with 0 */ 4130 *valp = 0; 4131 break; 4132 default: 4133 return -EINVAL; 4134 } 4135 4136 return 0; 4137 } 4138 4139 static int emulate_sys_reg(u32 id, u64 *valp) 4140 { 4141 struct arm64_ftr_reg *regp; 4142 4143 if (!is_emulated(id)) 4144 return -EINVAL; 4145 4146 if (sys_reg_CRm(id) == 0) 4147 return emulate_id_reg(id, valp); 4148 4149 regp = get_arm64_ftr_reg_nowarn(id); 4150 if (regp) 4151 *valp = arm64_ftr_reg_user_value(regp); 4152 else 4153 /* 4154 * The untracked registers are either IMPLEMENTATION DEFINED 4155 * (e.g, ID_AFR0_EL1) or reserved RAZ. 4156 */ 4157 *valp = 0; 4158 return 0; 4159 } 4160 4161 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt) 4162 { 4163 int rc; 4164 u64 val; 4165 4166 rc = emulate_sys_reg(sys_reg, &val); 4167 if (!rc) { 4168 pt_regs_write_reg(regs, rt, val); 4169 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE); 4170 } 4171 return rc; 4172 } 4173 4174 bool try_emulate_mrs(struct pt_regs *regs, u32 insn) 4175 { 4176 u32 sys_reg, rt; 4177 4178 if (compat_user_mode(regs) || !aarch64_insn_is_mrs(insn)) 4179 return false; 4180 4181 /* 4182 * sys_reg values are defined as used in mrs/msr instruction. 4183 * shift the imm value to get the encoding. 4184 */ 4185 sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5; 4186 rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn); 4187 return do_emulate_mrs(regs, sys_reg, rt) == 0; 4188 } 4189 4190 enum mitigation_state arm64_get_meltdown_state(void) 4191 { 4192 if (__meltdown_safe) 4193 return SPECTRE_UNAFFECTED; 4194 4195 if (arm64_kernel_unmapped_at_el0()) 4196 return SPECTRE_MITIGATED; 4197 4198 return SPECTRE_VULNERABLE; 4199 } 4200 4201 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr, 4202 char *buf) 4203 { 4204 switch (arm64_get_meltdown_state()) { 4205 case SPECTRE_UNAFFECTED: 4206 return sprintf(buf, "Not affected\n"); 4207 4208 case SPECTRE_MITIGATED: 4209 return sprintf(buf, "Mitigation: PTI\n"); 4210 4211 default: 4212 return sprintf(buf, "Vulnerable\n"); 4213 } 4214 } 4215