1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright 2018 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #include <linux/string_helpers.h> 28 #include <linux/uaccess.h> 29 #include <media/cec-notifier.h> 30 31 #include "dc.h" 32 #include "amdgpu.h" 33 #include "amdgpu_dm.h" 34 #include "amdgpu_dm_debugfs.h" 35 #include "amdgpu_dm_replay.h" 36 #include "amdgpu_dm_psr.h" 37 #include "dm_helpers.h" 38 #include "dmub/dmub_srv.h" 39 #include "resource.h" 40 #include "dsc.h" 41 #include "link_hwss.h" 42 #include "dc/dc_dmub_srv.h" 43 #include "link/protocols/link_dp_capability.h" 44 #include "inc/hw/dchubbub.h" 45 46 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 47 #include "amdgpu_dm_psr.h" 48 #endif 49 50 #define MULTIPLIER_TO_LR 270000 51 struct dmub_debugfs_trace_header { 52 uint32_t entry_count; 53 uint32_t reserved[3]; 54 }; 55 56 struct dmub_debugfs_trace_entry { 57 uint32_t trace_code; 58 uint32_t tick_count; 59 uint32_t param0; 60 uint32_t param1; 61 }; 62 63 static const char *const mst_progress_status[] = { 64 "probe", 65 "remote_edid", 66 "allocate_new_payload", 67 "clear_allocated_payload", 68 }; 69 70 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array 71 * 72 * Function takes in attributes passed to debugfs write entry 73 * and writes into param array. 74 * The user passes max_param_num to identify maximum number of 75 * parameters that could be parsed. 76 * 77 */ 78 static int parse_write_buffer_into_params(char *wr_buf, uint32_t wr_buf_size, 79 long *param, const char __user *buf, 80 int max_param_num, 81 uint8_t *param_nums) 82 { 83 char *wr_buf_ptr = NULL; 84 uint32_t wr_buf_count = 0; 85 int r; 86 char *sub_str = NULL; 87 const char delimiter[3] = {' ', '\n', '\0'}; 88 uint8_t param_index = 0; 89 90 *param_nums = 0; 91 92 wr_buf_ptr = wr_buf; 93 94 /* r is bytes not be copied */ 95 if (copy_from_user(wr_buf_ptr, buf, wr_buf_size)) { 96 DRM_DEBUG_DRIVER("user data could not be read successfully\n"); 97 return -EFAULT; 98 } 99 100 /* check number of parameters. isspace could not differ space and\n */ 101 while ((*wr_buf_ptr != 0xa) && (wr_buf_count < wr_buf_size)) { 102 /* skip space*/ 103 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 104 wr_buf_ptr++; 105 wr_buf_count++; 106 } 107 108 if (wr_buf_count == wr_buf_size) 109 break; 110 111 /* skip non-space*/ 112 while ((!isspace(*wr_buf_ptr)) && (wr_buf_count < wr_buf_size)) { 113 wr_buf_ptr++; 114 wr_buf_count++; 115 } 116 117 (*param_nums)++; 118 119 if (wr_buf_count == wr_buf_size) 120 break; 121 } 122 123 if (*param_nums > max_param_num) 124 *param_nums = max_param_num; 125 126 wr_buf_ptr = wr_buf; /* reset buf pointer */ 127 wr_buf_count = 0; /* number of char already checked */ 128 129 while (isspace(*wr_buf_ptr) && (wr_buf_count < wr_buf_size)) { 130 wr_buf_ptr++; 131 wr_buf_count++; 132 } 133 134 while (param_index < *param_nums) { 135 /* after strsep, wr_buf_ptr will be moved to after space */ 136 sub_str = strsep(&wr_buf_ptr, delimiter); 137 138 r = kstrtol(sub_str, 16, &(param[param_index])); 139 140 if (r) 141 DRM_DEBUG_DRIVER("string to int convert error code: %d\n", r); 142 143 param_index++; 144 } 145 146 return 0; 147 } 148 149 /* function description 150 * get/ set DP configuration: lane_count, link_rate, spread_spectrum 151 * 152 * valid lane count value: 1, 2, 4 153 * valid link rate value: 154 * 06h = 1.62Gbps per lane 155 * 0Ah = 2.7Gbps per lane 156 * 0Ch = 3.24Gbps per lane 157 * 14h = 5.4Gbps per lane 158 * 1Eh = 8.1Gbps per lane 159 * 160 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings 161 * 162 * --- to get dp configuration 163 * 164 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 165 * 166 * It will list current, verified, reported, preferred dp configuration. 167 * current -- for current video mode 168 * verified --- maximum configuration which pass link training 169 * reported --- DP rx report caps (DPCD register offset 0, 1 2) 170 * preferred --- user force settings 171 * 172 * --- set (or force) dp configuration 173 * 174 * echo <lane_count> <link_rate> > link_settings 175 * 176 * for example, to force to 2 lane, 2.7GHz, 177 * echo 4 0xa > /sys/kernel/debug/dri/0/DP-x/link_settings 178 * 179 * spread_spectrum could not be changed dynamically. 180 * 181 * in case invalid lane count, link rate are force, no hw programming will be 182 * done. please check link settings after force operation to see if HW get 183 * programming. 184 * 185 * cat /sys/kernel/debug/dri/0/DP-x/link_settings 186 * 187 * check current and preferred settings. 188 * 189 */ 190 static ssize_t dp_link_settings_read(struct file *f, char __user *buf, 191 size_t size, loff_t *pos) 192 { 193 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 194 struct dc_link *link = connector->dc_link; 195 char *rd_buf = NULL; 196 char *rd_buf_ptr = NULL; 197 const uint32_t rd_buf_size = 100; 198 uint32_t result = 0; 199 uint8_t str_len = 0; 200 int r; 201 202 if (*pos & 3 || size & 3) 203 return -EINVAL; 204 205 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 206 if (!rd_buf) 207 return 0; 208 209 rd_buf_ptr = rd_buf; 210 211 str_len = strlen("Current: %d 0x%x %d "); 212 snprintf(rd_buf_ptr, str_len, "Current: %d 0x%x %d ", 213 link->cur_link_settings.lane_count, 214 link->cur_link_settings.link_rate, 215 link->cur_link_settings.link_spread); 216 rd_buf_ptr += str_len; 217 218 str_len = strlen("Verified: %d 0x%x %d "); 219 snprintf(rd_buf_ptr, str_len, "Verified: %d 0x%x %d ", 220 link->verified_link_cap.lane_count, 221 link->verified_link_cap.link_rate, 222 link->verified_link_cap.link_spread); 223 rd_buf_ptr += str_len; 224 225 str_len = strlen("Reported: %d 0x%x %d "); 226 snprintf(rd_buf_ptr, str_len, "Reported: %d 0x%x %d ", 227 link->reported_link_cap.lane_count, 228 link->reported_link_cap.link_rate, 229 link->reported_link_cap.link_spread); 230 rd_buf_ptr += str_len; 231 232 str_len = strlen("Preferred: %d 0x%x %d "); 233 snprintf(rd_buf_ptr, str_len, "Preferred: %d 0x%x %d\n", 234 link->preferred_link_setting.lane_count, 235 link->preferred_link_setting.link_rate, 236 link->preferred_link_setting.link_spread); 237 238 while (size) { 239 if (*pos >= rd_buf_size) 240 break; 241 242 r = put_user(*(rd_buf + result), buf); 243 if (r) { 244 kfree(rd_buf); 245 return r; /* r = -EFAULT */ 246 } 247 248 buf += 1; 249 size -= 1; 250 *pos += 1; 251 result += 1; 252 } 253 254 kfree(rd_buf); 255 return result; 256 } 257 258 static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, 259 size_t size, loff_t *pos) 260 { 261 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 262 struct dc_link *link = connector->dc_link; 263 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 264 struct dc *dc = (struct dc *)link->dc; 265 struct dc_link_settings prefer_link_settings = {0}; 266 char *wr_buf = NULL; 267 const uint32_t wr_buf_size = 40; 268 /* 0: lane_count; 1: link_rate */ 269 int max_param_num = 2; 270 uint8_t param_nums = 0; 271 long param[2]; 272 bool valid_input = true; 273 274 if (size == 0) 275 return -EINVAL; 276 277 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 278 if (!wr_buf) 279 return -ENOSPC; 280 281 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 282 (long *)param, buf, 283 max_param_num, 284 ¶m_nums)) { 285 kfree(wr_buf); 286 return -EINVAL; 287 } 288 289 if (param_nums <= 0) { 290 kfree(wr_buf); 291 DRM_DEBUG_DRIVER("user data not be read\n"); 292 return -EINVAL; 293 } 294 295 switch (param[0]) { 296 case LANE_COUNT_ONE: 297 case LANE_COUNT_TWO: 298 case LANE_COUNT_FOUR: 299 break; 300 default: 301 valid_input = false; 302 break; 303 } 304 305 switch (param[1]) { 306 case LINK_RATE_LOW: 307 case LINK_RATE_RATE_2: 308 case LINK_RATE_RATE_3: 309 case LINK_RATE_HIGH: 310 case LINK_RATE_RBR2: 311 case LINK_RATE_RATE_6: 312 case LINK_RATE_HIGH2: 313 case LINK_RATE_HIGH3: 314 case LINK_RATE_UHBR10: 315 case LINK_RATE_UHBR13_5: 316 case LINK_RATE_UHBR20: 317 break; 318 default: 319 valid_input = false; 320 break; 321 } 322 323 if (!valid_input) { 324 kfree(wr_buf); 325 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 326 mutex_lock(&adev->dm.dc_lock); 327 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 328 mutex_unlock(&adev->dm.dc_lock); 329 return size; 330 } 331 332 /* save user force lane_count, link_rate to preferred settings 333 * spread spectrum will not be changed 334 */ 335 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 336 prefer_link_settings.use_link_rate_set = false; 337 prefer_link_settings.lane_count = param[0]; 338 prefer_link_settings.link_rate = param[1]; 339 340 mutex_lock(&adev->dm.dc_lock); 341 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, false); 342 mutex_unlock(&adev->dm.dc_lock); 343 344 kfree(wr_buf); 345 return size; 346 } 347 348 static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) 349 { 350 bool is_end_device = false; 351 struct drm_dp_mst_topology_mgr *mgr = NULL; 352 struct drm_dp_mst_port *port = NULL; 353 354 if (aconnector->mst_root && aconnector->mst_root->mst_mgr.mst_state) { 355 mgr = &aconnector->mst_root->mst_mgr; 356 port = aconnector->mst_output_port; 357 358 drm_modeset_lock(&mgr->base.lock, NULL); 359 if (port->pdt == DP_PEER_DEVICE_SST_SINK || 360 port->pdt == DP_PEER_DEVICE_DP_LEGACY_CONV) 361 is_end_device = true; 362 drm_modeset_unlock(&mgr->base.lock); 363 } 364 365 return is_end_device; 366 } 367 368 /* Change MST link setting 369 * 370 * valid lane count value: 1, 2, 4 371 * valid link rate value: 372 * 06h = 1.62Gbps per lane 373 * 0Ah = 2.7Gbps per lane 374 * 0Ch = 3.24Gbps per lane 375 * 14h = 5.4Gbps per lane 376 * 1Eh = 8.1Gbps per lane 377 * 3E8h = 10.0Gbps per lane 378 * 546h = 13.5Gbps per lane 379 * 7D0h = 20.0Gbps per lane 380 * 381 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/mst_link_settings 382 * 383 * for example, to force to 2 lane, 10.0GHz, 384 * echo 2 0x3e8 > /sys/kernel/debug/dri/0/DP-x/mst_link_settings 385 * 386 * Valid input will trigger hotplug event to get new link setting applied 387 * Invalid input will trigger training setting reset 388 * 389 * The usage can be referred to link_settings entry 390 * 391 */ 392 static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf, 393 size_t size, loff_t *pos) 394 { 395 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 396 struct dc_link *link = aconnector->dc_link; 397 struct amdgpu_device *adev = drm_to_adev(aconnector->base.dev); 398 struct dc *dc = (struct dc *)link->dc; 399 struct dc_link_settings prefer_link_settings = {0}; 400 char *wr_buf = NULL; 401 const uint32_t wr_buf_size = 40; 402 /* 0: lane_count; 1: link_rate */ 403 int max_param_num = 2; 404 uint8_t param_nums = 0; 405 long param[2]; 406 bool valid_input = true; 407 408 if (!dp_mst_is_end_device(aconnector)) 409 return -EINVAL; 410 411 if (size == 0) 412 return -EINVAL; 413 414 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 415 if (!wr_buf) 416 return -ENOSPC; 417 418 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 419 (long *)param, buf, 420 max_param_num, 421 ¶m_nums)) { 422 kfree(wr_buf); 423 return -EINVAL; 424 } 425 426 if (param_nums <= 0) { 427 kfree(wr_buf); 428 DRM_DEBUG_DRIVER("user data not be read\n"); 429 return -EINVAL; 430 } 431 432 switch (param[0]) { 433 case LANE_COUNT_ONE: 434 case LANE_COUNT_TWO: 435 case LANE_COUNT_FOUR: 436 break; 437 default: 438 valid_input = false; 439 break; 440 } 441 442 switch (param[1]) { 443 case LINK_RATE_LOW: 444 case LINK_RATE_HIGH: 445 case LINK_RATE_RBR2: 446 case LINK_RATE_HIGH2: 447 case LINK_RATE_HIGH3: 448 case LINK_RATE_UHBR10: 449 case LINK_RATE_UHBR13_5: 450 case LINK_RATE_UHBR20: 451 break; 452 default: 453 valid_input = false; 454 break; 455 } 456 457 if (!valid_input) { 458 kfree(wr_buf); 459 DRM_DEBUG_DRIVER("Invalid Input value No HW will be programmed\n"); 460 mutex_lock(&adev->dm.dc_lock); 461 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 462 mutex_unlock(&adev->dm.dc_lock); 463 return -EINVAL; 464 } 465 466 /* save user force lane_count, link_rate to preferred settings 467 * spread spectrum will not be changed 468 */ 469 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 470 prefer_link_settings.use_link_rate_set = false; 471 prefer_link_settings.lane_count = param[0]; 472 prefer_link_settings.link_rate = param[1]; 473 474 /* skip immediate retrain, and train to new link setting after hotplug event triggered */ 475 mutex_lock(&adev->dm.dc_lock); 476 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, NULL, link, true); 477 mutex_unlock(&adev->dm.dc_lock); 478 479 mutex_lock(&aconnector->base.dev->mode_config.mutex); 480 aconnector->base.force = DRM_FORCE_OFF; 481 mutex_unlock(&aconnector->base.dev->mode_config.mutex); 482 drm_kms_helper_hotplug_event(aconnector->base.dev); 483 484 msleep(100); 485 486 mutex_lock(&aconnector->base.dev->mode_config.mutex); 487 aconnector->base.force = DRM_FORCE_UNSPECIFIED; 488 mutex_unlock(&aconnector->base.dev->mode_config.mutex); 489 drm_kms_helper_hotplug_event(aconnector->base.dev); 490 491 kfree(wr_buf); 492 return size; 493 } 494 495 /* function: get current DP PHY settings: voltage swing, pre-emphasis, 496 * post-cursor2 (defined by VESA DP specification) 497 * 498 * valid values 499 * voltage swing: 0,1,2,3 500 * pre-emphasis : 0,1,2,3 501 * post cursor2 : 0,1,2,3 502 * 503 * 504 * how to use this debugfs 505 * 506 * debugfs is located at /sys/kernel/debug/dri/0/DP-x 507 * 508 * there will be directories, like DP-1, DP-2,DP-3, etc. for DP display 509 * 510 * To figure out which DP-x is the display for DP to be check, 511 * cd DP-x 512 * ls -ll 513 * There should be debugfs file, like link_settings, phy_settings. 514 * cat link_settings 515 * from lane_count, link_rate to figure which DP-x is for display to be worked 516 * on 517 * 518 * To get current DP PHY settings, 519 * cat phy_settings 520 * 521 * To change DP PHY settings, 522 * echo <voltage_swing> <pre-emphasis> <post_cursor2> > phy_settings 523 * for examle, to change voltage swing to 2, pre-emphasis to 3, post_cursor2 to 524 * 0, 525 * echo 2 3 0 > phy_settings 526 * 527 * To check if change be applied, get current phy settings by 528 * cat phy_settings 529 * 530 * In case invalid values are set by user, like 531 * echo 1 4 0 > phy_settings 532 * 533 * HW will NOT be programmed by these settings. 534 * cat phy_settings will show the previous valid settings. 535 */ 536 static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, 537 size_t size, loff_t *pos) 538 { 539 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 540 struct dc_link *link = connector->dc_link; 541 char *rd_buf = NULL; 542 const uint32_t rd_buf_size = 20; 543 uint32_t result = 0; 544 int r; 545 546 if (*pos & 3 || size & 3) 547 return -EINVAL; 548 549 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 550 if (!rd_buf) 551 return -EINVAL; 552 553 snprintf(rd_buf, rd_buf_size, " %d %d %d\n", 554 link->cur_lane_setting[0].VOLTAGE_SWING, 555 link->cur_lane_setting[0].PRE_EMPHASIS, 556 link->cur_lane_setting[0].POST_CURSOR2); 557 558 while (size) { 559 if (*pos >= rd_buf_size) 560 break; 561 562 r = put_user((*(rd_buf + result)), buf); 563 if (r) { 564 kfree(rd_buf); 565 return r; /* r = -EFAULT */ 566 } 567 568 buf += 1; 569 size -= 1; 570 *pos += 1; 571 result += 1; 572 } 573 574 kfree(rd_buf); 575 return result; 576 } 577 578 static int dp_lttpr_status_show(struct seq_file *m, void *unused) 579 { 580 struct drm_connector *connector = m->private; 581 struct amdgpu_dm_connector *aconnector = 582 to_amdgpu_dm_connector(connector); 583 struct dc_lttpr_caps caps = aconnector->dc_link->dpcd_caps.lttpr_caps; 584 585 if (connector->status != connector_status_connected) 586 return -ENODEV; 587 588 seq_printf(m, "phy repeater count: %u (raw: 0x%x)\n", 589 dp_parse_lttpr_repeater_count(caps.phy_repeater_cnt), 590 caps.phy_repeater_cnt); 591 592 seq_puts(m, "phy repeater mode: "); 593 594 switch (caps.mode) { 595 case DP_PHY_REPEATER_MODE_TRANSPARENT: 596 seq_puts(m, "transparent"); 597 break; 598 case DP_PHY_REPEATER_MODE_NON_TRANSPARENT: 599 seq_puts(m, "non-transparent"); 600 break; 601 case 0x00: 602 seq_puts(m, "non lttpr"); 603 break; 604 default: 605 seq_printf(m, "read error (raw: 0x%x)", caps.mode); 606 break; 607 } 608 609 seq_puts(m, "\n"); 610 return 0; 611 } 612 613 static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, 614 size_t size, loff_t *pos) 615 { 616 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 617 struct dc_link *link = connector->dc_link; 618 struct dc *dc = (struct dc *)link->dc; 619 char *wr_buf = NULL; 620 uint32_t wr_buf_size = 40; 621 long param[3]; 622 bool use_prefer_link_setting; 623 struct link_training_settings link_lane_settings = {0}; 624 int max_param_num = 3; 625 uint8_t param_nums = 0; 626 int r = 0; 627 628 629 if (size == 0) 630 return -EINVAL; 631 632 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 633 if (!wr_buf) 634 return -ENOSPC; 635 636 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 637 (long *)param, buf, 638 max_param_num, 639 ¶m_nums)) { 640 kfree(wr_buf); 641 return -EINVAL; 642 } 643 644 if (param_nums <= 0) { 645 kfree(wr_buf); 646 DRM_DEBUG_DRIVER("user data not be read\n"); 647 return -EINVAL; 648 } 649 650 if ((param[0] > VOLTAGE_SWING_MAX_LEVEL) || 651 (param[1] > PRE_EMPHASIS_MAX_LEVEL) || 652 (param[2] > POST_CURSOR2_MAX_LEVEL)) { 653 kfree(wr_buf); 654 DRM_DEBUG_DRIVER("Invalid Input No HW will be programmed\n"); 655 return size; 656 } 657 658 /* get link settings: lane count, link rate */ 659 use_prefer_link_setting = 660 ((link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN) && 661 (link->test_pattern_enabled)); 662 663 memset(&link_lane_settings, 0, sizeof(link_lane_settings)); 664 665 if (use_prefer_link_setting) { 666 link_lane_settings.link_settings.lane_count = 667 link->preferred_link_setting.lane_count; 668 link_lane_settings.link_settings.link_rate = 669 link->preferred_link_setting.link_rate; 670 link_lane_settings.link_settings.link_spread = 671 link->preferred_link_setting.link_spread; 672 } else { 673 link_lane_settings.link_settings.lane_count = 674 link->cur_link_settings.lane_count; 675 link_lane_settings.link_settings.link_rate = 676 link->cur_link_settings.link_rate; 677 link_lane_settings.link_settings.link_spread = 678 link->cur_link_settings.link_spread; 679 } 680 681 /* apply phy settings from user */ 682 for (r = 0; r < link_lane_settings.link_settings.lane_count; r++) { 683 link_lane_settings.hw_lane_settings[r].VOLTAGE_SWING = 684 (enum dc_voltage_swing) (param[0]); 685 link_lane_settings.hw_lane_settings[r].PRE_EMPHASIS = 686 (enum dc_pre_emphasis) (param[1]); 687 link_lane_settings.hw_lane_settings[r].POST_CURSOR2 = 688 (enum dc_post_cursor2) (param[2]); 689 } 690 691 /* program ASIC registers and DPCD registers */ 692 dc_link_set_drive_settings(dc, &link_lane_settings, link); 693 694 kfree(wr_buf); 695 return size; 696 } 697 698 /* function description 699 * 700 * set PHY layer or Link layer test pattern 701 * PHY test pattern is used for PHY SI check. 702 * Link layer test will not affect PHY SI. 703 * 704 * Reset Test Pattern: 705 * 0 = DP_TEST_PATTERN_VIDEO_MODE 706 * 707 * PHY test pattern supported: 708 * 1 = DP_TEST_PATTERN_D102 709 * 2 = DP_TEST_PATTERN_SYMBOL_ERROR 710 * 3 = DP_TEST_PATTERN_PRBS7 711 * 4 = DP_TEST_PATTERN_80BIT_CUSTOM 712 * 5 = DP_TEST_PATTERN_CP2520_1 713 * 6 = DP_TEST_PATTERN_CP2520_2 = DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE 714 * 7 = DP_TEST_PATTERN_CP2520_3 715 * 716 * DP PHY Link Training Patterns 717 * 8 = DP_TEST_PATTERN_TRAINING_PATTERN1 718 * 9 = DP_TEST_PATTERN_TRAINING_PATTERN2 719 * a = DP_TEST_PATTERN_TRAINING_PATTERN3 720 * b = DP_TEST_PATTERN_TRAINING_PATTERN4 721 * 722 * DP Link Layer Test pattern 723 * c = DP_TEST_PATTERN_COLOR_SQUARES 724 * d = DP_TEST_PATTERN_COLOR_SQUARES_CEA 725 * e = DP_TEST_PATTERN_VERTICAL_BARS 726 * f = DP_TEST_PATTERN_HORIZONTAL_BARS 727 * 10= DP_TEST_PATTERN_COLOR_RAMP 728 * 729 * debugfs phy_test_pattern is located at /syskernel/debug/dri/0/DP-x 730 * 731 * --- set test pattern 732 * echo <test pattern #> > test_pattern 733 * 734 * If test pattern # is not supported, NO HW programming will be done. 735 * for DP_TEST_PATTERN_80BIT_CUSTOM, it needs extra 10 bytes of data 736 * for the user pattern. input 10 bytes data are separated by space 737 * 738 * echo 0x4 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0xaa > test_pattern 739 * 740 * --- reset test pattern 741 * echo 0 > test_pattern 742 * 743 * --- HPD detection is disabled when set PHY test pattern 744 * 745 * when PHY test pattern (pattern # within [1,7]) is set, HPD pin of HW ASIC 746 * is disable. User could unplug DP display from DP connected and plug scope to 747 * check test pattern PHY SI. 748 * If there is need unplug scope and plug DP display back, do steps below: 749 * echo 0 > phy_test_pattern 750 * unplug scope 751 * plug DP display. 752 * 753 * "echo 0 > phy_test_pattern" will re-enable HPD pin again so that video sw 754 * driver could detect "unplug scope" and "plug DP display" 755 */ 756 static ssize_t dp_phy_test_pattern_debugfs_write(struct file *f, const char __user *buf, 757 size_t size, loff_t *pos) 758 { 759 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 760 struct dc_link *link = connector->dc_link; 761 char *wr_buf = NULL; 762 uint32_t wr_buf_size = 100; 763 long param[11] = {0x0}; 764 int max_param_num = 11; 765 enum dp_test_pattern test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 766 bool disable_hpd = false; 767 bool supports_hpd = link->irq_source_hpd != DC_IRQ_SOURCE_INVALID; 768 bool valid_test_pattern = false; 769 uint8_t param_nums = 0; 770 /* init with default 80bit custom pattern */ 771 uint8_t custom_pattern[10] = { 772 0x1f, 0x7c, 0xf0, 0xc1, 0x07, 773 0x1f, 0x7c, 0xf0, 0xc1, 0x07 774 }; 775 struct dc_link_settings prefer_link_settings = {LANE_COUNT_UNKNOWN, 776 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 777 struct dc_link_settings cur_link_settings = {LANE_COUNT_UNKNOWN, 778 LINK_RATE_UNKNOWN, LINK_SPREAD_DISABLED}; 779 struct link_training_settings link_training_settings = {0}; 780 int i; 781 782 if (size == 0) 783 return -EINVAL; 784 785 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 786 if (!wr_buf) 787 return -ENOSPC; 788 789 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 790 (long *)param, buf, 791 max_param_num, 792 ¶m_nums)) { 793 kfree(wr_buf); 794 return -EINVAL; 795 } 796 797 if (param_nums <= 0) { 798 kfree(wr_buf); 799 DRM_DEBUG_DRIVER("user data not be read\n"); 800 return -EINVAL; 801 } 802 803 804 test_pattern = param[0]; 805 806 switch (test_pattern) { 807 case DP_TEST_PATTERN_VIDEO_MODE: 808 case DP_TEST_PATTERN_COLOR_SQUARES: 809 case DP_TEST_PATTERN_COLOR_SQUARES_CEA: 810 case DP_TEST_PATTERN_VERTICAL_BARS: 811 case DP_TEST_PATTERN_HORIZONTAL_BARS: 812 case DP_TEST_PATTERN_COLOR_RAMP: 813 valid_test_pattern = true; 814 break; 815 816 case DP_TEST_PATTERN_D102: 817 case DP_TEST_PATTERN_SYMBOL_ERROR: 818 case DP_TEST_PATTERN_PRBS7: 819 case DP_TEST_PATTERN_80BIT_CUSTOM: 820 case DP_TEST_PATTERN_HBR2_COMPLIANCE_EYE: 821 case DP_TEST_PATTERN_TRAINING_PATTERN4: 822 disable_hpd = true; 823 valid_test_pattern = true; 824 break; 825 826 default: 827 valid_test_pattern = false; 828 test_pattern = DP_TEST_PATTERN_UNSUPPORTED; 829 break; 830 } 831 832 if (!valid_test_pattern) { 833 kfree(wr_buf); 834 DRM_DEBUG_DRIVER("Invalid Test Pattern Parameters\n"); 835 return size; 836 } 837 838 if (test_pattern == DP_TEST_PATTERN_80BIT_CUSTOM) { 839 for (i = 0; i < 10; i++) { 840 if ((uint8_t) param[i + 1] != 0x0) 841 break; 842 } 843 844 if (i < 10) { 845 /* not use default value */ 846 for (i = 0; i < 10; i++) 847 custom_pattern[i] = (uint8_t) param[i + 1]; 848 } 849 } 850 851 /* Usage: set DP physical test pattern using debugfs with normal DP 852 * panel. Then plug out DP panel and connect a scope to measure 853 * For normal video mode and test pattern generated from CRCT, 854 * they are visibile to user. So do not disable HPD. 855 * Video Mode is also set to clear the test pattern, so enable HPD 856 * because it might have been disabled after a test pattern was set. 857 * AUX depends on HPD * sequence dependent, do not move! 858 */ 859 if (supports_hpd && !disable_hpd) 860 dc_link_enable_hpd(link); 861 862 prefer_link_settings.lane_count = link->verified_link_cap.lane_count; 863 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; 864 prefer_link_settings.link_spread = link->verified_link_cap.link_spread; 865 866 cur_link_settings.lane_count = link->cur_link_settings.lane_count; 867 cur_link_settings.link_rate = link->cur_link_settings.link_rate; 868 cur_link_settings.link_spread = link->cur_link_settings.link_spread; 869 870 link_training_settings.link_settings = cur_link_settings; 871 872 873 if (test_pattern != DP_TEST_PATTERN_VIDEO_MODE) { 874 if (prefer_link_settings.lane_count != LANE_COUNT_UNKNOWN && 875 prefer_link_settings.link_rate != LINK_RATE_UNKNOWN && 876 (prefer_link_settings.lane_count != cur_link_settings.lane_count || 877 prefer_link_settings.link_rate != cur_link_settings.link_rate)) 878 link_training_settings.link_settings = prefer_link_settings; 879 } 880 881 for (i = 0; i < (unsigned int)(link_training_settings.link_settings.lane_count); i++) 882 link_training_settings.hw_lane_settings[i] = link->cur_lane_setting[i]; 883 884 dc_link_dp_set_test_pattern( 885 link, 886 test_pattern, 887 DP_TEST_PATTERN_COLOR_SPACE_RGB, 888 &link_training_settings, 889 custom_pattern, 890 10); 891 892 /* Usage: Set DP physical test pattern using AMDDP with normal DP panel 893 * Then plug out DP panel and connect a scope to measure DP PHY signal. 894 * Need disable interrupt to avoid SW driver disable DP output. This is 895 * done after the test pattern is set. 896 */ 897 if (valid_test_pattern && supports_hpd && disable_hpd) 898 dc_link_disable_hpd(link); 899 900 kfree(wr_buf); 901 902 return size; 903 } 904 905 /* 906 * Returns the DMCUB tracebuffer contents. 907 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_tracebuffer 908 */ 909 static int dmub_tracebuffer_show(struct seq_file *m, void *data) 910 { 911 struct amdgpu_device *adev = m->private; 912 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 913 struct dmub_fw_meta_info *fw_meta_info = NULL; 914 struct dmub_debugfs_trace_entry *entries; 915 uint8_t *tbuf_base; 916 uint32_t tbuf_size, max_entries, num_entries, first_entry, i; 917 918 if (!fb_info) 919 return 0; 920 921 tbuf_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_5_TRACEBUFF].cpu_addr; 922 if (!tbuf_base) 923 return 0; 924 925 if (adev->dm.dmub_srv) 926 fw_meta_info = &adev->dm.dmub_srv->meta_info; 927 928 tbuf_size = fw_meta_info ? fw_meta_info->trace_buffer_size : 929 DMUB_TRACE_BUFFER_SIZE; 930 max_entries = (tbuf_size - sizeof(struct dmub_debugfs_trace_header)) / 931 sizeof(struct dmub_debugfs_trace_entry); 932 933 num_entries = 934 ((struct dmub_debugfs_trace_header *)tbuf_base)->entry_count; 935 936 /* DMCUB tracebuffer is a ring. If it rolled over, print a hint that 937 * entries are being overwritten. 938 */ 939 if (num_entries > max_entries) 940 seq_printf(m, "...\n"); 941 942 first_entry = num_entries % max_entries; 943 num_entries = min(num_entries, max_entries); 944 945 entries = (struct dmub_debugfs_trace_entry 946 *)(tbuf_base + 947 sizeof(struct dmub_debugfs_trace_header)); 948 949 /* To print entries chronologically, start from the first entry till the 950 * top of buffer, then from base of buffer to first entry. 951 */ 952 for (i = first_entry; i < num_entries; ++i) { 953 struct dmub_debugfs_trace_entry *entry = &entries[i]; 954 955 seq_printf(m, 956 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 957 entry->trace_code, entry->tick_count, entry->param0, 958 entry->param1); 959 } 960 for (i = 0; i < first_entry; ++i) { 961 struct dmub_debugfs_trace_entry *entry = &entries[i]; 962 963 seq_printf(m, 964 "trace_code=%u tick_count=%u param0=%u param1=%u\n", 965 entry->trace_code, entry->tick_count, entry->param0, 966 entry->param1); 967 } 968 969 return 0; 970 } 971 972 /* 973 * Returns the DMCUB firmware state contents. 974 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state 975 */ 976 static int dmub_fw_state_show(struct seq_file *m, void *data) 977 { 978 struct amdgpu_device *adev = m->private; 979 struct dmub_srv_fb_info *fb_info = adev->dm.dmub_fb_info; 980 uint8_t *state_base; 981 uint32_t state_size; 982 983 if (!fb_info) 984 return 0; 985 986 state_base = (uint8_t *)fb_info->fb[DMUB_WINDOW_6_FW_STATE].cpu_addr; 987 if (!state_base) 988 return 0; 989 990 state_size = fb_info->fb[DMUB_WINDOW_6_FW_STATE].size; 991 992 return seq_write(m, state_base, state_size); 993 } 994 995 /* replay_capability_show() - show eDP panel replay capability 996 * 997 * The read function: replay_capability_show 998 * Shows if sink and driver has Replay capability or not. 999 * 1000 * cat /sys/kernel/debug/dri/0/eDP-X/replay_capability 1001 * 1002 * Expected output: 1003 * "Sink support: no\n" - if panel doesn't support Replay 1004 * "Sink support: yes\n" - if panel supports Replay 1005 * "Driver support: no\n" - if driver doesn't support Replay 1006 * "Driver support: yes\n" - if driver supports Replay 1007 */ 1008 static int replay_capability_show(struct seq_file *m, void *data) 1009 { 1010 struct drm_connector *connector = m->private; 1011 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1012 struct dc_link *link = aconnector->dc_link; 1013 bool sink_support_replay = false; 1014 bool driver_support_replay = false; 1015 1016 if (!link) 1017 return -ENODEV; 1018 1019 if (link->type == dc_connection_none) 1020 return -ENODEV; 1021 1022 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 1023 return -ENODEV; 1024 1025 /* If Replay is already set to support, skip the checks */ 1026 if (link->replay_settings.config.replay_supported) { 1027 sink_support_replay = true; 1028 driver_support_replay = true; 1029 } else if ((amdgpu_dc_debug_mask & DC_DISABLE_REPLAY)) { 1030 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector); 1031 } else { 1032 struct dc *dc = link->ctx->dc; 1033 1034 sink_support_replay = amdgpu_dm_link_supports_replay(link, aconnector); 1035 if (dc->ctx->dmub_srv && dc->ctx->dmub_srv->dmub) 1036 driver_support_replay = 1037 (bool)dc->ctx->dmub_srv->dmub->feature_caps.replay_supported; 1038 } 1039 1040 seq_printf(m, "Sink support: %s\n", str_yes_no(sink_support_replay)); 1041 seq_printf(m, "Driver support: %s\n", str_yes_no(driver_support_replay)); 1042 seq_printf(m, "Config support: %s\n", str_yes_no(link->replay_settings.config.replay_supported)); 1043 1044 return 0; 1045 } 1046 1047 /* psr_capability_show() - show eDP panel PSR capability 1048 * 1049 * The read function: sink_psr_capability_show 1050 * Shows if sink has PSR capability or not. 1051 * If yes - the PSR version is appended 1052 * 1053 * cat /sys/kernel/debug/dri/0/eDP-X/psr_capability 1054 * 1055 * Expected output: 1056 * "Sink support: no\n" - if panel doesn't support PSR 1057 * "Sink support: yes [0x01]\n" - if panel supports PSR1 1058 * "Driver support: no\n" - if driver doesn't support PSR 1059 * "Driver support: yes [0x01]\n" - if driver supports PSR1 1060 */ 1061 static int psr_capability_show(struct seq_file *m, void *data) 1062 { 1063 struct drm_connector *connector = m->private; 1064 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1065 struct dc_link *link = aconnector->dc_link; 1066 1067 if (!link) 1068 return -ENODEV; 1069 1070 if (link->type == dc_connection_none) 1071 return -ENODEV; 1072 1073 if (!(link->connector_signal & SIGNAL_TYPE_EDP)) 1074 return -ENODEV; 1075 1076 seq_printf(m, "Sink support: %s", str_yes_no(link->dpcd_caps.psr_info.psr_version != 0)); 1077 if (link->dpcd_caps.psr_info.psr_version) 1078 seq_printf(m, " [0x%02x]", link->dpcd_caps.psr_info.psr_version); 1079 seq_puts(m, "\n"); 1080 1081 seq_printf(m, "Driver support: %s", str_yes_no(link->psr_settings.psr_feature_enabled)); 1082 if (link->psr_settings.psr_version) 1083 seq_printf(m, " [0x%02x]", link->psr_settings.psr_version); 1084 seq_puts(m, "\n"); 1085 1086 return 0; 1087 } 1088 1089 /* 1090 * Returns the current bpc for the crtc. 1091 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_bpc 1092 */ 1093 static int amdgpu_current_bpc_show(struct seq_file *m, void *data) 1094 { 1095 struct drm_crtc *crtc = m->private; 1096 struct drm_device *dev = crtc->dev; 1097 struct dm_crtc_state *dm_crtc_state = NULL; 1098 int res = -ENODEV; 1099 unsigned int bpc; 1100 1101 mutex_lock(&dev->mode_config.mutex); 1102 drm_modeset_lock(&crtc->mutex, NULL); 1103 if (crtc->state == NULL) 1104 goto unlock; 1105 1106 dm_crtc_state = to_dm_crtc_state(crtc->state); 1107 if (dm_crtc_state->stream == NULL) 1108 goto unlock; 1109 1110 switch (dm_crtc_state->stream->timing.display_color_depth) { 1111 case COLOR_DEPTH_666: 1112 bpc = 6; 1113 break; 1114 case COLOR_DEPTH_888: 1115 bpc = 8; 1116 break; 1117 case COLOR_DEPTH_101010: 1118 bpc = 10; 1119 break; 1120 case COLOR_DEPTH_121212: 1121 bpc = 12; 1122 break; 1123 case COLOR_DEPTH_161616: 1124 bpc = 16; 1125 break; 1126 default: 1127 goto unlock; 1128 } 1129 1130 seq_printf(m, "Current: %u\n", bpc); 1131 res = 0; 1132 1133 unlock: 1134 drm_modeset_unlock(&crtc->mutex); 1135 mutex_unlock(&dev->mode_config.mutex); 1136 1137 return res; 1138 } 1139 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_bpc); 1140 1141 /* 1142 * Returns the current colorspace for the crtc. 1143 * Example usage: cat /sys/kernel/debug/dri/0/crtc-0/amdgpu_current_colorspace 1144 */ 1145 static int amdgpu_current_colorspace_show(struct seq_file *m, void *data) 1146 { 1147 struct drm_crtc *crtc = m->private; 1148 struct drm_device *dev = crtc->dev; 1149 struct dm_crtc_state *dm_crtc_state = NULL; 1150 int res = -ENODEV; 1151 1152 mutex_lock(&dev->mode_config.mutex); 1153 drm_modeset_lock(&crtc->mutex, NULL); 1154 if (crtc->state == NULL) 1155 goto unlock; 1156 1157 dm_crtc_state = to_dm_crtc_state(crtc->state); 1158 if (dm_crtc_state->stream == NULL) 1159 goto unlock; 1160 1161 switch (dm_crtc_state->stream->output_color_space) { 1162 case COLOR_SPACE_SRGB: 1163 seq_puts(m, "sRGB"); 1164 break; 1165 case COLOR_SPACE_YCBCR601: 1166 case COLOR_SPACE_YCBCR601_LIMITED: 1167 seq_puts(m, "BT601_YCC"); 1168 break; 1169 case COLOR_SPACE_YCBCR709: 1170 case COLOR_SPACE_YCBCR709_LIMITED: 1171 seq_puts(m, "BT709_YCC"); 1172 break; 1173 case COLOR_SPACE_ADOBERGB: 1174 seq_puts(m, "opRGB"); 1175 break; 1176 case COLOR_SPACE_2020_RGB_FULLRANGE: 1177 seq_puts(m, "BT2020_RGB"); 1178 break; 1179 case COLOR_SPACE_2020_YCBCR_LIMITED: 1180 seq_puts(m, "BT2020_YCC"); 1181 break; 1182 default: 1183 goto unlock; 1184 } 1185 res = 0; 1186 1187 unlock: 1188 drm_modeset_unlock(&crtc->mutex); 1189 mutex_unlock(&dev->mode_config.mutex); 1190 1191 return res; 1192 } 1193 DEFINE_SHOW_ATTRIBUTE(amdgpu_current_colorspace); 1194 1195 1196 /* 1197 * Example usage: 1198 * Disable dsc passthrough, i.e.,: have dsc decoding at converver, not external RX 1199 * echo 1 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 1200 * Enable dsc passthrough, i.e.,: have dsc passthrough to external RX 1201 * echo 0 /sys/kernel/debug/dri/0/DP-1/dsc_disable_passthrough 1202 */ 1203 static ssize_t dp_dsc_passthrough_set(struct file *f, const char __user *buf, 1204 size_t size, loff_t *pos) 1205 { 1206 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1207 char *wr_buf = NULL; 1208 uint32_t wr_buf_size = 42; 1209 int max_param_num = 1; 1210 long param; 1211 uint8_t param_nums = 0; 1212 1213 if (size == 0) 1214 return -EINVAL; 1215 1216 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1217 1218 if (!wr_buf) { 1219 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1220 return -ENOSPC; 1221 } 1222 1223 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1224 ¶m, buf, 1225 max_param_num, 1226 ¶m_nums)) { 1227 kfree(wr_buf); 1228 return -EINVAL; 1229 } 1230 1231 aconnector->dsc_settings.dsc_force_disable_passthrough = param; 1232 1233 kfree(wr_buf); 1234 return 0; 1235 } 1236 1237 /* 1238 * Returns the HDCP capability of the Display (1.4 for now). 1239 * 1240 * NOTE* Not all HDMI displays report their HDCP caps even when they are capable. 1241 * Since its rare for a display to not be HDCP 1.4 capable, we set HDMI as always capable. 1242 * 1243 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/hdcp_sink_capability 1244 * or cat /sys/kernel/debug/dri/0/HDMI-A-1/hdcp_sink_capability 1245 */ 1246 static int hdcp_sink_capability_show(struct seq_file *m, void *data) 1247 { 1248 struct drm_connector *connector = m->private; 1249 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1250 bool hdcp_cap, hdcp2_cap; 1251 1252 if (connector->status != connector_status_connected) 1253 return -ENODEV; 1254 1255 seq_printf(m, "%s:%d HDCP version: ", connector->name, connector->base.id); 1256 1257 hdcp_cap = dc_link_is_hdcp14(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1258 hdcp2_cap = dc_link_is_hdcp22(aconnector->dc_link, aconnector->dc_sink->sink_signal); 1259 1260 1261 if (hdcp_cap) 1262 seq_printf(m, "%s ", "HDCP1.4"); 1263 if (hdcp2_cap) 1264 seq_printf(m, "%s ", "HDCP2.2"); 1265 1266 if (!hdcp_cap && !hdcp2_cap) 1267 seq_printf(m, "%s ", "None"); 1268 1269 seq_puts(m, "\n"); 1270 1271 return 0; 1272 } 1273 1274 /* 1275 * Returns whether the connected display is internal and not hotpluggable. 1276 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/internal_display 1277 */ 1278 static int internal_display_show(struct seq_file *m, void *data) 1279 { 1280 struct drm_connector *connector = m->private; 1281 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1282 struct dc_link *link = aconnector->dc_link; 1283 1284 seq_printf(m, "Internal: %u\n", link->is_internal_display); 1285 1286 return 0; 1287 } 1288 1289 /* 1290 * Returns the number of segments used if ODM Combine mode is enabled. 1291 * Example usage: cat /sys/kernel/debug/dri/0/DP-1/odm_combine_segments 1292 */ 1293 static int odm_combine_segments_show(struct seq_file *m, void *unused) 1294 { 1295 struct drm_connector *connector = m->private; 1296 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1297 struct dc_link *link = aconnector->dc_link; 1298 struct pipe_ctx *pipe_ctx = NULL; 1299 int i, segments = -EOPNOTSUPP; 1300 1301 for (i = 0; i < MAX_PIPES; i++) { 1302 pipe_ctx = &link->dc->current_state->res_ctx.pipe_ctx[i]; 1303 if (pipe_ctx->stream && 1304 pipe_ctx->stream->link == link) 1305 break; 1306 } 1307 1308 if (connector->status != connector_status_connected) 1309 return -ENODEV; 1310 1311 if (pipe_ctx && pipe_ctx->stream_res.tg && 1312 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments) 1313 pipe_ctx->stream_res.tg->funcs->get_odm_combine_segments(pipe_ctx->stream_res.tg, &segments); 1314 1315 seq_printf(m, "%d\n", segments); 1316 return 0; 1317 } 1318 1319 /* function description 1320 * 1321 * generic SDP message access for testing 1322 * 1323 * debugfs sdp_message is located at /syskernel/debug/dri/0/DP-x 1324 * 1325 * SDP header 1326 * Hb0 : Secondary-Data Packet ID 1327 * Hb1 : Secondary-Data Packet type 1328 * Hb2 : Secondary-Data-packet-specific header, Byte 0 1329 * Hb3 : Secondary-Data-packet-specific header, Byte 1 1330 * 1331 * for using custom sdp message: input 4 bytes SDP header and 32 bytes raw data 1332 */ 1333 static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *buf, 1334 size_t size, loff_t *pos) 1335 { 1336 int r; 1337 uint8_t data[36] = {0}; 1338 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 1339 struct dm_crtc_state *acrtc_state; 1340 uint32_t write_size = 36; 1341 1342 if (connector->base.status != connector_status_connected) 1343 return -ENODEV; 1344 1345 if (size == 0) 1346 return 0; 1347 1348 if (!connector->base.state || !connector->base.state->crtc) 1349 return -ENODEV; 1350 1351 acrtc_state = to_dm_crtc_state(connector->base.state->crtc->state); 1352 1353 write_size = min_t(size_t, size, sizeof(data)); 1354 1355 r = copy_from_user(data, buf, write_size); 1356 1357 write_size -= r; 1358 1359 dc_stream_send_dp_sdp(acrtc_state->stream, data, write_size); 1360 1361 return write_size; 1362 } 1363 1364 /* function: Read link's DSC & FEC capabilities 1365 * 1366 * 1367 * Access it with the following command (you need to specify 1368 * connector like DP-1): 1369 * 1370 * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support 1371 * 1372 */ 1373 static int dp_dsc_fec_support_show(struct seq_file *m, void *data) 1374 { 1375 struct drm_connector *connector = m->private; 1376 struct drm_modeset_acquire_ctx ctx; 1377 struct drm_device *dev = connector->dev; 1378 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 1379 int ret = 0; 1380 bool try_again = false; 1381 bool is_fec_supported = false; 1382 bool is_dsc_supported = false; 1383 struct dpcd_caps dpcd_caps; 1384 1385 drm_modeset_acquire_init(&ctx, DRM_MODESET_ACQUIRE_INTERRUPTIBLE); 1386 do { 1387 try_again = false; 1388 ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); 1389 if (ret) { 1390 if (ret == -EDEADLK) { 1391 ret = drm_modeset_backoff(&ctx); 1392 if (!ret) { 1393 try_again = true; 1394 continue; 1395 } 1396 } 1397 break; 1398 } 1399 if (connector->status != connector_status_connected) { 1400 ret = -ENODEV; 1401 break; 1402 } 1403 dpcd_caps = aconnector->dc_link->dpcd_caps; 1404 if (aconnector->mst_output_port) { 1405 /* aconnector sets dsc_aux during get_modes call 1406 * if MST connector has it means it can either 1407 * enable DSC on the sink device or on MST branch 1408 * its connected to. 1409 */ 1410 if (aconnector->dsc_aux) { 1411 is_fec_supported = true; 1412 is_dsc_supported = true; 1413 } 1414 } else { 1415 is_fec_supported = dpcd_caps.fec_cap.raw & 0x1; 1416 is_dsc_supported = dpcd_caps.dsc_caps.dsc_basic_caps.raw[0] & 0x1; 1417 } 1418 } while (try_again); 1419 1420 drm_modeset_drop_locks(&ctx); 1421 drm_modeset_acquire_fini(&ctx); 1422 1423 seq_printf(m, "FEC_Sink_Support: %s\n", str_yes_no(is_fec_supported)); 1424 seq_printf(m, "DSC_Sink_Support: %s\n", str_yes_no(is_dsc_supported)); 1425 1426 return ret; 1427 } 1428 1429 /* function: Trigger virtual HPD redetection on connector 1430 * 1431 * This function will perform link rediscovery, link disable 1432 * and enable, and dm connector state update. 1433 * 1434 * Retrigger HPD on an existing connector by echoing 1 into 1435 * its respectful "trigger_hotplug" debugfs entry: 1436 * 1437 * echo 1 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1438 * 1439 * This function can perform HPD unplug: 1440 * 1441 * echo 0 > /sys/kernel/debug/dri/0/DP-X/trigger_hotplug 1442 * 1443 */ 1444 static ssize_t trigger_hotplug(struct file *f, const char __user *buf, 1445 size_t size, loff_t *pos) 1446 { 1447 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1448 struct drm_connector *connector = &aconnector->base; 1449 struct dc_link *link = NULL; 1450 struct drm_device *dev = connector->dev; 1451 struct amdgpu_device *adev = drm_to_adev(dev); 1452 enum dc_connection_type new_connection_type = dc_connection_none; 1453 char *wr_buf = NULL; 1454 uint32_t wr_buf_size = 42; 1455 int max_param_num = 1; 1456 long param[1] = {0}; 1457 uint8_t param_nums = 0; 1458 bool ret = false; 1459 1460 if (!aconnector->dc_link) 1461 return -EINVAL; 1462 1463 if (size == 0) 1464 return -EINVAL; 1465 1466 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1467 1468 if (!wr_buf) { 1469 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1470 return -ENOSPC; 1471 } 1472 1473 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1474 (long *)param, buf, 1475 max_param_num, 1476 ¶m_nums)) { 1477 kfree(wr_buf); 1478 return -EINVAL; 1479 } 1480 1481 kfree(wr_buf); 1482 1483 if (param_nums <= 0) { 1484 DRM_DEBUG_DRIVER("user data not be read\n"); 1485 return -EINVAL; 1486 } 1487 1488 mutex_lock(&aconnector->hpd_lock); 1489 1490 /* Don't support for mst end device*/ 1491 if (aconnector->mst_root) { 1492 mutex_unlock(&aconnector->hpd_lock); 1493 return -EINVAL; 1494 } 1495 1496 if (param[0] == 1) { 1497 1498 if (!dc_link_detect_connection_type(aconnector->dc_link, &new_connection_type) && 1499 new_connection_type != dc_connection_none) 1500 goto unlock; 1501 1502 mutex_lock(&adev->dm.dc_lock); 1503 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 1504 mutex_unlock(&adev->dm.dc_lock); 1505 1506 if (!ret) 1507 goto unlock; 1508 1509 amdgpu_dm_update_connector_after_detect(aconnector); 1510 1511 drm_modeset_lock_all(dev); 1512 dm_restore_drm_connector_state(dev, connector); 1513 drm_modeset_unlock_all(dev); 1514 1515 drm_kms_helper_connector_hotplug_event(connector); 1516 } else if (param[0] == 0) { 1517 if (!aconnector->dc_link) 1518 goto unlock; 1519 1520 link = aconnector->dc_link; 1521 1522 if (link->local_sink) { 1523 dc_sink_release(link->local_sink); 1524 link->local_sink = NULL; 1525 } 1526 1527 link->dpcd_sink_count = 0; 1528 link->type = dc_connection_none; 1529 link->dongle_max_pix_clk = 0; 1530 1531 amdgpu_dm_update_connector_after_detect(aconnector); 1532 1533 /* If the aconnector is the root node in mst topology */ 1534 if (aconnector->mst_mgr.mst_state == true) 1535 dc_link_reset_cur_dp_mst_topology(link); 1536 1537 drm_modeset_lock_all(dev); 1538 dm_restore_drm_connector_state(dev, connector); 1539 drm_modeset_unlock_all(dev); 1540 1541 drm_kms_helper_connector_hotplug_event(connector); 1542 } 1543 1544 unlock: 1545 mutex_unlock(&aconnector->hpd_lock); 1546 1547 return size; 1548 } 1549 1550 /* function: read DSC status on the connector 1551 * 1552 * The read function: dp_dsc_clock_en_read 1553 * returns current status of DSC clock on the connector. 1554 * The return is a boolean flag: 1 or 0. 1555 * 1556 * Access it with the following command (you need to specify 1557 * connector like DP-1): 1558 * 1559 * cat /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1560 * 1561 * Expected output: 1562 * 1 - means that DSC is currently enabled 1563 * 0 - means that DSC is disabled 1564 */ 1565 static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, 1566 size_t size, loff_t *pos) 1567 { 1568 char *rd_buf = NULL; 1569 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1570 struct display_stream_compressor *dsc; 1571 struct dcn_dsc_state dsc_state = {0}; 1572 const uint32_t rd_buf_size = 10; 1573 struct pipe_ctx *pipe_ctx; 1574 ssize_t result = 0; 1575 int i, r, str_len = 10; 1576 1577 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1578 1579 if (!rd_buf) 1580 return -ENOMEM; 1581 1582 for (i = 0; i < MAX_PIPES; i++) { 1583 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1584 if (pipe_ctx->stream && 1585 pipe_ctx->stream->link == aconnector->dc_link && 1586 pipe_ctx->stream->sink && 1587 pipe_ctx->stream->sink == aconnector->dc_sink) 1588 break; 1589 } 1590 1591 dsc = pipe_ctx->stream_res.dsc; 1592 if (dsc) 1593 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1594 1595 snprintf(rd_buf, str_len, 1596 "%d\n", 1597 dsc_state.dsc_clock_en); 1598 1599 while (size) { 1600 if (*pos >= rd_buf_size) 1601 break; 1602 1603 r = put_user(*(rd_buf + result), buf); 1604 if (r) { 1605 kfree(rd_buf); 1606 return r; /* r = -EFAULT */ 1607 } 1608 1609 buf += 1; 1610 size -= 1; 1611 *pos += 1; 1612 result += 1; 1613 } 1614 1615 kfree(rd_buf); 1616 return result; 1617 } 1618 1619 /* function: write force DSC on the connector 1620 * 1621 * The write function: dp_dsc_clock_en_write 1622 * enables to force DSC on the connector. 1623 * User can write to either force enable or force disable DSC 1624 * on the next modeset or set it to driver default 1625 * 1626 * Accepted inputs: 1627 * 0 - default DSC enablement policy 1628 * 1 - force enable DSC on the connector 1629 * 2 - force disable DSC on the connector (might cause fail in atomic_check) 1630 * 1631 * Writing DSC settings is done with the following command: 1632 * - To force enable DSC (you need to specify 1633 * connector like DP-1): 1634 * 1635 * echo 0x1 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1636 * 1637 * - To return to default state set the flag to zero and 1638 * let driver deal with DSC automatically 1639 * (you need to specify connector like DP-1): 1640 * 1641 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_clock_en 1642 * 1643 */ 1644 static ssize_t dp_dsc_clock_en_write(struct file *f, const char __user *buf, 1645 size_t size, loff_t *pos) 1646 { 1647 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1648 struct drm_connector *connector = &aconnector->base; 1649 struct drm_device *dev = connector->dev; 1650 struct drm_crtc *crtc = NULL; 1651 struct dm_crtc_state *dm_crtc_state = NULL; 1652 struct pipe_ctx *pipe_ctx; 1653 int i; 1654 char *wr_buf = NULL; 1655 uint32_t wr_buf_size = 42; 1656 int max_param_num = 1; 1657 long param[1] = {0}; 1658 uint8_t param_nums = 0; 1659 1660 if (size == 0) 1661 return -EINVAL; 1662 1663 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1664 1665 if (!wr_buf) { 1666 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1667 return -ENOSPC; 1668 } 1669 1670 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1671 (long *)param, buf, 1672 max_param_num, 1673 ¶m_nums)) { 1674 kfree(wr_buf); 1675 return -EINVAL; 1676 } 1677 1678 if (param_nums <= 0) { 1679 DRM_DEBUG_DRIVER("user data not be read\n"); 1680 kfree(wr_buf); 1681 return -EINVAL; 1682 } 1683 1684 for (i = 0; i < MAX_PIPES; i++) { 1685 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1686 if (pipe_ctx->stream && 1687 pipe_ctx->stream->link == aconnector->dc_link && 1688 pipe_ctx->stream->sink && 1689 pipe_ctx->stream->sink == aconnector->dc_sink) 1690 break; 1691 } 1692 1693 if (!pipe_ctx->stream) 1694 goto done; 1695 1696 // Get CRTC state 1697 mutex_lock(&dev->mode_config.mutex); 1698 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1699 1700 if (connector->state == NULL) 1701 goto unlock; 1702 1703 crtc = connector->state->crtc; 1704 if (crtc == NULL) 1705 goto unlock; 1706 1707 drm_modeset_lock(&crtc->mutex, NULL); 1708 if (crtc->state == NULL) 1709 goto unlock; 1710 1711 dm_crtc_state = to_dm_crtc_state(crtc->state); 1712 if (dm_crtc_state->stream == NULL) 1713 goto unlock; 1714 1715 if (param[0] == 1) 1716 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_ENABLE; 1717 else if (param[0] == 2) 1718 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DISABLE; 1719 else 1720 aconnector->dsc_settings.dsc_force_enable = DSC_CLK_FORCE_DEFAULT; 1721 1722 dm_crtc_state->dsc_force_changed = true; 1723 1724 unlock: 1725 if (crtc) 1726 drm_modeset_unlock(&crtc->mutex); 1727 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1728 mutex_unlock(&dev->mode_config.mutex); 1729 1730 done: 1731 kfree(wr_buf); 1732 return size; 1733 } 1734 1735 /* function: read DSC slice width parameter on the connector 1736 * 1737 * The read function: dp_dsc_slice_width_read 1738 * returns dsc slice width used in the current configuration 1739 * The return is an integer: 0 or other positive number 1740 * 1741 * Access the status with the following command: 1742 * 1743 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1744 * 1745 * 0 - means that DSC is disabled 1746 * 1747 * Any other number more than zero represents the 1748 * slice width currently used by DSC in pixels 1749 * 1750 */ 1751 static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, 1752 size_t size, loff_t *pos) 1753 { 1754 char *rd_buf = NULL; 1755 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1756 struct display_stream_compressor *dsc; 1757 struct dcn_dsc_state dsc_state = {0}; 1758 const uint32_t rd_buf_size = 100; 1759 struct pipe_ctx *pipe_ctx; 1760 ssize_t result = 0; 1761 int i, r, str_len = 30; 1762 1763 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1764 1765 if (!rd_buf) 1766 return -ENOMEM; 1767 1768 for (i = 0; i < MAX_PIPES; i++) { 1769 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1770 if (pipe_ctx->stream && 1771 pipe_ctx->stream->link == aconnector->dc_link && 1772 pipe_ctx->stream->sink && 1773 pipe_ctx->stream->sink == aconnector->dc_sink) 1774 break; 1775 } 1776 1777 dsc = pipe_ctx->stream_res.dsc; 1778 if (dsc) 1779 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1780 1781 snprintf(rd_buf, str_len, 1782 "%d\n", 1783 dsc_state.dsc_slice_width); 1784 1785 while (size) { 1786 if (*pos >= rd_buf_size) 1787 break; 1788 1789 r = put_user(*(rd_buf + result), buf); 1790 if (r) { 1791 kfree(rd_buf); 1792 return r; /* r = -EFAULT */ 1793 } 1794 1795 buf += 1; 1796 size -= 1; 1797 *pos += 1; 1798 result += 1; 1799 } 1800 1801 kfree(rd_buf); 1802 return result; 1803 } 1804 1805 /* function: write DSC slice width parameter 1806 * 1807 * The write function: dp_dsc_slice_width_write 1808 * overwrites automatically generated DSC configuration 1809 * of slice width. 1810 * 1811 * The user has to write the slice width divisible by the 1812 * picture width. 1813 * 1814 * Also the user has to write width in hexidecimal 1815 * rather than in decimal. 1816 * 1817 * Writing DSC settings is done with the following command: 1818 * - To force overwrite slice width: (example sets to 1920 pixels) 1819 * 1820 * echo 0x780 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1821 * 1822 * - To stop overwriting and let driver find the optimal size, 1823 * set the width to zero: 1824 * 1825 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_width 1826 * 1827 */ 1828 static ssize_t dp_dsc_slice_width_write(struct file *f, const char __user *buf, 1829 size_t size, loff_t *pos) 1830 { 1831 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1832 struct pipe_ctx *pipe_ctx; 1833 struct drm_connector *connector = &aconnector->base; 1834 struct drm_device *dev = connector->dev; 1835 struct drm_crtc *crtc = NULL; 1836 struct dm_crtc_state *dm_crtc_state = NULL; 1837 int i; 1838 char *wr_buf = NULL; 1839 uint32_t wr_buf_size = 42; 1840 int max_param_num = 1; 1841 long param[1] = {0}; 1842 uint8_t param_nums = 0; 1843 1844 if (size == 0) 1845 return -EINVAL; 1846 1847 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 1848 1849 if (!wr_buf) { 1850 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 1851 return -ENOSPC; 1852 } 1853 1854 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 1855 (long *)param, buf, 1856 max_param_num, 1857 ¶m_nums)) { 1858 kfree(wr_buf); 1859 return -EINVAL; 1860 } 1861 1862 if (param_nums <= 0) { 1863 DRM_DEBUG_DRIVER("user data not be read\n"); 1864 kfree(wr_buf); 1865 return -EINVAL; 1866 } 1867 1868 for (i = 0; i < MAX_PIPES; i++) { 1869 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1870 if (pipe_ctx->stream && 1871 pipe_ctx->stream->link == aconnector->dc_link && 1872 pipe_ctx->stream->sink && 1873 pipe_ctx->stream->sink == aconnector->dc_sink) 1874 break; 1875 } 1876 1877 if (!pipe_ctx->stream) 1878 goto done; 1879 1880 // Safely get CRTC state 1881 mutex_lock(&dev->mode_config.mutex); 1882 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 1883 1884 if (connector->state == NULL) 1885 goto unlock; 1886 1887 crtc = connector->state->crtc; 1888 if (crtc == NULL) 1889 goto unlock; 1890 1891 drm_modeset_lock(&crtc->mutex, NULL); 1892 if (crtc->state == NULL) 1893 goto unlock; 1894 1895 dm_crtc_state = to_dm_crtc_state(crtc->state); 1896 if (dm_crtc_state->stream == NULL) 1897 goto unlock; 1898 1899 if (param[0] > 0) 1900 aconnector->dsc_settings.dsc_num_slices_h = DIV_ROUND_UP( 1901 pipe_ctx->stream->timing.h_addressable, 1902 param[0]); 1903 else 1904 aconnector->dsc_settings.dsc_num_slices_h = 0; 1905 1906 dm_crtc_state->dsc_force_changed = true; 1907 1908 unlock: 1909 if (crtc) 1910 drm_modeset_unlock(&crtc->mutex); 1911 drm_modeset_unlock(&dev->mode_config.connection_mutex); 1912 mutex_unlock(&dev->mode_config.mutex); 1913 1914 done: 1915 kfree(wr_buf); 1916 return size; 1917 } 1918 1919 /* function: read DSC slice height parameter on the connector 1920 * 1921 * The read function: dp_dsc_slice_height_read 1922 * returns dsc slice height used in the current configuration 1923 * The return is an integer: 0 or other positive number 1924 * 1925 * Access the status with the following command: 1926 * 1927 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 1928 * 1929 * 0 - means that DSC is disabled 1930 * 1931 * Any other number more than zero represents the 1932 * slice height currently used by DSC in pixels 1933 * 1934 */ 1935 static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, 1936 size_t size, loff_t *pos) 1937 { 1938 char *rd_buf = NULL; 1939 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 1940 struct display_stream_compressor *dsc; 1941 struct dcn_dsc_state dsc_state = {0}; 1942 const uint32_t rd_buf_size = 100; 1943 struct pipe_ctx *pipe_ctx; 1944 ssize_t result = 0; 1945 int i, r, str_len = 30; 1946 1947 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 1948 1949 if (!rd_buf) 1950 return -ENOMEM; 1951 1952 for (i = 0; i < MAX_PIPES; i++) { 1953 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 1954 if (pipe_ctx->stream && 1955 pipe_ctx->stream->link == aconnector->dc_link && 1956 pipe_ctx->stream->sink && 1957 pipe_ctx->stream->sink == aconnector->dc_sink) 1958 break; 1959 } 1960 1961 dsc = pipe_ctx->stream_res.dsc; 1962 if (dsc) 1963 dsc->funcs->dsc_read_state(dsc, &dsc_state); 1964 1965 snprintf(rd_buf, str_len, 1966 "%d\n", 1967 dsc_state.dsc_slice_height); 1968 1969 while (size) { 1970 if (*pos >= rd_buf_size) 1971 break; 1972 1973 r = put_user(*(rd_buf + result), buf); 1974 if (r) { 1975 kfree(rd_buf); 1976 return r; /* r = -EFAULT */ 1977 } 1978 1979 buf += 1; 1980 size -= 1; 1981 *pos += 1; 1982 result += 1; 1983 } 1984 1985 kfree(rd_buf); 1986 return result; 1987 } 1988 1989 /* function: write DSC slice height parameter 1990 * 1991 * The write function: dp_dsc_slice_height_write 1992 * overwrites automatically generated DSC configuration 1993 * of slice height. 1994 * 1995 * The user has to write the slice height divisible by the 1996 * picture height. 1997 * 1998 * Also the user has to write height in hexidecimal 1999 * rather than in decimal. 2000 * 2001 * Writing DSC settings is done with the following command: 2002 * - To force overwrite slice height (example sets to 128 pixels): 2003 * 2004 * echo 0x80 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 2005 * 2006 * - To stop overwriting and let driver find the optimal size, 2007 * set the height to zero: 2008 * 2009 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_slice_height 2010 * 2011 */ 2012 static ssize_t dp_dsc_slice_height_write(struct file *f, const char __user *buf, 2013 size_t size, loff_t *pos) 2014 { 2015 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2016 struct drm_connector *connector = &aconnector->base; 2017 struct drm_device *dev = connector->dev; 2018 struct drm_crtc *crtc = NULL; 2019 struct dm_crtc_state *dm_crtc_state = NULL; 2020 struct pipe_ctx *pipe_ctx; 2021 int i; 2022 char *wr_buf = NULL; 2023 uint32_t wr_buf_size = 42; 2024 int max_param_num = 1; 2025 uint8_t param_nums = 0; 2026 long param[1] = {0}; 2027 2028 if (size == 0) 2029 return -EINVAL; 2030 2031 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2032 2033 if (!wr_buf) { 2034 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2035 return -ENOSPC; 2036 } 2037 2038 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2039 (long *)param, buf, 2040 max_param_num, 2041 ¶m_nums)) { 2042 kfree(wr_buf); 2043 return -EINVAL; 2044 } 2045 2046 if (param_nums <= 0) { 2047 DRM_DEBUG_DRIVER("user data not be read\n"); 2048 kfree(wr_buf); 2049 return -EINVAL; 2050 } 2051 2052 for (i = 0; i < MAX_PIPES; i++) { 2053 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2054 if (pipe_ctx->stream && 2055 pipe_ctx->stream->link == aconnector->dc_link && 2056 pipe_ctx->stream->sink && 2057 pipe_ctx->stream->sink == aconnector->dc_sink) 2058 break; 2059 } 2060 2061 if (!pipe_ctx->stream) 2062 goto done; 2063 2064 // Get CRTC state 2065 mutex_lock(&dev->mode_config.mutex); 2066 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2067 2068 if (connector->state == NULL) 2069 goto unlock; 2070 2071 crtc = connector->state->crtc; 2072 if (crtc == NULL) 2073 goto unlock; 2074 2075 drm_modeset_lock(&crtc->mutex, NULL); 2076 if (crtc->state == NULL) 2077 goto unlock; 2078 2079 dm_crtc_state = to_dm_crtc_state(crtc->state); 2080 if (dm_crtc_state->stream == NULL) 2081 goto unlock; 2082 2083 if (param[0] > 0) 2084 aconnector->dsc_settings.dsc_num_slices_v = DIV_ROUND_UP( 2085 pipe_ctx->stream->timing.v_addressable, 2086 param[0]); 2087 else 2088 aconnector->dsc_settings.dsc_num_slices_v = 0; 2089 2090 dm_crtc_state->dsc_force_changed = true; 2091 2092 unlock: 2093 if (crtc) 2094 drm_modeset_unlock(&crtc->mutex); 2095 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2096 mutex_unlock(&dev->mode_config.mutex); 2097 2098 done: 2099 kfree(wr_buf); 2100 return size; 2101 } 2102 2103 /* function: read DSC target rate on the connector in bits per pixel 2104 * 2105 * The read function: dp_dsc_bits_per_pixel_read 2106 * returns target rate of compression in bits per pixel 2107 * The return is an integer: 0 or other positive integer 2108 * 2109 * Access it with the following command: 2110 * 2111 * cat /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2112 * 2113 * 0 - means that DSC is disabled 2114 */ 2115 static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, 2116 size_t size, loff_t *pos) 2117 { 2118 char *rd_buf = NULL; 2119 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2120 struct display_stream_compressor *dsc; 2121 struct dcn_dsc_state dsc_state = {0}; 2122 const uint32_t rd_buf_size = 100; 2123 struct pipe_ctx *pipe_ctx; 2124 ssize_t result = 0; 2125 int i, r, str_len = 30; 2126 2127 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2128 2129 if (!rd_buf) 2130 return -ENOMEM; 2131 2132 for (i = 0; i < MAX_PIPES; i++) { 2133 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2134 if (pipe_ctx->stream && 2135 pipe_ctx->stream->link == aconnector->dc_link && 2136 pipe_ctx->stream->sink && 2137 pipe_ctx->stream->sink == aconnector->dc_sink) 2138 break; 2139 } 2140 2141 dsc = pipe_ctx->stream_res.dsc; 2142 if (dsc) 2143 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2144 2145 snprintf(rd_buf, str_len, 2146 "%d\n", 2147 dsc_state.dsc_bits_per_pixel); 2148 2149 while (size) { 2150 if (*pos >= rd_buf_size) 2151 break; 2152 2153 r = put_user(*(rd_buf + result), buf); 2154 if (r) { 2155 kfree(rd_buf); 2156 return r; /* r = -EFAULT */ 2157 } 2158 2159 buf += 1; 2160 size -= 1; 2161 *pos += 1; 2162 result += 1; 2163 } 2164 2165 kfree(rd_buf); 2166 return result; 2167 } 2168 2169 /* function: write DSC target rate in bits per pixel 2170 * 2171 * The write function: dp_dsc_bits_per_pixel_write 2172 * overwrites automatically generated DSC configuration 2173 * of DSC target bit rate. 2174 * 2175 * Also the user has to write bpp in hexidecimal 2176 * rather than in decimal. 2177 * 2178 * Writing DSC settings is done with the following command: 2179 * - To force overwrite rate (example sets to 256 bpp x 1/16): 2180 * 2181 * echo 0x100 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2182 * 2183 * - To stop overwriting and let driver find the optimal rate, 2184 * set the rate to zero: 2185 * 2186 * echo 0x0 > /sys/kernel/debug/dri/0/DP-X/dsc_bits_per_pixel 2187 * 2188 */ 2189 static ssize_t dp_dsc_bits_per_pixel_write(struct file *f, const char __user *buf, 2190 size_t size, loff_t *pos) 2191 { 2192 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2193 struct drm_connector *connector = &aconnector->base; 2194 struct drm_device *dev = connector->dev; 2195 struct drm_crtc *crtc = NULL; 2196 struct dm_crtc_state *dm_crtc_state = NULL; 2197 struct pipe_ctx *pipe_ctx; 2198 int i; 2199 char *wr_buf = NULL; 2200 uint32_t wr_buf_size = 42; 2201 int max_param_num = 1; 2202 uint8_t param_nums = 0; 2203 long param[1] = {0}; 2204 2205 if (size == 0) 2206 return -EINVAL; 2207 2208 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2209 2210 if (!wr_buf) { 2211 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2212 return -ENOSPC; 2213 } 2214 2215 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2216 (long *)param, buf, 2217 max_param_num, 2218 ¶m_nums)) { 2219 kfree(wr_buf); 2220 return -EINVAL; 2221 } 2222 2223 if (param_nums <= 0) { 2224 DRM_DEBUG_DRIVER("user data not be read\n"); 2225 kfree(wr_buf); 2226 return -EINVAL; 2227 } 2228 2229 for (i = 0; i < MAX_PIPES; i++) { 2230 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2231 if (pipe_ctx->stream && 2232 pipe_ctx->stream->link == aconnector->dc_link && 2233 pipe_ctx->stream->sink && 2234 pipe_ctx->stream->sink == aconnector->dc_sink) 2235 break; 2236 } 2237 2238 if (!pipe_ctx->stream) 2239 goto done; 2240 2241 // Get CRTC state 2242 mutex_lock(&dev->mode_config.mutex); 2243 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2244 2245 if (connector->state == NULL) 2246 goto unlock; 2247 2248 crtc = connector->state->crtc; 2249 if (crtc == NULL) 2250 goto unlock; 2251 2252 drm_modeset_lock(&crtc->mutex, NULL); 2253 if (crtc->state == NULL) 2254 goto unlock; 2255 2256 dm_crtc_state = to_dm_crtc_state(crtc->state); 2257 if (dm_crtc_state->stream == NULL) 2258 goto unlock; 2259 2260 aconnector->dsc_settings.dsc_bits_per_pixel = param[0]; 2261 2262 dm_crtc_state->dsc_force_changed = true; 2263 2264 unlock: 2265 if (crtc) 2266 drm_modeset_unlock(&crtc->mutex); 2267 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2268 mutex_unlock(&dev->mode_config.mutex); 2269 2270 done: 2271 kfree(wr_buf); 2272 return size; 2273 } 2274 2275 /* function: read DSC picture width parameter on the connector 2276 * 2277 * The read function: dp_dsc_pic_width_read 2278 * returns dsc picture width used in the current configuration 2279 * It is the same as h_addressable of the current 2280 * display's timing 2281 * The return is an integer: 0 or other positive integer 2282 * If 0 then DSC is disabled. 2283 * 2284 * Access it with the following command: 2285 * 2286 * cat /sys/kernel/debug/dri/0/DP-X/dsc_pic_width 2287 * 2288 * 0 - means that DSC is disabled 2289 */ 2290 static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, 2291 size_t size, loff_t *pos) 2292 { 2293 char *rd_buf = NULL; 2294 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2295 struct display_stream_compressor *dsc; 2296 struct dcn_dsc_state dsc_state = {0}; 2297 const uint32_t rd_buf_size = 100; 2298 struct pipe_ctx *pipe_ctx; 2299 ssize_t result = 0; 2300 int i, r, str_len = 30; 2301 2302 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2303 2304 if (!rd_buf) 2305 return -ENOMEM; 2306 2307 for (i = 0; i < MAX_PIPES; i++) { 2308 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2309 if (pipe_ctx->stream && 2310 pipe_ctx->stream->link == aconnector->dc_link && 2311 pipe_ctx->stream->sink && 2312 pipe_ctx->stream->sink == aconnector->dc_sink) 2313 break; 2314 } 2315 2316 dsc = pipe_ctx->stream_res.dsc; 2317 if (dsc) 2318 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2319 2320 snprintf(rd_buf, str_len, 2321 "%d\n", 2322 dsc_state.dsc_pic_width); 2323 2324 while (size) { 2325 if (*pos >= rd_buf_size) 2326 break; 2327 2328 r = put_user(*(rd_buf + result), buf); 2329 if (r) { 2330 kfree(rd_buf); 2331 return r; /* r = -EFAULT */ 2332 } 2333 2334 buf += 1; 2335 size -= 1; 2336 *pos += 1; 2337 result += 1; 2338 } 2339 2340 kfree(rd_buf); 2341 return result; 2342 } 2343 2344 static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, 2345 size_t size, loff_t *pos) 2346 { 2347 char *rd_buf = NULL; 2348 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2349 struct display_stream_compressor *dsc; 2350 struct dcn_dsc_state dsc_state = {0}; 2351 const uint32_t rd_buf_size = 100; 2352 struct pipe_ctx *pipe_ctx; 2353 ssize_t result = 0; 2354 int i, r, str_len = 30; 2355 2356 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2357 2358 if (!rd_buf) 2359 return -ENOMEM; 2360 2361 for (i = 0; i < MAX_PIPES; i++) { 2362 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2363 if (pipe_ctx->stream && 2364 pipe_ctx->stream->link == aconnector->dc_link && 2365 pipe_ctx->stream->sink && 2366 pipe_ctx->stream->sink == aconnector->dc_sink) 2367 break; 2368 } 2369 2370 dsc = pipe_ctx->stream_res.dsc; 2371 if (dsc) 2372 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2373 2374 snprintf(rd_buf, str_len, 2375 "%d\n", 2376 dsc_state.dsc_pic_height); 2377 2378 while (size) { 2379 if (*pos >= rd_buf_size) 2380 break; 2381 2382 r = put_user(*(rd_buf + result), buf); 2383 if (r) { 2384 kfree(rd_buf); 2385 return r; /* r = -EFAULT */ 2386 } 2387 2388 buf += 1; 2389 size -= 1; 2390 *pos += 1; 2391 result += 1; 2392 } 2393 2394 kfree(rd_buf); 2395 return result; 2396 } 2397 2398 /* function: read DSC chunk size parameter on the connector 2399 * 2400 * The read function: dp_dsc_chunk_size_read 2401 * returns dsc chunk size set in the current configuration 2402 * The value is calculated automatically by DSC code 2403 * and depends on slice parameters and bpp target rate 2404 * The return is an integer: 0 or other positive integer 2405 * If 0 then DSC is disabled. 2406 * 2407 * Access it with the following command: 2408 * 2409 * cat /sys/kernel/debug/dri/0/DP-X/dsc_chunk_size 2410 * 2411 * 0 - means that DSC is disabled 2412 */ 2413 static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, 2414 size_t size, loff_t *pos) 2415 { 2416 char *rd_buf = NULL; 2417 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2418 struct display_stream_compressor *dsc; 2419 struct dcn_dsc_state dsc_state = {0}; 2420 const uint32_t rd_buf_size = 100; 2421 struct pipe_ctx *pipe_ctx; 2422 ssize_t result = 0; 2423 int i, r, str_len = 30; 2424 2425 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2426 2427 if (!rd_buf) 2428 return -ENOMEM; 2429 2430 for (i = 0; i < MAX_PIPES; i++) { 2431 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2432 if (pipe_ctx->stream && 2433 pipe_ctx->stream->link == aconnector->dc_link && 2434 pipe_ctx->stream->sink && 2435 pipe_ctx->stream->sink == aconnector->dc_sink) 2436 break; 2437 } 2438 2439 dsc = pipe_ctx->stream_res.dsc; 2440 if (dsc) 2441 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2442 2443 snprintf(rd_buf, str_len, 2444 "%d\n", 2445 dsc_state.dsc_chunk_size); 2446 2447 while (size) { 2448 if (*pos >= rd_buf_size) 2449 break; 2450 2451 r = put_user(*(rd_buf + result), buf); 2452 if (r) { 2453 kfree(rd_buf); 2454 return r; /* r = -EFAULT */ 2455 } 2456 2457 buf += 1; 2458 size -= 1; 2459 *pos += 1; 2460 result += 1; 2461 } 2462 2463 kfree(rd_buf); 2464 return result; 2465 } 2466 2467 /* function: read DSC slice bpg offset on the connector 2468 * 2469 * The read function: dp_dsc_slice_bpg_offset_read 2470 * returns dsc bpg slice offset set in the current configuration 2471 * The value is calculated automatically by DSC code 2472 * and depends on slice parameters and bpp target rate 2473 * The return is an integer: 0 or other positive integer 2474 * If 0 then DSC is disabled. 2475 * 2476 * Access it with the following command: 2477 * 2478 * cat /sys/kernel/debug/dri/0/DP-X/dsc_slice_bpg_offset 2479 * 2480 * 0 - means that DSC is disabled 2481 */ 2482 static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, 2483 size_t size, loff_t *pos) 2484 { 2485 char *rd_buf = NULL; 2486 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2487 struct display_stream_compressor *dsc; 2488 struct dcn_dsc_state dsc_state = {0}; 2489 const uint32_t rd_buf_size = 100; 2490 struct pipe_ctx *pipe_ctx; 2491 ssize_t result = 0; 2492 int i, r, str_len = 30; 2493 2494 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2495 2496 if (!rd_buf) 2497 return -ENOMEM; 2498 2499 for (i = 0; i < MAX_PIPES; i++) { 2500 pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; 2501 if (pipe_ctx->stream && 2502 pipe_ctx->stream->link == aconnector->dc_link && 2503 pipe_ctx->stream->sink && 2504 pipe_ctx->stream->sink == aconnector->dc_sink) 2505 break; 2506 } 2507 2508 dsc = pipe_ctx->stream_res.dsc; 2509 if (dsc) 2510 dsc->funcs->dsc_read_state(dsc, &dsc_state); 2511 2512 snprintf(rd_buf, str_len, 2513 "%d\n", 2514 dsc_state.dsc_slice_bpg_offset); 2515 2516 while (size) { 2517 if (*pos >= rd_buf_size) 2518 break; 2519 2520 r = put_user(*(rd_buf + result), buf); 2521 if (r) { 2522 kfree(rd_buf); 2523 return r; /* r = -EFAULT */ 2524 } 2525 2526 buf += 1; 2527 size -= 1; 2528 *pos += 1; 2529 result += 1; 2530 } 2531 2532 kfree(rd_buf); 2533 return result; 2534 } 2535 2536 2537 /* 2538 * function description: Read max_requested_bpc property from the connector 2539 * 2540 * Access it with the following command: 2541 * 2542 * cat /sys/kernel/debug/dri/0/DP-X/max_bpc 2543 * 2544 */ 2545 static ssize_t dp_max_bpc_read(struct file *f, char __user *buf, 2546 size_t size, loff_t *pos) 2547 { 2548 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2549 struct drm_connector *connector = &aconnector->base; 2550 struct drm_device *dev = connector->dev; 2551 struct dm_connector_state *state; 2552 ssize_t result = 0; 2553 char *rd_buf = NULL; 2554 char *rd_buf_ptr = NULL; 2555 const uint32_t rd_buf_size = 10; 2556 int r; 2557 2558 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 2559 2560 if (!rd_buf) 2561 return -ENOMEM; 2562 2563 mutex_lock(&dev->mode_config.mutex); 2564 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2565 2566 if (connector->state == NULL) 2567 goto unlock; 2568 2569 state = to_dm_connector_state(connector->state); 2570 2571 rd_buf_ptr = rd_buf; 2572 snprintf(rd_buf_ptr, rd_buf_size, 2573 "%u\n", 2574 state->base.max_requested_bpc); 2575 2576 while (size) { 2577 if (*pos >= rd_buf_size) 2578 break; 2579 2580 r = put_user(*(rd_buf + result), buf); 2581 if (r) { 2582 result = r; /* r = -EFAULT */ 2583 goto unlock; 2584 } 2585 buf += 1; 2586 size -= 1; 2587 *pos += 1; 2588 result += 1; 2589 } 2590 unlock: 2591 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2592 mutex_unlock(&dev->mode_config.mutex); 2593 kfree(rd_buf); 2594 return result; 2595 } 2596 2597 2598 /* 2599 * function description: Set max_requested_bpc property on the connector 2600 * 2601 * This function will not force the input BPC on connector, it will only 2602 * change the max value. This is equivalent to setting max_bpc through 2603 * xrandr. 2604 * 2605 * The BPC value written must be >= 6 and <= 16. Values outside of this 2606 * range will result in errors. 2607 * 2608 * BPC values: 2609 * 0x6 - 6 BPC 2610 * 0x8 - 8 BPC 2611 * 0xa - 10 BPC 2612 * 0xc - 12 BPC 2613 * 0x10 - 16 BPC 2614 * 2615 * Write the max_bpc in the following way: 2616 * 2617 * echo 0x6 > /sys/kernel/debug/dri/0/DP-X/max_bpc 2618 * 2619 */ 2620 static ssize_t dp_max_bpc_write(struct file *f, const char __user *buf, 2621 size_t size, loff_t *pos) 2622 { 2623 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2624 struct drm_connector *connector = &aconnector->base; 2625 struct dm_connector_state *state; 2626 struct drm_device *dev = connector->dev; 2627 char *wr_buf = NULL; 2628 uint32_t wr_buf_size = 42; 2629 int max_param_num = 1; 2630 long param[1] = {0}; 2631 uint8_t param_nums = 0; 2632 2633 if (size == 0) 2634 return -EINVAL; 2635 2636 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 2637 2638 if (!wr_buf) { 2639 DRM_DEBUG_DRIVER("no memory to allocate write buffer\n"); 2640 return -ENOSPC; 2641 } 2642 2643 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 2644 (long *)param, buf, 2645 max_param_num, 2646 ¶m_nums)) { 2647 kfree(wr_buf); 2648 return -EINVAL; 2649 } 2650 2651 if (param_nums <= 0) { 2652 DRM_DEBUG_DRIVER("user data not be read\n"); 2653 kfree(wr_buf); 2654 return -EINVAL; 2655 } 2656 2657 if (param[0] < 6 || param[0] > 16) { 2658 DRM_DEBUG_DRIVER("bad max_bpc value\n"); 2659 kfree(wr_buf); 2660 return -EINVAL; 2661 } 2662 2663 mutex_lock(&dev->mode_config.mutex); 2664 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); 2665 2666 if (connector->state == NULL) 2667 goto unlock; 2668 2669 state = to_dm_connector_state(connector->state); 2670 state->base.max_requested_bpc = param[0]; 2671 unlock: 2672 drm_modeset_unlock(&dev->mode_config.connection_mutex); 2673 mutex_unlock(&dev->mode_config.mutex); 2674 2675 kfree(wr_buf); 2676 return size; 2677 } 2678 2679 /* 2680 * IPS status. Read only. 2681 * 2682 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_status 2683 */ 2684 static int ips_status_show(struct seq_file *m, void *unused) 2685 { 2686 struct amdgpu_device *adev = m->private; 2687 struct dc *dc = adev->dm.dc; 2688 struct dc_dmub_srv *dc_dmub_srv; 2689 2690 seq_printf(m, "IPS config: %d\n", dc->config.disable_ips); 2691 seq_printf(m, "Idle optimization: %d\n", dc->idle_optimizations_allowed); 2692 2693 if (adev->dm.idle_workqueue) { 2694 seq_printf(m, "Idle workqueue - enabled: %d\n", adev->dm.idle_workqueue->enable); 2695 seq_printf(m, "Idle workqueue - running: %d\n", adev->dm.idle_workqueue->running); 2696 } 2697 2698 dc_dmub_srv = dc->ctx->dmub_srv; 2699 if (dc_dmub_srv && dc_dmub_srv->dmub) { 2700 uint32_t rcg_count, ips1_count, ips2_count; 2701 volatile const struct dmub_shared_state_ips_fw *ips_fw = 2702 &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw; 2703 rcg_count = ips_fw->rcg_entry_count; 2704 ips1_count = ips_fw->ips1_entry_count; 2705 ips2_count = ips_fw->ips2_entry_count; 2706 seq_printf(m, "entry counts: rcg=%u ips1=%u ips2=%u\n", 2707 rcg_count, 2708 ips1_count, 2709 ips2_count); 2710 rcg_count = ips_fw->rcg_exit_count; 2711 ips1_count = ips_fw->ips1_exit_count; 2712 ips2_count = ips_fw->ips2_exit_count; 2713 seq_printf(m, "exit counts: rcg=%u ips1=%u ips2=%u", 2714 rcg_count, 2715 ips1_count, 2716 ips2_count); 2717 seq_puts(m, "\n"); 2718 } 2719 return 0; 2720 } 2721 2722 /* 2723 * IPS residency information from DMUB service. Read only. 2724 * 2725 * For time-window (segment) measurement: 2726 * 1) echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency_cntl 2727 * 2) sleep <seconds> 2728 * 3) echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency_cntl 2729 * 4) cat /sys/kernel/debug/dri/0/amdgpu_dm_ips_residency 2730 */ 2731 static int ips_residency_show(struct seq_file *m, void *unused) 2732 { 2733 struct amdgpu_device *adev = m->private; 2734 struct dc *dc = adev->dm.dc; 2735 uint8_t panel_inst = 0; 2736 enum ips_residency_mode mode; 2737 struct dmub_ips_residency_info info; 2738 2739 mutex_lock(&adev->dm.dc_lock); 2740 2741 mode = IPS_RESIDENCY__IPS1_RCG; 2742 if (!dc_dmub_srv_ips_query_residency_info(dc->ctx, panel_inst, &info, mode)) { 2743 seq_printf(m, "ISP query failed\n"); 2744 } else { 2745 unsigned int pct, frac; 2746 pct = info.residency_millipercent / 1000; 2747 frac = info.residency_millipercent % 1000; 2748 2749 seq_printf(m, "IPS residency: %u.%03u%% \n", pct, frac); 2750 seq_printf(m, " entry_counter: %u\n", info.entry_counter); 2751 seq_printf(m, " total_time_us: %llu\n", 2752 (unsigned long long)info.total_time_us); 2753 seq_printf(m, " total_inactive_time_us: %llu\n", 2754 (unsigned long long)info.total_inactive_time_us); 2755 } 2756 mutex_unlock(&adev->dm.dc_lock); 2757 return 0; 2758 } 2759 2760 static int ips_residency_cntl_get(void *data, u64 *val) 2761 { 2762 *val = 0; 2763 return 0; 2764 } 2765 2766 static int ips_residency_cntl_set(void *data, u64 val) 2767 { 2768 struct amdgpu_device *adev = data; 2769 struct dc *dc = adev->dm.dc; 2770 uint8_t panel_inst = 0; 2771 int ret = 0; 2772 2773 mutex_lock(&adev->dm.dc_lock); 2774 if (!dc_dmub_srv_ips_residency_cntl(dc->ctx, panel_inst, !!val)) 2775 ret = -EIO; 2776 mutex_unlock(&adev->dm.dc_lock); 2777 2778 return ret; 2779 } 2780 2781 /* 2782 * Backlight at this moment. Read only. 2783 * As written to display, taking ABM and backlight lut into account. 2784 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2785 * 2786 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/current_backlight 2787 */ 2788 static int current_backlight_show(struct seq_file *m, void *unused) 2789 { 2790 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2791 struct dc_link *link = aconnector->dc_link; 2792 unsigned int backlight; 2793 2794 backlight = dc_link_get_backlight_level(link); 2795 seq_printf(m, "0x%x\n", backlight); 2796 2797 return 0; 2798 } 2799 2800 /* 2801 * Backlight value that is being approached. Read only. 2802 * As written to display, taking ABM and backlight lut into account. 2803 * Ranges from 0x0 to 0x10000 (= 100% PWM) 2804 * 2805 * Example usage: cat /sys/kernel/debug/dri/0/eDP-1/target_backlight 2806 */ 2807 static int target_backlight_show(struct seq_file *m, void *unused) 2808 { 2809 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 2810 struct dc_link *link = aconnector->dc_link; 2811 unsigned int backlight; 2812 2813 backlight = dc_link_get_target_backlight_pwm(link); 2814 seq_printf(m, "0x%x\n", backlight); 2815 2816 return 0; 2817 } 2818 2819 /* 2820 * function description: Determine if the connector is mst connector 2821 * 2822 * This function helps to determine whether a connector is a mst connector. 2823 * - "root" stands for the root connector of the topology 2824 * - "branch" stands for branch device of the topology 2825 * - "end" stands for leaf node connector of the topology 2826 * - "no" stands for the connector is not a device of a mst topology 2827 * Access it with the following command: 2828 * 2829 * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector 2830 * 2831 */ 2832 static int dp_is_mst_connector_show(struct seq_file *m, void *unused) 2833 { 2834 struct drm_connector *connector = m->private; 2835 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2836 struct drm_dp_mst_topology_mgr *mgr = NULL; 2837 struct drm_dp_mst_port *port = NULL; 2838 char *role = NULL; 2839 2840 mutex_lock(&aconnector->hpd_lock); 2841 2842 if (aconnector->mst_mgr.mst_state) { 2843 role = "root"; 2844 } else if (aconnector->mst_root && 2845 aconnector->mst_root->mst_mgr.mst_state) { 2846 2847 role = "end"; 2848 2849 mgr = &aconnector->mst_root->mst_mgr; 2850 port = aconnector->mst_output_port; 2851 2852 drm_modeset_lock(&mgr->base.lock, NULL); 2853 if (port->pdt == DP_PEER_DEVICE_MST_BRANCHING && 2854 port->mcs) 2855 role = "branch"; 2856 drm_modeset_unlock(&mgr->base.lock); 2857 2858 } else { 2859 role = "no"; 2860 } 2861 2862 seq_printf(m, "%s\n", role); 2863 2864 mutex_unlock(&aconnector->hpd_lock); 2865 2866 return 0; 2867 } 2868 2869 /* 2870 * function description: Read out the mst progress status 2871 * 2872 * This function helps to determine the mst progress status of 2873 * a mst connector. 2874 * 2875 * Access it with the following command: 2876 * 2877 * cat /sys/kernel/debug/dri/0/DP-X/mst_progress_status 2878 * 2879 */ 2880 static int dp_mst_progress_status_show(struct seq_file *m, void *unused) 2881 { 2882 struct drm_connector *connector = m->private; 2883 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2884 struct amdgpu_device *adev = drm_to_adev(connector->dev); 2885 int i; 2886 2887 mutex_lock(&aconnector->hpd_lock); 2888 mutex_lock(&adev->dm.dc_lock); 2889 2890 if (aconnector->mst_status == MST_STATUS_DEFAULT) { 2891 seq_puts(m, "disabled\n"); 2892 } else { 2893 for (i = 0; i < sizeof(mst_progress_status)/sizeof(char *); i++) 2894 seq_printf(m, "%s:%s\n", 2895 mst_progress_status[i], 2896 aconnector->mst_status & BIT(i) ? "done" : "not_done"); 2897 } 2898 2899 mutex_unlock(&adev->dm.dc_lock); 2900 mutex_unlock(&aconnector->hpd_lock); 2901 2902 return 0; 2903 } 2904 2905 /* 2906 * Reports whether the connected display is a USB4 DPIA tunneled display 2907 * Example usage: cat /sys/kernel/debug/dri/0/DP-8/is_dpia_link 2908 */ 2909 static int is_dpia_link_show(struct seq_file *m, void *data) 2910 { 2911 struct drm_connector *connector = m->private; 2912 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2913 struct dc_link *link = aconnector->dc_link; 2914 2915 if (connector->status != connector_status_connected) 2916 return -ENODEV; 2917 2918 seq_printf(m, "%s\n", (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) ? "yes" : 2919 (link->ep_type == DISPLAY_ENDPOINT_PHY) ? "no" : "unknown"); 2920 2921 return 0; 2922 } 2923 2924 /** 2925 * hdmi_cec_state_show - Read out the HDMI-CEC feature status 2926 * @m: sequence file. 2927 * @data: unused. 2928 * 2929 * Return 0 on success 2930 */ 2931 static int hdmi_cec_state_show(struct seq_file *m, void *data) 2932 { 2933 struct drm_connector *connector = m->private; 2934 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); 2935 2936 seq_printf(m, "%s:%d\n", connector->name, connector->base.id); 2937 seq_printf(m, "HDMI-CEC status: %d\n", aconnector->notifier ? 1 : 0); 2938 2939 return 0; 2940 } 2941 2942 /** 2943 * hdmi_cec_state_write - Enable/Disable HDMI-CEC feature from driver side 2944 * @f: file structure. 2945 * @buf: userspace buffer. set to '1' to enable; '0' to disable cec feature. 2946 * @size: size of buffer from userpsace. 2947 * @pos: unused. 2948 * 2949 * Return size on success, error code on failure 2950 */ 2951 static ssize_t hdmi_cec_state_write(struct file *f, const char __user *buf, 2952 size_t size, loff_t *pos) 2953 { 2954 int ret; 2955 bool enable; 2956 struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; 2957 struct drm_device *ddev = aconnector->base.dev; 2958 2959 if (size == 0) 2960 return -EINVAL; 2961 2962 ret = kstrtobool_from_user(buf, size, &enable); 2963 if (ret) { 2964 drm_dbg_driver(ddev, "invalid user data !\n"); 2965 return ret; 2966 } 2967 2968 if (enable) { 2969 if (aconnector->notifier) 2970 return -EINVAL; 2971 ret = amdgpu_dm_initialize_hdmi_connector(aconnector); 2972 if (ret) 2973 return ret; 2974 hdmi_cec_set_edid(aconnector); 2975 } else { 2976 if (!aconnector->notifier) 2977 return -EINVAL; 2978 cec_notifier_conn_unregister(aconnector->notifier); 2979 aconnector->notifier = NULL; 2980 } 2981 2982 return size; 2983 } 2984 2985 DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); 2986 DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); 2987 DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); 2988 DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); 2989 DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); 2990 DEFINE_SHOW_ATTRIBUTE(internal_display); 2991 DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); 2992 DEFINE_SHOW_ATTRIBUTE(replay_capability); 2993 DEFINE_SHOW_ATTRIBUTE(psr_capability); 2994 DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); 2995 DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); 2996 DEFINE_SHOW_ATTRIBUTE(is_dpia_link); 2997 DEFINE_SHOW_STORE_ATTRIBUTE(hdmi_cec_state); 2998 2999 static const struct file_operations dp_dsc_clock_en_debugfs_fops = { 3000 .owner = THIS_MODULE, 3001 .read = dp_dsc_clock_en_read, 3002 .write = dp_dsc_clock_en_write, 3003 .llseek = default_llseek 3004 }; 3005 3006 static const struct file_operations dp_dsc_slice_width_debugfs_fops = { 3007 .owner = THIS_MODULE, 3008 .read = dp_dsc_slice_width_read, 3009 .write = dp_dsc_slice_width_write, 3010 .llseek = default_llseek 3011 }; 3012 3013 static const struct file_operations dp_dsc_slice_height_debugfs_fops = { 3014 .owner = THIS_MODULE, 3015 .read = dp_dsc_slice_height_read, 3016 .write = dp_dsc_slice_height_write, 3017 .llseek = default_llseek 3018 }; 3019 3020 static const struct file_operations dp_dsc_bits_per_pixel_debugfs_fops = { 3021 .owner = THIS_MODULE, 3022 .read = dp_dsc_bits_per_pixel_read, 3023 .write = dp_dsc_bits_per_pixel_write, 3024 .llseek = default_llseek 3025 }; 3026 3027 static const struct file_operations dp_dsc_pic_width_debugfs_fops = { 3028 .owner = THIS_MODULE, 3029 .read = dp_dsc_pic_width_read, 3030 .llseek = default_llseek 3031 }; 3032 3033 static const struct file_operations dp_dsc_pic_height_debugfs_fops = { 3034 .owner = THIS_MODULE, 3035 .read = dp_dsc_pic_height_read, 3036 .llseek = default_llseek 3037 }; 3038 3039 static const struct file_operations dp_dsc_chunk_size_debugfs_fops = { 3040 .owner = THIS_MODULE, 3041 .read = dp_dsc_chunk_size_read, 3042 .llseek = default_llseek 3043 }; 3044 3045 static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { 3046 .owner = THIS_MODULE, 3047 .read = dp_dsc_slice_bpg_offset_read, 3048 .llseek = default_llseek 3049 }; 3050 3051 static const struct file_operations trigger_hotplug_debugfs_fops = { 3052 .owner = THIS_MODULE, 3053 .write = trigger_hotplug, 3054 .llseek = default_llseek 3055 }; 3056 3057 static const struct file_operations dp_link_settings_debugfs_fops = { 3058 .owner = THIS_MODULE, 3059 .read = dp_link_settings_read, 3060 .write = dp_link_settings_write, 3061 .llseek = default_llseek 3062 }; 3063 3064 static const struct file_operations dp_phy_settings_debugfs_fop = { 3065 .owner = THIS_MODULE, 3066 .read = dp_phy_settings_read, 3067 .write = dp_phy_settings_write, 3068 .llseek = default_llseek 3069 }; 3070 3071 static const struct file_operations dp_phy_test_pattern_fops = { 3072 .owner = THIS_MODULE, 3073 .write = dp_phy_test_pattern_debugfs_write, 3074 .llseek = default_llseek 3075 }; 3076 3077 static const struct file_operations sdp_message_fops = { 3078 .owner = THIS_MODULE, 3079 .write = dp_sdp_message_debugfs_write, 3080 .llseek = default_llseek 3081 }; 3082 3083 static const struct file_operations dp_max_bpc_debugfs_fops = { 3084 .owner = THIS_MODULE, 3085 .read = dp_max_bpc_read, 3086 .write = dp_max_bpc_write, 3087 .llseek = default_llseek 3088 }; 3089 3090 static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { 3091 .owner = THIS_MODULE, 3092 .write = dp_dsc_passthrough_set, 3093 .llseek = default_llseek 3094 }; 3095 3096 static const struct file_operations dp_mst_link_settings_debugfs_fops = { 3097 .owner = THIS_MODULE, 3098 .write = dp_mst_link_setting, 3099 .llseek = default_llseek 3100 }; 3101 3102 static const struct { 3103 char *name; 3104 const struct file_operations *fops; 3105 } dp_debugfs_entries[] = { 3106 {"link_settings", &dp_link_settings_debugfs_fops}, 3107 {"phy_settings", &dp_phy_settings_debugfs_fop}, 3108 {"lttpr_status", &dp_lttpr_status_fops}, 3109 {"test_pattern", &dp_phy_test_pattern_fops}, 3110 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 3111 {"sdp_message", &sdp_message_fops}, 3112 {"dsc_clock_en", &dp_dsc_clock_en_debugfs_fops}, 3113 {"dsc_slice_width", &dp_dsc_slice_width_debugfs_fops}, 3114 {"dsc_slice_height", &dp_dsc_slice_height_debugfs_fops}, 3115 {"dsc_bits_per_pixel", &dp_dsc_bits_per_pixel_debugfs_fops}, 3116 {"dsc_pic_width", &dp_dsc_pic_width_debugfs_fops}, 3117 {"dsc_pic_height", &dp_dsc_pic_height_debugfs_fops}, 3118 {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, 3119 {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, 3120 {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, 3121 {"max_bpc", &dp_max_bpc_debugfs_fops}, 3122 {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, 3123 {"is_mst_connector", &dp_is_mst_connector_fops}, 3124 {"mst_progress_status", &dp_mst_progress_status_fops}, 3125 {"is_dpia_link", &is_dpia_link_fops}, 3126 {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} 3127 }; 3128 3129 static const struct { 3130 char *name; 3131 const struct file_operations *fops; 3132 } hdmi_debugfs_entries[] = { 3133 {"hdcp_sink_capability", &hdcp_sink_capability_fops}, 3134 {"hdmi_cec_state", &hdmi_cec_state_fops} 3135 }; 3136 3137 /* 3138 * Force YUV420 output if available from the given mode 3139 */ 3140 static int force_yuv420_output_set(void *data, u64 val) 3141 { 3142 struct amdgpu_dm_connector *connector = data; 3143 3144 connector->force_yuv420_output = (bool)val; 3145 connector->force_yuv_pixel_format = PIXEL_ENCODING_YCBCR420; 3146 3147 return 0; 3148 } 3149 3150 /* 3151 * Check if YUV420 is forced when available from the given mode 3152 */ 3153 static int force_yuv420_output_get(void *data, u64 *val) 3154 { 3155 struct amdgpu_dm_connector *connector = data; 3156 3157 *val = connector->force_yuv420_output; 3158 3159 return 0; 3160 } 3161 3162 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, 3163 force_yuv420_output_set, "%llu\n"); 3164 3165 static int force_yuv422_output_set(void *data, u64 val) 3166 { 3167 struct amdgpu_dm_connector *connector = data; 3168 3169 connector->force_yuv422_output = (bool)val; 3170 connector->force_yuv_pixel_format = PIXEL_ENCODING_YCBCR422; 3171 3172 return 0; 3173 } 3174 3175 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv422_output_fops, NULL, 3176 force_yuv422_output_set, "%llu\n"); 3177 3178 static int force_yuv444_output_set(void *data, u64 val) 3179 { 3180 struct amdgpu_dm_connector *connector = data; 3181 3182 connector->force_yuv_pixel_format = PIXEL_ENCODING_YCBCR444; 3183 3184 return 0; 3185 } 3186 3187 DEFINE_DEBUGFS_ATTRIBUTE(force_yuv444_output_fops, NULL, 3188 force_yuv444_output_set, "%llu\n"); 3189 3190 /* 3191 * Read Replay state 3192 */ 3193 static int replay_get_state(void *data, u64 *val) 3194 { 3195 struct amdgpu_dm_connector *connector = data; 3196 struct dc_link *link = connector->dc_link; 3197 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 3198 struct dc *dc = adev->dm.dc; 3199 uint64_t state = REPLAY_STATE_INVALID; 3200 bool reallow_idle = false; 3201 3202 mutex_lock(&adev->dm.dc_lock); 3203 3204 if (dc->idle_optimizations_allowed) { 3205 dc_allow_idle_optimizations(dc, false); 3206 reallow_idle = true; 3207 } 3208 3209 dc_link_get_replay_state(link, &state); 3210 3211 if (reallow_idle) 3212 dc_allow_idle_optimizations(dc, true); 3213 3214 mutex_unlock(&adev->dm.dc_lock); 3215 3216 *val = state; 3217 3218 return 0; 3219 } 3220 3221 /* 3222 * Start / Stop capture Replay residency 3223 */ 3224 static int replay_set_residency(void *data, u64 val) 3225 { 3226 struct amdgpu_dm_connector *connector = data; 3227 struct dc_link *link = connector->dc_link; 3228 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 3229 struct dc *dc = adev->dm.dc; 3230 bool is_start = (val != 0); 3231 u32 residency = 0; 3232 bool reallow_idle = false; 3233 3234 mutex_lock(&adev->dm.dc_lock); 3235 3236 if (dc->idle_optimizations_allowed) { 3237 dc_allow_idle_optimizations(dc, false); 3238 reallow_idle = true; 3239 } 3240 3241 link->dc->link_srv->edp_replay_residency(link, &residency, is_start, PR_RESIDENCY_MODE_PHY); 3242 3243 if (reallow_idle) 3244 dc_allow_idle_optimizations(dc, true); 3245 3246 mutex_unlock(&adev->dm.dc_lock); 3247 3248 return 0; 3249 } 3250 3251 /* 3252 * Read Replay residency 3253 */ 3254 static int replay_get_residency(void *data, u64 *val) 3255 { 3256 struct amdgpu_dm_connector *connector = data; 3257 struct dc_link *link = connector->dc_link; 3258 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 3259 struct dc *dc = adev->dm.dc; 3260 u32 residency = 0; 3261 bool reallow_idle = false; 3262 3263 mutex_lock(&adev->dm.dc_lock); 3264 3265 if (dc->idle_optimizations_allowed) { 3266 dc_allow_idle_optimizations(dc, false); 3267 reallow_idle = true; 3268 } 3269 3270 link->dc->link_srv->edp_replay_residency(link, &residency, false, PR_RESIDENCY_MODE_PHY); 3271 3272 if (reallow_idle) 3273 dc_allow_idle_optimizations(dc, true); 3274 3275 mutex_unlock(&adev->dm.dc_lock); 3276 3277 *val = (u64)residency; 3278 3279 return 0; 3280 } 3281 3282 /* 3283 * Read PSR state 3284 */ 3285 static int psr_get(void *data, u64 *val) 3286 { 3287 struct amdgpu_dm_connector *connector = data; 3288 struct dc_link *link = connector->dc_link; 3289 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 3290 struct dc *dc = adev->dm.dc; 3291 enum dc_psr_state state = PSR_STATE0; 3292 bool reallow_idle = false; 3293 3294 mutex_lock(&adev->dm.dc_lock); 3295 3296 if (dc->idle_optimizations_allowed) { 3297 dc_allow_idle_optimizations(dc, false); 3298 reallow_idle = true; 3299 } 3300 3301 dc_link_get_psr_state(link, &state); 3302 3303 if (reallow_idle) 3304 dc_allow_idle_optimizations(dc, true); 3305 3306 mutex_unlock(&adev->dm.dc_lock); 3307 3308 *val = state; 3309 3310 return 0; 3311 } 3312 3313 /* 3314 * Read PSR state residency 3315 */ 3316 static int psr_read_residency(void *data, u64 *val) 3317 { 3318 struct amdgpu_dm_connector *connector = data; 3319 struct dc_link *link = connector->dc_link; 3320 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 3321 struct dc *dc = adev->dm.dc; 3322 u32 residency = 0; 3323 bool reallow_idle = false; 3324 3325 mutex_lock(&adev->dm.dc_lock); 3326 3327 if (dc->idle_optimizations_allowed) { 3328 dc_allow_idle_optimizations(dc, false); 3329 reallow_idle = true; 3330 } 3331 3332 link->dc->link_srv->edp_get_psr_residency(link, &residency, PSR_RESIDENCY_MODE_PHY); 3333 3334 if (reallow_idle) 3335 dc_allow_idle_optimizations(dc, true); 3336 3337 mutex_unlock(&adev->dm.dc_lock); 3338 3339 *val = (u64)residency; 3340 3341 return 0; 3342 } 3343 3344 /* read allow_edp_hotplug_detection */ 3345 static int allow_edp_hotplug_detection_get(void *data, u64 *val) 3346 { 3347 struct amdgpu_dm_connector *aconnector = data; 3348 struct drm_connector *connector = &aconnector->base; 3349 struct drm_device *dev = connector->dev; 3350 struct amdgpu_device *adev = drm_to_adev(dev); 3351 3352 *val = adev->dm.dc->config.allow_edp_hotplug_detection; 3353 3354 return 0; 3355 } 3356 3357 /* set allow_edp_hotplug_detection */ 3358 static int allow_edp_hotplug_detection_set(void *data, u64 val) 3359 { 3360 struct amdgpu_dm_connector *aconnector = data; 3361 struct drm_connector *connector = &aconnector->base; 3362 struct drm_device *dev = connector->dev; 3363 struct amdgpu_device *adev = drm_to_adev(dev); 3364 3365 adev->dm.dc->config.allow_edp_hotplug_detection = (uint32_t) val; 3366 3367 return 0; 3368 } 3369 3370 /* check if kernel disallow eDP enter psr state 3371 * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr 3372 * 0: allow edp enter psr; 1: disallow 3373 */ 3374 static int disallow_edp_enter_psr_get(void *data, u64 *val) 3375 { 3376 struct amdgpu_dm_connector *aconnector = data; 3377 3378 *val = (u64) aconnector->disallow_edp_enter_psr; 3379 return 0; 3380 } 3381 3382 /* set kernel disallow eDP enter psr state 3383 * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr 3384 * 0: allow edp enter psr; 1: disallow 3385 * 3386 * usage: test app read crc from PSR eDP rx. 3387 * 3388 * during kernel boot up, kernel write dpcd 0x170 = 5. 3389 * this notify eDP rx psr enable and let rx check crc. 3390 * rx fw will start checking crc for rx internal logic. 3391 * crc read count within dpcd 0x246 is not updated and 3392 * value is 0. when eDP tx driver wants to read rx crc 3393 * from dpcd 0x246, 0x270, read count 0 lead tx driver 3394 * timeout. 3395 * 3396 * to avoid this, we add this debugfs to let test app to disbable 3397 * rx crc checking for rx internal logic. then test app can read 3398 * non-zero crc read count. 3399 * 3400 * expected app sequence is as below: 3401 * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2. 3402 * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr 3403 * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but 3404 * without dpcd 0x170 = 5. 3405 * 4. read crc from rx dpcd 0x270, 0x246, etc. 3406 * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr. 3407 * this will let eDP back to normal with psr setup dpcd 0x170 = 5. 3408 */ 3409 static int disallow_edp_enter_psr_set(void *data, u64 val) 3410 { 3411 struct amdgpu_dm_connector *aconnector = data; 3412 struct dc_link *link = aconnector->dc_link; 3413 3414 aconnector->disallow_edp_enter_psr = (val != 0); 3415 3416 /* eDP PSR enable / disable is happened during mode change in power module. 3417 * Only psr_settings.psr_version is used to decide whether PSR is enabled or not. 3418 * So here we only update psr_version based on debugfs setting. 3419 * If disallow_edp_enter_psr is true, set psr_version to unsupported; 3420 * if disallow_edp_enter_psr is false, set psr_version based on sink capability. 3421 */ 3422 if (aconnector->disallow_edp_enter_psr) 3423 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED; 3424 else if (aconnector->psr_caps.psr_version == 1) 3425 link->psr_settings.psr_version = DC_PSR_VERSION_1; 3426 else if (aconnector->psr_caps.psr_version == 2) 3427 link->psr_settings.psr_version = DC_PSR_VERSION_SU_1; 3428 return 0; 3429 } 3430 3431 3432 /* check if kernel disallow eDP enter replay state 3433 * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay 3434 * 0: allow edp enter replay; 1: disallow 3435 */ 3436 static int disallow_edp_enter_replay_get(void *data, u64 *val) 3437 { 3438 struct amdgpu_dm_connector *aconnector = data; 3439 3440 *val = (u64) aconnector->disallow_edp_enter_replay; 3441 return 0; 3442 } 3443 3444 /* set kernel disallow eDP enter replay state 3445 * echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay 3446 * 0: allow edp enter replay; 1: disallow 3447 * 3448 * usage: test app read crc from PSR eDP rx. 3449 * 3450 * during kernel boot up, kernel write dpcd 0x37b to 3451 * notify eDP rx replay enable. 3452 * rx fw will start checking crc for rx internal logic. 3453 * crc read count within dpcd 0x246 is not updated and 3454 * value is 0. when eDP tx driver wants to read rx crc 3455 * from dpcd 0x246, 0x270, read count 0 lead tx driver 3456 * timeout. 3457 * 3458 * to avoid this, we add this debugfs to let test app to disbable 3459 * rx replay. then test app can read non-zero crc read count. 3460 * 3461 * expected app sequence is as below: 3462 * 1. disable eDP PHY and notify eDP rx with dpcd 0x600 = 2. 3463 * 2. echo 0x1 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay 3464 * 3. enable eDP PHY and notify eDP rx with dpcd 0x600 = 1 but 3465 * without programming dpcd 0x37b. 3466 * 4. read crc from rx dpcd 0x270, 0x246, etc. 3467 * 5. echo 0x0 /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay. 3468 * this will let eDP back to normal with replay setup dpcd 0x37b. 3469 */ 3470 static int disallow_edp_enter_replay_set(void *data, u64 val) 3471 { 3472 struct amdgpu_dm_connector *aconnector = data; 3473 struct dc_link *link = aconnector->dc_link; 3474 3475 aconnector->disallow_edp_enter_replay = (val != 0); 3476 3477 /* eDP replay enable / disable is happened during mode change in power module. 3478 * Only replay_settings.config.replay_supported is used to decide whether 3479 * replay is enabled or not. So here we only update replay_supported based on 3480 * debugfs setting. 3481 * If disallow_edp_enter_replay is true, set replay_supported to false. 3482 * if disallow_edp_enter_replay is false, set replay_supported back based on 3483 * sink replay capability. 3484 */ 3485 if (aconnector->disallow_edp_enter_replay) 3486 link->replay_settings.config.replay_supported = false; 3487 else 3488 link->replay_settings.config.replay_supported = 3489 link->replay_settings.config.replay_cap_support; 3490 return 0; 3491 } 3492 3493 3494 static int dmub_trace_mask_set(void *data, u64 val) 3495 { 3496 struct amdgpu_device *adev = data; 3497 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub; 3498 enum dmub_gpint_command cmd; 3499 u64 mask = 0xffff; 3500 u8 shift = 0; 3501 u32 res; 3502 int i; 3503 3504 if (!srv->fw_version) 3505 return -EINVAL; 3506 3507 for (i = 0; i < 4; i++) { 3508 res = (val & mask) >> shift; 3509 3510 switch (i) { 3511 case 0: 3512 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0; 3513 break; 3514 case 1: 3515 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1; 3516 break; 3517 case 2: 3518 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD2; 3519 break; 3520 case 3: 3521 cmd = DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD3; 3522 break; 3523 } 3524 3525 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, res, NULL, DM_DMUB_WAIT_TYPE_WAIT)) 3526 return -EIO; 3527 3528 usleep_range(100, 1000); 3529 3530 mask <<= 16; 3531 shift += 16; 3532 } 3533 3534 return 0; 3535 } 3536 3537 static int dmub_trace_mask_show(void *data, u64 *val) 3538 { 3539 enum dmub_gpint_command cmd = DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD0; 3540 struct amdgpu_device *adev = data; 3541 struct dmub_srv *srv = adev->dm.dc->ctx->dmub_srv->dmub; 3542 u8 shift = 0; 3543 u64 raw = 0; 3544 u64 res = 0; 3545 int i = 0; 3546 3547 if (!srv->fw_version) 3548 return -EINVAL; 3549 3550 while (i < 4) { 3551 uint32_t response; 3552 3553 if (!dc_wake_and_execute_gpint(adev->dm.dc->ctx, cmd, 0, &response, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) 3554 return -EIO; 3555 3556 raw = response; 3557 usleep_range(100, 1000); 3558 3559 cmd++; 3560 res |= (raw << shift); 3561 shift += 16; 3562 i++; 3563 } 3564 3565 *val = res; 3566 3567 return 0; 3568 } 3569 3570 DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show, 3571 dmub_trace_mask_set, "0x%llx\n"); 3572 3573 /* 3574 * Set dmcub trace event IRQ enable or disable. 3575 * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 3576 * Usage to disable dmcub trace event IRQ: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 3577 */ 3578 static int dmcub_trace_event_state_set(void *data, u64 val) 3579 { 3580 struct amdgpu_device *adev = data; 3581 3582 if (val == 1 || val == 0) { 3583 dc_dmub_trace_event_control(adev->dm.dc, val); 3584 adev->dm.dmcub_trace_event_en = (bool)val; 3585 } else 3586 return 0; 3587 3588 return 0; 3589 } 3590 3591 /* 3592 * The interface doesn't need get function, so it will return the 3593 * value of zero 3594 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en 3595 */ 3596 static int dmcub_trace_event_state_get(void *data, u64 *val) 3597 { 3598 struct amdgpu_device *adev = data; 3599 3600 *val = adev->dm.dmcub_trace_event_en; 3601 return 0; 3602 } 3603 3604 DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, 3605 dmcub_trace_event_state_set, "%llu\n"); 3606 3607 DEFINE_DEBUGFS_ATTRIBUTE(replay_state_fops, replay_get_state, NULL, "%llu\n"); 3608 DEFINE_DEBUGFS_ATTRIBUTE(replay_residency_fops, replay_get_residency, replay_set_residency, 3609 "%llu\n"); 3610 DEFINE_DEBUGFS_ATTRIBUTE(psr_fops, psr_get, NULL, "%llu\n"); 3611 DEFINE_DEBUGFS_ATTRIBUTE(psr_residency_fops, psr_read_residency, NULL, 3612 "%llu\n"); 3613 3614 DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops, 3615 allow_edp_hotplug_detection_get, 3616 allow_edp_hotplug_detection_set, "%llu\n"); 3617 3618 DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops, 3619 disallow_edp_enter_psr_get, 3620 disallow_edp_enter_psr_set, "%llu\n"); 3621 3622 DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_replay_fops, 3623 disallow_edp_enter_replay_get, 3624 disallow_edp_enter_replay_set, "%llu\n"); 3625 3626 DEFINE_DEBUGFS_ATTRIBUTE(ips_residency_cntl_fops, ips_residency_cntl_get, 3627 ips_residency_cntl_set, "%llu\n"); 3628 3629 DEFINE_SHOW_ATTRIBUTE(current_backlight); 3630 DEFINE_SHOW_ATTRIBUTE(target_backlight); 3631 DEFINE_SHOW_ATTRIBUTE(ips_status); 3632 DEFINE_SHOW_ATTRIBUTE(ips_residency); 3633 3634 static const struct { 3635 char *name; 3636 const struct file_operations *fops; 3637 } connector_debugfs_entries[] = { 3638 {"force_yuv420_output", &force_yuv420_output_fops}, 3639 {"force_yuv422_output", &force_yuv422_output_fops}, 3640 {"force_yuv444_output", &force_yuv444_output_fops}, 3641 {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, 3642 {"internal_display", &internal_display_fops}, 3643 {"odm_combine_segments", &odm_combine_segments_fops} 3644 }; 3645 3646 /* 3647 * Returns supported customized link rates by this eDP panel. 3648 * Example usage: cat /sys/kernel/debug/dri/0/eDP-x/ilr_setting 3649 */ 3650 static int edp_ilr_show(struct seq_file *m, void *unused) 3651 { 3652 struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(m->private); 3653 struct dc_link *link = aconnector->dc_link; 3654 uint8_t supported_link_rates[16]; 3655 uint32_t link_rate_in_khz; 3656 uint32_t entry = 0; 3657 uint8_t dpcd_rev; 3658 3659 memset(supported_link_rates, 0, sizeof(supported_link_rates)); 3660 dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 3661 supported_link_rates, sizeof(supported_link_rates)); 3662 3663 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 3664 3665 if (dpcd_rev >= DP_DPCD_REV_13 && 3666 (supported_link_rates[entry+1] != 0 || supported_link_rates[entry] != 0)) { 3667 3668 for (entry = 0; entry < 16; entry += 2) { 3669 link_rate_in_khz = (supported_link_rates[entry+1] * 0x100 + 3670 supported_link_rates[entry]) * 200; 3671 seq_printf(m, "[%d] %d kHz\n", entry/2, link_rate_in_khz); 3672 } 3673 } else { 3674 seq_puts(m, "ILR is not supported by this eDP panel.\n"); 3675 } 3676 3677 return 0; 3678 } 3679 3680 /* 3681 * Set supported customized link rate to eDP panel. 3682 * 3683 * echo <lane_count> <link_rate option> > ilr_setting 3684 * 3685 * for example, supported ILR : [0] 1620000 kHz [1] 2160000 kHz [2] 2430000 kHz ... 3686 * echo 4 1 > /sys/kernel/debug/dri/0/eDP-x/ilr_setting 3687 * to set 4 lanes and 2.16 GHz 3688 */ 3689 static ssize_t edp_ilr_write(struct file *f, const char __user *buf, 3690 size_t size, loff_t *pos) 3691 { 3692 struct amdgpu_dm_connector *connector = file_inode(f)->i_private; 3693 struct dc_link *link = connector->dc_link; 3694 struct amdgpu_device *adev = drm_to_adev(connector->base.dev); 3695 struct dc *dc = (struct dc *)link->dc; 3696 struct dc_link_settings prefer_link_settings; 3697 char *wr_buf = NULL; 3698 const uint32_t wr_buf_size = 40; 3699 /* 0: lane_count; 1: link_rate */ 3700 int max_param_num = 2; 3701 uint8_t param_nums = 0; 3702 long param[2]; 3703 bool valid_input = true; 3704 uint8_t supported_link_rates[16] = {0}; 3705 uint32_t entry = 0; 3706 uint32_t link_rate_in_khz = 0; 3707 uint8_t dpcd_rev = 0; 3708 3709 if (size == 0) 3710 return -EINVAL; 3711 3712 wr_buf = kcalloc(wr_buf_size, sizeof(char), GFP_KERNEL); 3713 if (!wr_buf) 3714 return -ENOMEM; 3715 3716 if (parse_write_buffer_into_params(wr_buf, wr_buf_size, 3717 (long *)param, buf, 3718 max_param_num, 3719 ¶m_nums)) { 3720 kfree(wr_buf); 3721 return -EINVAL; 3722 } 3723 3724 if (param_nums <= 0) { 3725 kfree(wr_buf); 3726 return -EINVAL; 3727 } 3728 3729 switch (param[0]) { 3730 case LANE_COUNT_ONE: 3731 case LANE_COUNT_TWO: 3732 case LANE_COUNT_FOUR: 3733 break; 3734 default: 3735 valid_input = false; 3736 break; 3737 } 3738 3739 if (param[1] >= link->dpcd_caps.edp_supported_link_rates_count) 3740 valid_input = false; 3741 3742 if (!valid_input) { 3743 kfree(wr_buf); 3744 DRM_DEBUG_DRIVER("Invalid Input value. No HW will be programmed\n"); 3745 prefer_link_settings.use_link_rate_set = false; 3746 mutex_lock(&adev->dm.dc_lock); 3747 dc_link_set_preferred_training_settings(dc, NULL, NULL, link, false); 3748 mutex_unlock(&adev->dm.dc_lock); 3749 return size; 3750 } 3751 3752 if (!dm_helpers_dp_read_dpcd(link->ctx, link, DP_SUPPORTED_LINK_RATES, 3753 supported_link_rates, sizeof(supported_link_rates))) 3754 return -EINVAL; 3755 3756 dpcd_rev = link->dpcd_caps.dpcd_rev.raw; 3757 if (dpcd_rev < DP_DPCD_REV_13 || 3758 (supported_link_rates[entry + 1] == 0 && supported_link_rates[entry] == 0)) { 3759 return size; 3760 } 3761 3762 entry = param[1] * 2; 3763 link_rate_in_khz = (supported_link_rates[entry + 1] * 0x100 + 3764 supported_link_rates[entry]) * 200; 3765 3766 /* save user force lane_count, link_rate to preferred settings 3767 * spread spectrum will not be changed 3768 */ 3769 prefer_link_settings.link_spread = link->cur_link_settings.link_spread; 3770 prefer_link_settings.lane_count = param[0]; 3771 prefer_link_settings.use_link_rate_set = true; 3772 prefer_link_settings.link_rate_set = param[1]; 3773 prefer_link_settings.link_rate = link_rate_in_khz / MULTIPLIER_TO_LR; 3774 3775 mutex_lock(&adev->dm.dc_lock); 3776 dc_link_set_preferred_training_settings(dc, &prefer_link_settings, 3777 NULL, link, false); 3778 mutex_unlock(&adev->dm.dc_lock); 3779 3780 kfree(wr_buf); 3781 return size; 3782 } 3783 3784 static int edp_ilr_open(struct inode *inode, struct file *file) 3785 { 3786 return single_open(file, edp_ilr_show, inode->i_private); 3787 } 3788 3789 static const struct file_operations edp_ilr_debugfs_fops = { 3790 .owner = THIS_MODULE, 3791 .open = edp_ilr_open, 3792 .read = seq_read, 3793 .llseek = seq_lseek, 3794 .release = single_release, 3795 .write = edp_ilr_write 3796 }; 3797 3798 void connector_debugfs_init(struct amdgpu_dm_connector *connector) 3799 { 3800 int i; 3801 struct dentry *dir = connector->base.debugfs_entry; 3802 3803 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || 3804 connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3805 for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { 3806 debugfs_create_file(dp_debugfs_entries[i].name, 3807 0644, dir, connector, 3808 dp_debugfs_entries[i].fops); 3809 } 3810 } 3811 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { 3812 debugfs_create_file("replay_capability", 0444, dir, connector, 3813 &replay_capability_fops); 3814 debugfs_create_file("replay_state", 0444, dir, connector, &replay_state_fops); 3815 debugfs_create_file_unsafe("replay_residency", 0444, dir, 3816 connector, &replay_residency_fops); 3817 debugfs_create_file_unsafe("psr_capability", 0444, dir, connector, &psr_capability_fops); 3818 debugfs_create_file_unsafe("psr_state", 0444, dir, connector, &psr_fops); 3819 debugfs_create_file_unsafe("psr_residency", 0444, dir, 3820 connector, &psr_residency_fops); 3821 debugfs_create_file("amdgpu_current_backlight_pwm", 0444, dir, connector, 3822 ¤t_backlight_fops); 3823 debugfs_create_file("amdgpu_target_backlight_pwm", 0444, dir, connector, 3824 &target_backlight_fops); 3825 debugfs_create_file("ilr_setting", 0644, dir, connector, 3826 &edp_ilr_debugfs_fops); 3827 debugfs_create_file("allow_edp_hotplug_detection", 0644, dir, connector, 3828 &allow_edp_hotplug_detection_fops); 3829 debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector, 3830 &disallow_edp_enter_psr_fops); 3831 debugfs_create_file("disallow_edp_enter_replay", 0644, dir, connector, 3832 &disallow_edp_enter_replay_fops); 3833 } 3834 3835 for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { 3836 debugfs_create_file(connector_debugfs_entries[i].name, 3837 0644, dir, connector, 3838 connector_debugfs_entries[i].fops); 3839 } 3840 3841 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { 3842 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_entries); i++) { 3843 debugfs_create_file(hdmi_debugfs_entries[i].name, 3844 0644, dir, connector, 3845 hdmi_debugfs_entries[i].fops); 3846 } 3847 } 3848 } 3849 3850 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 3851 /* 3852 * Set crc window coordinate x start 3853 */ 3854 static int crc_win_x_start_set(void *data, u64 val) 3855 { 3856 struct drm_crtc *crtc = data; 3857 struct drm_device *drm_dev = crtc->dev; 3858 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3859 3860 spin_lock_irq(&drm_dev->event_lock); 3861 acrtc->dm_irq_params.window_param[0].x_start = (uint16_t) val; 3862 acrtc->dm_irq_params.window_param[0].update_win = false; 3863 spin_unlock_irq(&drm_dev->event_lock); 3864 3865 return 0; 3866 } 3867 3868 /* 3869 * Get crc window coordinate x start 3870 */ 3871 static int crc_win_x_start_get(void *data, u64 *val) 3872 { 3873 struct drm_crtc *crtc = data; 3874 struct drm_device *drm_dev = crtc->dev; 3875 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3876 3877 spin_lock_irq(&drm_dev->event_lock); 3878 *val = acrtc->dm_irq_params.window_param[0].x_start; 3879 spin_unlock_irq(&drm_dev->event_lock); 3880 3881 return 0; 3882 } 3883 3884 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_start_fops, crc_win_x_start_get, 3885 crc_win_x_start_set, "%llu\n"); 3886 3887 3888 /* 3889 * Set crc window coordinate y start 3890 */ 3891 static int crc_win_y_start_set(void *data, u64 val) 3892 { 3893 struct drm_crtc *crtc = data; 3894 struct drm_device *drm_dev = crtc->dev; 3895 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3896 3897 spin_lock_irq(&drm_dev->event_lock); 3898 acrtc->dm_irq_params.window_param[0].y_start = (uint16_t) val; 3899 acrtc->dm_irq_params.window_param[0].update_win = false; 3900 spin_unlock_irq(&drm_dev->event_lock); 3901 3902 return 0; 3903 } 3904 3905 /* 3906 * Get crc window coordinate y start 3907 */ 3908 static int crc_win_y_start_get(void *data, u64 *val) 3909 { 3910 struct drm_crtc *crtc = data; 3911 struct drm_device *drm_dev = crtc->dev; 3912 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3913 3914 spin_lock_irq(&drm_dev->event_lock); 3915 *val = acrtc->dm_irq_params.window_param[0].y_start; 3916 spin_unlock_irq(&drm_dev->event_lock); 3917 3918 return 0; 3919 } 3920 3921 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_start_fops, crc_win_y_start_get, 3922 crc_win_y_start_set, "%llu\n"); 3923 3924 /* 3925 * Set crc window coordinate x end 3926 */ 3927 static int crc_win_x_end_set(void *data, u64 val) 3928 { 3929 struct drm_crtc *crtc = data; 3930 struct drm_device *drm_dev = crtc->dev; 3931 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3932 3933 spin_lock_irq(&drm_dev->event_lock); 3934 acrtc->dm_irq_params.window_param[0].x_end = (uint16_t) val; 3935 acrtc->dm_irq_params.window_param[0].update_win = false; 3936 spin_unlock_irq(&drm_dev->event_lock); 3937 3938 return 0; 3939 } 3940 3941 /* 3942 * Get crc window coordinate x end 3943 */ 3944 static int crc_win_x_end_get(void *data, u64 *val) 3945 { 3946 struct drm_crtc *crtc = data; 3947 struct drm_device *drm_dev = crtc->dev; 3948 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3949 3950 spin_lock_irq(&drm_dev->event_lock); 3951 *val = acrtc->dm_irq_params.window_param[0].x_end; 3952 spin_unlock_irq(&drm_dev->event_lock); 3953 3954 return 0; 3955 } 3956 3957 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_x_end_fops, crc_win_x_end_get, 3958 crc_win_x_end_set, "%llu\n"); 3959 3960 /* 3961 * Set crc window coordinate y end 3962 */ 3963 static int crc_win_y_end_set(void *data, u64 val) 3964 { 3965 struct drm_crtc *crtc = data; 3966 struct drm_device *drm_dev = crtc->dev; 3967 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3968 3969 spin_lock_irq(&drm_dev->event_lock); 3970 acrtc->dm_irq_params.window_param[0].y_end = (uint16_t) val; 3971 acrtc->dm_irq_params.window_param[0].update_win = false; 3972 spin_unlock_irq(&drm_dev->event_lock); 3973 3974 return 0; 3975 } 3976 3977 /* 3978 * Get crc window coordinate y end 3979 */ 3980 static int crc_win_y_end_get(void *data, u64 *val) 3981 { 3982 struct drm_crtc *crtc = data; 3983 struct drm_device *drm_dev = crtc->dev; 3984 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 3985 3986 spin_lock_irq(&drm_dev->event_lock); 3987 *val = acrtc->dm_irq_params.window_param[0].y_end; 3988 spin_unlock_irq(&drm_dev->event_lock); 3989 3990 return 0; 3991 } 3992 3993 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get, 3994 crc_win_y_end_set, "%llu\n"); 3995 /* 3996 * Trigger to commit crc window 3997 */ 3998 static int crc_win_update_set(void *data, u64 val) 3999 { 4000 struct drm_crtc *crtc = data; 4001 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4002 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 4003 4004 if (val) { 4005 mutex_lock(&adev->dm.dc_lock); 4006 /* PSR Replay may write to OTG CRC window control register, 4007 * so inactive it before starting secure_display by sending disable event. 4008 */ 4009 amdgpu_dm_psr_set_event(&adev->dm, acrtc->dm_irq_params.stream, true, 4010 psr_event_crc_window_active, true); 4011 amdgpu_dm_replay_set_event(&adev->dm, acrtc->dm_irq_params.stream, true, 4012 replay_event_crc_window_active, true); 4013 4014 spin_lock_irq(&adev_to_drm(adev)->event_lock); 4015 acrtc->dm_irq_params.window_param[0].enable = true; 4016 acrtc->dm_irq_params.window_param[0].update_win = true; 4017 acrtc->dm_irq_params.window_param[0].skip_frame_cnt = 0; 4018 acrtc->dm_irq_params.crc_window_activated = true; 4019 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 4020 mutex_unlock(&adev->dm.dc_lock); 4021 } else { 4022 /* Clear disable events to allow PSR/Replay to active */ 4023 mutex_lock(&adev->dm.dc_lock); 4024 amdgpu_dm_psr_set_event(&adev->dm, acrtc->dm_irq_params.stream, false, 4025 psr_event_crc_window_active, false); 4026 amdgpu_dm_replay_set_event(&adev->dm, acrtc->dm_irq_params.stream, false, 4027 replay_event_crc_window_active, false); 4028 mutex_unlock(&adev->dm.dc_lock); 4029 } 4030 return 0; 4031 } 4032 4033 /* 4034 * Get crc window update flag 4035 */ 4036 static int crc_win_update_get(void *data, u64 *val) 4037 { 4038 *val = 0; 4039 return 0; 4040 } 4041 4042 DEFINE_DEBUGFS_ATTRIBUTE(crc_win_update_fops, crc_win_update_get, 4043 crc_win_update_set, "%llu\n"); 4044 4045 /* 4046 * Trigger to set crc polynomial mode 4047 * 0: 16-bit CRC, 1: 32-bit CRC 4048 * only accepts 0 or 1 for supported hwip versions 4049 */ 4050 static int crc_poly_mode_set(void *data, u64 val) 4051 { 4052 struct drm_crtc *crtc = data; 4053 struct amdgpu_crtc *acrtc; 4054 struct amdgpu_device *adev = drm_to_adev(crtc->dev); 4055 4056 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 6, 0)) && 4057 (amdgpu_ip_version(adev, DCE_HWIP, 0) != IP_VERSION(4, 0, 1)) && 4058 (val < 2)) { 4059 acrtc = to_amdgpu_crtc(crtc); 4060 mutex_lock(&adev->dm.dc_lock); 4061 spin_lock_irq(&adev_to_drm(adev)->event_lock); 4062 acrtc->dm_irq_params.crc_poly_mode = val; 4063 spin_unlock_irq(&adev_to_drm(adev)->event_lock); 4064 mutex_unlock(&adev->dm.dc_lock); 4065 } 4066 4067 return 0; 4068 } 4069 4070 /* 4071 * Get crc polynomial mode (0: 16-bit CRC, 1: 32-bit CRC) 4072 */ 4073 static int crc_poly_mode_get(void *data, u64 *val) 4074 { 4075 struct drm_crtc *crtc = data; 4076 struct drm_device *drm_dev = crtc->dev; 4077 struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); 4078 4079 spin_lock_irq(&drm_dev->event_lock); 4080 *val = acrtc->dm_irq_params.crc_poly_mode; 4081 spin_unlock_irq(&drm_dev->event_lock); 4082 4083 return 0; 4084 } 4085 4086 DEFINE_DEBUGFS_ATTRIBUTE(crc_poly_mode_fops, crc_poly_mode_get, 4087 crc_poly_mode_set, "%llu\n"); 4088 #endif 4089 void crtc_debugfs_init(struct drm_crtc *crtc) 4090 { 4091 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY 4092 struct dentry *dir = debugfs_lookup("crc", crtc->debugfs_entry); 4093 4094 if (!dir) 4095 return; 4096 4097 debugfs_create_file_unsafe("crc_win_x_start", 0644, dir, crtc, 4098 &crc_win_x_start_fops); 4099 debugfs_create_file_unsafe("crc_win_y_start", 0644, dir, crtc, 4100 &crc_win_y_start_fops); 4101 debugfs_create_file_unsafe("crc_win_x_end", 0644, dir, crtc, 4102 &crc_win_x_end_fops); 4103 debugfs_create_file_unsafe("crc_win_y_end", 0644, dir, crtc, 4104 &crc_win_y_end_fops); 4105 debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc, 4106 &crc_win_update_fops); 4107 debugfs_create_file_unsafe("crc_poly_mode", 0644, dir, crtc, 4108 &crc_poly_mode_fops); 4109 dput(dir); 4110 #endif 4111 debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, 4112 crtc, &amdgpu_current_bpc_fops); 4113 debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry, 4114 crtc, &amdgpu_current_colorspace_fops); 4115 } 4116 4117 /* 4118 * Writes DTN log state to the user supplied buffer. 4119 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 4120 */ 4121 static ssize_t dtn_log_read( 4122 struct file *f, 4123 char __user *buf, 4124 size_t size, 4125 loff_t *pos) 4126 { 4127 struct amdgpu_device *adev = file_inode(f)->i_private; 4128 struct dc *dc = adev->dm.dc; 4129 struct dc_log_buffer_ctx log_ctx = { 0 }; 4130 ssize_t result = 0; 4131 4132 if (!buf || !size) 4133 return -EINVAL; 4134 4135 if (!dc->hwss.log_hw_state) 4136 return 0; 4137 4138 dc->hwss.log_hw_state(dc, &log_ctx); 4139 4140 if (*pos < log_ctx.pos) { 4141 size_t to_copy = log_ctx.pos - *pos; 4142 4143 to_copy = min(to_copy, size); 4144 4145 if (!copy_to_user(buf, log_ctx.buf + *pos, to_copy)) { 4146 *pos += to_copy; 4147 result = to_copy; 4148 } 4149 } 4150 4151 kfree(log_ctx.buf); 4152 4153 return result; 4154 } 4155 4156 /* 4157 * Writes DTN log state to dmesg when triggered via a write. 4158 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dtn_log 4159 */ 4160 static ssize_t dtn_log_write( 4161 struct file *f, 4162 const char __user *buf, 4163 size_t size, 4164 loff_t *pos) 4165 { 4166 struct amdgpu_device *adev = file_inode(f)->i_private; 4167 struct dc *dc = adev->dm.dc; 4168 4169 /* Write triggers log output via dmesg. */ 4170 if (size == 0) 4171 return 0; 4172 4173 if (dc->hwss.log_hw_state) 4174 dc->hwss.log_hw_state(dc, NULL); 4175 4176 return size; 4177 } 4178 4179 static int mst_topo_show(struct seq_file *m, void *unused) 4180 { 4181 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 4182 struct drm_device *dev = adev_to_drm(adev); 4183 struct drm_connector *connector; 4184 struct drm_connector_list_iter conn_iter; 4185 struct amdgpu_dm_connector *aconnector; 4186 4187 drm_connector_list_iter_begin(dev, &conn_iter); 4188 drm_for_each_connector_iter(connector, &conn_iter) { 4189 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) 4190 continue; 4191 4192 aconnector = to_amdgpu_dm_connector(connector); 4193 4194 /* Ensure we're only dumping the topology of a root mst node */ 4195 if (!aconnector->mst_mgr.mst_state) 4196 continue; 4197 4198 seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); 4199 drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); 4200 } 4201 drm_connector_list_iter_end(&conn_iter); 4202 4203 return 0; 4204 } 4205 4206 /* 4207 * Sets trigger hpd for MST topologies. 4208 * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. 4209 * All topologies will be disconnected if val of 0 is set . 4210 * Usage to enable topologies: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 4211 * Usage to disable topologies: echo 0 > /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 4212 */ 4213 static int trigger_hpd_mst_set(void *data, u64 val) 4214 { 4215 struct amdgpu_device *adev = data; 4216 struct drm_device *dev = adev_to_drm(adev); 4217 struct drm_connector_list_iter iter; 4218 struct amdgpu_dm_connector *aconnector; 4219 struct drm_connector *connector; 4220 struct dc_link *link = NULL; 4221 int ret; 4222 4223 if (val == 1) { 4224 drm_connector_list_iter_begin(dev, &iter); 4225 drm_for_each_connector_iter(connector, &iter) { 4226 aconnector = to_amdgpu_dm_connector(connector); 4227 if (aconnector->dc_link->type == dc_connection_mst_branch && 4228 aconnector->mst_mgr.aux) { 4229 mutex_lock(&adev->dm.dc_lock); 4230 ret = dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD); 4231 mutex_unlock(&adev->dm.dc_lock); 4232 4233 if (!ret) 4234 DRM_ERROR("DM_MST: Failed to detect dc link!"); 4235 4236 ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true); 4237 if (ret < 0) 4238 DRM_ERROR("DM_MST: Failed to set the device into MST mode!"); 4239 } 4240 } 4241 } else if (val == 0) { 4242 drm_connector_list_iter_begin(dev, &iter); 4243 drm_for_each_connector_iter(connector, &iter) { 4244 aconnector = to_amdgpu_dm_connector(connector); 4245 if (!aconnector->dc_link) 4246 continue; 4247 4248 if (!aconnector->mst_root) 4249 continue; 4250 4251 link = aconnector->dc_link; 4252 dc_link_dp_receiver_power_ctrl(link, false); 4253 drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_root->mst_mgr, false); 4254 link->mst_stream_alloc_table.stream_count = 0; 4255 memset(link->mst_stream_alloc_table.stream_allocations, 0, 4256 sizeof(link->mst_stream_alloc_table.stream_allocations)); 4257 } 4258 } else { 4259 return 0; 4260 } 4261 drm_kms_helper_hotplug_event(dev); 4262 4263 return 0; 4264 } 4265 4266 /* 4267 * The interface doesn't need get function, so it will return the 4268 * value of zero 4269 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_trigger_hpd_mst 4270 */ 4271 static int trigger_hpd_mst_get(void *data, u64 *val) 4272 { 4273 *val = 0; 4274 return 0; 4275 } 4276 4277 DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, 4278 trigger_hpd_mst_set, "%llu\n"); 4279 4280 4281 /* 4282 * Sets the force_timing_sync debug option from the given string. 4283 * All connected displays will be force synchronized immediately. 4284 * Usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 4285 */ 4286 static int force_timing_sync_set(void *data, u64 val) 4287 { 4288 struct amdgpu_device *adev = data; 4289 4290 adev->dm.force_timing_sync = (bool)val; 4291 4292 amdgpu_dm_trigger_timing_sync(adev_to_drm(adev)); 4293 4294 return 0; 4295 } 4296 4297 /* 4298 * Gets the force_timing_sync debug option value into the given buffer. 4299 * Usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_force_timing_sync 4300 */ 4301 static int force_timing_sync_get(void *data, u64 *val) 4302 { 4303 struct amdgpu_device *adev = data; 4304 4305 *val = adev->dm.force_timing_sync; 4306 4307 return 0; 4308 } 4309 4310 DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, 4311 force_timing_sync_set, "%llu\n"); 4312 4313 4314 /* 4315 * Disables all HPD and HPD RX interrupt handling in the 4316 * driver when set to 1. Default is 0. 4317 */ 4318 static int disable_hpd_set(void *data, u64 val) 4319 { 4320 struct amdgpu_device *adev = data; 4321 4322 adev->dm.disable_hpd_irq = (bool)val; 4323 4324 return 0; 4325 } 4326 4327 4328 /* 4329 * Returns 1 if HPD and HPRX interrupt handling is disabled, 4330 * 0 otherwise. 4331 */ 4332 static int disable_hpd_get(void *data, u64 *val) 4333 { 4334 struct amdgpu_device *adev = data; 4335 4336 *val = adev->dm.disable_hpd_irq; 4337 4338 return 0; 4339 } 4340 4341 DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, 4342 disable_hpd_set, "%llu\n"); 4343 4344 /* 4345 * Prints hardware capabilities. These are used for IGT testing. 4346 */ 4347 static int capabilities_show(struct seq_file *m, void *unused) 4348 { 4349 struct amdgpu_device *adev = (struct amdgpu_device *)m->private; 4350 struct dc *dc = adev->dm.dc; 4351 bool mall_supported = dc->caps.mall_size_total; 4352 bool subvp_supported = dc->caps.subvp_fw_processing_delay_us; 4353 unsigned int mall_in_use = false; 4354 unsigned int subvp_in_use = false; 4355 4356 struct hubbub *hubbub = dc->res_pool->hubbub; 4357 4358 if (hubbub && hubbub->funcs->get_mall_en) 4359 hubbub->funcs->get_mall_en(hubbub, &mall_in_use); 4360 4361 if (dc->cap_funcs.get_subvp_en) 4362 subvp_in_use = dc->cap_funcs.get_subvp_en(dc, dc->current_state); 4363 4364 seq_printf(m, "mall supported: %s, enabled: %s\n", 4365 mall_supported ? "yes" : "no", mall_in_use ? "yes" : "no"); 4366 seq_printf(m, "sub-viewport supported: %s, enabled: %s\n", 4367 subvp_supported ? "yes" : "no", subvp_in_use ? "yes" : "no"); 4368 4369 return 0; 4370 } 4371 4372 DEFINE_SHOW_ATTRIBUTE(capabilities); 4373 4374 /* 4375 * Temporary w/a to force sst sequence in M42D DP2 mst receiver 4376 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_set_mst_en_for_sst 4377 */ 4378 static int dp_force_sst_set(void *data, u64 val) 4379 { 4380 struct amdgpu_device *adev = data; 4381 4382 adev->dm.dc->debug.set_mst_en_for_sst = val; 4383 4384 return 0; 4385 } 4386 4387 static int dp_force_sst_get(void *data, u64 *val) 4388 { 4389 struct amdgpu_device *adev = data; 4390 4391 *val = adev->dm.dc->debug.set_mst_en_for_sst; 4392 4393 return 0; 4394 } 4395 DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, 4396 dp_force_sst_set, "%llu\n"); 4397 4398 /* 4399 * Force DP2 sequence without VESA certified cable. 4400 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id 4401 */ 4402 static int dp_ignore_cable_id_set(void *data, u64 val) 4403 { 4404 struct amdgpu_device *adev = data; 4405 4406 adev->dm.dc->debug.ignore_cable_id = val; 4407 4408 return 0; 4409 } 4410 4411 static int dp_ignore_cable_id_get(void *data, u64 *val) 4412 { 4413 struct amdgpu_device *adev = data; 4414 4415 *val = adev->dm.dc->debug.ignore_cable_id; 4416 4417 return 0; 4418 } 4419 DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, 4420 dp_ignore_cable_id_set, "%llu\n"); 4421 4422 /* 4423 * Sets the DC visual confirm debug option from the given string. 4424 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_visual_confirm 4425 */ 4426 static int visual_confirm_set(void *data, u64 val) 4427 { 4428 struct amdgpu_device *adev = data; 4429 4430 adev->dm.dc->debug.visual_confirm = (enum visual_confirm)val; 4431 4432 return 0; 4433 } 4434 4435 /* 4436 * Reads the DC visual confirm debug option value into the given buffer. 4437 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_visual_confirm 4438 */ 4439 static int visual_confirm_get(void *data, u64 *val) 4440 { 4441 struct amdgpu_device *adev = data; 4442 4443 *val = adev->dm.dc->debug.visual_confirm; 4444 4445 return 0; 4446 } 4447 4448 DEFINE_SHOW_ATTRIBUTE(mst_topo); 4449 DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, 4450 visual_confirm_set, "%llu\n"); 4451 4452 4453 /* 4454 * Sets the DC skip_detection_link_training debug option from the given string. 4455 * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_skip_detection_link_training 4456 */ 4457 static int skip_detection_link_training_set(void *data, u64 val) 4458 { 4459 struct amdgpu_device *adev = data; 4460 4461 if (val == 0) 4462 adev->dm.dc->debug.skip_detection_link_training = false; 4463 else 4464 adev->dm.dc->debug.skip_detection_link_training = true; 4465 4466 return 0; 4467 } 4468 4469 /* 4470 * Reads the DC skip_detection_link_training debug option value into the given buffer. 4471 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_skip_detection_link_training 4472 */ 4473 static int skip_detection_link_training_get(void *data, u64 *val) 4474 { 4475 struct amdgpu_device *adev = data; 4476 4477 *val = adev->dm.dc->debug.skip_detection_link_training; 4478 4479 return 0; 4480 } 4481 4482 DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, 4483 skip_detection_link_training_get, 4484 skip_detection_link_training_set, "%llu\n"); 4485 4486 /* 4487 * Dumps the DCC_EN bit for each pipe. 4488 * Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dcc_en 4489 */ 4490 static ssize_t dcc_en_bits_read( 4491 struct file *f, 4492 char __user *buf, 4493 size_t size, 4494 loff_t *pos) 4495 { 4496 struct amdgpu_device *adev = file_inode(f)->i_private; 4497 struct dc *dc = adev->dm.dc; 4498 char *rd_buf = NULL; 4499 const uint32_t rd_buf_size = 32; 4500 uint32_t result = 0; 4501 int offset = 0; 4502 int num_pipes = dc->res_pool->pipe_count; 4503 int *dcc_en_bits; 4504 int i, r; 4505 4506 dcc_en_bits = kzalloc_objs(int, num_pipes); 4507 if (!dcc_en_bits) 4508 return -ENOMEM; 4509 4510 if (!dc->hwss.get_dcc_en_bits) { 4511 kfree(dcc_en_bits); 4512 return 0; 4513 } 4514 4515 dc->hwss.get_dcc_en_bits(dc, dcc_en_bits); 4516 4517 rd_buf = kcalloc(rd_buf_size, sizeof(char), GFP_KERNEL); 4518 if (!rd_buf) { 4519 kfree(dcc_en_bits); 4520 return -ENOMEM; 4521 } 4522 4523 for (i = 0; i < num_pipes; i++) 4524 offset += snprintf(rd_buf + offset, rd_buf_size - offset, 4525 "%d ", dcc_en_bits[i]); 4526 rd_buf[strlen(rd_buf)] = '\n'; 4527 4528 kfree(dcc_en_bits); 4529 4530 while (size) { 4531 if (*pos >= rd_buf_size) 4532 break; 4533 r = put_user(*(rd_buf + result), buf); 4534 if (r) { 4535 kfree(rd_buf); 4536 return r; /* r = -EFAULT */ 4537 } 4538 buf += 1; 4539 size -= 1; 4540 *pos += 1; 4541 result += 1; 4542 } 4543 4544 kfree(rd_buf); 4545 return result; 4546 } 4547 4548 void dtn_debugfs_init(struct amdgpu_device *adev) 4549 { 4550 static const struct file_operations dtn_log_fops = { 4551 .owner = THIS_MODULE, 4552 .read = dtn_log_read, 4553 .write = dtn_log_write, 4554 .llseek = default_llseek 4555 }; 4556 static const struct file_operations dcc_en_bits_fops = { 4557 .owner = THIS_MODULE, 4558 .read = dcc_en_bits_read, 4559 .llseek = default_llseek 4560 }; 4561 4562 struct drm_minor *minor = adev_to_drm(adev)->primary; 4563 struct dentry *root = minor->debugfs_root; 4564 4565 debugfs_create_file("amdgpu_mst_topology", 0444, root, 4566 adev, &mst_topo_fops); 4567 debugfs_create_file("amdgpu_dm_capabilities", 0444, root, 4568 adev, &capabilities_fops); 4569 debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, 4570 &dtn_log_fops); 4571 debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, 4572 &dp_set_mst_en_for_sst_ops); 4573 debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, 4574 &dp_ignore_cable_id_ops); 4575 4576 debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, 4577 &visual_confirm_fops); 4578 4579 debugfs_create_file_unsafe("amdgpu_dm_skip_detection_link_training", 0644, root, adev, 4580 &skip_detection_link_training_fops); 4581 4582 debugfs_create_file_unsafe("amdgpu_dm_dmub_tracebuffer", 0644, root, 4583 adev, &dmub_tracebuffer_fops); 4584 4585 debugfs_create_file_unsafe("amdgpu_dm_dmub_fw_state", 0644, root, 4586 adev, &dmub_fw_state_fops); 4587 4588 debugfs_create_file_unsafe("amdgpu_dm_force_timing_sync", 0644, root, 4589 adev, &force_timing_sync_ops); 4590 4591 debugfs_create_file_unsafe("amdgpu_dm_dmub_trace_mask", 0644, root, 4592 adev, &dmub_trace_mask_fops); 4593 4594 debugfs_create_file_unsafe("amdgpu_dm_dmcub_trace_event_en", 0644, root, 4595 adev, &dmcub_trace_event_state_fops); 4596 4597 debugfs_create_file_unsafe("amdgpu_dm_trigger_hpd_mst", 0644, root, 4598 adev, &trigger_hpd_mst_ops); 4599 4600 debugfs_create_file_unsafe("amdgpu_dm_dcc_en", 0644, root, adev, 4601 &dcc_en_bits_fops); 4602 4603 debugfs_create_file_unsafe("amdgpu_dm_disable_hpd", 0644, root, adev, 4604 &disable_hpd_ops); 4605 4606 if (adev->dm.dc->caps.ips_support) { 4607 debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev, 4608 &ips_status_fops); 4609 4610 debugfs_create_file_unsafe("amdgpu_dm_ips_residency_cntl", 0644, root, adev, 4611 &ips_residency_cntl_fops); 4612 4613 debugfs_create_file_unsafe("amdgpu_dm_ips_residency", 0644, root, adev, 4614 &ips_residency_fops); 4615 } 4616 } 4617