1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments TSC2046 SPI ADC driver
4 *
5 * Copyright (c) 2021 Oleksij Rempel <kernel@pengutronix.de>, Pengutronix
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/cleanup.h>
10 #include <linux/delay.h>
11 #include <linux/module.h>
12 #include <linux/regulator/consumer.h>
13 #include <linux/spi/spi.h>
14 #include <linux/units.h>
15
16 #include <linux/unaligned.h>
17
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/trigger_consumer.h>
20 #include <linux/iio/triggered_buffer.h>
21 #include <linux/iio/trigger.h>
22
23 /*
24 * The PENIRQ of TSC2046 controller is implemented as level shifter attached to
25 * the X+ line. If voltage of the X+ line reaches a specific level the IRQ will
26 * be activated or deactivated.
27 * To make this kind of IRQ reusable as trigger following additions were
28 * implemented:
29 * - rate limiting:
30 * For typical touchscreen use case, we need to trigger about each 10ms.
31 * - hrtimer:
32 * Continue triggering at least once after the IRQ was deactivated. Then
33 * deactivate this trigger to stop sampling in order to reduce power
34 * consumption.
35 */
36
37 #define TI_TSC2046_NAME "tsc2046"
38
39 /* This driver doesn't aim at the peak continuous sample rate */
40 #define TI_TSC2046_MAX_SAMPLE_RATE 125000
41 #define TI_TSC2046_SAMPLE_BITS \
42 BITS_PER_TYPE(struct tsc2046_adc_atom)
43 #define TI_TSC2046_MAX_CLK_FREQ \
44 (TI_TSC2046_MAX_SAMPLE_RATE * TI_TSC2046_SAMPLE_BITS)
45
46 #define TI_TSC2046_SAMPLE_INTERVAL_US 10000
47
48 #define TI_TSC2046_START BIT(7)
49 #define TI_TSC2046_ADDR GENMASK(6, 4)
50 #define TI_TSC2046_ADDR_TEMP1 7
51 #define TI_TSC2046_ADDR_AUX 6
52 #define TI_TSC2046_ADDR_X 5
53 #define TI_TSC2046_ADDR_Z2 4
54 #define TI_TSC2046_ADDR_Z1 3
55 #define TI_TSC2046_ADDR_VBAT 2
56 #define TI_TSC2046_ADDR_Y 1
57 #define TI_TSC2046_ADDR_TEMP0 0
58
59 /*
60 * The mode bit sets the resolution of the ADC. With this bit low, the next
61 * conversion has 12-bit resolution, whereas with this bit high, the next
62 * conversion has 8-bit resolution. This driver is optimized for 12-bit mode.
63 * So, for this driver, this bit should stay zero.
64 */
65 #define TI_TSC2046_8BIT_MODE BIT(3)
66
67 /*
68 * SER/DFR - The SER/DFR bit controls the reference mode, either single-ended
69 * (high) or differential (low).
70 */
71 #define TI_TSC2046_SER BIT(2)
72
73 /*
74 * If VREF_ON and ADC_ON are both zero, then the chip operates in
75 * auto-wake/suspend mode. In most case this bits should stay zero.
76 */
77 #define TI_TSC2046_PD1_VREF_ON BIT(1)
78 #define TI_TSC2046_PD0_ADC_ON BIT(0)
79
80 /*
81 * All supported devices can do 8 or 12bit resolution. This driver
82 * supports only 12bit mode, here we have a 16bit data transfer, where
83 * the MSB and the 3 LSB are 0.
84 */
85 #define TI_TSC2046_DATA_12BIT GENMASK(14, 3)
86
87 #define TI_TSC2046_MAX_CHAN 8
88 #define TI_TSC2046_MIN_POLL_CNT 3
89 #define TI_TSC2046_EXT_POLL_CNT 3
90 #define TI_TSC2046_POLL_CNT \
91 (TI_TSC2046_MIN_POLL_CNT + TI_TSC2046_EXT_POLL_CNT)
92 #define TI_TSC2046_INT_VREF 2500
93
94 /* Represents a HW sample */
95 struct tsc2046_adc_atom {
96 /*
97 * Command transmitted to the controller. This field is empty on the RX
98 * buffer.
99 */
100 u8 cmd;
101 /*
102 * Data received from the controller. This field is empty for the TX
103 * buffer
104 */
105 __be16 data;
106 } __packed;
107
108 /* Layout of atomic buffers within big buffer */
109 struct tsc2046_adc_group_layout {
110 /* Group offset within the SPI RX buffer */
111 unsigned int offset;
112 /*
113 * Amount of tsc2046_adc_atom structs within the same command gathered
114 * within same group.
115 */
116 unsigned int count;
117 /*
118 * Settling samples (tsc2046_adc_atom structs) which should be skipped
119 * before good samples will start.
120 */
121 unsigned int skip;
122 };
123
124 struct tsc2046_adc_dcfg {
125 const struct iio_chan_spec *channels;
126 unsigned int num_channels;
127 };
128
129 struct tsc2046_adc_ch_cfg {
130 unsigned int settling_time_us;
131 unsigned int oversampling_ratio;
132 };
133
134 enum tsc2046_state {
135 TSC2046_STATE_SHUTDOWN,
136 TSC2046_STATE_STANDBY,
137 TSC2046_STATE_POLL,
138 TSC2046_STATE_POLL_IRQ_DISABLE,
139 TSC2046_STATE_ENABLE_IRQ,
140 };
141
142 struct tsc2046_adc_priv {
143 struct spi_device *spi;
144 const struct tsc2046_adc_dcfg *dcfg;
145 bool internal_vref;
146
147 struct iio_trigger *trig;
148 struct hrtimer trig_timer;
149 enum tsc2046_state state;
150 int poll_cnt;
151 spinlock_t state_lock;
152
153 struct spi_transfer xfer;
154 struct spi_message msg;
155
156 struct {
157 /* Scan data for each channel */
158 u16 data[TI_TSC2046_MAX_CHAN];
159 /* Timestamp */
160 aligned_s64 ts;
161 } scan_buf;
162
163 /*
164 * Lock to protect the layout and the SPI transfer buffer.
165 * tsc2046_adc_group_layout can be changed within update_scan_mode(),
166 * in this case the l[] and tx/rx buffer will be out of sync to each
167 * other.
168 */
169 struct mutex slock;
170 struct tsc2046_adc_group_layout l[TI_TSC2046_MAX_CHAN];
171 struct tsc2046_adc_atom *rx;
172 struct tsc2046_adc_atom *tx;
173
174 unsigned int count;
175 unsigned int groups;
176 u32 effective_speed_hz;
177 u32 scan_interval_us;
178 u32 time_per_scan_us;
179 u32 time_per_bit_ns;
180 unsigned int vref_mv;
181
182 struct tsc2046_adc_ch_cfg ch_cfg[TI_TSC2046_MAX_CHAN];
183 };
184
185 #define TI_TSC2046_V_CHAN(index, bits, name) \
186 { \
187 .type = IIO_VOLTAGE, \
188 .indexed = 1, \
189 .channel = index, \
190 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
191 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
192 .datasheet_name = "#name", \
193 .scan_index = index, \
194 .scan_type = { \
195 .sign = 'u', \
196 .realbits = bits, \
197 .storagebits = 16, \
198 .endianness = IIO_CPU, \
199 }, \
200 }
201
202 #define DECLARE_TI_TSC2046_8_CHANNELS(name, bits) \
203 const struct iio_chan_spec name ## _channels[] = { \
204 TI_TSC2046_V_CHAN(0, bits, TEMP0), \
205 TI_TSC2046_V_CHAN(1, bits, Y), \
206 TI_TSC2046_V_CHAN(2, bits, VBAT), \
207 TI_TSC2046_V_CHAN(3, bits, Z1), \
208 TI_TSC2046_V_CHAN(4, bits, Z2), \
209 TI_TSC2046_V_CHAN(5, bits, X), \
210 TI_TSC2046_V_CHAN(6, bits, AUX), \
211 TI_TSC2046_V_CHAN(7, bits, TEMP1), \
212 IIO_CHAN_SOFT_TIMESTAMP(8), \
213 }
214
215 static DECLARE_TI_TSC2046_8_CHANNELS(tsc2046_adc, 12);
216
217 static const struct tsc2046_adc_dcfg tsc2046_adc_dcfg_tsc2046e = {
218 .channels = tsc2046_adc_channels,
219 .num_channels = ARRAY_SIZE(tsc2046_adc_channels),
220 };
221
222 /*
223 * Convert time to a number of samples which can be transferred within this
224 * time.
225 */
tsc2046_adc_time_to_count(struct tsc2046_adc_priv * priv,unsigned long time)226 static unsigned int tsc2046_adc_time_to_count(struct tsc2046_adc_priv *priv,
227 unsigned long time)
228 {
229 unsigned int bit_count, sample_count;
230
231 bit_count = DIV_ROUND_UP(time * NSEC_PER_USEC, priv->time_per_bit_ns);
232 sample_count = DIV_ROUND_UP(bit_count, TI_TSC2046_SAMPLE_BITS);
233
234 dev_dbg(&priv->spi->dev, "Effective speed %u, time per bit: %u, count bits: %u, count samples: %u\n",
235 priv->effective_speed_hz, priv->time_per_bit_ns,
236 bit_count, sample_count);
237
238 return sample_count;
239 }
240
tsc2046_adc_get_cmd(struct tsc2046_adc_priv * priv,int ch_idx,bool keep_power)241 static u8 tsc2046_adc_get_cmd(struct tsc2046_adc_priv *priv, int ch_idx,
242 bool keep_power)
243 {
244 u32 pd;
245
246 /*
247 * if PD bits are 0, controller will automatically disable ADC, VREF and
248 * enable IRQ.
249 */
250 if (keep_power)
251 pd = TI_TSC2046_PD0_ADC_ON;
252 else
253 pd = 0;
254
255 switch (ch_idx) {
256 case TI_TSC2046_ADDR_TEMP1:
257 case TI_TSC2046_ADDR_AUX:
258 case TI_TSC2046_ADDR_VBAT:
259 case TI_TSC2046_ADDR_TEMP0:
260 pd |= TI_TSC2046_SER;
261 if (priv->internal_vref)
262 pd |= TI_TSC2046_PD1_VREF_ON;
263 }
264
265 return TI_TSC2046_START | FIELD_PREP(TI_TSC2046_ADDR, ch_idx) | pd;
266 }
267
tsc2046_adc_get_value(struct tsc2046_adc_atom * buf)268 static u16 tsc2046_adc_get_value(struct tsc2046_adc_atom *buf)
269 {
270 return FIELD_GET(TI_TSC2046_DATA_12BIT, get_unaligned_be16(&buf->data));
271 }
272
tsc2046_adc_read_one(struct tsc2046_adc_priv * priv,int ch_idx,u32 * effective_speed_hz)273 static int tsc2046_adc_read_one(struct tsc2046_adc_priv *priv, int ch_idx,
274 u32 *effective_speed_hz)
275 {
276 struct tsc2046_adc_ch_cfg *ch = &priv->ch_cfg[ch_idx];
277 unsigned int val, val_normalized = 0;
278 int ret, i, count_skip = 0, max_count;
279 struct spi_transfer xfer = { };
280 struct spi_message msg;
281 u8 cmd;
282
283 if (!effective_speed_hz) {
284 count_skip = tsc2046_adc_time_to_count(priv, ch->settling_time_us);
285 max_count = count_skip + ch->oversampling_ratio;
286 } else {
287 max_count = 1;
288 }
289
290 if (sizeof(struct tsc2046_adc_atom) * max_count > PAGE_SIZE)
291 return -ENOSPC;
292
293 struct tsc2046_adc_atom *tx_buf __free(kfree) = kzalloc_objs(*tx_buf,
294 max_count);
295 if (!tx_buf)
296 return -ENOMEM;
297
298 struct tsc2046_adc_atom *rx_buf __free(kfree) = kzalloc_objs(*rx_buf,
299 max_count);
300 if (!rx_buf)
301 return -ENOMEM;
302
303 /*
304 * Do not enable automatic power down on working samples. Otherwise the
305 * plates will never be completely charged.
306 */
307 cmd = tsc2046_adc_get_cmd(priv, ch_idx, true);
308
309 for (i = 0; i < max_count - 1; i++)
310 tx_buf[i].cmd = cmd;
311
312 /* automatically power down on last sample */
313 tx_buf[i].cmd = tsc2046_adc_get_cmd(priv, ch_idx, false);
314
315 xfer.tx_buf = tx_buf;
316 xfer.rx_buf = rx_buf;
317 xfer.len = sizeof(*tx_buf) * max_count;
318 spi_message_init_with_transfers(&msg, &xfer, 1);
319
320 /*
321 * We aren't using spi_write_then_read() because we need to be able
322 * to get hold of the effective_speed_hz from the xfer
323 */
324 ret = spi_sync(priv->spi, &msg);
325 if (ret) {
326 dev_err_ratelimited(&priv->spi->dev, "SPI transfer failed %pe\n",
327 ERR_PTR(ret));
328 return ret;
329 }
330
331 if (effective_speed_hz)
332 *effective_speed_hz = xfer.effective_speed_hz;
333
334 for (i = 0; i < max_count - count_skip; i++) {
335 val = tsc2046_adc_get_value(&rx_buf[count_skip + i]);
336 val_normalized += val;
337 }
338
339 return DIV_ROUND_UP(val_normalized, max_count - count_skip);
340 }
341
tsc2046_adc_group_set_layout(struct tsc2046_adc_priv * priv,unsigned int group,unsigned int ch_idx)342 static size_t tsc2046_adc_group_set_layout(struct tsc2046_adc_priv *priv,
343 unsigned int group,
344 unsigned int ch_idx)
345 {
346 struct tsc2046_adc_ch_cfg *ch = &priv->ch_cfg[ch_idx];
347 struct tsc2046_adc_group_layout *cur;
348 unsigned int max_count, count_skip;
349 unsigned int offset = 0;
350
351 if (group)
352 offset = priv->l[group - 1].offset + priv->l[group - 1].count;
353
354 count_skip = tsc2046_adc_time_to_count(priv, ch->settling_time_us);
355 max_count = count_skip + ch->oversampling_ratio;
356
357 cur = &priv->l[group];
358 cur->offset = offset;
359 cur->count = max_count;
360 cur->skip = count_skip;
361
362 return sizeof(*priv->tx) * max_count;
363 }
364
tsc2046_adc_group_set_cmd(struct tsc2046_adc_priv * priv,unsigned int group,int ch_idx)365 static void tsc2046_adc_group_set_cmd(struct tsc2046_adc_priv *priv,
366 unsigned int group, int ch_idx)
367 {
368 struct tsc2046_adc_group_layout *l = &priv->l[group];
369 unsigned int i;
370 u8 cmd;
371
372 /*
373 * Do not enable automatic power down on working samples. Otherwise the
374 * plates will never be completely charged.
375 */
376 cmd = tsc2046_adc_get_cmd(priv, ch_idx, true);
377
378 for (i = 0; i < l->count - 1; i++)
379 priv->tx[l->offset + i].cmd = cmd;
380
381 /* automatically power down on last sample */
382 priv->tx[l->offset + i].cmd = tsc2046_adc_get_cmd(priv, ch_idx, false);
383 }
384
tsc2046_adc_get_val(struct tsc2046_adc_priv * priv,int group)385 static u16 tsc2046_adc_get_val(struct tsc2046_adc_priv *priv, int group)
386 {
387 struct tsc2046_adc_group_layout *l;
388 unsigned int val, val_normalized = 0;
389 int valid_count, i;
390
391 l = &priv->l[group];
392 valid_count = l->count - l->skip;
393
394 for (i = 0; i < valid_count; i++) {
395 val = tsc2046_adc_get_value(&priv->rx[l->offset + l->skip + i]);
396 val_normalized += val;
397 }
398
399 return DIV_ROUND_UP(val_normalized, valid_count);
400 }
401
tsc2046_adc_scan(struct iio_dev * indio_dev)402 static int tsc2046_adc_scan(struct iio_dev *indio_dev)
403 {
404 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
405 struct device *dev = &priv->spi->dev;
406 int group;
407 int ret;
408
409 ret = spi_sync(priv->spi, &priv->msg);
410 if (ret < 0) {
411 dev_err_ratelimited(dev, "SPI transfer failed: %pe\n", ERR_PTR(ret));
412 return ret;
413 }
414
415 for (group = 0; group < priv->groups; group++)
416 priv->scan_buf.data[group] = tsc2046_adc_get_val(priv, group);
417
418 ret = iio_push_to_buffers_with_ts(indio_dev, &priv->scan_buf,
419 sizeof(priv->scan_buf),
420 iio_get_time_ns(indio_dev));
421 /* If the consumer is kfifo, we may get a EBUSY here - ignore it. */
422 if (ret < 0 && ret != -EBUSY) {
423 dev_err_ratelimited(dev, "Failed to push scan buffer %pe\n",
424 ERR_PTR(ret));
425
426 return ret;
427 }
428
429 return 0;
430 }
431
tsc2046_adc_trigger_handler(int irq,void * p)432 static irqreturn_t tsc2046_adc_trigger_handler(int irq, void *p)
433 {
434 struct iio_poll_func *pf = p;
435 struct iio_dev *indio_dev = pf->indio_dev;
436 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
437
438 mutex_lock(&priv->slock);
439 tsc2046_adc_scan(indio_dev);
440 mutex_unlock(&priv->slock);
441
442 iio_trigger_notify_done(indio_dev->trig);
443
444 return IRQ_HANDLED;
445 }
446
tsc2046_adc_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)447 static int tsc2046_adc_read_raw(struct iio_dev *indio_dev,
448 struct iio_chan_spec const *chan,
449 int *val, int *val2, long m)
450 {
451 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
452 int ret;
453
454 switch (m) {
455 case IIO_CHAN_INFO_RAW:
456 ret = tsc2046_adc_read_one(priv, chan->channel, NULL);
457 if (ret < 0)
458 return ret;
459
460 *val = ret;
461
462 return IIO_VAL_INT;
463 case IIO_CHAN_INFO_SCALE:
464 /*
465 * Note: the TSC2046 has internal voltage divider on the VBAT
466 * line. This divider can be influenced by external divider.
467 * So, it is better to use external voltage-divider driver
468 * instead, which is calculating complete chain.
469 */
470 *val = priv->vref_mv;
471 *val2 = chan->scan_type.realbits;
472 return IIO_VAL_FRACTIONAL_LOG2;
473 }
474
475 return -EINVAL;
476 }
477
tsc2046_adc_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)478 static int tsc2046_adc_update_scan_mode(struct iio_dev *indio_dev,
479 const unsigned long *active_scan_mask)
480 {
481 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
482 unsigned int ch_idx, group = 0;
483 size_t size;
484
485 mutex_lock(&priv->slock);
486
487 size = 0;
488 for_each_set_bit(ch_idx, active_scan_mask, ARRAY_SIZE(priv->l)) {
489 size += tsc2046_adc_group_set_layout(priv, group, ch_idx);
490 tsc2046_adc_group_set_cmd(priv, group, ch_idx);
491 group++;
492 }
493
494 priv->groups = group;
495 priv->xfer.len = size;
496 priv->time_per_scan_us = size * 8 * priv->time_per_bit_ns / NSEC_PER_USEC;
497
498 if (priv->scan_interval_us < priv->time_per_scan_us)
499 dev_warn(&priv->spi->dev, "The scan interval (%d) is less then calculated scan time (%d)\n",
500 priv->scan_interval_us, priv->time_per_scan_us);
501
502 mutex_unlock(&priv->slock);
503
504 return 0;
505 }
506
507 static const struct iio_info tsc2046_adc_info = {
508 .read_raw = tsc2046_adc_read_raw,
509 .update_scan_mode = tsc2046_adc_update_scan_mode,
510 };
511
tsc2046_adc_timer(struct hrtimer * hrtimer)512 static enum hrtimer_restart tsc2046_adc_timer(struct hrtimer *hrtimer)
513 {
514 struct tsc2046_adc_priv *priv = container_of(hrtimer,
515 struct tsc2046_adc_priv,
516 trig_timer);
517 unsigned long flags;
518
519 /*
520 * This state machine should address following challenges :
521 * - the interrupt source is based on level shifter attached to the X
522 * channel of ADC. It will change the state every time we switch
523 * between channels. So, we need to disable IRQ if we do
524 * iio_trigger_poll().
525 * - we should do iio_trigger_poll() at some reduced sample rate
526 * - we should still trigger for some amount of time after last
527 * interrupt with enabled IRQ was processed.
528 */
529
530 spin_lock_irqsave(&priv->state_lock, flags);
531 switch (priv->state) {
532 case TSC2046_STATE_ENABLE_IRQ:
533 if (priv->poll_cnt < TI_TSC2046_POLL_CNT) {
534 priv->poll_cnt++;
535 hrtimer_start(&priv->trig_timer,
536 us_to_ktime(priv->scan_interval_us),
537 HRTIMER_MODE_REL_SOFT);
538
539 if (priv->poll_cnt >= TI_TSC2046_MIN_POLL_CNT) {
540 priv->state = TSC2046_STATE_POLL_IRQ_DISABLE;
541 enable_irq(priv->spi->irq);
542 } else {
543 priv->state = TSC2046_STATE_POLL;
544 }
545 } else {
546 priv->state = TSC2046_STATE_STANDBY;
547 enable_irq(priv->spi->irq);
548 }
549 break;
550 case TSC2046_STATE_POLL_IRQ_DISABLE:
551 disable_irq_nosync(priv->spi->irq);
552 fallthrough;
553 case TSC2046_STATE_POLL:
554 priv->state = TSC2046_STATE_ENABLE_IRQ;
555 /* iio_trigger_poll() starts hrtimer */
556 iio_trigger_poll(priv->trig);
557 break;
558 case TSC2046_STATE_SHUTDOWN:
559 break;
560 case TSC2046_STATE_STANDBY:
561 fallthrough;
562 default:
563 dev_warn(&priv->spi->dev, "Got unexpected state: %i\n",
564 priv->state);
565 break;
566 }
567 spin_unlock_irqrestore(&priv->state_lock, flags);
568
569 return HRTIMER_NORESTART;
570 }
571
tsc2046_adc_irq(int irq,void * dev_id)572 static irqreturn_t tsc2046_adc_irq(int irq, void *dev_id)
573 {
574 struct iio_dev *indio_dev = dev_id;
575 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
576 unsigned long flags;
577
578 hrtimer_try_to_cancel(&priv->trig_timer);
579
580 spin_lock_irqsave(&priv->state_lock, flags);
581 if (priv->state != TSC2046_STATE_SHUTDOWN) {
582 priv->state = TSC2046_STATE_ENABLE_IRQ;
583 priv->poll_cnt = 0;
584
585 /* iio_trigger_poll() starts hrtimer */
586 disable_irq_nosync(priv->spi->irq);
587 iio_trigger_poll(priv->trig);
588 }
589 spin_unlock_irqrestore(&priv->state_lock, flags);
590
591 return IRQ_HANDLED;
592 }
593
tsc2046_adc_reenable_trigger(struct iio_trigger * trig)594 static void tsc2046_adc_reenable_trigger(struct iio_trigger *trig)
595 {
596 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
597 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
598 ktime_t tim;
599
600 /*
601 * We can sample it as fast as we can, but usually we do not need so
602 * many samples. Reduce the sample rate for default (touchscreen) use
603 * case.
604 */
605 tim = us_to_ktime(priv->scan_interval_us - priv->time_per_scan_us);
606 hrtimer_start(&priv->trig_timer, tim, HRTIMER_MODE_REL_SOFT);
607 }
608
tsc2046_adc_set_trigger_state(struct iio_trigger * trig,bool enable)609 static int tsc2046_adc_set_trigger_state(struct iio_trigger *trig, bool enable)
610 {
611 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
612 struct tsc2046_adc_priv *priv = iio_priv(indio_dev);
613 unsigned long flags;
614
615 if (enable) {
616 spin_lock_irqsave(&priv->state_lock, flags);
617 if (priv->state == TSC2046_STATE_SHUTDOWN) {
618 priv->state = TSC2046_STATE_STANDBY;
619 enable_irq(priv->spi->irq);
620 }
621 spin_unlock_irqrestore(&priv->state_lock, flags);
622 } else {
623 spin_lock_irqsave(&priv->state_lock, flags);
624
625 if (priv->state == TSC2046_STATE_STANDBY ||
626 priv->state == TSC2046_STATE_POLL_IRQ_DISABLE)
627 disable_irq_nosync(priv->spi->irq);
628
629 priv->state = TSC2046_STATE_SHUTDOWN;
630 spin_unlock_irqrestore(&priv->state_lock, flags);
631
632 hrtimer_cancel(&priv->trig_timer);
633 }
634
635 return 0;
636 }
637
638 static const struct iio_trigger_ops tsc2046_adc_trigger_ops = {
639 .set_trigger_state = tsc2046_adc_set_trigger_state,
640 .reenable = tsc2046_adc_reenable_trigger,
641 };
642
tsc2046_adc_setup_spi_msg(struct tsc2046_adc_priv * priv)643 static int tsc2046_adc_setup_spi_msg(struct tsc2046_adc_priv *priv)
644 {
645 unsigned int ch_idx;
646 size_t size;
647 int ret;
648
649 /*
650 * Make dummy read to set initial power state and get real SPI clock
651 * freq. It seems to be not important which channel is used for this
652 * case.
653 */
654 ret = tsc2046_adc_read_one(priv, TI_TSC2046_ADDR_TEMP0,
655 &priv->effective_speed_hz);
656 if (ret < 0)
657 return ret;
658
659 /*
660 * In case SPI controller do not report effective_speed_hz, use
661 * configure value and hope it will match.
662 */
663 if (!priv->effective_speed_hz)
664 priv->effective_speed_hz = priv->spi->max_speed_hz;
665
666
667 priv->scan_interval_us = TI_TSC2046_SAMPLE_INTERVAL_US;
668 priv->time_per_bit_ns = DIV_ROUND_UP(NSEC_PER_SEC,
669 priv->effective_speed_hz);
670
671 /*
672 * Calculate and allocate maximal size buffer if all channels are
673 * enabled.
674 */
675 size = 0;
676 for (ch_idx = 0; ch_idx < ARRAY_SIZE(priv->l); ch_idx++)
677 size += tsc2046_adc_group_set_layout(priv, ch_idx, ch_idx);
678
679 if (size > PAGE_SIZE) {
680 dev_err(&priv->spi->dev,
681 "Calculated scan buffer is too big. Try to reduce spi-max-frequency, settling-time-us or oversampling-ratio\n");
682 return -ENOSPC;
683 }
684
685 priv->tx = devm_kzalloc(&priv->spi->dev, size, GFP_KERNEL);
686 if (!priv->tx)
687 return -ENOMEM;
688
689 priv->rx = devm_kzalloc(&priv->spi->dev, size, GFP_KERNEL);
690 if (!priv->rx)
691 return -ENOMEM;
692
693 priv->xfer.tx_buf = priv->tx;
694 priv->xfer.rx_buf = priv->rx;
695 priv->xfer.len = size;
696 spi_message_init_with_transfers(&priv->msg, &priv->xfer, 1);
697
698 return 0;
699 }
700
tsc2046_adc_parse_fwnode(struct tsc2046_adc_priv * priv)701 static void tsc2046_adc_parse_fwnode(struct tsc2046_adc_priv *priv)
702 {
703 struct fwnode_handle *child;
704 struct device *dev = &priv->spi->dev;
705 unsigned int i;
706
707 for (i = 0; i < ARRAY_SIZE(priv->ch_cfg); i++) {
708 priv->ch_cfg[i].settling_time_us = 1;
709 priv->ch_cfg[i].oversampling_ratio = 1;
710 }
711
712 device_for_each_child_node(dev, child) {
713 u32 stl, overs, reg;
714 int ret;
715
716 ret = fwnode_property_read_u32(child, "reg", ®);
717 if (ret) {
718 dev_err(dev, "invalid reg on %pfw, err: %pe\n", child,
719 ERR_PTR(ret));
720 continue;
721 }
722
723 if (reg >= ARRAY_SIZE(priv->ch_cfg)) {
724 dev_err(dev, "%pfw: Unsupported reg value: %i, max supported is: %zu.\n",
725 child, reg, ARRAY_SIZE(priv->ch_cfg));
726 continue;
727 }
728
729 ret = fwnode_property_read_u32(child, "settling-time-us", &stl);
730 if (!ret)
731 priv->ch_cfg[reg].settling_time_us = stl;
732
733 ret = fwnode_property_read_u32(child, "oversampling-ratio",
734 &overs);
735 if (!ret)
736 priv->ch_cfg[reg].oversampling_ratio = overs;
737 }
738 }
739
tsc2046_adc_probe(struct spi_device * spi)740 static int tsc2046_adc_probe(struct spi_device *spi)
741 {
742 const struct tsc2046_adc_dcfg *dcfg;
743 struct device *dev = &spi->dev;
744 struct tsc2046_adc_priv *priv;
745 struct iio_dev *indio_dev;
746 struct iio_trigger *trig;
747 int ret;
748
749 if (spi->max_speed_hz > TI_TSC2046_MAX_CLK_FREQ) {
750 dev_err(dev, "SPI max_speed_hz is too high: %d Hz. Max supported freq is %zu Hz\n",
751 spi->max_speed_hz, TI_TSC2046_MAX_CLK_FREQ);
752 return -EINVAL;
753 }
754
755 dcfg = spi_get_device_match_data(spi);
756 if (!dcfg)
757 return -EINVAL;
758
759 spi->mode &= ~SPI_MODE_X_MASK;
760 spi->mode |= SPI_MODE_0;
761 ret = spi_setup(spi);
762 if (ret < 0)
763 return dev_err_probe(dev, ret, "Error in SPI setup\n");
764
765 indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
766 if (!indio_dev)
767 return -ENOMEM;
768
769 priv = iio_priv(indio_dev);
770 priv->dcfg = dcfg;
771
772 priv->spi = spi;
773
774 indio_dev->name = TI_TSC2046_NAME;
775 indio_dev->modes = INDIO_DIRECT_MODE;
776 indio_dev->channels = dcfg->channels;
777 indio_dev->num_channels = dcfg->num_channels;
778 indio_dev->info = &tsc2046_adc_info;
779
780 ret = devm_regulator_get_enable_read_voltage(dev, "vref");
781 if (ret < 0 && ret != -ENODEV)
782 return ret;
783
784 priv->internal_vref = ret == -ENODEV;
785 priv->vref_mv = priv->internal_vref ? TI_TSC2046_INT_VREF : ret / MILLI;
786
787 tsc2046_adc_parse_fwnode(priv);
788
789 ret = tsc2046_adc_setup_spi_msg(priv);
790 if (ret)
791 return ret;
792
793 mutex_init(&priv->slock);
794
795 ret = devm_request_irq(dev, spi->irq, &tsc2046_adc_irq,
796 IRQF_NO_AUTOEN, indio_dev->name, indio_dev);
797 if (ret)
798 return ret;
799
800 trig = devm_iio_trigger_alloc(dev, "touchscreen-%s", indio_dev->name);
801 if (!trig)
802 return -ENOMEM;
803
804 priv->trig = trig;
805 iio_trigger_set_drvdata(trig, indio_dev);
806 trig->ops = &tsc2046_adc_trigger_ops;
807
808 spin_lock_init(&priv->state_lock);
809 priv->state = TSC2046_STATE_SHUTDOWN;
810 hrtimer_setup(&priv->trig_timer, tsc2046_adc_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_SOFT);
811
812 ret = devm_iio_trigger_register(dev, trig);
813 if (ret) {
814 dev_err(dev, "failed to register trigger\n");
815 return ret;
816 }
817
818 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
819 &tsc2046_adc_trigger_handler, NULL);
820 if (ret) {
821 dev_err(dev, "Failed to setup triggered buffer\n");
822 return ret;
823 }
824
825 /* set default trigger */
826 indio_dev->trig = iio_trigger_get(priv->trig);
827
828 return devm_iio_device_register(dev, indio_dev);
829 }
830
831 static const struct of_device_id ads7950_of_table[] = {
832 { .compatible = "ti,tsc2046e-adc", .data = &tsc2046_adc_dcfg_tsc2046e },
833 { }
834 };
835 MODULE_DEVICE_TABLE(of, ads7950_of_table);
836
837 static const struct spi_device_id tsc2046_adc_spi_ids[] = {
838 { "tsc2046e-adc", (unsigned long)&tsc2046_adc_dcfg_tsc2046e },
839 { }
840 };
841 MODULE_DEVICE_TABLE(spi, tsc2046_adc_spi_ids);
842
843 static struct spi_driver tsc2046_adc_driver = {
844 .driver = {
845 .name = "tsc2046",
846 .of_match_table = ads7950_of_table,
847 },
848 .id_table = tsc2046_adc_spi_ids,
849 .probe = tsc2046_adc_probe,
850 };
851 module_spi_driver(tsc2046_adc_driver);
852
853 MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
854 MODULE_DESCRIPTION("TI TSC2046 ADC");
855 MODULE_LICENSE("GPL v2");
856