1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __SPI_DW_H__
3 #define __SPI_DW_H__
4
5 #include <linux/bits.h>
6 #include <linux/completion.h>
7 #include <linux/debugfs.h>
8 #include <linux/irqreturn.h>
9 #include <linux/io.h>
10 #include <linux/scatterlist.h>
11 #include <linux/spi/spi-mem.h>
12 #include <linux/bitfield.h>
13
14 /* Synopsys DW SSI IP-core virtual IDs */
15 #define DW_PSSI_ID 0
16 #define DW_HSSI_ID 1
17
18 /* Synopsys DW SSI component versions (FourCC sequence) */
19 #define DW_HSSI_102A 0x3130322a
20 #define DW_HSSI_103A 0x3130332a
21 #define DW_HSSI_200A 0x3230302a
22 #define DW_PSSI_400A 0x3430302a
23
24 /* DW SSI IP-core ID and version check helpers */
25 #define dw_spi_ip_is(_dws, _ip) \
26 ((_dws)->ip == DW_ ## _ip ## _ID)
27
28 #define __dw_spi_ver_cmp(_dws, _ip, _ver, _op) \
29 (dw_spi_ip_is(_dws, _ip) && (_dws)->ver _op DW_ ## _ip ## _ ## _ver)
30
31 #define dw_spi_ver_is(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, ==)
32
33 #define dw_spi_ver_is_ge(_dws, _ip, _ver) __dw_spi_ver_cmp(_dws, _ip, _ver, >=)
34
35 /* DW SPI controller capabilities */
36 #define DW_SPI_CAP_CS_OVERRIDE BIT(0)
37 #define DW_SPI_CAP_DFS32 BIT(1)
38 #define DW_SPI_CAP_EMODE BIT(2)
39
40 /* Register offsets (Generic for both DWC APB SSI and DWC SSI IP-cores) */
41 #define DW_SPI_CTRLR0 0x00
42 #define DW_SPI_CTRLR1 0x04
43 #define DW_SPI_SSIENR 0x08
44 #define DW_SPI_MWCR 0x0c
45 #define DW_SPI_SER 0x10
46 #define DW_SPI_BAUDR 0x14
47 #define DW_SPI_TXFTLR 0x18
48 #define DW_SPI_RXFTLR 0x1c
49 #define DW_SPI_TXFLR 0x20
50 #define DW_SPI_RXFLR 0x24
51 #define DW_SPI_SR 0x28
52 #define DW_SPI_IMR 0x2c
53 #define DW_SPI_ISR 0x30
54 #define DW_SPI_RISR 0x34
55 #define DW_SPI_TXOICR 0x38
56 #define DW_SPI_RXOICR 0x3c
57 #define DW_SPI_RXUICR 0x40
58 #define DW_SPI_MSTICR 0x44
59 #define DW_SPI_ICR 0x48
60 #define DW_SPI_DMACR 0x4c
61 #define DW_SPI_DMATDLR 0x50
62 #define DW_SPI_DMARDLR 0x54
63 #define DW_SPI_IDR 0x58
64 #define DW_SPI_VERSION 0x5c
65 #define DW_SPI_DR 0x60
66 #define DW_SPI_RX_SAMPLE_DLY 0xf0
67 #define DW_SPI_SPI_CTRLR0 0xf4
68 #define DW_SPI_CS_OVERRIDE 0xf4
69
70 /* Register offsets (StarFive JHB100 DWC SSI IP-cores) */
71 #define DW_SPI_JHB100_INST 0x1000
72 #define DW_SPI_JHB100_ADDR 0x1004
73 #define DW_SPI_JHB100_FILTER_IMR 0x1008
74
75 /* Bit fields in CTRLR0 (DWC APB SSI) */
76 #define DW_PSSI_CTRLR0_DFS_MASK GENMASK(3, 0)
77 #define DW_PSSI_CTRLR0_DFS32_MASK GENMASK(20, 16)
78
79 #define DW_PSSI_CTRLR0_FRF_MASK GENMASK(5, 4)
80 #define DW_SPI_CTRLR0_FRF_MOTO_SPI 0x0
81 #define DW_SPI_CTRLR0_FRF_TI_SSP 0x1
82 #define DW_SPI_CTRLR0_FRF_NS_MICROWIRE 0x2
83 #define DW_SPI_CTRLR0_FRF_RESV 0x3
84
85 #define DW_PSSI_CTRLR0_MODE_MASK GENMASK(7, 6)
86 #define DW_PSSI_CTRLR0_SCPHA BIT(6)
87 #define DW_PSSI_CTRLR0_SCPOL BIT(7)
88
89 #define DW_PSSI_CTRLR0_TMOD_MASK GENMASK(9, 8)
90 #define DW_SPI_CTRLR0_TMOD_TR 0x0 /* xmit & recv */
91 #define DW_SPI_CTRLR0_TMOD_TO 0x1 /* xmit only */
92 #define DW_SPI_CTRLR0_TMOD_RO 0x2 /* recv only */
93 #define DW_SPI_CTRLR0_TMOD_EPROMREAD 0x3 /* eeprom read mode */
94
95 #define DW_PSSI_CTRLR0_SLV_OE BIT(10)
96 #define DW_PSSI_CTRLR0_SRL BIT(11)
97 #define DW_PSSI_CTRLR0_CFS BIT(12)
98
99 /* Bit fields in CTRLR0 (DWC SSI with AHB interface) */
100 #define DW_HSSI_CTRLR0_DFS_MASK GENMASK(4, 0)
101 #define DW_HSSI_CTRLR0_FRF_MASK GENMASK(7, 6)
102 #define DW_HSSI_CTRLR0_SCPHA BIT(8)
103 #define DW_HSSI_CTRLR0_SCPOL BIT(9)
104 #define DW_HSSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
105 #define DW_HSSI_CTRLR0_SRL BIT(13)
106 #define DW_HSSI_CTRLR0_MST BIT(31)
107 #define DW_HSSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
108 #define DW_PSSI_CTRLR0_SPI_FRF_MASK GENMASK(22, 21)
109 #define DW_SPI_CTRLR0_SPI_FRF_STD_SPI 0x0
110 #define DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI 0x1
111 #define DW_SPI_CTRLR0_SPI_FRF_QUAD_SPI 0x2
112 #define DW_SPI_CTRLR0_SPI_FRF_OCT_SPI 0x3
113
114 /* Bit fields in CTRLR1 */
115 #define DW_SPI_NDF_MASK GENMASK(15, 0)
116
117 /* Bit fields in SR, 7 bits */
118 #define DW_SPI_SR_MASK GENMASK(6, 0)
119 #define DW_SPI_SR_BUSY BIT(0)
120 #define DW_SPI_SR_TF_NOT_FULL BIT(1)
121 #define DW_SPI_SR_TF_EMPT BIT(2)
122 #define DW_SPI_SR_RF_NOT_EMPT BIT(3)
123 #define DW_SPI_SR_RF_FULL BIT(4)
124 #define DW_SPI_SR_TX_ERR BIT(5)
125 #define DW_SPI_SR_DCOL BIT(6)
126
127 /* Bit fields in ISR, IMR, RISR, 7 bits */
128 #define DW_SPI_INT_MASK GENMASK(5, 0)
129 #define DW_SPI_INT_TXEI BIT(0)
130 #define DW_SPI_INT_TXOI BIT(1)
131 #define DW_SPI_INT_RXUI BIT(2)
132 #define DW_SPI_INT_RXOI BIT(3)
133 #define DW_SPI_INT_RXFI BIT(4)
134 #define DW_SPI_INT_MSTI BIT(5)
135
136 /* Bit fields in DMACR */
137 #define DW_SPI_DMACR_RDMAE BIT(0)
138 #define DW_SPI_DMACR_TDMAE BIT(1)
139
140 /* Bit fields in SPI_CTRLR0 */
141 #define DW_SPI_ENH_CTRLR0_CLK_STRETCH_EN BIT(30)
142 #define DW_SPI_ENH_CTRLR0_WAIT_CYCLE_MASK GENMASK(15, 11)
143 #define DW_SPI_ENH_CTRLR0_INST_L_MASK GENMASK(9, 8)
144 #define DW_SPI_ENH_CTRLR0_INST_L_INST_L0 0x0
145 #define DW_SPI_ENH_CTRLR0_INST_L_INST_L8 0x2
146 #define DW_SPI_ENH_CTRLR0_INST_L_INST_L16 0x3
147 #define DW_SPI_ENH_CTRLR0_ADDR_L_MASK GENMASK(5, 2)
148 #define DW_SPI_ENH_CTRLR0_TRANS_TYPE_TT0 0x0
149 #define DW_SPI_ENH_CTRLR0_TRANS_TYPE_TT1 0x1
150 #define DW_SPI_ENH_CTRLR0_TRANS_TYPE_TT2 0x2
151 #define DW_SPI_ENH_CTRLR0_TRANS_TYPE_MASK GENMASK(1, 0)
152
153 /* Mem/DMA operations helpers */
154 #define DW_SPI_WAIT_RETRIES 5
155 #define DW_SPI_BUF_SIZE \
156 (sizeof_field(struct spi_mem_op, cmd.opcode) + \
157 sizeof_field(struct spi_mem_op, addr.val) + 256)
158 #define DW_SPI_GET_BYTE(_val, _idx) \
159 ((_val) >> (BITS_PER_BYTE * (_idx)) & 0xff)
160
161 /* Slave spi_transfer/spi_mem_op related */
162 struct dw_spi_cfg {
163 u8 tmode;
164 u8 dfs;
165 u32 ndf;
166 u32 freq;
167 u8 spi_frf;
168 };
169
170 struct dw_spi_enh_cfg {
171 u8 wait_c;
172 u8 inst_l;
173 u8 addr_l;
174 u8 trans_t;
175 };
176
177 struct dw_spi;
178 struct dw_spi_dma_ops {
179 int (*dma_init)(struct device *dev, struct dw_spi *dws);
180 void (*dma_exit)(struct dw_spi *dws);
181 int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
182 bool (*can_dma)(struct spi_controller *ctlr, struct spi_device *spi,
183 struct spi_transfer *xfer);
184 int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
185 void (*dma_stop)(struct dw_spi *dws);
186 };
187
188 struct dw_spi {
189 struct spi_controller *ctlr;
190
191 u32 ip; /* Synopsys DW SSI IP-core ID */
192 u32 ver; /* Synopsys component version */
193 u32 caps; /* DW SPI capabilities */
194
195 void __iomem *regs;
196 unsigned long paddr;
197 int irq;
198 u32 fifo_len; /* depth of the FIFO buffer */
199 unsigned int dfs_offset; /* CTRLR0 DFS field offset */
200 u32 max_mem_freq; /* max mem-ops bus freq */
201 u32 max_freq; /* max bus freq supported */
202
203 u32 reg_io_width; /* DR I/O width in bytes */
204 u32 num_cs; /* chip select lines */
205 u16 bus_num;
206 void (*set_cs)(struct spi_device *spi, bool enable);
207 int (*set_addr_nbyte)(struct spi_device *spi, u8 nbyte);
208
209 /* Current message transfer state info */
210 void *tx;
211 unsigned int tx_len;
212 void *rx;
213 unsigned int rx_len;
214 u8 buf[DW_SPI_BUF_SIZE];
215 int dma_mapped;
216 u8 n_bytes; /* current is a 1/2 bytes op */
217 irqreturn_t (*transfer_handler)(struct dw_spi *dws);
218 u32 current_freq; /* frequency in hz */
219 u32 cur_rx_sample_dly;
220 u32 def_rx_sample_dly_ns;
221
222 /* Custom memory operations */
223 struct spi_controller_mem_ops mem_ops;
224
225 /* DMA info */
226 struct dma_chan *txchan;
227 u32 txburst;
228 struct dma_chan *rxchan;
229 u32 rxburst;
230 u32 dma_sg_burst;
231 u32 dma_addr_widths;
232 unsigned long dma_chan_busy;
233 dma_addr_t dma_addr; /* phy address of the Data register */
234 const struct dw_spi_dma_ops *dma_ops;
235 struct completion dma_completion;
236
237 #define DW_SPI_QUIRK_JHB100 BIT(0)
238 u32 quirk_flags;
239
240 #ifdef CONFIG_DEBUG_FS
241 struct dentry *debugfs;
242 struct debugfs_regset32 regset;
243 #endif
244 };
245
dw_readl(struct dw_spi * dws,u32 offset)246 static inline u32 dw_readl(struct dw_spi *dws, u32 offset)
247 {
248 return __raw_readl(dws->regs + offset);
249 }
250
dw_writel(struct dw_spi * dws,u32 offset,u32 val)251 static inline void dw_writel(struct dw_spi *dws, u32 offset, u32 val)
252 {
253 __raw_writel(val, dws->regs + offset);
254 }
255
dw_read_io_reg(struct dw_spi * dws,u32 offset)256 static inline u32 dw_read_io_reg(struct dw_spi *dws, u32 offset)
257 {
258 switch (dws->reg_io_width) {
259 case 2:
260 return readw_relaxed(dws->regs + offset);
261 case 4:
262 default:
263 return readl_relaxed(dws->regs + offset);
264 }
265 }
266
dw_write_io_reg(struct dw_spi * dws,u32 offset,u32 val)267 static inline void dw_write_io_reg(struct dw_spi *dws, u32 offset, u32 val)
268 {
269 switch (dws->reg_io_width) {
270 case 2:
271 writew_relaxed(val, dws->regs + offset);
272 break;
273 case 4:
274 default:
275 writel_relaxed(val, dws->regs + offset);
276 break;
277 }
278 }
279
dw_spi_enable_chip(struct dw_spi * dws,int enable)280 static inline void dw_spi_enable_chip(struct dw_spi *dws, int enable)
281 {
282 dw_writel(dws, DW_SPI_SSIENR, (enable ? 1 : 0));
283 }
284
dw_spi_set_clk(struct dw_spi * dws,u16 div)285 static inline void dw_spi_set_clk(struct dw_spi *dws, u16 div)
286 {
287 dw_writel(dws, DW_SPI_BAUDR, div);
288 }
289
290 /* Disable IRQ bits */
dw_spi_mask_intr(struct dw_spi * dws,u32 mask)291 static inline void dw_spi_mask_intr(struct dw_spi *dws, u32 mask)
292 {
293 u32 new_mask;
294
295 new_mask = dw_readl(dws, DW_SPI_IMR) & ~mask;
296 dw_writel(dws, DW_SPI_IMR, new_mask);
297 }
298
299 /* Enable IRQ bits */
dw_spi_umask_intr(struct dw_spi * dws,u32 mask)300 static inline void dw_spi_umask_intr(struct dw_spi *dws, u32 mask)
301 {
302 u32 new_mask;
303
304 new_mask = dw_readl(dws, DW_SPI_IMR) | mask;
305 dw_writel(dws, DW_SPI_IMR, new_mask);
306 }
307
308 /* Disable JHB100 SPI filter IRQ bits */
dw_spi_jhb100_mask_intr(struct dw_spi * dws,u32 mask)309 static inline void dw_spi_jhb100_mask_intr(struct dw_spi *dws, u32 mask)
310 {
311 u32 new_mask;
312
313 new_mask = dw_readl(dws, DW_SPI_JHB100_FILTER_IMR) & ~mask;
314 dw_writel(dws, DW_SPI_JHB100_FILTER_IMR, new_mask);
315 }
316
317 /*
318 * This disables the SPI controller, interrupts, clears the interrupts status
319 * and CS, then re-enables the controller back. Transmit and receive FIFO
320 * buffers are cleared when the device is disabled.
321 */
dw_spi_reset_chip(struct dw_spi * dws)322 static inline void dw_spi_reset_chip(struct dw_spi *dws)
323 {
324 dw_spi_enable_chip(dws, 0);
325 dw_spi_mask_intr(dws, 0xff);
326 dw_readl(dws, DW_SPI_ICR);
327 dw_writel(dws, DW_SPI_SER, 0);
328 dw_spi_enable_chip(dws, 1);
329 }
330
dw_spi_shutdown_chip(struct dw_spi * dws)331 static inline void dw_spi_shutdown_chip(struct dw_spi *dws)
332 {
333 dw_spi_enable_chip(dws, 0);
334 dw_spi_set_clk(dws, 0);
335 dws->current_freq = 0;
336 dws->cur_rx_sample_dly = 0;
337 }
338
339 extern void dw_spi_set_cs(struct spi_device *spi, bool enable);
340 extern void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
341 struct dw_spi_cfg *cfg, struct dw_spi_enh_cfg *enh_cfg);
342 extern int dw_spi_check_status(struct dw_spi *dws, bool raw);
343 extern int dw_spi_add_controller(struct device *dev, struct dw_spi *dws);
344 extern void dw_spi_remove_controller(struct dw_spi *dws);
345 extern int dw_spi_suspend_controller(struct dw_spi *dws);
346 extern int dw_spi_resume_controller(struct dw_spi *dws);
347
348 #ifdef CONFIG_SPI_DW_DMA
349
350 extern void dw_spi_dma_setup_mfld(struct dw_spi *dws);
351 extern void dw_spi_dma_setup_generic(struct dw_spi *dws);
352
353 #else
354
dw_spi_dma_setup_mfld(struct dw_spi * dws)355 static inline void dw_spi_dma_setup_mfld(struct dw_spi *dws) {}
dw_spi_dma_setup_generic(struct dw_spi * dws)356 static inline void dw_spi_dma_setup_generic(struct dw_spi *dws) {}
357
358 #endif /* !CONFIG_SPI_DW_DMA */
359
360 #endif /* __SPI_DW_H__ */
361