1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v11_0.h"
29 #include "smu11_driver_if_vangogh.h"
30 #include "vangogh_ppt.h"
31 #include "smu_v11_5_ppsmc.h"
32 #include "smu_v11_5_pmfw.h"
33 #include "smu_cmn.h"
34 #include "soc15_common.h"
35 #include "asic_reg/gc/gc_10_3_0_offset.h"
36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
37 #include <asm/processor.h>
38
39 /*
40 * DO NOT use these for err/warn/info/debug messages.
41 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
42 * They are more MGPU friendly.
43 */
44 #undef pr_err
45 #undef pr_warn
46 #undef pr_info
47 #undef pr_debug
48
49 // Registers related to GFXOFF
50 // addressBlock: smuio_smuio_SmuSmuioDec
51 // base address: 0x5a000
52 #define mmSMUIO_GFX_MISC_CNTL 0x00c5
53 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX 0
54
55 //SMUIO_GFX_MISC_CNTL
56 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT 0x0
57 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT 0x1
58 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK 0x00000001L
59 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK 0x00000006L
60
61 static const struct smu_feature_bits vangogh_dpm_features = {
62 .bits = {
63 SMU_FEATURE_BIT_INIT(FEATURE_CCLK_DPM_BIT),
64 SMU_FEATURE_BIT_INIT(FEATURE_VCN_DPM_BIT),
65 SMU_FEATURE_BIT_INIT(FEATURE_FCLK_DPM_BIT),
66 SMU_FEATURE_BIT_INIT(FEATURE_SOCCLK_DPM_BIT),
67 SMU_FEATURE_BIT_INIT(FEATURE_MP0CLK_DPM_BIT),
68 SMU_FEATURE_BIT_INIT(FEATURE_LCLK_DPM_BIT),
69 SMU_FEATURE_BIT_INIT(FEATURE_SHUBCLK_DPM_BIT),
70 SMU_FEATURE_BIT_INIT(FEATURE_DCFCLK_DPM_BIT),
71 SMU_FEATURE_BIT_INIT(FEATURE_GFX_DPM_BIT)
72 }
73 };
74
75 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
76 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
77 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 0),
78 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 0),
79 MSG_MAP(EnableGfxOff, PPSMC_MSG_EnableGfxOff, 0),
80 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
81 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
82 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 0),
83 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 0),
84 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
85 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
86 MSG_MAP(RlcPowerNotify, PPSMC_MSG_RlcPowerNotify, 0),
87 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 0),
88 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxclk, 0),
89 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 0),
90 MSG_MAP(SetHardMinIspiclkByFreq, PPSMC_MSG_SetHardMinIspiclkByFreq, 0),
91 MSG_MAP(SetHardMinIspxclkByFreq, PPSMC_MSG_SetHardMinIspxclkByFreq, 0),
92 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 0),
93 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 0),
94 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 0),
95 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
96 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 0),
97 MSG_MAP(GetEnabledSmuFeatures, PPSMC_MSG_GetEnabledSmuFeatures, 0),
98 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 0),
99 MSG_MAP(SetSoftMinFclk, PPSMC_MSG_SetSoftMinFclk, 0),
100 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 0),
101 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 0),
102 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 0),
103 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 0),
104 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 0),
105 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 0),
106 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 0),
107 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 0),
108 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 0),
109 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 0),
110 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
111 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
112 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 0),
113 MSG_MAP(SetSoftMinSocclkByFreq, PPSMC_MSG_SetSoftMinSocclkByFreq, 0),
114 MSG_MAP(PowerUpCvip, PPSMC_MSG_PowerUpCvip, 0),
115 MSG_MAP(PowerDownCvip, PPSMC_MSG_PowerDownCvip, 0),
116 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
117 MSG_MAP(GetThermalLimit, PPSMC_MSG_GetThermalLimit, 0),
118 MSG_MAP(GetCurrentTemperature, PPSMC_MSG_GetCurrentTemperature, 0),
119 MSG_MAP(GetCurrentPower, PPSMC_MSG_GetCurrentPower, 0),
120 MSG_MAP(GetCurrentVoltage, PPSMC_MSG_GetCurrentVoltage, 0),
121 MSG_MAP(GetCurrentCurrent, PPSMC_MSG_GetCurrentCurrent, 0),
122 MSG_MAP(GetAverageCpuActivity, PPSMC_MSG_GetAverageCpuActivity, 0),
123 MSG_MAP(GetAverageGfxActivity, PPSMC_MSG_GetAverageGfxActivity, 0),
124 MSG_MAP(GetAveragePower, PPSMC_MSG_GetAveragePower, 0),
125 MSG_MAP(GetAverageTemperature, PPSMC_MSG_GetAverageTemperature, 0),
126 MSG_MAP(SetAveragePowerTimeConstant, PPSMC_MSG_SetAveragePowerTimeConstant, 0),
127 MSG_MAP(SetAverageActivityTimeConstant, PPSMC_MSG_SetAverageActivityTimeConstant, 0),
128 MSG_MAP(SetAverageTemperatureTimeConstant, PPSMC_MSG_SetAverageTemperatureTimeConstant, 0),
129 MSG_MAP(SetMitigationEndHysteresis, PPSMC_MSG_SetMitigationEndHysteresis, 0),
130 MSG_MAP(GetCurrentFreq, PPSMC_MSG_GetCurrentFreq, 0),
131 MSG_MAP(SetReducedPptLimit, PPSMC_MSG_SetReducedPptLimit, 0),
132 MSG_MAP(SetReducedThermalLimit, PPSMC_MSG_SetReducedThermalLimit, 0),
133 MSG_MAP(DramLogSetDramAddr, PPSMC_MSG_DramLogSetDramAddr, 0),
134 MSG_MAP(StartDramLogging, PPSMC_MSG_StartDramLogging, 0),
135 MSG_MAP(StopDramLogging, PPSMC_MSG_StopDramLogging, 0),
136 MSG_MAP(SetSoftMinCclk, PPSMC_MSG_SetSoftMinCclk, 0),
137 MSG_MAP(SetSoftMaxCclk, PPSMC_MSG_SetSoftMaxCclk, 0),
138 MSG_MAP(RequestActiveWgp, PPSMC_MSG_RequestActiveWgp, 0),
139 MSG_MAP(SetFastPPTLimit, PPSMC_MSG_SetFastPPTLimit, 0),
140 MSG_MAP(SetSlowPPTLimit, PPSMC_MSG_SetSlowPPTLimit, 0),
141 MSG_MAP(GetFastPPTLimit, PPSMC_MSG_GetFastPPTLimit, 0),
142 MSG_MAP(GetSlowPPTLimit, PPSMC_MSG_GetSlowPPTLimit, 0),
143 MSG_MAP(GetGfxOffStatus, PPSMC_MSG_GetGfxOffStatus, 0),
144 MSG_MAP(GetGfxOffEntryCount, PPSMC_MSG_GetGfxOffEntryCount, 0),
145 MSG_MAP(LogGfxOffResidency, PPSMC_MSG_LogGfxOffResidency, 0),
146 };
147
148 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
149 FEA_MAP(PPT),
150 FEA_MAP(TDC),
151 FEA_MAP(THERMAL),
152 FEA_MAP(DS_GFXCLK),
153 FEA_MAP(DS_SOCCLK),
154 FEA_MAP(DS_LCLK),
155 FEA_MAP(DS_FCLK),
156 FEA_MAP(DS_MP1CLK),
157 FEA_MAP(DS_MP0CLK),
158 FEA_MAP(ATHUB_PG),
159 FEA_MAP(CCLK_DPM),
160 FEA_MAP(FAN_CONTROLLER),
161 FEA_MAP(ULV),
162 FEA_MAP(VCN_DPM),
163 FEA_MAP(LCLK_DPM),
164 FEA_MAP(SHUBCLK_DPM),
165 FEA_MAP(DCFCLK_DPM),
166 FEA_MAP(DS_DCFCLK),
167 FEA_MAP(S0I2),
168 FEA_MAP(SMU_LOW_POWER),
169 FEA_MAP(GFX_DEM),
170 FEA_MAP(PSI),
171 FEA_MAP(PROCHOT),
172 FEA_MAP(CPUOFF),
173 FEA_MAP(STAPM),
174 FEA_MAP(S0I3),
175 FEA_MAP(DF_CSTATES),
176 FEA_MAP(PERF_LIMIT),
177 FEA_MAP(CORE_DLDO),
178 FEA_MAP(RSMU_LOW_POWER),
179 FEA_MAP(SMN_LOW_POWER),
180 FEA_MAP(THM_LOW_POWER),
181 FEA_MAP(SMUIO_LOW_POWER),
182 FEA_MAP(MP1_LOW_POWER),
183 FEA_MAP(DS_VCN),
184 FEA_MAP(CPPC),
185 FEA_MAP(OS_CSTATES),
186 FEA_MAP(ISP_DPM),
187 FEA_MAP(A55_DPM),
188 FEA_MAP(CVIP_DSP_DPM),
189 FEA_MAP(MSMU_LOW_POWER),
190 FEA_MAP_REVERSE(SOCCLK),
191 FEA_MAP_REVERSE(FCLK),
192 FEA_MAP_HALF_REVERSE(GFX),
193 };
194
195 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
196 TAB_MAP_VALID(WATERMARKS),
197 TAB_MAP_VALID(SMU_METRICS),
198 TAB_MAP_VALID(CUSTOM_DPM),
199 TAB_MAP_VALID(DPMCLOCKS),
200 };
201
202 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
203 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
204 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
205 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
206 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
207 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
208 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED, WORKLOAD_PPLIB_CAPPED_BIT),
209 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED, WORKLOAD_PPLIB_UNCAPPED_BIT),
210 };
211
212 static const uint8_t vangogh_throttler_map[] = {
213 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
214 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
215 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
216 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
217 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
218 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
219 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
220 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
221 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
222 [THROTTLER_STATUS_BIT_TDC_GFX] = (SMU_THROTTLER_TDC_GFX_BIT),
223 [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
224 };
225
vangogh_tables_init(struct smu_context * smu)226 static int vangogh_tables_init(struct smu_context *smu)
227 {
228 struct smu_table_context *smu_table = &smu->smu_table;
229 struct smu_table *tables = smu_table->tables;
230 int ret;
231
232 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
233 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
234 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
235 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
236 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
237 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
238 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
239 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
240 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)),
241 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
242
243 smu_table->metrics_table = kzalloc(max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)), GFP_KERNEL);
244 if (!smu_table->metrics_table)
245 goto err0_out;
246 smu_table->metrics_time = 0;
247
248 ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS,
249 max3(sizeof(struct gpu_metrics_v2_2),
250 sizeof(struct gpu_metrics_v2_3),
251 sizeof(struct gpu_metrics_v2_4)),
252 SMU_GPU_METRICS_CACHE_INTERVAL);
253 if (ret)
254 goto err1_out;
255
256 smu_table->watermarks_table = kzalloc_obj(Watermarks_t);
257 if (!smu_table->watermarks_table)
258 goto err2_out;
259
260 smu_table->clocks_table = kzalloc_obj(DpmClocks_t);
261 if (!smu_table->clocks_table)
262 goto err3_out;
263
264 return 0;
265
266 err3_out:
267 kfree(smu_table->watermarks_table);
268 err2_out:
269 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
270 err1_out:
271 kfree(smu_table->metrics_table);
272 err0_out:
273 return -ENOMEM;
274 }
275
vangogh_get_legacy_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)276 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
277 MetricsMember_t member,
278 uint32_t *value)
279 {
280 struct smu_table_context *smu_table = &smu->smu_table;
281 SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table;
282 int ret = 0;
283
284 ret = smu_cmn_get_metrics_table(smu,
285 NULL,
286 false);
287 if (ret)
288 return ret;
289
290 switch (member) {
291 case METRICS_CURR_GFXCLK:
292 *value = metrics->GfxclkFrequency;
293 break;
294 case METRICS_AVERAGE_SOCCLK:
295 *value = metrics->SocclkFrequency;
296 break;
297 case METRICS_AVERAGE_VCLK:
298 *value = metrics->VclkFrequency;
299 break;
300 case METRICS_AVERAGE_DCLK:
301 *value = metrics->DclkFrequency;
302 break;
303 case METRICS_CURR_UCLK:
304 *value = metrics->MemclkFrequency;
305 break;
306 case METRICS_AVERAGE_GFXACTIVITY:
307 *value = metrics->GfxActivity / 100;
308 break;
309 case METRICS_AVERAGE_VCNACTIVITY:
310 *value = metrics->UvdActivity / 100;
311 break;
312 case METRICS_AVERAGE_SOCKETPOWER:
313 *value = (metrics->CurrentSocketPower << 8) /
314 1000 ;
315 break;
316 case METRICS_TEMPERATURE_EDGE:
317 *value = metrics->GfxTemperature / 100 *
318 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
319 break;
320 case METRICS_TEMPERATURE_HOTSPOT:
321 *value = metrics->SocTemperature / 100 *
322 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
323 break;
324 case METRICS_THROTTLER_STATUS:
325 *value = metrics->ThrottlerStatus;
326 break;
327 case METRICS_VOLTAGE_VDDGFX:
328 *value = metrics->Voltage[2];
329 break;
330 case METRICS_VOLTAGE_VDDSOC:
331 *value = metrics->Voltage[1];
332 break;
333 case METRICS_AVERAGE_CPUCLK:
334 memcpy(value, &metrics->CoreFrequency[0],
335 smu->cpu_core_num * sizeof(uint16_t));
336 break;
337 default:
338 *value = UINT_MAX;
339 break;
340 }
341
342 return ret;
343 }
344
vangogh_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)345 static int vangogh_get_smu_metrics_data(struct smu_context *smu,
346 MetricsMember_t member,
347 uint32_t *value)
348 {
349 struct smu_table_context *smu_table = &smu->smu_table;
350 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
351 int ret = 0;
352
353 ret = smu_cmn_get_metrics_table(smu,
354 NULL,
355 false);
356 if (ret)
357 return ret;
358
359 switch (member) {
360 case METRICS_CURR_GFXCLK:
361 *value = metrics->Current.GfxclkFrequency;
362 break;
363 case METRICS_AVERAGE_SOCCLK:
364 *value = metrics->Current.SocclkFrequency;
365 break;
366 case METRICS_AVERAGE_VCLK:
367 *value = metrics->Current.VclkFrequency;
368 break;
369 case METRICS_AVERAGE_DCLK:
370 *value = metrics->Current.DclkFrequency;
371 break;
372 case METRICS_CURR_UCLK:
373 *value = metrics->Current.MemclkFrequency;
374 break;
375 case METRICS_AVERAGE_GFXACTIVITY:
376 *value = metrics->Current.GfxActivity;
377 break;
378 case METRICS_AVERAGE_VCNACTIVITY:
379 *value = metrics->Current.UvdActivity;
380 break;
381 case METRICS_AVERAGE_SOCKETPOWER:
382 *value = (metrics->Average.CurrentSocketPower << 8) /
383 1000;
384 break;
385 case METRICS_CURR_SOCKETPOWER:
386 *value = (metrics->Current.CurrentSocketPower << 8) /
387 1000;
388 break;
389 case METRICS_TEMPERATURE_EDGE:
390 *value = metrics->Current.GfxTemperature / 100 *
391 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
392 break;
393 case METRICS_TEMPERATURE_HOTSPOT:
394 *value = metrics->Current.SocTemperature / 100 *
395 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
396 break;
397 case METRICS_THROTTLER_STATUS:
398 *value = metrics->Current.ThrottlerStatus;
399 break;
400 case METRICS_VOLTAGE_VDDGFX:
401 *value = metrics->Current.Voltage[2];
402 break;
403 case METRICS_VOLTAGE_VDDSOC:
404 *value = metrics->Current.Voltage[1];
405 break;
406 case METRICS_AVERAGE_CPUCLK:
407 memcpy(value, &metrics->Current.CoreFrequency[0],
408 smu->cpu_core_num * sizeof(uint16_t));
409 break;
410 default:
411 *value = UINT_MAX;
412 break;
413 }
414
415 return ret;
416 }
417
vangogh_common_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)418 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu,
419 MetricsMember_t member,
420 uint32_t *value)
421 {
422 int ret = 0;
423
424 if (smu->smc_fw_if_version < 0x3)
425 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);
426 else
427 ret = vangogh_get_smu_metrics_data(smu, member, value);
428
429 return ret;
430 }
431
vangogh_allocate_dpm_context(struct smu_context * smu)432 static int vangogh_allocate_dpm_context(struct smu_context *smu)
433 {
434 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
435
436 smu_dpm->dpm_context = kzalloc_obj(struct smu_11_0_dpm_context);
437 if (!smu_dpm->dpm_context)
438 return -ENOMEM;
439
440 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
441
442 return 0;
443 }
444
vangogh_init_smc_tables(struct smu_context * smu)445 static int vangogh_init_smc_tables(struct smu_context *smu)
446 {
447 int ret = 0;
448
449 ret = vangogh_tables_init(smu);
450 if (ret)
451 return ret;
452
453 ret = vangogh_allocate_dpm_context(smu);
454 if (ret)
455 return ret;
456
457 #ifdef CONFIG_X86
458 /* AMD x86 APU only */
459 smu->cpu_core_num = topology_num_cores_per_package();
460 #else
461 smu->cpu_core_num = 4;
462 #endif
463
464 return smu_v11_0_init_smc_tables(smu);
465 }
466
vangogh_dpm_set_vcn_enable(struct smu_context * smu,bool enable,int inst)467 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu,
468 bool enable,
469 int inst)
470 {
471 int ret = 0;
472
473 if (enable) {
474 /* vcn dpm on is a prerequisite for vcn power gate messages */
475 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
476 if (ret)
477 return ret;
478 } else {
479 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
480 if (ret)
481 return ret;
482 }
483
484 return ret;
485 }
486
vangogh_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)487 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
488 {
489 int ret = 0;
490
491 if (enable) {
492 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
493 if (ret)
494 return ret;
495 } else {
496 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
497 if (ret)
498 return ret;
499 }
500
501 return ret;
502 }
503
vangogh_is_dpm_running(struct smu_context * smu)504 static bool vangogh_is_dpm_running(struct smu_context *smu)
505 {
506 struct amdgpu_device *adev = smu->adev;
507 int ret = 0;
508 struct smu_feature_bits feature_enabled;
509
510 /* we need to re-init after suspend so return false */
511 if (adev->in_suspend)
512 return false;
513
514 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
515
516 if (ret)
517 return false;
518
519 return smu_feature_bits_test_mask(&feature_enabled,
520 vangogh_dpm_features.bits);
521 }
522
vangogh_get_dpm_clk_limited(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)523 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
524 uint32_t dpm_level, uint32_t *freq)
525 {
526 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
527
528 if (!clk_table || clk_type >= SMU_CLK_COUNT)
529 return -EINVAL;
530
531 switch (clk_type) {
532 case SMU_SOCCLK:
533 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
534 return -EINVAL;
535 *freq = clk_table->SocClocks[dpm_level];
536 break;
537 case SMU_VCLK:
538 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
539 return -EINVAL;
540 *freq = clk_table->VcnClocks[dpm_level].vclk;
541 break;
542 case SMU_DCLK:
543 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
544 return -EINVAL;
545 *freq = clk_table->VcnClocks[dpm_level].dclk;
546 break;
547 case SMU_UCLK:
548 case SMU_MCLK:
549 if (dpm_level >= clk_table->NumDfPstatesEnabled)
550 return -EINVAL;
551 *freq = clk_table->DfPstateTable[dpm_level].memclk;
552
553 break;
554 case SMU_FCLK:
555 if (dpm_level >= clk_table->NumDfPstatesEnabled)
556 return -EINVAL;
557 *freq = clk_table->DfPstateTable[dpm_level].fclk;
558 break;
559 default:
560 return -EINVAL;
561 }
562
563 return 0;
564 }
565
vangogh_emit_legacy_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf,int * offset)566 static int vangogh_emit_legacy_clk_levels(struct smu_context *smu,
567 enum smu_clk_type clk_type, char *buf,
568 int *offset)
569 {
570 int i, idx, size = *offset, ret = 0, start_offset = *offset;
571 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
572 SmuMetrics_legacy_t metrics;
573 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
574 uint32_t cur_value = 0, value = 0, count = 0;
575 bool cur_value_match_level = false;
576
577 memset(&metrics, 0, sizeof(metrics));
578
579 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
580 if (ret)
581 return ret;
582
583 switch (clk_type) {
584 case SMU_OD_SCLK:
585 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
586 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
587 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
588 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
589 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
590 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
591 }
592 break;
593 case SMU_OD_CCLK:
594 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
595 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
596 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
597 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
598 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
599 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
600 }
601 break;
602 case SMU_OD_RANGE:
603 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
604 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
605 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
606 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
607 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
608 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
609 }
610 break;
611 case SMU_SOCCLK:
612 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
613 count = clk_table->NumSocClkLevelsEnabled;
614 cur_value = metrics.SocclkFrequency;
615 break;
616 case SMU_VCLK:
617 count = clk_table->VcnClkLevelsEnabled;
618 cur_value = metrics.VclkFrequency;
619 break;
620 case SMU_DCLK:
621 count = clk_table->VcnClkLevelsEnabled;
622 cur_value = metrics.DclkFrequency;
623 break;
624 case SMU_MCLK:
625 count = clk_table->NumDfPstatesEnabled;
626 cur_value = metrics.MemclkFrequency;
627 break;
628 case SMU_FCLK:
629 count = clk_table->NumDfPstatesEnabled;
630 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
631 if (ret)
632 return ret;
633 break;
634 default:
635 break;
636 }
637
638 switch (clk_type) {
639 case SMU_SOCCLK:
640 case SMU_VCLK:
641 case SMU_DCLK:
642 case SMU_MCLK:
643 case SMU_FCLK:
644 for (i = 0; i < count; i++) {
645 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
646 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
647 if (ret)
648 return ret;
649 if (!value)
650 continue;
651 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
652 cur_value == value ? "*" : "");
653 if (cur_value == value)
654 cur_value_match_level = true;
655 }
656
657 if (!cur_value_match_level)
658 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
659 break;
660 default:
661 break;
662 }
663
664 *offset += size - start_offset;
665
666 return 0;
667 }
668
vangogh_emit_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf,int * offset)669 static int vangogh_emit_clk_levels(struct smu_context *smu,
670 enum smu_clk_type clk_type, char *buf,
671 int *offset)
672 {
673 int i, idx, size = *offset, ret = 0, start_offset = *offset;
674 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
675 SmuMetrics_t metrics;
676 uint32_t cur_value = 0, value = 0, count = 0;
677 bool cur_value_match_level = false;
678 uint32_t min, max;
679
680 memset(&metrics, 0, sizeof(metrics));
681
682 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
683 if (ret)
684 return ret;
685
686 switch (clk_type) {
687 case SMU_OD_SCLK:
688 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
689 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
690 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
691 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
692 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
693 break;
694 case SMU_OD_CCLK:
695 size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n", smu->cpu_core_id_select);
696 size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
697 (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
698 size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
699 (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
700 break;
701 case SMU_OD_RANGE:
702 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
703 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
704 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
705 size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
706 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
707 break;
708 case SMU_SOCCLK:
709 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
710 count = clk_table->NumSocClkLevelsEnabled;
711 cur_value = metrics.Current.SocclkFrequency;
712 break;
713 case SMU_VCLK:
714 count = clk_table->VcnClkLevelsEnabled;
715 cur_value = metrics.Current.VclkFrequency;
716 break;
717 case SMU_DCLK:
718 count = clk_table->VcnClkLevelsEnabled;
719 cur_value = metrics.Current.DclkFrequency;
720 break;
721 case SMU_MCLK:
722 count = clk_table->NumDfPstatesEnabled;
723 cur_value = metrics.Current.MemclkFrequency;
724 break;
725 case SMU_FCLK:
726 count = clk_table->NumDfPstatesEnabled;
727 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
728 if (ret)
729 return ret;
730 break;
731 case SMU_GFXCLK:
732 case SMU_SCLK:
733 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
734 if (ret) {
735 return ret;
736 }
737 break;
738 default:
739 break;
740 }
741
742 switch (clk_type) {
743 case SMU_SOCCLK:
744 case SMU_VCLK:
745 case SMU_DCLK:
746 case SMU_MCLK:
747 case SMU_FCLK:
748 for (i = 0; i < count; i++) {
749 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
750 ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
751 if (ret)
752 return ret;
753 if (!value)
754 continue;
755 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
756 cur_value == value ? "*" : "");
757 if (cur_value == value)
758 cur_value_match_level = true;
759 }
760
761 if (!cur_value_match_level)
762 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
763 break;
764 case SMU_GFXCLK:
765 case SMU_SCLK:
766 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
767 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
768 if (cur_value == max)
769 i = 2;
770 else if (cur_value == min)
771 i = 0;
772 else
773 i = 1;
774 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
775 i == 0 ? "*" : "");
776 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
777 i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
778 i == 1 ? "*" : "");
779 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
780 i == 2 ? "*" : "");
781 break;
782 default:
783 break;
784 }
785
786 *offset += size - start_offset;
787
788 return 0;
789 }
790
vangogh_common_emit_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf,int * offset)791 static int vangogh_common_emit_clk_levels(struct smu_context *smu,
792 enum smu_clk_type clk_type, char *buf,
793 int *offset)
794 {
795 int ret = 0;
796
797 if (smu->smc_fw_if_version < 0x3)
798 ret = vangogh_emit_legacy_clk_levels(smu, clk_type, buf, offset);
799 else
800 ret = vangogh_emit_clk_levels(smu, clk_type, buf, offset);
801
802 return ret;
803 }
804
vangogh_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * vclk_mask,uint32_t * dclk_mask,uint32_t * mclk_mask,uint32_t * fclk_mask,uint32_t * soc_mask)805 static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
806 enum amd_dpm_forced_level level,
807 uint32_t *vclk_mask,
808 uint32_t *dclk_mask,
809 uint32_t *mclk_mask,
810 uint32_t *fclk_mask,
811 uint32_t *soc_mask)
812 {
813 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
814
815 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
816 if (mclk_mask)
817 *mclk_mask = clk_table->NumDfPstatesEnabled - 1;
818
819 if (fclk_mask)
820 *fclk_mask = clk_table->NumDfPstatesEnabled - 1;
821
822 if (soc_mask)
823 *soc_mask = 0;
824 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
825 if (mclk_mask)
826 *mclk_mask = 0;
827
828 if (fclk_mask)
829 *fclk_mask = 0;
830
831 if (soc_mask)
832 *soc_mask = 1;
833
834 if (vclk_mask)
835 *vclk_mask = 1;
836
837 if (dclk_mask)
838 *dclk_mask = 1;
839 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) {
840 if (mclk_mask)
841 *mclk_mask = 0;
842
843 if (fclk_mask)
844 *fclk_mask = 0;
845
846 if (soc_mask)
847 *soc_mask = 1;
848
849 if (vclk_mask)
850 *vclk_mask = 1;
851
852 if (dclk_mask)
853 *dclk_mask = 1;
854 }
855
856 return 0;
857 }
858
vangogh_clk_dpm_is_enabled(struct smu_context * smu,enum smu_clk_type clk_type)859 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
860 enum smu_clk_type clk_type)
861 {
862 enum smu_feature_mask feature_id = 0;
863
864 switch (clk_type) {
865 case SMU_MCLK:
866 case SMU_UCLK:
867 case SMU_FCLK:
868 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
869 break;
870 case SMU_GFXCLK:
871 case SMU_SCLK:
872 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
873 break;
874 case SMU_SOCCLK:
875 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
876 break;
877 case SMU_VCLK:
878 case SMU_DCLK:
879 feature_id = SMU_FEATURE_VCN_DPM_BIT;
880 break;
881 default:
882 return true;
883 }
884
885 if (!smu_cmn_feature_is_enabled(smu, feature_id))
886 return false;
887
888 return true;
889 }
890
vangogh_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)891 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
892 enum smu_clk_type clk_type,
893 uint32_t *min,
894 uint32_t *max)
895 {
896 int ret = 0;
897 uint32_t soc_mask;
898 uint32_t vclk_mask;
899 uint32_t dclk_mask;
900 uint32_t mclk_mask;
901 uint32_t fclk_mask;
902 uint32_t clock_limit;
903
904 if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
905 switch (clk_type) {
906 case SMU_MCLK:
907 case SMU_UCLK:
908 clock_limit = smu->smu_table.boot_values.uclk;
909 break;
910 case SMU_FCLK:
911 clock_limit = smu->smu_table.boot_values.fclk;
912 break;
913 case SMU_GFXCLK:
914 case SMU_SCLK:
915 clock_limit = smu->smu_table.boot_values.gfxclk;
916 break;
917 case SMU_SOCCLK:
918 clock_limit = smu->smu_table.boot_values.socclk;
919 break;
920 case SMU_VCLK:
921 clock_limit = smu->smu_table.boot_values.vclk;
922 break;
923 case SMU_DCLK:
924 clock_limit = smu->smu_table.boot_values.dclk;
925 break;
926 default:
927 clock_limit = 0;
928 break;
929 }
930
931 /* clock in Mhz unit */
932 if (min)
933 *min = clock_limit / 100;
934 if (max)
935 *max = clock_limit / 100;
936
937 return 0;
938 }
939 if (max) {
940 ret = vangogh_get_profiling_clk_mask(smu,
941 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
942 &vclk_mask,
943 &dclk_mask,
944 &mclk_mask,
945 &fclk_mask,
946 &soc_mask);
947 if (ret)
948 goto failed;
949
950 switch (clk_type) {
951 case SMU_UCLK:
952 case SMU_MCLK:
953 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
954 if (ret)
955 goto failed;
956 break;
957 case SMU_SOCCLK:
958 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
959 if (ret)
960 goto failed;
961 break;
962 case SMU_FCLK:
963 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
964 if (ret)
965 goto failed;
966 break;
967 case SMU_VCLK:
968 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
969 if (ret)
970 goto failed;
971 break;
972 case SMU_DCLK:
973 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
974 if (ret)
975 goto failed;
976 break;
977 default:
978 ret = -EINVAL;
979 goto failed;
980 }
981 }
982 if (min) {
983 ret = vangogh_get_profiling_clk_mask(smu,
984 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK,
985 NULL,
986 NULL,
987 &mclk_mask,
988 &fclk_mask,
989 &soc_mask);
990 if (ret)
991 goto failed;
992
993 vclk_mask = dclk_mask = 0;
994
995 switch (clk_type) {
996 case SMU_UCLK:
997 case SMU_MCLK:
998 ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
999 if (ret)
1000 goto failed;
1001 break;
1002 case SMU_SOCCLK:
1003 ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
1004 if (ret)
1005 goto failed;
1006 break;
1007 case SMU_FCLK:
1008 ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
1009 if (ret)
1010 goto failed;
1011 break;
1012 case SMU_VCLK:
1013 ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
1014 if (ret)
1015 goto failed;
1016 break;
1017 case SMU_DCLK:
1018 ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
1019 if (ret)
1020 goto failed;
1021 break;
1022 default:
1023 ret = -EINVAL;
1024 goto failed;
1025 }
1026 }
1027 failed:
1028 return ret;
1029 }
1030
vangogh_get_power_profile_mode(struct smu_context * smu,char * buf)1031 static int vangogh_get_power_profile_mode(struct smu_context *smu,
1032 char *buf)
1033 {
1034 uint32_t i, size = 0;
1035 int16_t workload_type = 0;
1036
1037 if (!buf)
1038 return -EINVAL;
1039
1040 for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
1041 /*
1042 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1043 * Not all profile modes are supported on vangogh.
1044 */
1045 workload_type = smu_cmn_to_asic_specific_index(smu,
1046 CMN2ASIC_MAPPING_WORKLOAD,
1047 i);
1048
1049 if (workload_type < 0)
1050 continue;
1051
1052 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1053 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1054 }
1055
1056 return size;
1057 }
1058
vangogh_set_power_profile_mode(struct smu_context * smu,u32 workload_mask,long * custom_params,u32 custom_params_max_idx)1059 static int vangogh_set_power_profile_mode(struct smu_context *smu,
1060 u32 workload_mask,
1061 long *custom_params,
1062 u32 custom_params_max_idx)
1063 {
1064 u32 backend_workload_mask = 0;
1065 int ret;
1066
1067 smu_cmn_get_backend_workload_mask(smu, workload_mask,
1068 &backend_workload_mask);
1069
1070 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1071 backend_workload_mask,
1072 NULL);
1073 if (ret) {
1074 dev_err_once(smu->adev->dev, "Fail to set workload mask 0x%08x\n",
1075 workload_mask);
1076 return ret;
1077 }
1078
1079 return ret;
1080 }
1081
vangogh_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1082 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
1083 enum smu_clk_type clk_type,
1084 uint32_t min,
1085 uint32_t max,
1086 bool automatic)
1087 {
1088 int ret = 0;
1089
1090 if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
1091 return 0;
1092
1093 switch (clk_type) {
1094 case SMU_GFXCLK:
1095 case SMU_SCLK:
1096 ret = smu_cmn_send_smc_msg_with_param(smu,
1097 SMU_MSG_SetHardMinGfxClk,
1098 min, NULL);
1099 if (ret)
1100 return ret;
1101
1102 ret = smu_cmn_send_smc_msg_with_param(smu,
1103 SMU_MSG_SetSoftMaxGfxClk,
1104 max, NULL);
1105 if (ret)
1106 return ret;
1107 break;
1108 case SMU_FCLK:
1109 ret = smu_cmn_send_smc_msg_with_param(smu,
1110 SMU_MSG_SetHardMinFclkByFreq,
1111 min, NULL);
1112 if (ret)
1113 return ret;
1114
1115 ret = smu_cmn_send_smc_msg_with_param(smu,
1116 SMU_MSG_SetSoftMaxFclkByFreq,
1117 max, NULL);
1118 if (ret)
1119 return ret;
1120 break;
1121 case SMU_SOCCLK:
1122 ret = smu_cmn_send_smc_msg_with_param(smu,
1123 SMU_MSG_SetHardMinSocclkByFreq,
1124 min, NULL);
1125 if (ret)
1126 return ret;
1127
1128 ret = smu_cmn_send_smc_msg_with_param(smu,
1129 SMU_MSG_SetSoftMaxSocclkByFreq,
1130 max, NULL);
1131 if (ret)
1132 return ret;
1133 break;
1134 case SMU_VCLK:
1135 ret = smu_cmn_send_smc_msg_with_param(smu,
1136 SMU_MSG_SetHardMinVcn,
1137 min << 16, NULL);
1138 if (ret)
1139 return ret;
1140 ret = smu_cmn_send_smc_msg_with_param(smu,
1141 SMU_MSG_SetSoftMaxVcn,
1142 max << 16, NULL);
1143 if (ret)
1144 return ret;
1145 break;
1146 case SMU_DCLK:
1147 ret = smu_cmn_send_smc_msg_with_param(smu,
1148 SMU_MSG_SetHardMinVcn,
1149 min, NULL);
1150 if (ret)
1151 return ret;
1152 ret = smu_cmn_send_smc_msg_with_param(smu,
1153 SMU_MSG_SetSoftMaxVcn,
1154 max, NULL);
1155 if (ret)
1156 return ret;
1157 break;
1158 default:
1159 return -EINVAL;
1160 }
1161
1162 return ret;
1163 }
1164
vangogh_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1165 static int vangogh_force_clk_levels(struct smu_context *smu,
1166 enum smu_clk_type clk_type, uint32_t mask)
1167 {
1168 uint32_t soft_min_level = 0, soft_max_level = 0;
1169 uint32_t min_freq = 0, max_freq = 0;
1170 int ret = 0 ;
1171
1172 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1173 soft_max_level = mask ? (fls(mask) - 1) : 0;
1174
1175 switch (clk_type) {
1176 case SMU_SOCCLK:
1177 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1178 soft_min_level, &min_freq);
1179 if (ret)
1180 return ret;
1181 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1182 soft_max_level, &max_freq);
1183 if (ret)
1184 return ret;
1185 ret = smu_cmn_send_smc_msg_with_param(smu,
1186 SMU_MSG_SetSoftMaxSocclkByFreq,
1187 max_freq, NULL);
1188 if (ret)
1189 return ret;
1190 ret = smu_cmn_send_smc_msg_with_param(smu,
1191 SMU_MSG_SetHardMinSocclkByFreq,
1192 min_freq, NULL);
1193 if (ret)
1194 return ret;
1195 break;
1196 case SMU_FCLK:
1197 ret = vangogh_get_dpm_clk_limited(smu,
1198 clk_type, soft_min_level, &min_freq);
1199 if (ret)
1200 return ret;
1201 ret = vangogh_get_dpm_clk_limited(smu,
1202 clk_type, soft_max_level, &max_freq);
1203 if (ret)
1204 return ret;
1205 ret = smu_cmn_send_smc_msg_with_param(smu,
1206 SMU_MSG_SetSoftMaxFclkByFreq,
1207 max_freq, NULL);
1208 if (ret)
1209 return ret;
1210 ret = smu_cmn_send_smc_msg_with_param(smu,
1211 SMU_MSG_SetHardMinFclkByFreq,
1212 min_freq, NULL);
1213 if (ret)
1214 return ret;
1215 break;
1216 case SMU_VCLK:
1217 ret = vangogh_get_dpm_clk_limited(smu,
1218 clk_type, soft_min_level, &min_freq);
1219 if (ret)
1220 return ret;
1221
1222 ret = vangogh_get_dpm_clk_limited(smu,
1223 clk_type, soft_max_level, &max_freq);
1224 if (ret)
1225 return ret;
1226
1227
1228 ret = smu_cmn_send_smc_msg_with_param(smu,
1229 SMU_MSG_SetHardMinVcn,
1230 min_freq << 16, NULL);
1231 if (ret)
1232 return ret;
1233
1234 ret = smu_cmn_send_smc_msg_with_param(smu,
1235 SMU_MSG_SetSoftMaxVcn,
1236 max_freq << 16, NULL);
1237 if (ret)
1238 return ret;
1239
1240 break;
1241 case SMU_DCLK:
1242 ret = vangogh_get_dpm_clk_limited(smu,
1243 clk_type, soft_min_level, &min_freq);
1244 if (ret)
1245 return ret;
1246
1247 ret = vangogh_get_dpm_clk_limited(smu,
1248 clk_type, soft_max_level, &max_freq);
1249 if (ret)
1250 return ret;
1251
1252 ret = smu_cmn_send_smc_msg_with_param(smu,
1253 SMU_MSG_SetHardMinVcn,
1254 min_freq, NULL);
1255 if (ret)
1256 return ret;
1257
1258 ret = smu_cmn_send_smc_msg_with_param(smu,
1259 SMU_MSG_SetSoftMaxVcn,
1260 max_freq, NULL);
1261 if (ret)
1262 return ret;
1263
1264 break;
1265 default:
1266 break;
1267 }
1268
1269 return ret;
1270 }
1271
vangogh_force_dpm_limit_value(struct smu_context * smu,bool highest)1272 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
1273 {
1274 int ret = 0, i = 0;
1275 uint32_t min_freq, max_freq, force_freq;
1276 enum smu_clk_type clk_type;
1277
1278 enum smu_clk_type clks[] = {
1279 SMU_SOCCLK,
1280 SMU_VCLK,
1281 SMU_DCLK,
1282 SMU_FCLK,
1283 };
1284
1285 for (i = 0; i < ARRAY_SIZE(clks); i++) {
1286 clk_type = clks[i];
1287 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1288 if (ret)
1289 return ret;
1290
1291 force_freq = highest ? max_freq : min_freq;
1292 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq, false);
1293 if (ret)
1294 return ret;
1295 }
1296
1297 return ret;
1298 }
1299
vangogh_unforce_dpm_levels(struct smu_context * smu)1300 static int vangogh_unforce_dpm_levels(struct smu_context *smu)
1301 {
1302 int ret = 0, i = 0;
1303 uint32_t min_freq, max_freq;
1304 enum smu_clk_type clk_type;
1305
1306 struct clk_feature_map {
1307 enum smu_clk_type clk_type;
1308 uint32_t feature;
1309 } clk_feature_map[] = {
1310 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
1311 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
1312 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
1313 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT},
1314 };
1315
1316 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
1317
1318 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
1319 continue;
1320
1321 clk_type = clk_feature_map[i].clk_type;
1322
1323 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1324
1325 if (ret)
1326 return ret;
1327
1328 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq, false);
1329
1330 if (ret)
1331 return ret;
1332 }
1333
1334 return ret;
1335 }
1336
vangogh_set_peak_clock_by_device(struct smu_context * smu)1337 static int vangogh_set_peak_clock_by_device(struct smu_context *smu)
1338 {
1339 int ret = 0;
1340 uint32_t socclk_freq = 0, fclk_freq = 0;
1341 uint32_t vclk_freq = 0, dclk_freq = 0;
1342
1343 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq);
1344 if (ret)
1345 return ret;
1346
1347 ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq, false);
1348 if (ret)
1349 return ret;
1350
1351 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq);
1352 if (ret)
1353 return ret;
1354
1355 ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq, false);
1356 if (ret)
1357 return ret;
1358
1359 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq);
1360 if (ret)
1361 return ret;
1362
1363 ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq, false);
1364 if (ret)
1365 return ret;
1366
1367 ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq);
1368 if (ret)
1369 return ret;
1370
1371 ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq, false);
1372 if (ret)
1373 return ret;
1374
1375 return ret;
1376 }
1377
vangogh_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1378 static int vangogh_set_performance_level(struct smu_context *smu,
1379 enum amd_dpm_forced_level level)
1380 {
1381 int ret = 0, i;
1382 uint32_t soc_mask, mclk_mask, fclk_mask;
1383 uint32_t vclk_mask = 0, dclk_mask = 0;
1384
1385 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1386 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1387
1388 switch (level) {
1389 case AMD_DPM_FORCED_LEVEL_HIGH:
1390 smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq;
1391 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1392
1393
1394 ret = vangogh_force_dpm_limit_value(smu, true);
1395 if (ret)
1396 return ret;
1397 break;
1398 case AMD_DPM_FORCED_LEVEL_LOW:
1399 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1400 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1401
1402 ret = vangogh_force_dpm_limit_value(smu, false);
1403 if (ret)
1404 return ret;
1405 break;
1406 case AMD_DPM_FORCED_LEVEL_AUTO:
1407 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1408 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1409
1410 ret = vangogh_unforce_dpm_levels(smu);
1411 if (ret)
1412 return ret;
1413 break;
1414 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1415 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1416 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1417
1418 ret = vangogh_get_profiling_clk_mask(smu, level,
1419 &vclk_mask,
1420 &dclk_mask,
1421 &mclk_mask,
1422 &fclk_mask,
1423 &soc_mask);
1424 if (ret)
1425 return ret;
1426
1427 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1428 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1429 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
1430 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
1431 break;
1432 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1433 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1434 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1435 break;
1436 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1437 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1438 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1439
1440 ret = vangogh_get_profiling_clk_mask(smu, level,
1441 NULL,
1442 NULL,
1443 &mclk_mask,
1444 &fclk_mask,
1445 NULL);
1446 if (ret)
1447 return ret;
1448
1449 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1450 break;
1451 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1452 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1453 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1454
1455 ret = vangogh_set_peak_clock_by_device(smu);
1456 if (ret)
1457 return ret;
1458 break;
1459 case AMD_DPM_FORCED_LEVEL_MANUAL:
1460 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1461 default:
1462 return 0;
1463 }
1464
1465 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1466 smu->gfx_actual_hard_min_freq, NULL);
1467 if (ret)
1468 return ret;
1469
1470 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1471 smu->gfx_actual_soft_max_freq, NULL);
1472 if (ret)
1473 return ret;
1474
1475 if (smu->adev->pm.fw_version >= 0x43f1b00) {
1476 for (i = 0; i < smu->cpu_core_num; i++) {
1477 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
1478 ((i << 20)
1479 | smu->cpu_actual_soft_min_freq),
1480 NULL);
1481 if (ret)
1482 return ret;
1483
1484 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
1485 ((i << 20)
1486 | smu->cpu_actual_soft_max_freq),
1487 NULL);
1488 if (ret)
1489 return ret;
1490 }
1491 }
1492
1493 return ret;
1494 }
1495
vangogh_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1496 static int vangogh_read_sensor(struct smu_context *smu,
1497 enum amd_pp_sensors sensor,
1498 void *data, uint32_t *size)
1499 {
1500 int ret = 0;
1501
1502 if (!data || !size)
1503 return -EINVAL;
1504
1505 switch (sensor) {
1506 case AMDGPU_PP_SENSOR_GPU_LOAD:
1507 ret = vangogh_common_get_smu_metrics_data(smu,
1508 METRICS_AVERAGE_GFXACTIVITY,
1509 (uint32_t *)data);
1510 *size = 4;
1511 break;
1512 case AMDGPU_PP_SENSOR_VCN_LOAD:
1513 ret = vangogh_common_get_smu_metrics_data(smu,
1514 METRICS_AVERAGE_VCNACTIVITY,
1515 (uint32_t *)data);
1516 *size = 4;
1517 break;
1518 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1519 ret = vangogh_common_get_smu_metrics_data(smu,
1520 METRICS_AVERAGE_SOCKETPOWER,
1521 (uint32_t *)data);
1522 *size = 4;
1523 break;
1524 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1525 ret = vangogh_common_get_smu_metrics_data(smu,
1526 METRICS_CURR_SOCKETPOWER,
1527 (uint32_t *)data);
1528 *size = 4;
1529 break;
1530 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1531 ret = vangogh_common_get_smu_metrics_data(smu,
1532 METRICS_TEMPERATURE_EDGE,
1533 (uint32_t *)data);
1534 *size = 4;
1535 break;
1536 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1537 ret = vangogh_common_get_smu_metrics_data(smu,
1538 METRICS_TEMPERATURE_HOTSPOT,
1539 (uint32_t *)data);
1540 *size = 4;
1541 break;
1542 case AMDGPU_PP_SENSOR_GFX_MCLK:
1543 ret = vangogh_common_get_smu_metrics_data(smu,
1544 METRICS_CURR_UCLK,
1545 (uint32_t *)data);
1546 *(uint32_t *)data *= 100;
1547 *size = 4;
1548 break;
1549 case AMDGPU_PP_SENSOR_GFX_SCLK:
1550 ret = vangogh_common_get_smu_metrics_data(smu,
1551 METRICS_CURR_GFXCLK,
1552 (uint32_t *)data);
1553 *(uint32_t *)data *= 100;
1554 *size = 4;
1555 break;
1556 case AMDGPU_PP_SENSOR_VDDGFX:
1557 ret = vangogh_common_get_smu_metrics_data(smu,
1558 METRICS_VOLTAGE_VDDGFX,
1559 (uint32_t *)data);
1560 *size = 4;
1561 break;
1562 case AMDGPU_PP_SENSOR_VDDNB:
1563 ret = vangogh_common_get_smu_metrics_data(smu,
1564 METRICS_VOLTAGE_VDDSOC,
1565 (uint32_t *)data);
1566 *size = 4;
1567 break;
1568 case AMDGPU_PP_SENSOR_CPU_CLK:
1569 ret = vangogh_common_get_smu_metrics_data(smu,
1570 METRICS_AVERAGE_CPUCLK,
1571 (uint32_t *)data);
1572 *size = smu->cpu_core_num * sizeof(uint16_t);
1573 break;
1574 default:
1575 ret = -EOPNOTSUPP;
1576 break;
1577 }
1578
1579 return ret;
1580 }
1581
vangogh_get_apu_thermal_limit(struct smu_context * smu,uint32_t * limit)1582 static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit)
1583 {
1584 return smu_cmn_send_smc_msg_with_param(smu,
1585 SMU_MSG_GetThermalLimit,
1586 0, limit);
1587 }
1588
vangogh_set_apu_thermal_limit(struct smu_context * smu,uint32_t limit)1589 static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit)
1590 {
1591 return smu_cmn_send_smc_msg_with_param(smu,
1592 SMU_MSG_SetReducedThermalLimit,
1593 limit, NULL);
1594 }
1595
1596
vangogh_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1597 static int vangogh_set_watermarks_table(struct smu_context *smu,
1598 struct pp_smu_wm_range_sets *clock_ranges)
1599 {
1600 int i;
1601 int ret = 0;
1602 Watermarks_t *table = smu->smu_table.watermarks_table;
1603
1604 if (!table || !clock_ranges)
1605 return -EINVAL;
1606
1607 if (clock_ranges) {
1608 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1609 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1610 return -EINVAL;
1611
1612 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1613 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1614 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1615 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1616 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1617 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1618 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1619 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1620 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1621
1622 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1623 clock_ranges->reader_wm_sets[i].wm_inst;
1624 }
1625
1626 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1627 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1628 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1629 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1630 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1631 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1632 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1633 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1634 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1635
1636 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1637 clock_ranges->writer_wm_sets[i].wm_inst;
1638 }
1639
1640 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1641 }
1642
1643 /* pass data to smu controller */
1644 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1645 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1646 ret = smu_cmn_write_watermarks_table(smu);
1647 if (ret) {
1648 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1649 return ret;
1650 }
1651 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1652 }
1653
1654 return 0;
1655 }
1656
vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context * smu,void ** table)1657 static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu,
1658 void **table)
1659 {
1660 struct gpu_metrics_v2_3 *gpu_metrics =
1661 (struct gpu_metrics_v2_3 *)smu_driver_table_ptr(
1662 smu, SMU_DRIVER_TABLE_GPU_METRICS);
1663 SmuMetrics_legacy_t metrics;
1664 int ret = 0;
1665
1666 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1667 if (ret)
1668 return ret;
1669
1670 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
1671
1672 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1673 gpu_metrics->temperature_soc = metrics.SocTemperature;
1674 memcpy(&gpu_metrics->temperature_core[0],
1675 &metrics.CoreTemperature[0],
1676 sizeof(uint16_t) * 4);
1677 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1678
1679 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1680 gpu_metrics->average_mm_activity = metrics.UvdActivity;
1681
1682 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1683 gpu_metrics->average_cpu_power = metrics.Power[0];
1684 gpu_metrics->average_soc_power = metrics.Power[1];
1685 gpu_metrics->average_gfx_power = metrics.Power[2];
1686 memcpy(&gpu_metrics->average_core_power[0],
1687 &metrics.CorePower[0],
1688 sizeof(uint16_t) * 4);
1689
1690 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1691 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1692 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1693 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1694 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1695 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1696
1697 memcpy(&gpu_metrics->current_coreclk[0],
1698 &metrics.CoreFrequency[0],
1699 sizeof(uint16_t) * 4);
1700 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1701
1702 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1703 gpu_metrics->indep_throttle_status =
1704 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1705 vangogh_throttler_map);
1706
1707 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1708
1709 *table = (void *)gpu_metrics;
1710
1711 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
1712
1713 return sizeof(struct gpu_metrics_v2_3);
1714 }
1715
vangogh_get_legacy_gpu_metrics(struct smu_context * smu,void ** table)1716 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
1717 void **table)
1718 {
1719 struct gpu_metrics_v2_2 *gpu_metrics =
1720 (struct gpu_metrics_v2_2 *)smu_driver_table_ptr(
1721 smu, SMU_DRIVER_TABLE_GPU_METRICS);
1722 SmuMetrics_legacy_t metrics;
1723 int ret = 0;
1724
1725 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1726 if (ret)
1727 return ret;
1728
1729 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1730
1731 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1732 gpu_metrics->temperature_soc = metrics.SocTemperature;
1733 memcpy(&gpu_metrics->temperature_core[0],
1734 &metrics.CoreTemperature[0],
1735 sizeof(uint16_t) * 4);
1736 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1737
1738 gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1739 gpu_metrics->average_mm_activity = metrics.UvdActivity;
1740
1741 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1742 gpu_metrics->average_cpu_power = metrics.Power[0];
1743 gpu_metrics->average_soc_power = metrics.Power[1];
1744 gpu_metrics->average_gfx_power = metrics.Power[2];
1745 memcpy(&gpu_metrics->average_core_power[0],
1746 &metrics.CorePower[0],
1747 sizeof(uint16_t) * 4);
1748
1749 gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1750 gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1751 gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1752 gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1753 gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1754 gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1755
1756 memcpy(&gpu_metrics->current_coreclk[0],
1757 &metrics.CoreFrequency[0],
1758 sizeof(uint16_t) * 4);
1759 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1760
1761 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1762 gpu_metrics->indep_throttle_status =
1763 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1764 vangogh_throttler_map);
1765
1766 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1767
1768 *table = (void *)gpu_metrics;
1769
1770 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
1771
1772 return sizeof(struct gpu_metrics_v2_2);
1773 }
1774
vangogh_get_gpu_metrics_v2_3(struct smu_context * smu,void ** table)1775 static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu,
1776 void **table)
1777 {
1778 struct gpu_metrics_v2_3 *gpu_metrics =
1779 (struct gpu_metrics_v2_3 *)smu_driver_table_ptr(
1780 smu, SMU_DRIVER_TABLE_GPU_METRICS);
1781 SmuMetrics_t metrics;
1782 int ret = 0;
1783
1784 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1785 if (ret)
1786 return ret;
1787
1788 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
1789
1790 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1791 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1792 memcpy(&gpu_metrics->temperature_core[0],
1793 &metrics.Current.CoreTemperature[0],
1794 sizeof(uint16_t) * 4);
1795 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1796
1797 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
1798 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
1799 memcpy(&gpu_metrics->average_temperature_core[0],
1800 &metrics.Average.CoreTemperature[0],
1801 sizeof(uint16_t) * 4);
1802 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
1803
1804 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1805 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1806
1807 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1808 gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1809 gpu_metrics->average_soc_power = metrics.Current.Power[1];
1810 gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1811 memcpy(&gpu_metrics->average_core_power[0],
1812 &metrics.Average.CorePower[0],
1813 sizeof(uint16_t) * 4);
1814
1815 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1816 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1817 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1818 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1819 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1820 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1821
1822 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1823 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1824 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1825 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1826 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1827 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1828
1829 memcpy(&gpu_metrics->current_coreclk[0],
1830 &metrics.Current.CoreFrequency[0],
1831 sizeof(uint16_t) * 4);
1832 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1833
1834 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1835 gpu_metrics->indep_throttle_status =
1836 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1837 vangogh_throttler_map);
1838
1839 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1840
1841 *table = (void *)gpu_metrics;
1842
1843 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
1844
1845 return sizeof(struct gpu_metrics_v2_3);
1846 }
1847
vangogh_get_gpu_metrics_v2_4(struct smu_context * smu,void ** table)1848 static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu,
1849 void **table)
1850 {
1851 SmuMetrics_t metrics;
1852 struct gpu_metrics_v2_4 *gpu_metrics =
1853 (struct gpu_metrics_v2_4 *)smu_driver_table_ptr(
1854 smu, SMU_DRIVER_TABLE_GPU_METRICS);
1855 int ret = 0;
1856
1857 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1858 if (ret)
1859 return ret;
1860
1861 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4);
1862
1863 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1864 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1865 memcpy(&gpu_metrics->temperature_core[0],
1866 &metrics.Current.CoreTemperature[0],
1867 sizeof(uint16_t) * 4);
1868 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1869
1870 gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
1871 gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
1872 memcpy(&gpu_metrics->average_temperature_core[0],
1873 &metrics.Average.CoreTemperature[0],
1874 sizeof(uint16_t) * 4);
1875 gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
1876
1877 gpu_metrics->average_gfx_activity = metrics.Average.GfxActivity;
1878 gpu_metrics->average_mm_activity = metrics.Average.UvdActivity;
1879
1880 gpu_metrics->average_socket_power = metrics.Average.CurrentSocketPower;
1881 gpu_metrics->average_cpu_power = metrics.Average.Power[0];
1882 gpu_metrics->average_soc_power = metrics.Average.Power[1];
1883 gpu_metrics->average_gfx_power = metrics.Average.Power[2];
1884
1885 gpu_metrics->average_cpu_voltage = metrics.Average.Voltage[0];
1886 gpu_metrics->average_soc_voltage = metrics.Average.Voltage[1];
1887 gpu_metrics->average_gfx_voltage = metrics.Average.Voltage[2];
1888
1889 gpu_metrics->average_cpu_current = metrics.Average.Current[0];
1890 gpu_metrics->average_soc_current = metrics.Average.Current[1];
1891 gpu_metrics->average_gfx_current = metrics.Average.Current[2];
1892
1893 memcpy(&gpu_metrics->average_core_power[0],
1894 &metrics.Average.CorePower[0],
1895 sizeof(uint16_t) * 4);
1896
1897 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1898 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1899 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1900 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1901 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1902 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1903
1904 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1905 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1906 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1907 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1908 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1909 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1910
1911 memcpy(&gpu_metrics->current_coreclk[0],
1912 &metrics.Current.CoreFrequency[0],
1913 sizeof(uint16_t) * 4);
1914 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1915
1916 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1917 gpu_metrics->indep_throttle_status =
1918 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1919 vangogh_throttler_map);
1920
1921 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1922
1923 *table = (void *)gpu_metrics;
1924
1925 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
1926
1927 return sizeof(struct gpu_metrics_v2_4);
1928 }
1929
vangogh_get_gpu_metrics(struct smu_context * smu,void ** table)1930 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
1931 void **table)
1932 {
1933 struct gpu_metrics_v2_2 *gpu_metrics =
1934 (struct gpu_metrics_v2_2 *)smu_driver_table_ptr(
1935 smu, SMU_DRIVER_TABLE_GPU_METRICS);
1936 SmuMetrics_t metrics;
1937 int ret = 0;
1938
1939 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1940 if (ret)
1941 return ret;
1942
1943 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1944
1945 gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1946 gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1947 memcpy(&gpu_metrics->temperature_core[0],
1948 &metrics.Current.CoreTemperature[0],
1949 sizeof(uint16_t) * 4);
1950 gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1951
1952 gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1953 gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1954
1955 gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1956 gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1957 gpu_metrics->average_soc_power = metrics.Current.Power[1];
1958 gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1959 memcpy(&gpu_metrics->average_core_power[0],
1960 &metrics.Average.CorePower[0],
1961 sizeof(uint16_t) * 4);
1962
1963 gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1964 gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1965 gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1966 gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1967 gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1968 gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1969
1970 gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1971 gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1972 gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1973 gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1974 gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1975 gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1976
1977 memcpy(&gpu_metrics->current_coreclk[0],
1978 &metrics.Current.CoreFrequency[0],
1979 sizeof(uint16_t) * 4);
1980 gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1981
1982 gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1983 gpu_metrics->indep_throttle_status =
1984 smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1985 vangogh_throttler_map);
1986
1987 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1988
1989 *table = (void *)gpu_metrics;
1990
1991 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
1992
1993 return sizeof(struct gpu_metrics_v2_2);
1994 }
1995
vangogh_common_get_gpu_metrics(struct smu_context * smu,void ** table)1996 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
1997 void **table)
1998 {
1999 uint32_t smu_program;
2000 uint32_t fw_version;
2001 int ret = 0;
2002
2003 smu_program = (smu->smc_fw_version >> 24) & 0xff;
2004 fw_version = smu->smc_fw_version & 0xffffff;
2005 if (smu_program == 6) {
2006 if (fw_version >= 0x3F0800)
2007 ret = vangogh_get_gpu_metrics_v2_4(smu, table);
2008 else
2009 ret = vangogh_get_gpu_metrics_v2_3(smu, table);
2010
2011 } else {
2012 if (smu->smc_fw_version >= 0x043F3E00) {
2013 if (smu->smc_fw_if_version < 0x3)
2014 ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table);
2015 else
2016 ret = vangogh_get_gpu_metrics_v2_3(smu, table);
2017 } else {
2018 if (smu->smc_fw_if_version < 0x3)
2019 ret = vangogh_get_legacy_gpu_metrics(smu, table);
2020 else
2021 ret = vangogh_get_gpu_metrics(smu, table);
2022 }
2023 }
2024
2025 return ret;
2026 }
2027
vangogh_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2028 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
2029 long input[], uint32_t size)
2030 {
2031 int ret = 0;
2032 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2033
2034 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
2035 dev_warn(smu->adev->dev,
2036 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
2037 return -EINVAL;
2038 }
2039
2040 switch (type) {
2041 case PP_OD_EDIT_CCLK_VDDC_TABLE:
2042 if (size != 3) {
2043 dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
2044 return -EINVAL;
2045 }
2046 if (input[0] >= smu->cpu_core_num) {
2047 dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
2048 smu->cpu_core_num);
2049 }
2050 smu->cpu_core_id_select = input[0];
2051 if (input[1] == 0) {
2052 if (input[2] < smu->cpu_default_soft_min_freq) {
2053 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2054 input[2], smu->cpu_default_soft_min_freq);
2055 return -EINVAL;
2056 }
2057 smu->cpu_actual_soft_min_freq = input[2];
2058 } else if (input[1] == 1) {
2059 if (input[2] > smu->cpu_default_soft_max_freq) {
2060 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2061 input[2], smu->cpu_default_soft_max_freq);
2062 return -EINVAL;
2063 }
2064 smu->cpu_actual_soft_max_freq = input[2];
2065 } else {
2066 return -EINVAL;
2067 }
2068 break;
2069 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2070 if (size != 2) {
2071 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2072 return -EINVAL;
2073 }
2074
2075 if (input[0] == 0) {
2076 if (input[1] < smu->gfx_default_hard_min_freq) {
2077 dev_warn(smu->adev->dev,
2078 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2079 input[1], smu->gfx_default_hard_min_freq);
2080 return -EINVAL;
2081 }
2082 smu->gfx_actual_hard_min_freq = input[1];
2083 } else if (input[0] == 1) {
2084 if (input[1] > smu->gfx_default_soft_max_freq) {
2085 dev_warn(smu->adev->dev,
2086 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2087 input[1], smu->gfx_default_soft_max_freq);
2088 return -EINVAL;
2089 }
2090 smu->gfx_actual_soft_max_freq = input[1];
2091 } else {
2092 return -EINVAL;
2093 }
2094 break;
2095 case PP_OD_RESTORE_DEFAULT_TABLE:
2096 if (size != 0) {
2097 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2098 return -EINVAL;
2099 } else {
2100 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2101 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2102 smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
2103 smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
2104 }
2105 break;
2106 case PP_OD_COMMIT_DPM_TABLE:
2107 if (size != 0) {
2108 dev_err(smu->adev->dev, "Input parameter number not correct\n");
2109 return -EINVAL;
2110 } else {
2111 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2112 dev_err(smu->adev->dev,
2113 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2114 smu->gfx_actual_hard_min_freq,
2115 smu->gfx_actual_soft_max_freq);
2116 return -EINVAL;
2117 }
2118
2119 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2120 smu->gfx_actual_hard_min_freq, NULL);
2121 if (ret) {
2122 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2123 return ret;
2124 }
2125
2126 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2127 smu->gfx_actual_soft_max_freq, NULL);
2128 if (ret) {
2129 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2130 return ret;
2131 }
2132
2133 if (smu->adev->pm.fw_version < 0x43f1b00) {
2134 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n");
2135 break;
2136 }
2137
2138 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
2139 ((smu->cpu_core_id_select << 20)
2140 | smu->cpu_actual_soft_min_freq),
2141 NULL);
2142 if (ret) {
2143 dev_err(smu->adev->dev, "Set hard min cclk failed!");
2144 return ret;
2145 }
2146
2147 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
2148 ((smu->cpu_core_id_select << 20)
2149 | smu->cpu_actual_soft_max_freq),
2150 NULL);
2151 if (ret) {
2152 dev_err(smu->adev->dev, "Set soft max cclk failed!");
2153 return ret;
2154 }
2155 }
2156 break;
2157 default:
2158 return -ENOSYS;
2159 }
2160
2161 return ret;
2162 }
2163
vangogh_set_default_dpm_tables(struct smu_context * smu)2164 static int vangogh_set_default_dpm_tables(struct smu_context *smu)
2165 {
2166 struct smu_table_context *smu_table = &smu->smu_table;
2167
2168 return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
2169 }
2170
vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)2171 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
2172 {
2173 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
2174
2175 smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
2176 smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
2177 smu->gfx_actual_hard_min_freq = 0;
2178 smu->gfx_actual_soft_max_freq = 0;
2179
2180 smu->cpu_default_soft_min_freq = 1400;
2181 smu->cpu_default_soft_max_freq = 3500;
2182 smu->cpu_actual_soft_min_freq = 0;
2183 smu->cpu_actual_soft_max_freq = 0;
2184
2185 return 0;
2186 }
2187
vangogh_get_dpm_clock_table(struct smu_context * smu,struct dpm_clocks * clock_table)2188 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
2189 {
2190 DpmClocks_t *table = smu->smu_table.clocks_table;
2191 int i;
2192
2193 if (!clock_table || !table)
2194 return -EINVAL;
2195
2196 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
2197 clock_table->SocClocks[i].Freq = table->SocClocks[i];
2198 clock_table->SocClocks[i].Vol = table->SocVoltage[i];
2199 }
2200
2201 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2202 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk;
2203 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage;
2204 }
2205
2206 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2207 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk;
2208 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage;
2209 }
2210
2211 return 0;
2212 }
2213
vangogh_notify_rlc_state(struct smu_context * smu,bool en)2214 static int vangogh_notify_rlc_state(struct smu_context *smu, bool en)
2215 {
2216 struct amdgpu_device *adev = smu->adev;
2217 int ret = 0;
2218
2219 if (adev->pm.fw_version >= 0x43f1700 && !en)
2220 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
2221 RLC_STATUS_OFF, NULL);
2222
2223 return ret;
2224 }
2225
vangogh_post_smu_init(struct smu_context * smu)2226 static int vangogh_post_smu_init(struct smu_context *smu)
2227 {
2228 struct amdgpu_device *adev = smu->adev;
2229 uint32_t tmp;
2230 int ret = 0;
2231 uint8_t aon_bits = 0;
2232 /* Two CUs in one WGP */
2233 uint32_t req_active_wgps = adev->gfx.cu_info.number/2;
2234 uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
2235 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2236
2237 if (adev->in_s0ix)
2238 return 0;
2239
2240 /* allow message will be sent after enable message on Vangogh*/
2241 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
2242 (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2243 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
2244 if (ret) {
2245 dev_err(adev->dev, "Failed to Enable GfxOff!\n");
2246 return ret;
2247 }
2248 } else {
2249 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2250 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n");
2251 }
2252
2253 /* if all CUs are active, no need to power off any WGPs */
2254 if (total_cu == adev->gfx.cu_info.number)
2255 return 0;
2256
2257 /*
2258 * Calculate the total bits number of always on WGPs for all SA/SEs in
2259 * RLC_PG_ALWAYS_ON_WGP_MASK.
2260 */
2261 tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
2262 tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK;
2263
2264 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2265
2266 /* Do not request any WGPs less than set in the AON_WGP_MASK */
2267 if (aon_bits > req_active_wgps) {
2268 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n");
2269 return 0;
2270 } else {
2271 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL);
2272 }
2273 }
2274
vangogh_mode_reset(struct smu_context * smu,int type)2275 static int vangogh_mode_reset(struct smu_context *smu, int type)
2276 {
2277 struct smu_msg_ctl *ctl = &smu->msg_ctl;
2278 int ret;
2279
2280 mutex_lock(&ctl->lock);
2281 ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset, type);
2282 mutex_unlock(&ctl->lock);
2283
2284 mdelay(10);
2285
2286 return ret;
2287 }
2288
vangogh_mode2_reset(struct smu_context * smu)2289 static int vangogh_mode2_reset(struct smu_context *smu)
2290 {
2291 return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
2292 }
2293
2294 /**
2295 * vangogh_get_gfxoff_status - Get gfxoff status
2296 *
2297 * @smu: amdgpu_device pointer
2298 *
2299 * Get current gfxoff status
2300 *
2301 * Return:
2302 * * 0 - GFXOFF (default if enabled).
2303 * * 1 - Transition out of GFX State.
2304 * * 2 - Not in GFXOFF.
2305 * * 3 - Transition into GFXOFF.
2306 */
vangogh_get_gfxoff_status(struct smu_context * smu)2307 static u32 vangogh_get_gfxoff_status(struct smu_context *smu)
2308 {
2309 struct amdgpu_device *adev = smu->adev;
2310 u32 reg, gfxoff_status;
2311
2312 reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
2313 gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
2314 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
2315
2316 return gfxoff_status;
2317 }
2318
vangogh_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2319 static int vangogh_get_power_limit(struct smu_context *smu,
2320 uint32_t *current_power_limit,
2321 uint32_t *default_power_limit,
2322 uint32_t *max_power_limit,
2323 uint32_t *min_power_limit)
2324 {
2325 struct smu_11_5_power_context *power_context = smu->smu_power.power_context;
2326 uint32_t ppt_limit;
2327 int ret = 0;
2328
2329 if (smu->adev->pm.fw_version < 0x43f1e00)
2330 return ret;
2331
2332 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit);
2333 if (ret) {
2334 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n");
2335 return ret;
2336 }
2337 /* convert from milliwatt to watt */
2338 if (current_power_limit)
2339 *current_power_limit = ppt_limit / 1000;
2340 if (default_power_limit)
2341 *default_power_limit = ppt_limit / 1000;
2342 if (max_power_limit)
2343 *max_power_limit = 29;
2344 if (min_power_limit)
2345 *min_power_limit = 0;
2346
2347 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
2348 if (ret) {
2349 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
2350 return ret;
2351 }
2352 /* convert from milliwatt to watt */
2353 power_context->current_fast_ppt_limit =
2354 power_context->default_fast_ppt_limit = ppt_limit / 1000;
2355 power_context->max_fast_ppt_limit = 30;
2356
2357 return ret;
2358 }
2359
vangogh_get_ppt_limit(struct smu_context * smu,uint32_t * ppt_limit,enum smu_ppt_limit_type type,enum smu_ppt_limit_level level)2360 static int vangogh_get_ppt_limit(struct smu_context *smu,
2361 uint32_t *ppt_limit,
2362 enum smu_ppt_limit_type type,
2363 enum smu_ppt_limit_level level)
2364 {
2365 struct smu_11_5_power_context *power_context = smu->smu_power.power_context;
2366
2367 if (!power_context)
2368 return -EOPNOTSUPP;
2369
2370 if (type == SMU_FAST_PPT_LIMIT) {
2371 switch (level) {
2372 case SMU_PPT_LIMIT_MAX:
2373 *ppt_limit = power_context->max_fast_ppt_limit;
2374 break;
2375 case SMU_PPT_LIMIT_CURRENT:
2376 *ppt_limit = power_context->current_fast_ppt_limit;
2377 break;
2378 case SMU_PPT_LIMIT_DEFAULT:
2379 *ppt_limit = power_context->default_fast_ppt_limit;
2380 break;
2381 default:
2382 break;
2383 }
2384 }
2385
2386 return 0;
2387 }
2388
vangogh_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t ppt_limit)2389 static int vangogh_set_power_limit(struct smu_context *smu,
2390 enum smu_ppt_limit_type limit_type,
2391 uint32_t ppt_limit)
2392 {
2393 struct smu_11_5_power_context *power_context =
2394 smu->smu_power.power_context;
2395 int ret = 0;
2396
2397 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
2398 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
2399 return -EOPNOTSUPP;
2400 }
2401
2402 switch (limit_type) {
2403 case SMU_DEFAULT_PPT_LIMIT:
2404 ret = smu_cmn_send_smc_msg_with_param(smu,
2405 SMU_MSG_SetSlowPPTLimit,
2406 ppt_limit * 1000, /* convert from watt to milliwatt */
2407 NULL);
2408 if (ret)
2409 return ret;
2410
2411 smu->current_power_limit = ppt_limit;
2412 break;
2413 case SMU_FAST_PPT_LIMIT:
2414 if (ppt_limit > power_context->max_fast_ppt_limit) {
2415 dev_err(smu->adev->dev,
2416 "New power limit (%d) is over the max allowed %d\n",
2417 ppt_limit, power_context->max_fast_ppt_limit);
2418 return ret;
2419 }
2420
2421 ret = smu_cmn_send_smc_msg_with_param(smu,
2422 SMU_MSG_SetFastPPTLimit,
2423 ppt_limit * 1000, /* convert from watt to milliwatt */
2424 NULL);
2425 if (ret)
2426 return ret;
2427
2428 power_context->current_fast_ppt_limit = ppt_limit;
2429 break;
2430 default:
2431 return -EINVAL;
2432 }
2433
2434 return ret;
2435 }
2436
2437 /**
2438 * vangogh_set_gfxoff_residency
2439 *
2440 * @smu: amdgpu_device pointer
2441 * @start: start/stop residency log
2442 *
2443 * This function will be used to log gfxoff residency
2444 *
2445 *
2446 * Returns standard response codes.
2447 */
vangogh_set_gfxoff_residency(struct smu_context * smu,bool start)2448 static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)
2449 {
2450 int ret = 0;
2451 u32 residency;
2452 struct amdgpu_device *adev = smu->adev;
2453
2454 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
2455 return 0;
2456
2457 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency,
2458 start, &residency);
2459 if (ret)
2460 return ret;
2461
2462 if (!start)
2463 adev->gfx.gfx_off_residency = residency;
2464
2465 return ret;
2466 }
2467
2468 /**
2469 * vangogh_get_gfxoff_residency
2470 *
2471 * @smu: amdgpu_device pointer
2472 * @residency: placeholder for return value
2473 *
2474 * This function will be used to get gfxoff residency.
2475 *
2476 * Returns standard response codes.
2477 */
vangogh_get_gfxoff_residency(struct smu_context * smu,uint32_t * residency)2478 static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency)
2479 {
2480 struct amdgpu_device *adev = smu->adev;
2481
2482 *residency = adev->gfx.gfx_off_residency;
2483
2484 return 0;
2485 }
2486
2487 /**
2488 * vangogh_get_gfxoff_entrycount - get gfxoff entry count
2489 *
2490 * @smu: amdgpu_device pointer
2491 * @entrycount: placeholder for return value
2492 *
2493 * This function will be used to get gfxoff entry count
2494 *
2495 * Returns standard response codes.
2496 */
vangogh_get_gfxoff_entrycount(struct smu_context * smu,uint64_t * entrycount)2497 static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount)
2498 {
2499 int ret = 0, value = 0;
2500 struct amdgpu_device *adev = smu->adev;
2501
2502 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
2503 return 0;
2504
2505 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value);
2506 *entrycount = value + adev->gfx.gfx_off_entrycount;
2507
2508 return ret;
2509 }
2510
2511 static const struct pptable_funcs vangogh_ppt_funcs = {
2512
2513 .check_fw_status = smu_v11_0_check_fw_status,
2514 .check_fw_version = smu_v11_0_check_fw_version,
2515 .init_smc_tables = vangogh_init_smc_tables,
2516 .fini_smc_tables = smu_v11_0_fini_smc_tables,
2517 .init_power = smu_v11_0_init_power,
2518 .fini_power = smu_v11_0_fini_power,
2519 .register_irq_handler = smu_v11_0_register_irq_handler,
2520 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2521 .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
2522 .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
2523 .is_dpm_running = vangogh_is_dpm_running,
2524 .read_sensor = vangogh_read_sensor,
2525 .get_apu_thermal_limit = vangogh_get_apu_thermal_limit,
2526 .set_apu_thermal_limit = vangogh_set_apu_thermal_limit,
2527 .get_enabled_mask = smu_cmn_get_enabled_mask,
2528 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2529 .set_watermarks_table = vangogh_set_watermarks_table,
2530 .set_driver_table_location = smu_v11_0_set_driver_table_location,
2531 .interrupt_work = smu_v11_0_interrupt_work,
2532 .get_gpu_metrics = vangogh_common_get_gpu_metrics,
2533 .od_edit_dpm_table = vangogh_od_edit_dpm_table,
2534 .emit_clk_levels = vangogh_common_emit_clk_levels,
2535 .set_default_dpm_table = vangogh_set_default_dpm_tables,
2536 .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
2537 .notify_rlc_state = vangogh_notify_rlc_state,
2538 .feature_is_enabled = smu_cmn_feature_is_enabled,
2539 .set_power_profile_mode = vangogh_set_power_profile_mode,
2540 .get_power_profile_mode = vangogh_get_power_profile_mode,
2541 .get_dpm_clock_table = vangogh_get_dpm_clock_table,
2542 .force_clk_levels = vangogh_force_clk_levels,
2543 .set_performance_level = vangogh_set_performance_level,
2544 .post_init = vangogh_post_smu_init,
2545 .mode2_reset = vangogh_mode2_reset,
2546 .gfx_off_control = smu_v11_0_gfx_off_control,
2547 .get_gfx_off_status = vangogh_get_gfxoff_status,
2548 .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount,
2549 .get_gfx_off_residency = vangogh_get_gfxoff_residency,
2550 .set_gfx_off_residency = vangogh_set_gfxoff_residency,
2551 .get_ppt_limit = vangogh_get_ppt_limit,
2552 .get_power_limit = vangogh_get_power_limit,
2553 .set_power_limit = vangogh_set_power_limit,
2554 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2555 };
2556
vangogh_set_ppt_funcs(struct smu_context * smu)2557 void vangogh_set_ppt_funcs(struct smu_context *smu)
2558 {
2559 smu->ppt_funcs = &vangogh_ppt_funcs;
2560 smu->feature_map = vangogh_feature_mask_map;
2561 smu->table_map = vangogh_table_map;
2562 smu->workload_map = vangogh_workload_map;
2563 smu->is_apu = true;
2564 smu_v11_0_init_msg_ctl(smu, vangogh_message_map);
2565 }
2566