1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2021 Intel Corporation
4 */
5
6 #include "xe_pci.h"
7
8 #include <kunit/static_stub.h>
9 #include <linux/device/driver.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/pm_runtime.h>
13
14 #include <drm/drm_color_mgmt.h>
15 #include <drm/drm_drv.h>
16 #include <drm/intel/pciids.h>
17
18 #include "display/xe_display.h"
19 #include "regs/xe_gt_regs.h"
20 #include "regs/xe_regs.h"
21 #include "xe_configfs.h"
22 #include "xe_device.h"
23 #include "xe_drv.h"
24 #include "xe_gt.h"
25 #include "xe_gt_sriov_vf.h"
26 #include "xe_guc.h"
27 #include "xe_mmio.h"
28 #include "xe_module.h"
29 #include "xe_pci_rebar.h"
30 #include "xe_pci_sriov.h"
31 #include "xe_pci_types.h"
32 #include "xe_pm.h"
33 #include "xe_printk.h"
34 #include "xe_sriov.h"
35 #include "xe_step.h"
36 #include "xe_survivability_mode.h"
37 #include "xe_tile.h"
38
39 enum toggle_d3cold {
40 D3COLD_DISABLE,
41 D3COLD_ENABLE,
42 };
43
44 __diag_push();
45 __diag_ignore_all("-Woverride-init", "Allow field overrides in table");
46
47 #define PLATFORM(x) \
48 .platform = XE_##x, \
49 .platform_name = #x
50
51 #define NOP(x) x
52
53 static const struct xe_graphics_desc graphics_xelp = {
54 .hw_engine_mask = BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0),
55 };
56
57 #define XE_HP_FEATURES \
58 .has_range_tlb_inval = true
59
60 static const struct xe_graphics_desc graphics_xehpg = {
61 .hw_engine_mask =
62 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
63 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
64 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
65
66 XE_HP_FEATURES,
67 };
68
69 static const struct xe_graphics_desc graphics_xehpc = {
70 .hw_engine_mask =
71 BIT(XE_HW_ENGINE_BCS0) | BIT(XE_HW_ENGINE_BCS1) |
72 BIT(XE_HW_ENGINE_BCS2) | BIT(XE_HW_ENGINE_BCS3) |
73 BIT(XE_HW_ENGINE_BCS4) | BIT(XE_HW_ENGINE_BCS5) |
74 BIT(XE_HW_ENGINE_BCS6) | BIT(XE_HW_ENGINE_BCS7) |
75 BIT(XE_HW_ENGINE_BCS8) |
76 BIT(XE_HW_ENGINE_CCS0) | BIT(XE_HW_ENGINE_CCS1) |
77 BIT(XE_HW_ENGINE_CCS2) | BIT(XE_HW_ENGINE_CCS3),
78
79 XE_HP_FEATURES,
80
81 .has_asid = 1,
82 .has_atomic_enable_pte_bit = 1,
83 .has_usm = 1,
84 };
85
86 static const struct xe_graphics_desc graphics_xelpg = {
87 .hw_engine_mask =
88 BIT(XE_HW_ENGINE_RCS0) | BIT(XE_HW_ENGINE_BCS0) |
89 BIT(XE_HW_ENGINE_CCS0),
90
91 XE_HP_FEATURES,
92 };
93
94 #define XE2_GFX_FEATURES \
95 .has_asid = 1, \
96 .has_atomic_enable_pte_bit = 1, \
97 .has_range_tlb_inval = 1, \
98 .has_usm = 1, \
99 .has_64bit_timestamp = 1, \
100 .hw_engine_mask = \
101 BIT(XE_HW_ENGINE_RCS0) | \
102 BIT(XE_HW_ENGINE_BCS8) | BIT(XE_HW_ENGINE_BCS0) | \
103 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
104
105 static const struct xe_graphics_desc graphics_xe2 = {
106 XE2_GFX_FEATURES,
107 };
108
109 static const struct xe_graphics_desc graphics_xe3p_xpc = {
110 XE2_GFX_FEATURES,
111 .has_indirect_ring_state = 1,
112 .hw_engine_mask =
113 GENMASK(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS1) |
114 GENMASK(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0),
115 };
116
117 static const struct xe_media_desc media_xem = {
118 .hw_engine_mask =
119 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
120 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0),
121 };
122
123 static const struct xe_media_desc media_xelpmp = {
124 .hw_engine_mask =
125 GENMASK(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0) |
126 GENMASK(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0) |
127 BIT(XE_HW_ENGINE_GSCCS0)
128 };
129
130 /* Pre-GMDID Graphics IPs */
131 static const struct xe_ip graphics_ip_xelp = { 1200, "Xe_LP", &graphics_xelp };
132 static const struct xe_ip graphics_ip_xelpp = { 1210, "Xe_LP+", &graphics_xelp };
133 static const struct xe_ip graphics_ip_xehpg = { 1255, "Xe_HPG", &graphics_xehpg };
134 static const struct xe_ip graphics_ip_xehpc = { 1260, "Xe_HPC", &graphics_xehpc };
135
136 /* GMDID-based Graphics IPs */
137 static const struct xe_ip graphics_ips[] = {
138 { 1270, "Xe_LPG", &graphics_xelpg },
139 { 1271, "Xe_LPG", &graphics_xelpg },
140 { 1274, "Xe_LPG+", &graphics_xelpg },
141 { 2001, "Xe2_HPG", &graphics_xe2 },
142 { 2002, "Xe2_HPG", &graphics_xe2 },
143 { 2004, "Xe2_LPG", &graphics_xe2 },
144 { 3000, "Xe3_LPG", &graphics_xe2 },
145 { 3001, "Xe3_LPG", &graphics_xe2 },
146 { 3003, "Xe3_LPG", &graphics_xe2 },
147 { 3004, "Xe3_LPG", &graphics_xe2 },
148 { 3005, "Xe3_LPG", &graphics_xe2 },
149 { 3511, "Xe3p_XPC", &graphics_xe3p_xpc },
150 };
151
152 /* Pre-GMDID Media IPs */
153 static const struct xe_ip media_ip_xem = { 1200, "Xe_M", &media_xem };
154 static const struct xe_ip media_ip_xehpm = { 1255, "Xe_HPM", &media_xem };
155
156 /* GMDID-based Media IPs */
157 static const struct xe_ip media_ips[] = {
158 { 1300, "Xe_LPM+", &media_xelpmp },
159 { 1301, "Xe2_HPM", &media_xelpmp },
160 { 2000, "Xe2_LPM", &media_xelpmp },
161 { 3000, "Xe3_LPM", &media_xelpmp },
162 { 3002, "Xe3_LPM", &media_xelpmp },
163 { 3500, "Xe3p_LPM", &media_xelpmp },
164 { 3503, "Xe3p_HPM", &media_xelpmp },
165 };
166
167 static const struct xe_device_desc tgl_desc = {
168 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
169 .pre_gmdid_media_ip = &media_ip_xem,
170 PLATFORM(TIGERLAKE),
171 .dma_mask_size = 39,
172 .has_cached_pt = true,
173 .has_display = true,
174 .has_llc = true,
175 .has_sriov = true,
176 .max_gt_per_tile = 1,
177 .require_force_probe = true,
178 .va_bits = 48,
179 .vm_max_level = 3,
180 };
181
182 static const struct xe_device_desc rkl_desc = {
183 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
184 .pre_gmdid_media_ip = &media_ip_xem,
185 PLATFORM(ROCKETLAKE),
186 .dma_mask_size = 39,
187 .has_cached_pt = true,
188 .has_display = true,
189 .has_llc = true,
190 .max_gt_per_tile = 1,
191 .require_force_probe = true,
192 .va_bits = 48,
193 .vm_max_level = 3,
194 };
195
196 static const u16 adls_rpls_ids[] = { INTEL_RPLS_IDS(NOP), 0 };
197
198 static const struct xe_device_desc adl_s_desc = {
199 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
200 .pre_gmdid_media_ip = &media_ip_xem,
201 PLATFORM(ALDERLAKE_S),
202 .dma_mask_size = 39,
203 .has_cached_pt = true,
204 .has_display = true,
205 .has_llc = true,
206 .has_sriov = true,
207 .max_gt_per_tile = 1,
208 .require_force_probe = true,
209 .subplatforms = (const struct xe_subplatform_desc[]) {
210 { XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
211 {},
212 },
213 .va_bits = 48,
214 .vm_max_level = 3,
215 };
216
217 static const u16 adlp_rplu_ids[] = { INTEL_RPLU_IDS(NOP), 0 };
218
219 static const struct xe_device_desc adl_p_desc = {
220 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
221 .pre_gmdid_media_ip = &media_ip_xem,
222 PLATFORM(ALDERLAKE_P),
223 .dma_mask_size = 39,
224 .has_cached_pt = true,
225 .has_display = true,
226 .has_llc = true,
227 .has_sriov = true,
228 .max_gt_per_tile = 1,
229 .require_force_probe = true,
230 .subplatforms = (const struct xe_subplatform_desc[]) {
231 { XE_SUBPLATFORM_ALDERLAKE_P_RPLU, "RPLU", adlp_rplu_ids },
232 {},
233 },
234 .va_bits = 48,
235 .vm_max_level = 3,
236 };
237
238 static const struct xe_device_desc adl_n_desc = {
239 .pre_gmdid_graphics_ip = &graphics_ip_xelp,
240 .pre_gmdid_media_ip = &media_ip_xem,
241 PLATFORM(ALDERLAKE_N),
242 .dma_mask_size = 39,
243 .has_cached_pt = true,
244 .has_display = true,
245 .has_llc = true,
246 .has_sriov = true,
247 .max_gt_per_tile = 1,
248 .require_force_probe = true,
249 .va_bits = 48,
250 .vm_max_level = 3,
251 };
252
253 #define DGFX_FEATURES \
254 .is_dgfx = 1
255
256 static const struct xe_device_desc dg1_desc = {
257 .pre_gmdid_graphics_ip = &graphics_ip_xelpp,
258 .pre_gmdid_media_ip = &media_ip_xem,
259 DGFX_FEATURES,
260 PLATFORM(DG1),
261 .dma_mask_size = 39,
262 .has_display = true,
263 .has_gsc_nvm = 1,
264 .has_heci_gscfi = 1,
265 .max_gt_per_tile = 1,
266 .require_force_probe = true,
267 .va_bits = 48,
268 .vm_max_level = 3,
269 };
270
271 static const u16 dg2_g10_ids[] = { INTEL_DG2_G10_IDS(NOP), INTEL_ATS_M150_IDS(NOP), 0 };
272 static const u16 dg2_g11_ids[] = { INTEL_DG2_G11_IDS(NOP), INTEL_ATS_M75_IDS(NOP), 0 };
273 static const u16 dg2_g12_ids[] = { INTEL_DG2_G12_IDS(NOP), 0 };
274
275 #define DG2_FEATURES \
276 DGFX_FEATURES, \
277 PLATFORM(DG2), \
278 .has_flat_ccs = 1, \
279 .has_gsc_nvm = 1, \
280 .has_heci_gscfi = 1, \
281 .subplatforms = (const struct xe_subplatform_desc[]) { \
282 { XE_SUBPLATFORM_DG2_G10, "G10", dg2_g10_ids }, \
283 { XE_SUBPLATFORM_DG2_G11, "G11", dg2_g11_ids }, \
284 { XE_SUBPLATFORM_DG2_G12, "G12", dg2_g12_ids }, \
285 { } \
286 }, \
287 .va_bits = 48, \
288 .vm_max_level = 3, \
289 .vram_flags = XE_VRAM_FLAGS_NEED64K
290
291 static const struct xe_device_desc ats_m_desc = {
292 .pre_gmdid_graphics_ip = &graphics_ip_xehpg,
293 .pre_gmdid_media_ip = &media_ip_xehpm,
294 .dma_mask_size = 46,
295 .max_gt_per_tile = 1,
296 .require_force_probe = true,
297
298 DG2_FEATURES,
299 .has_display = false,
300 .has_sriov = true,
301 };
302
303 static const struct xe_device_desc dg2_desc = {
304 .pre_gmdid_graphics_ip = &graphics_ip_xehpg,
305 .pre_gmdid_media_ip = &media_ip_xehpm,
306 .dma_mask_size = 46,
307 .max_gt_per_tile = 1,
308 .require_force_probe = true,
309
310 DG2_FEATURES,
311 .has_display = true,
312 .has_fan_control = true,
313 .has_mbx_power_limits = false,
314 };
315
316 static const __maybe_unused struct xe_device_desc pvc_desc = {
317 .pre_gmdid_graphics_ip = &graphics_ip_xehpc,
318 DGFX_FEATURES,
319 PLATFORM(PVC),
320 .dma_mask_size = 52,
321 .has_display = false,
322 .has_gsc_nvm = 1,
323 .has_heci_gscfi = 1,
324 .max_gt_per_tile = 1,
325 .max_remote_tiles = 1,
326 .require_force_probe = true,
327 .va_bits = 57,
328 .vm_max_level = 4,
329 .vram_flags = XE_VRAM_FLAGS_NEED64K,
330 .has_mbx_power_limits = false,
331 };
332
333 static const struct xe_device_desc mtl_desc = {
334 /* .graphics and .media determined via GMD_ID */
335 .require_force_probe = true,
336 PLATFORM(METEORLAKE),
337 .dma_mask_size = 46,
338 .has_display = true,
339 .has_pxp = true,
340 .max_gt_per_tile = 2,
341 .va_bits = 48,
342 .vm_max_level = 3,
343 };
344
345 static const struct xe_device_desc lnl_desc = {
346 PLATFORM(LUNARLAKE),
347 .dma_mask_size = 46,
348 .has_display = true,
349 .has_flat_ccs = 1,
350 .has_pxp = true,
351 .max_gt_per_tile = 2,
352 .needs_scratch = true,
353 .va_bits = 48,
354 .vm_max_level = 4,
355 };
356
357 static const u16 bmg_g21_ids[] = { INTEL_BMG_G21_IDS(NOP), 0 };
358
359 static const struct xe_device_desc bmg_desc = {
360 DGFX_FEATURES,
361 PLATFORM(BATTLEMAGE),
362 .dma_mask_size = 46,
363 .has_display = true,
364 .has_fan_control = true,
365 .has_flat_ccs = 1,
366 .has_mbx_power_limits = true,
367 .has_mbx_thermal_info = true,
368 .has_gsc_nvm = 1,
369 .has_heci_cscfi = 1,
370 .has_i2c = true,
371 .has_late_bind = true,
372 .has_pre_prod_wa = 1,
373 .has_soc_remapper_telem = true,
374 .has_sriov = true,
375 .max_gt_per_tile = 2,
376 .needs_scratch = true,
377 .subplatforms = (const struct xe_subplatform_desc[]) {
378 { XE_SUBPLATFORM_BATTLEMAGE_G21, "G21", bmg_g21_ids },
379 { }
380 },
381 .va_bits = 48,
382 .vm_max_level = 4,
383 };
384
385 static const struct xe_device_desc ptl_desc = {
386 PLATFORM(PANTHERLAKE),
387 .dma_mask_size = 46,
388 .has_display = true,
389 .has_flat_ccs = 1,
390 .has_sriov = true,
391 .has_pre_prod_wa = 1,
392 .has_pxp = true,
393 .max_gt_per_tile = 2,
394 .needs_scratch = true,
395 .needs_shared_vf_gt_wq = true,
396 .va_bits = 48,
397 .vm_max_level = 4,
398 };
399
400 static const struct xe_device_desc nvls_desc = {
401 PLATFORM(NOVALAKE_S),
402 .dma_mask_size = 46,
403 .has_display = true,
404 .has_flat_ccs = 1,
405 .has_pre_prod_wa = 1,
406 .max_gt_per_tile = 2,
407 .require_force_probe = true,
408 .va_bits = 48,
409 .vm_max_level = 4,
410 };
411
412 static const struct xe_device_desc cri_desc = {
413 DGFX_FEATURES,
414 PLATFORM(CRESCENTISLAND),
415 .dma_mask_size = 52,
416 .has_display = false,
417 .has_flat_ccs = false,
418 .has_gsc_nvm = 1,
419 .has_i2c = true,
420 .has_mbx_power_limits = true,
421 .has_mbx_thermal_info = true,
422 .has_mert = true,
423 .has_pre_prod_wa = 1,
424 .has_soc_remapper_sysctrl = true,
425 .has_soc_remapper_telem = true,
426 .has_sriov = true,
427 .max_gt_per_tile = 2,
428 .require_force_probe = true,
429 .va_bits = 57,
430 .vm_max_level = 4,
431 };
432
433 #undef PLATFORM
434 __diag_pop();
435
436 /*
437 * Make sure any device matches here are from most specific to most
438 * general. For example, since the Quanta match is based on the subsystem
439 * and subvendor IDs, we need it to come before the more general IVB
440 * PCI ID matches, otherwise we'll use the wrong info struct above.
441 */
442 static const struct pci_device_id pciidlist[] = {
443 INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_desc),
444 INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_desc),
445 INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
446 INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
447 INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
448 INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
449 INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
450 INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
451 INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
452 INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
453 INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
454 INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
455 INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
456 INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc),
457 INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
458 INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
459 INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
460 INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
461 INTEL_CRI_IDS(INTEL_PCI_DEVICE, &cri_desc),
462 { }
463 };
464 MODULE_DEVICE_TABLE(pci, pciidlist);
465
466 /* is device_id present in comma separated list of ids */
device_id_in_list(u16 device_id,const char * devices,bool negative)467 static bool device_id_in_list(u16 device_id, const char *devices, bool negative)
468 {
469 char *s, *p, *tok;
470 bool ret;
471
472 if (!devices || !*devices)
473 return false;
474
475 /* match everything */
476 if (negative && strcmp(devices, "!*") == 0)
477 return true;
478 if (!negative && strcmp(devices, "*") == 0)
479 return true;
480
481 s = kstrdup(devices, GFP_KERNEL);
482 if (!s)
483 return false;
484
485 for (p = s, ret = false; (tok = strsep(&p, ",")) != NULL; ) {
486 u16 val;
487
488 if (negative && tok[0] == '!')
489 tok++;
490 else if ((negative && tok[0] != '!') ||
491 (!negative && tok[0] == '!'))
492 continue;
493
494 if (kstrtou16(tok, 16, &val) == 0 && val == device_id) {
495 ret = true;
496 break;
497 }
498 }
499
500 kfree(s);
501
502 return ret;
503 }
504
id_forced(u16 device_id)505 static bool id_forced(u16 device_id)
506 {
507 return device_id_in_list(device_id, xe_modparam.force_probe, false);
508 }
509
id_blocked(u16 device_id)510 static bool id_blocked(u16 device_id)
511 {
512 return device_id_in_list(device_id, xe_modparam.force_probe, true);
513 }
514
515 static const struct xe_subplatform_desc *
find_subplatform(const struct xe_device * xe,const struct xe_device_desc * desc)516 find_subplatform(const struct xe_device *xe, const struct xe_device_desc *desc)
517 {
518 const struct xe_subplatform_desc *sp;
519 const u16 *id;
520
521 for (sp = desc->subplatforms; sp && sp->subplatform; sp++)
522 for (id = sp->pciidlist; *id; id++)
523 if (*id == xe->info.devid)
524 return sp;
525
526 return NULL;
527 }
528
529 enum xe_gmdid_type {
530 GMDID_GRAPHICS,
531 GMDID_MEDIA
532 };
533
read_gmdid(struct xe_device * xe,enum xe_gmdid_type type,u32 * ver,u32 * revid)534 static int read_gmdid(struct xe_device *xe, enum xe_gmdid_type type, u32 *ver, u32 *revid)
535 {
536 struct xe_mmio *mmio = xe_root_tile_mmio(xe);
537 struct xe_reg gmdid_reg = GMD_ID;
538 u32 val;
539
540 KUNIT_STATIC_STUB_REDIRECT(read_gmdid, xe, type, ver, revid);
541
542 if (IS_SRIOV_VF(xe)) {
543 /*
544 * To get the value of the GMDID register, VFs must obtain it
545 * from the GuC using MMIO communication.
546 *
547 * Note that at this point the GTs are not initialized and only
548 * tile-level access to MMIO registers is possible. To use our
549 * existing GuC communication functions we must create a dummy
550 * GT structure and perform at least basic xe_gt and xe_guc
551 * initialization.
552 */
553 struct xe_gt *gt __free(kfree) = NULL;
554 int err;
555
556 /* Don't try to read media ver if media GT is not allowed */
557 if (type == GMDID_MEDIA && !xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) {
558 *ver = *revid = 0;
559 return 0;
560 }
561
562 gt = kzalloc(sizeof(*gt), GFP_KERNEL);
563 if (!gt)
564 return -ENOMEM;
565
566 gt->tile = &xe->tiles[0];
567 if (type == GMDID_MEDIA) {
568 gt->info.id = 1;
569 gt->info.type = XE_GT_TYPE_MEDIA;
570 } else {
571 gt->info.id = 0;
572 gt->info.type = XE_GT_TYPE_MAIN;
573 }
574
575 xe_gt_mmio_init(gt);
576 xe_guc_comm_init_early(>->uc.guc);
577
578 err = xe_gt_sriov_vf_bootstrap(gt);
579 if (err)
580 return err;
581
582 val = xe_gt_sriov_vf_gmdid(gt);
583 } else {
584 /*
585 * GMD_ID is a GT register, but at this point in the driver
586 * init we haven't fully initialized the GT yet so we need to
587 * read the register with the tile's MMIO accessor. That means
588 * we need to apply the GSI offset manually since it won't get
589 * automatically added as it would if we were using a GT mmio
590 * accessor.
591 */
592 if (type == GMDID_MEDIA)
593 gmdid_reg.addr += MEDIA_GT_GSI_OFFSET;
594
595 val = xe_mmio_read32(mmio, gmdid_reg);
596 }
597
598 *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val) * 100 + REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
599 *revid = REG_FIELD_GET(GMD_ID_REVID, val);
600
601 return 0;
602 }
603
find_graphics_ip(unsigned int verx100)604 static const struct xe_ip *find_graphics_ip(unsigned int verx100)
605 {
606 KUNIT_STATIC_STUB_REDIRECT(find_graphics_ip, verx100);
607
608 for (int i = 0; i < ARRAY_SIZE(graphics_ips); i++)
609 if (graphics_ips[i].verx100 == verx100)
610 return &graphics_ips[i];
611 return NULL;
612 }
613
find_media_ip(unsigned int verx100)614 static const struct xe_ip *find_media_ip(unsigned int verx100)
615 {
616 KUNIT_STATIC_STUB_REDIRECT(find_media_ip, verx100);
617
618 for (int i = 0; i < ARRAY_SIZE(media_ips); i++)
619 if (media_ips[i].verx100 == verx100)
620 return &media_ips[i];
621 return NULL;
622 }
623
624 /*
625 * Read IP version from hardware and select graphics/media IP descriptors
626 * based on the result.
627 */
handle_gmdid(struct xe_device * xe,const struct xe_ip ** graphics_ip,const struct xe_ip ** media_ip,u32 * graphics_revid,u32 * media_revid)628 static int handle_gmdid(struct xe_device *xe,
629 const struct xe_ip **graphics_ip,
630 const struct xe_ip **media_ip,
631 u32 *graphics_revid,
632 u32 *media_revid)
633 {
634 u32 ver;
635 int ret;
636
637 *graphics_ip = NULL;
638 *media_ip = NULL;
639
640 ret = read_gmdid(xe, GMDID_GRAPHICS, &ver, graphics_revid);
641 if (ret)
642 return ret;
643
644 *graphics_ip = find_graphics_ip(ver);
645 if (!*graphics_ip) {
646 drm_err(&xe->drm, "Hardware reports unknown graphics version %u.%02u\n",
647 ver / 100, ver % 100);
648 }
649
650 ret = read_gmdid(xe, GMDID_MEDIA, &ver, media_revid);
651 if (ret)
652 return ret;
653
654 /* Media may legitimately be fused off / not present */
655 if (ver == 0)
656 return 0;
657
658 *media_ip = find_media_ip(ver);
659 if (!*media_ip) {
660 drm_err(&xe->drm, "Hardware reports unknown media version %u.%02u\n",
661 ver / 100, ver % 100);
662 }
663
664 return 0;
665 }
666
667 /*
668 * Initialize device info content that only depends on static driver_data
669 * passed to the driver at probe time from PCI ID table.
670 */
xe_info_init_early(struct xe_device * xe,const struct xe_device_desc * desc,const struct xe_subplatform_desc * subplatform_desc)671 static int xe_info_init_early(struct xe_device *xe,
672 const struct xe_device_desc *desc,
673 const struct xe_subplatform_desc *subplatform_desc)
674 {
675 int err;
676
677 xe->info.platform_name = desc->platform_name;
678 xe->info.platform = desc->platform;
679 xe->info.subplatform = subplatform_desc ?
680 subplatform_desc->subplatform : XE_SUBPLATFORM_NONE;
681
682 xe->info.dma_mask_size = desc->dma_mask_size;
683 xe->info.va_bits = desc->va_bits;
684 xe->info.vm_max_level = desc->vm_max_level;
685 xe->info.vram_flags = desc->vram_flags;
686
687 xe->info.is_dgfx = desc->is_dgfx;
688 xe->info.has_cached_pt = desc->has_cached_pt;
689 xe->info.has_fan_control = desc->has_fan_control;
690 /* runtime fusing may force flat_ccs to disabled later */
691 xe->info.has_flat_ccs = desc->has_flat_ccs;
692 xe->info.has_mbx_power_limits = desc->has_mbx_power_limits;
693 xe->info.has_mbx_thermal_info = desc->has_mbx_thermal_info;
694 xe->info.has_gsc_nvm = desc->has_gsc_nvm;
695 xe->info.has_heci_gscfi = desc->has_heci_gscfi;
696 xe->info.has_heci_cscfi = desc->has_heci_cscfi;
697 xe->info.has_i2c = desc->has_i2c;
698 xe->info.has_late_bind = desc->has_late_bind;
699 xe->info.has_llc = desc->has_llc;
700 xe->info.has_mert = desc->has_mert;
701 xe->info.has_page_reclaim_hw_assist = desc->has_page_reclaim_hw_assist;
702 xe->info.has_pre_prod_wa = desc->has_pre_prod_wa;
703 xe->info.has_pxp = desc->has_pxp;
704 xe->info.has_soc_remapper_sysctrl = desc->has_soc_remapper_sysctrl;
705 xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
706 xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
707 desc->has_sriov;
708 xe->info.skip_guc_pc = desc->skip_guc_pc;
709 xe->info.skip_mtcfg = desc->skip_mtcfg;
710 xe->info.skip_pcode = desc->skip_pcode;
711 xe->info.needs_scratch = desc->needs_scratch;
712 xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
713
714 xe->info.probe_display = IS_ENABLED(CONFIG_DRM_XE_DISPLAY) &&
715 xe_modparam.probe_display &&
716 desc->has_display;
717
718 xe_assert(xe, desc->max_gt_per_tile > 0);
719 xe_assert(xe, desc->max_gt_per_tile <= XE_MAX_GT_PER_TILE);
720 xe->info.max_gt_per_tile = desc->max_gt_per_tile;
721 xe->info.tile_count = 1 + desc->max_remote_tiles;
722
723 err = xe_tile_init_early(xe_device_get_root_tile(xe), xe, 0);
724 if (err)
725 return err;
726
727 return 0;
728 }
729
730 /*
731 * Possibly override number of tile based on configuration register.
732 */
xe_info_probe_tile_count(struct xe_device * xe)733 static void xe_info_probe_tile_count(struct xe_device *xe)
734 {
735 struct xe_mmio *mmio;
736 u8 tile_count;
737 u32 mtcfg;
738
739 KUNIT_STATIC_STUB_REDIRECT(xe_info_probe_tile_count, xe);
740
741 /*
742 * Probe for tile count only for platforms that support multiple
743 * tiles.
744 */
745 if (xe->info.tile_count == 1)
746 return;
747
748 if (xe->info.skip_mtcfg)
749 return;
750
751 mmio = xe_root_tile_mmio(xe);
752
753 /*
754 * Although the per-tile mmio regs are not yet initialized, this
755 * is fine as it's going to the root tile's mmio, that's
756 * guaranteed to be initialized earlier in xe_mmio_probe_early()
757 */
758 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR);
759 tile_count = REG_FIELD_GET(TILE_COUNT, mtcfg) + 1;
760
761 if (tile_count < xe->info.tile_count) {
762 drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n",
763 xe->info.tile_count, tile_count);
764 xe->info.tile_count = tile_count;
765 }
766 }
767
alloc_primary_gt(struct xe_tile * tile,const struct xe_graphics_desc * graphics_desc,const struct xe_media_desc * media_desc)768 static struct xe_gt *alloc_primary_gt(struct xe_tile *tile,
769 const struct xe_graphics_desc *graphics_desc,
770 const struct xe_media_desc *media_desc)
771 {
772 struct xe_device *xe = tile_to_xe(tile);
773 struct xe_gt *gt;
774
775 if (!xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev))) {
776 xe_info(xe, "Primary GT disabled via configfs\n");
777 return NULL;
778 }
779
780 gt = xe_gt_alloc(tile);
781 if (IS_ERR(gt))
782 return gt;
783
784 gt->info.type = XE_GT_TYPE_MAIN;
785 gt->info.id = tile->id * xe->info.max_gt_per_tile;
786 gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
787 gt->info.multi_queue_engine_class_mask = graphics_desc->multi_queue_engine_class_mask;
788 gt->info.engine_mask = graphics_desc->hw_engine_mask;
789
790 /*
791 * Before media version 13, the media IP was part of the primary GT
792 * so we need to add the media engines to the primary GT's engine list.
793 */
794 if (MEDIA_VER(xe) < 13 && media_desc)
795 gt->info.engine_mask |= media_desc->hw_engine_mask;
796
797 return gt;
798 }
799
alloc_media_gt(struct xe_tile * tile,const struct xe_media_desc * media_desc)800 static struct xe_gt *alloc_media_gt(struct xe_tile *tile,
801 const struct xe_media_desc *media_desc)
802 {
803 struct xe_device *xe = tile_to_xe(tile);
804 struct xe_gt *gt;
805
806 if (!xe_configfs_media_gt_allowed(to_pci_dev(xe->drm.dev))) {
807 xe_info(xe, "Media GT disabled via configfs\n");
808 return NULL;
809 }
810
811 if (MEDIA_VER(xe) < 13 || !media_desc)
812 return NULL;
813
814 gt = xe_gt_alloc(tile);
815 if (IS_ERR(gt))
816 return gt;
817
818 gt->info.type = XE_GT_TYPE_MEDIA;
819 gt->info.id = tile->id * xe->info.max_gt_per_tile + 1;
820 gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
821 gt->info.engine_mask = media_desc->hw_engine_mask;
822
823 return gt;
824 }
825
826 /*
827 * Initialize device info content that does require knowledge about
828 * graphics / media IP version.
829 * Make sure that GT / tile structures allocated by the driver match the data
830 * present in device info.
831 */
xe_info_init(struct xe_device * xe,const struct xe_device_desc * desc)832 static int xe_info_init(struct xe_device *xe,
833 const struct xe_device_desc *desc)
834 {
835 u32 graphics_gmdid_revid = 0, media_gmdid_revid = 0;
836 const struct xe_ip *graphics_ip;
837 const struct xe_ip *media_ip;
838 const struct xe_graphics_desc *graphics_desc;
839 const struct xe_media_desc *media_desc;
840 struct xe_tile *tile;
841 struct xe_gt *gt;
842 int ret;
843 u8 id;
844
845 /*
846 * If this platform supports GMD_ID, we'll detect the proper IP
847 * descriptor to use from hardware registers.
848 * desc->pre_gmdid_graphics_ip will only ever be set at this point for
849 * platforms before GMD_ID. In that case the IP descriptions and
850 * versions are simply derived from that.
851 */
852 if (desc->pre_gmdid_graphics_ip) {
853 graphics_ip = desc->pre_gmdid_graphics_ip;
854 media_ip = desc->pre_gmdid_media_ip;
855 xe->info.step = xe_step_pre_gmdid_get(xe);
856 } else {
857 xe_assert(xe, !desc->pre_gmdid_media_ip);
858 ret = handle_gmdid(xe, &graphics_ip, &media_ip,
859 &graphics_gmdid_revid, &media_gmdid_revid);
860 if (ret)
861 return ret;
862
863 xe->info.step = xe_step_gmdid_get(xe,
864 graphics_gmdid_revid,
865 media_gmdid_revid);
866 }
867
868 /*
869 * If we couldn't detect the graphics IP, that's considered a fatal
870 * error and we should abort driver load. Failing to detect media
871 * IP is non-fatal; we'll just proceed without enabling media support.
872 */
873 if (!graphics_ip)
874 return -ENODEV;
875
876 xe->info.graphics_verx100 = graphics_ip->verx100;
877 xe->info.graphics_name = graphics_ip->name;
878 graphics_desc = graphics_ip->desc;
879
880 if (media_ip) {
881 xe->info.media_verx100 = media_ip->verx100;
882 xe->info.media_name = media_ip->name;
883 media_desc = media_ip->desc;
884 } else {
885 xe->info.media_name = "none";
886 media_desc = NULL;
887 }
888
889 xe->info.has_asid = graphics_desc->has_asid;
890 xe->info.has_atomic_enable_pte_bit = graphics_desc->has_atomic_enable_pte_bit;
891 if (xe->info.platform != XE_PVC)
892 xe->info.has_device_atomics_on_smem = 1;
893
894 xe->info.has_range_tlb_inval = graphics_desc->has_range_tlb_inval;
895 xe->info.has_usm = graphics_desc->has_usm;
896 xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp;
897 xe->info.has_mem_copy_instr = GRAPHICS_VER(xe) >= 20;
898
899 xe_info_probe_tile_count(xe);
900
901 for_each_remote_tile(tile, xe, id) {
902 int err;
903
904 err = xe_tile_init_early(tile, xe, id);
905 if (err)
906 return err;
907 }
908
909 /* Allocate any GT and VRAM structures necessary for the platform. */
910 for_each_tile(tile, xe, id) {
911 int err;
912
913 err = xe_tile_alloc_vram(tile);
914 if (err)
915 return err;
916
917 tile->primary_gt = alloc_primary_gt(tile, graphics_desc, media_desc);
918 if (IS_ERR(tile->primary_gt))
919 return PTR_ERR(tile->primary_gt);
920
921 /*
922 * It's not currently possible to probe a device with the
923 * primary GT disabled. With some work, this may be future in
924 * the possible for igpu platforms (although probably not for
925 * dgpu's since access to the primary GT's BCS engines is
926 * required for VRAM management).
927 */
928 if (!tile->primary_gt) {
929 drm_err(&xe->drm, "Cannot probe device with without a primary GT\n");
930 return -ENODEV;
931 }
932
933 tile->media_gt = alloc_media_gt(tile, media_desc);
934 if (IS_ERR(tile->media_gt))
935 return PTR_ERR(tile->media_gt);
936 }
937
938 /*
939 * Now that we have tiles and GTs defined, let's loop over valid GTs
940 * in order to define gt_count.
941 */
942 for_each_gt(gt, xe, id)
943 xe->info.gt_count++;
944
945 return 0;
946 }
947
xe_pci_remove(struct pci_dev * pdev)948 static void xe_pci_remove(struct pci_dev *pdev)
949 {
950 struct xe_device *xe = pdev_to_xe_device(pdev);
951
952 if (IS_SRIOV_PF(xe))
953 xe_pci_sriov_configure(pdev, 0);
954
955 if (xe_survivability_mode_is_boot_enabled(xe))
956 return;
957
958 xe_device_remove(xe);
959 xe_pm_fini(xe);
960 }
961
962 /*
963 * Probe the PCI device, initialize various parts of the driver.
964 *
965 * Fault injection is used to test the error paths of some initialization
966 * functions called either directly from xe_pci_probe() or indirectly for
967 * example through xe_device_probe(). Those functions use the kernel fault
968 * injection capabilities infrastructure, see
969 * Documentation/fault-injection/fault-injection.rst for details. The macro
970 * ALLOW_ERROR_INJECTION() is used to conditionally skip function execution
971 * at runtime and use a provided return value. The first requirement for
972 * error injectable functions is proper handling of the error code by the
973 * caller for recovery, which is always the case here. The second
974 * requirement is that no state is changed before the first error return.
975 * It is not strictly fulfilled for all initialization functions using the
976 * ALLOW_ERROR_INJECTION() macro but this is acceptable because for those
977 * error cases at probe time, the error code is simply propagated up by the
978 * caller. Therefore there is no consequence on those specific callers when
979 * function error injection skips the whole function.
980 */
xe_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)981 static int xe_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
982 {
983 const struct xe_device_desc *desc = (const void *)ent->driver_data;
984 const struct xe_subplatform_desc *subplatform_desc;
985 struct xe_device *xe;
986 int err;
987
988 xe_configfs_check_device(pdev);
989
990 if (desc->require_force_probe && !id_forced(pdev->device)) {
991 dev_info(&pdev->dev,
992 "Your graphics device %04x is not officially supported\n"
993 "by xe driver in this kernel version. To force Xe probe,\n"
994 "use xe.force_probe='%04x' and i915.force_probe='!%04x'\n"
995 "module parameters or CONFIG_DRM_XE_FORCE_PROBE='%04x' and\n"
996 "CONFIG_DRM_I915_FORCE_PROBE='!%04x' configuration options.\n",
997 pdev->device, pdev->device, pdev->device,
998 pdev->device, pdev->device);
999 return -ENODEV;
1000 }
1001
1002 if (id_blocked(pdev->device)) {
1003 dev_info(&pdev->dev, "Probe blocked for device [%04x:%04x].\n",
1004 pdev->vendor, pdev->device);
1005 return -ENODEV;
1006 }
1007
1008 if (xe_display_driver_probe_defer(pdev))
1009 return -EPROBE_DEFER;
1010
1011 err = pcim_enable_device(pdev);
1012 if (err)
1013 return err;
1014
1015 xe = xe_device_create(pdev, ent);
1016 if (IS_ERR(xe))
1017 return PTR_ERR(xe);
1018
1019 pci_set_drvdata(pdev, &xe->drm);
1020
1021 xe_pm_assert_unbounded_bridge(xe);
1022 subplatform_desc = find_subplatform(xe, desc);
1023
1024 pci_set_master(pdev);
1025
1026 err = xe_info_init_early(xe, desc, subplatform_desc);
1027 if (err)
1028 return err;
1029
1030 xe_pci_rebar_resize(xe);
1031
1032 err = xe_device_probe_early(xe);
1033 /*
1034 * In Boot Survivability mode, no drm card is exposed and driver
1035 * is loaded with bare minimum to allow for firmware to be
1036 * flashed through mei. Return success, if survivability mode
1037 * is enabled due to pcode failure or configfs being set
1038 */
1039 if (xe_survivability_mode_is_boot_enabled(xe))
1040 return 0;
1041
1042 if (err)
1043 return err;
1044
1045 err = xe_info_init(xe, desc);
1046 if (err)
1047 return err;
1048
1049 err = xe_display_probe(xe);
1050 if (err)
1051 return err;
1052
1053 drm_dbg(&xe->drm, "%s %s %04x:%04x dgfx:%d gfx:%s (%d.%02d) media:%s (%d.%02d) display:%s dma_m_s:%d tc:%d gscfi:%d cscfi:%d",
1054 desc->platform_name,
1055 subplatform_desc ? subplatform_desc->name : "",
1056 xe->info.devid, xe->info.revid,
1057 xe->info.is_dgfx,
1058 xe->info.graphics_name,
1059 xe->info.graphics_verx100 / 100,
1060 xe->info.graphics_verx100 % 100,
1061 xe->info.media_name,
1062 xe->info.media_verx100 / 100,
1063 xe->info.media_verx100 % 100,
1064 str_yes_no(xe->info.probe_display),
1065 xe->info.dma_mask_size, xe->info.tile_count,
1066 xe->info.has_heci_gscfi, xe->info.has_heci_cscfi);
1067
1068 drm_dbg(&xe->drm, "Stepping = (G:%s, M:%s, B:%s)\n",
1069 xe_step_name(xe->info.step.graphics),
1070 xe_step_name(xe->info.step.media),
1071 xe_step_name(xe->info.step.basedie));
1072
1073 drm_dbg(&xe->drm, "SR-IOV support: %s (mode: %s)\n",
1074 str_yes_no(xe_device_has_sriov(xe)),
1075 xe_sriov_mode_to_string(xe_device_sriov_mode(xe)));
1076
1077 err = xe_pm_init_early(xe);
1078 if (err)
1079 return err;
1080
1081 err = xe_device_probe(xe);
1082 if (err)
1083 return err;
1084
1085 err = xe_pm_init(xe);
1086 if (err)
1087 goto err_driver_cleanup;
1088
1089 drm_dbg(&xe->drm, "d3cold: capable=%s\n",
1090 str_yes_no(xe->d3cold.capable));
1091
1092 return 0;
1093
1094 err_driver_cleanup:
1095 xe_pci_remove(pdev);
1096 return err;
1097 }
1098
xe_pci_shutdown(struct pci_dev * pdev)1099 static void xe_pci_shutdown(struct pci_dev *pdev)
1100 {
1101 xe_device_shutdown(pdev_to_xe_device(pdev));
1102 }
1103
1104 #ifdef CONFIG_PM_SLEEP
d3cold_toggle(struct pci_dev * pdev,enum toggle_d3cold toggle)1105 static void d3cold_toggle(struct pci_dev *pdev, enum toggle_d3cold toggle)
1106 {
1107 struct xe_device *xe = pdev_to_xe_device(pdev);
1108 struct pci_dev *root_pdev;
1109
1110 if (!xe->d3cold.capable)
1111 return;
1112
1113 root_pdev = pcie_find_root_port(pdev);
1114 if (!root_pdev)
1115 return;
1116
1117 switch (toggle) {
1118 case D3COLD_DISABLE:
1119 pci_d3cold_disable(root_pdev);
1120 break;
1121 case D3COLD_ENABLE:
1122 pci_d3cold_enable(root_pdev);
1123 break;
1124 }
1125 }
1126
xe_pci_suspend(struct device * dev)1127 static int xe_pci_suspend(struct device *dev)
1128 {
1129 struct pci_dev *pdev = to_pci_dev(dev);
1130 struct xe_device *xe = pdev_to_xe_device(pdev);
1131 int err;
1132
1133 if (xe_survivability_mode_is_boot_enabled(xe))
1134 return -EBUSY;
1135
1136 err = xe_pm_suspend(xe);
1137 if (err)
1138 return err;
1139
1140 /*
1141 * Enabling D3Cold is needed for S2Idle/S0ix.
1142 * It is save to allow here since xe_pm_suspend has evicted
1143 * the local memory and the direct complete optimization is disabled.
1144 */
1145 d3cold_toggle(pdev, D3COLD_ENABLE);
1146
1147 pci_save_state(pdev);
1148 pci_disable_device(pdev);
1149 pci_set_power_state(pdev, PCI_D3cold);
1150
1151 return 0;
1152 }
1153
xe_pci_resume(struct device * dev)1154 static int xe_pci_resume(struct device *dev)
1155 {
1156 struct pci_dev *pdev = to_pci_dev(dev);
1157 int err;
1158
1159 /* Give back the D3Cold decision to the runtime P M*/
1160 d3cold_toggle(pdev, D3COLD_DISABLE);
1161
1162 err = pci_set_power_state(pdev, PCI_D0);
1163 if (err)
1164 return err;
1165
1166 pci_restore_state(pdev);
1167
1168 err = pci_enable_device(pdev);
1169 if (err)
1170 return err;
1171
1172 pci_set_master(pdev);
1173
1174 err = xe_pm_resume(pdev_to_xe_device(pdev));
1175 if (err)
1176 return err;
1177
1178 return 0;
1179 }
1180
xe_pci_runtime_suspend(struct device * dev)1181 static int xe_pci_runtime_suspend(struct device *dev)
1182 {
1183 struct pci_dev *pdev = to_pci_dev(dev);
1184 struct xe_device *xe = pdev_to_xe_device(pdev);
1185 int err;
1186
1187 /*
1188 * We hold an additional reference to the runtime PM to keep PF in D0
1189 * during VFs lifetime, as our VFs do not implement the PM capability.
1190 * This means we should never be runtime suspending as long as VFs are
1191 * enabled.
1192 */
1193 xe_assert(xe, !IS_SRIOV_VF(xe));
1194 xe_assert(xe, !pci_num_vf(pdev));
1195
1196 err = xe_pm_runtime_suspend(xe);
1197 if (err)
1198 return err;
1199
1200 pci_save_state(pdev);
1201
1202 if (xe->d3cold.allowed) {
1203 d3cold_toggle(pdev, D3COLD_ENABLE);
1204 pci_disable_device(pdev);
1205 pci_ignore_hotplug(pdev);
1206 pci_set_power_state(pdev, PCI_D3cold);
1207 } else {
1208 d3cold_toggle(pdev, D3COLD_DISABLE);
1209 pci_set_power_state(pdev, PCI_D3hot);
1210 }
1211
1212 return 0;
1213 }
1214
xe_pci_runtime_resume(struct device * dev)1215 static int xe_pci_runtime_resume(struct device *dev)
1216 {
1217 struct pci_dev *pdev = to_pci_dev(dev);
1218 struct xe_device *xe = pdev_to_xe_device(pdev);
1219 int err;
1220
1221 err = pci_set_power_state(pdev, PCI_D0);
1222 if (err)
1223 return err;
1224
1225 pci_restore_state(pdev);
1226
1227 if (xe->d3cold.allowed) {
1228 err = pci_enable_device(pdev);
1229 if (err)
1230 return err;
1231
1232 pci_set_master(pdev);
1233 }
1234
1235 return xe_pm_runtime_resume(xe);
1236 }
1237
xe_pci_runtime_idle(struct device * dev)1238 static int xe_pci_runtime_idle(struct device *dev)
1239 {
1240 struct pci_dev *pdev = to_pci_dev(dev);
1241 struct xe_device *xe = pdev_to_xe_device(pdev);
1242
1243 xe_pm_d3cold_allowed_toggle(xe);
1244
1245 return 0;
1246 }
1247
1248 static const struct dev_pm_ops xe_pm_ops = {
1249 SET_SYSTEM_SLEEP_PM_OPS(xe_pci_suspend, xe_pci_resume)
1250 SET_RUNTIME_PM_OPS(xe_pci_runtime_suspend, xe_pci_runtime_resume, xe_pci_runtime_idle)
1251 };
1252 #endif
1253
1254 static struct pci_driver xe_pci_driver = {
1255 .name = DRIVER_NAME,
1256 .id_table = pciidlist,
1257 .probe = xe_pci_probe,
1258 .remove = xe_pci_remove,
1259 .shutdown = xe_pci_shutdown,
1260 .sriov_configure = xe_pci_sriov_configure,
1261 #ifdef CONFIG_PM_SLEEP
1262 .driver.pm = &xe_pm_ops,
1263 #endif
1264 };
1265
1266 /**
1267 * xe_pci_to_pf_device() - Get PF &xe_device.
1268 * @pdev: the VF &pci_dev device
1269 *
1270 * Return: pointer to PF &xe_device, NULL otherwise.
1271 */
xe_pci_to_pf_device(struct pci_dev * pdev)1272 struct xe_device *xe_pci_to_pf_device(struct pci_dev *pdev)
1273 {
1274 struct drm_device *drm;
1275
1276 drm = pci_iov_get_pf_drvdata(pdev, &xe_pci_driver);
1277 if (IS_ERR(drm))
1278 return NULL;
1279
1280 return to_xe_device(drm);
1281 }
1282
xe_register_pci_driver(void)1283 int xe_register_pci_driver(void)
1284 {
1285 return pci_register_driver(&xe_pci_driver);
1286 }
1287
xe_unregister_pci_driver(void)1288 void xe_unregister_pci_driver(void)
1289 {
1290 pci_unregister_driver(&xe_pci_driver);
1291 }
1292
1293 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST)
1294 #include "tests/xe_pci.c"
1295 #endif
1296