xref: /linux/drivers/gpu/drm/renesas/rz-du/rzg2l_du_vsp.h (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * RZ/G2L Display Unit VSP-Based Compositor
4  *
5  * Copyright (C) 2023 Renesas Electronics Corporation
6  *
7  * Based on rcar_du_vsp.h
8  */
9 
10 #ifndef __RZG2L_DU_VSP_H__
11 #define __RZG2L_DU_VSP_H__
12 
13 #include <drm/drm_plane.h>
14 #include <linux/container_of.h>
15 #include <linux/scatterlist.h>
16 
17 struct device;
18 struct drm_framebuffer;
19 struct rzg2l_du_device;
20 struct rzg2l_du_format_info;
21 struct rzg2l_du_vsp;
22 
23 struct rzg2l_du_vsp_plane {
24 	struct drm_plane plane;
25 	struct rzg2l_du_vsp *vsp;
26 	unsigned int index;
27 };
28 
29 struct rzg2l_du_vsp {
30 	unsigned int index;
31 	struct device *vsp;
32 	struct rzg2l_du_device *dev;
33 };
34 
to_rzg2l_vsp_plane(struct drm_plane * p)35 static inline struct rzg2l_du_vsp_plane *to_rzg2l_vsp_plane(struct drm_plane *p)
36 {
37 	return container_of(p, struct rzg2l_du_vsp_plane, plane);
38 }
39 
40 /**
41  * struct rzg2l_du_vsp_plane_state - Driver-specific plane state
42  * @state: base DRM plane state
43  * @format: information about the pixel format used by the plane
44  */
45 struct rzg2l_du_vsp_plane_state {
46 	struct drm_plane_state state;
47 
48 	const struct rzg2l_du_format_info *format;
49 };
50 
51 static inline struct rzg2l_du_vsp_plane_state *
to_rzg2l_vsp_plane_state(struct drm_plane_state * state)52 to_rzg2l_vsp_plane_state(struct drm_plane_state *state)
53 {
54 	return container_of(state, struct rzg2l_du_vsp_plane_state, state);
55 }
56 
57 #if IS_ENABLED(CONFIG_VIDEO_RENESAS_VSP1)
58 int rzg2l_du_vsp_init(struct rzg2l_du_vsp *vsp, struct device_node *np,
59 		      unsigned int crtcs);
60 void rzg2l_du_vsp_enable(struct rzg2l_du_crtc *crtc);
61 void rzg2l_du_vsp_disable(struct rzg2l_du_crtc *crtc);
62 void rzg2l_du_vsp_atomic_flush(struct rzg2l_du_crtc *crtc);
63 struct drm_plane *rzg2l_du_vsp_get_drm_plane(struct rzg2l_du_crtc *crtc,
64 					     unsigned int pipe_index);
65 #else
rzg2l_du_vsp_init(struct rzg2l_du_vsp * vsp,struct device_node * np,unsigned int crtcs)66 static inline int rzg2l_du_vsp_init(struct rzg2l_du_vsp *vsp, struct device_node *np,
67 				    unsigned int crtcs)
68 {
69 	return -ENXIO;
70 }
71 
rzg2l_du_vsp_enable(struct rzg2l_du_crtc * crtc)72 static inline void rzg2l_du_vsp_enable(struct rzg2l_du_crtc *crtc) { };
rzg2l_du_vsp_disable(struct rzg2l_du_crtc * crtc)73 static inline void rzg2l_du_vsp_disable(struct rzg2l_du_crtc *crtc) { };
rzg2l_du_vsp_atomic_flush(struct rzg2l_du_crtc * crtc)74 static inline void rzg2l_du_vsp_atomic_flush(struct rzg2l_du_crtc *crtc) { };
rzg2l_du_vsp_get_drm_plane(struct rzg2l_du_crtc * crtc,unsigned int pipe_index)75 static inline struct drm_plane *rzg2l_du_vsp_get_drm_plane(struct rzg2l_du_crtc *crtc,
76 							   unsigned int pipe_index)
77 {
78 	return ERR_PTR(-ENXIO);
79 }
80 #endif
81 
82 #endif /* __RZG2L_DU_VSP_H__ */
83