1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * ALSA SoC Audio Layer - Rockchip SAI Controller driver 4 * 5 * Copyright (c) 2022 Rockchip Electronics Co. Ltd. 6 * Copyright (c) 2025 Collabora Ltd. 7 */ 8 9 #include <linux/module.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/delay.h> 12 #include <linux/of_device.h> 13 #include <linux/clk.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 #include <linux/spinlock.h> 19 #include <sound/pcm_params.h> 20 #include <sound/dmaengine_pcm.h> 21 #include <sound/tlv.h> 22 23 #include "rockchip_sai.h" 24 25 #define DRV_NAME "rockchip-sai" 26 27 #define CLK_SHIFT_RATE_HZ_MAX 5 28 #define FW_RATIO_MAX 8 29 #define FW_RATIO_MIN 1 30 #define MAXBURST_PER_FIFO 8 31 32 #define TIMEOUT_US 1000 33 #define WAIT_TIME_MS_MAX 10000 34 35 #define MAX_LANES 4 36 37 enum fpw_mode { 38 FPW_ONE_BCLK_WIDTH, 39 FPW_ONE_SLOT_WIDTH, 40 FPW_HALF_FRAME_WIDTH, 41 }; 42 43 struct rk_sai_dev { 44 struct device *dev; 45 struct clk *hclk; 46 struct clk *mclk; 47 struct regmap *regmap; 48 struct reset_control *rst_h; 49 struct reset_control *rst_m; 50 struct snd_dmaengine_dai_dma_data capture_dma_data; 51 struct snd_dmaengine_dai_dma_data playback_dma_data; 52 struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1]; 53 unsigned int mclk_rate; 54 unsigned int wait_time[SNDRV_PCM_STREAM_LAST + 1]; 55 unsigned int tx_lanes; 56 unsigned int rx_lanes; 57 unsigned int sdi[MAX_LANES]; 58 unsigned int sdo[MAX_LANES]; 59 unsigned int version; 60 enum fpw_mode fpw; 61 int fw_ratio; 62 bool has_capture; 63 bool has_playback; 64 bool is_master_mode; 65 bool is_tdm; 66 bool initialized; 67 /* protects register writes that depend on the state of XFER[1:0] */ 68 spinlock_t xfer_lock; 69 }; 70 71 static bool rockchip_sai_stream_valid(struct snd_pcm_substream *substream, 72 struct snd_soc_dai *dai) 73 { 74 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 75 76 if (!substream) 77 return false; 78 79 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK && 80 sai->has_playback) 81 return true; 82 83 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE && 84 sai->has_capture) 85 return true; 86 87 return false; 88 } 89 90 static int rockchip_sai_fsync_lost_detect(struct rk_sai_dev *sai, bool en) 91 { 92 unsigned int fw, cnt; 93 94 if (sai->is_master_mode || sai->version < SAI_VER_2311) 95 return 0; 96 97 regmap_read(sai->regmap, SAI_FSCR, &fw); 98 cnt = SAI_FSCR_FW_V(fw) << 1; /* two fsync lost */ 99 100 regmap_update_bits(sai->regmap, SAI_INTCR, 101 SAI_INTCR_FSLOSTC, SAI_INTCR_FSLOSTC); 102 regmap_update_bits(sai->regmap, SAI_INTCR, 103 SAI_INTCR_FSLOST_MASK, 104 SAI_INTCR_FSLOST(en)); 105 /* 106 * The `cnt` is the number of SCLK cycles of the CRU's SCLK signal that 107 * should be used as timeout. Consequently, in slave mode, this value 108 * is only correct if the CRU SCLK is equal to the external SCLK. 109 */ 110 regmap_update_bits(sai->regmap, SAI_FS_TIMEOUT, 111 SAI_FS_TIMEOUT_VAL_MASK | SAI_FS_TIMEOUT_EN_MASK, 112 SAI_FS_TIMEOUT_VAL(cnt) | SAI_FS_TIMEOUT_EN(en)); 113 114 return 0; 115 } 116 117 static int rockchip_sai_fsync_err_detect(struct rk_sai_dev *sai, 118 bool en) 119 { 120 if (sai->is_master_mode || sai->version < SAI_VER_2311) 121 return 0; 122 123 regmap_update_bits(sai->regmap, SAI_INTCR, 124 SAI_INTCR_FSERRC, SAI_INTCR_FSERRC); 125 regmap_update_bits(sai->regmap, SAI_INTCR, 126 SAI_INTCR_FSERR_MASK, 127 SAI_INTCR_FSERR(en)); 128 129 return 0; 130 } 131 132 static int rockchip_sai_poll_clk_idle(struct rk_sai_dev *sai) 133 { 134 unsigned int reg, idle, val; 135 int ret; 136 137 if (sai->version >= SAI_VER_2307) { 138 reg = SAI_STATUS; 139 idle = SAI_STATUS_FS_IDLE; 140 idle = sai->version >= SAI_VER_2311 ? idle >> 1 : idle; 141 } else { 142 reg = SAI_XFER; 143 idle = SAI_XFER_FS_IDLE; 144 } 145 146 ret = regmap_read_poll_timeout_atomic(sai->regmap, reg, val, 147 (val & idle), 10, TIMEOUT_US); 148 if (ret < 0) 149 dev_warn(sai->dev, "Failed to idle FS\n"); 150 151 return ret; 152 } 153 154 static int rockchip_sai_poll_stream_idle(struct rk_sai_dev *sai, bool playback, bool capture) 155 { 156 unsigned int reg, val; 157 unsigned int idle = 0; 158 int ret; 159 160 if (sai->version >= SAI_VER_2307) { 161 reg = SAI_STATUS; 162 if (playback) 163 idle |= SAI_STATUS_TX_IDLE; 164 if (capture) 165 idle |= SAI_STATUS_RX_IDLE; 166 idle = sai->version >= SAI_VER_2311 ? idle >> 1 : idle; 167 } else { 168 reg = SAI_XFER; 169 if (playback) 170 idle |= SAI_XFER_TX_IDLE; 171 if (capture) 172 idle |= SAI_XFER_RX_IDLE; 173 } 174 175 ret = regmap_read_poll_timeout_atomic(sai->regmap, reg, val, 176 (val & idle), 10, TIMEOUT_US); 177 if (ret < 0) 178 dev_warn(sai->dev, "Failed to idle stream\n"); 179 180 return ret; 181 } 182 183 /** 184 * rockchip_sai_xfer_clk_stop_and_wait() - stop the xfer clock and wait for it to be idle 185 * @sai: pointer to the driver instance's rk_sai_dev struct 186 * @to_restore: pointer to store the CLK/FSS register values in as they were 187 * found before they were cleared, or NULL. 188 * 189 * Clear the XFER_CLK and XFER_FSS registers if needed, then busy-waits for the 190 * XFER clocks to be idle. Before clearing the bits, it stores the state of the 191 * registers as it encountered them in to_restore if it isn't NULL. 192 * 193 * Context: Any context. Expects sai->xfer_lock to be held by caller. 194 */ 195 static void rockchip_sai_xfer_clk_stop_and_wait(struct rk_sai_dev *sai, unsigned int *to_restore) 196 { 197 unsigned int mask = SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK; 198 unsigned int disable = SAI_XFER_CLK_DIS | SAI_XFER_FSS_DIS; 199 unsigned int val; 200 201 assert_spin_locked(&sai->xfer_lock); 202 203 regmap_read(sai->regmap, SAI_XFER, &val); 204 if ((val & mask) == disable) 205 goto wait_for_idle; 206 207 if (sai->is_master_mode) 208 regmap_update_bits(sai->regmap, SAI_XFER, mask, disable); 209 210 wait_for_idle: 211 rockchip_sai_poll_clk_idle(sai); 212 213 if (to_restore) 214 *to_restore = val; 215 } 216 217 static int rockchip_sai_runtime_suspend(struct device *dev) 218 { 219 struct rk_sai_dev *sai = dev_get_drvdata(dev); 220 unsigned long flags; 221 222 rockchip_sai_fsync_lost_detect(sai, 0); 223 rockchip_sai_fsync_err_detect(sai, 0); 224 225 spin_lock_irqsave(&sai->xfer_lock, flags); 226 rockchip_sai_xfer_clk_stop_and_wait(sai, NULL); 227 spin_unlock_irqrestore(&sai->xfer_lock, flags); 228 229 regcache_cache_only(sai->regmap, true); 230 /* 231 * After FS is idle, we should wait at least 2 BCLK cycles to make sure 232 * the CLK gate operation has completed, and only then disable mclk. 233 * 234 * Otherwise, the BCLK is still ungated, and once the mclk is enabled, 235 * there is a risk that a few BCLK cycles leak. This is true especially 236 * at low speeds, such as with a samplerate of 8k. 237 * 238 * Ideally we'd adjust the delay based on the samplerate, but it's such 239 * a tiny value that we can just delay for the maximum clock period 240 * for the sake of simplicity. 241 * 242 * The maximum BCLK period is 31us @ 8K-8Bit (64kHz BCLK). We wait for 243 * 40us to give ourselves a safety margin in case udelay falls short. 244 */ 245 udelay(40); 246 clk_disable_unprepare(sai->mclk); 247 clk_disable_unprepare(sai->hclk); 248 249 return 0; 250 } 251 252 static int rockchip_sai_runtime_resume(struct device *dev) 253 { 254 struct rk_sai_dev *sai = dev_get_drvdata(dev); 255 int ret; 256 257 ret = clk_prepare_enable(sai->hclk); 258 if (ret) 259 goto err_hclk; 260 261 ret = clk_prepare_enable(sai->mclk); 262 if (ret) 263 goto err_mclk; 264 265 regcache_cache_only(sai->regmap, false); 266 regcache_mark_dirty(sai->regmap); 267 ret = regcache_sync(sai->regmap); 268 if (ret) 269 goto err_regmap; 270 271 return 0; 272 273 err_regmap: 274 clk_disable_unprepare(sai->mclk); 275 err_mclk: 276 clk_disable_unprepare(sai->hclk); 277 err_hclk: 278 return ret; 279 } 280 281 static void rockchip_sai_fifo_xrun_detect(struct rk_sai_dev *sai, 282 int stream, bool en) 283 { 284 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 285 /* clear irq status which was asserted before TXUIE enabled */ 286 regmap_update_bits(sai->regmap, SAI_INTCR, 287 SAI_INTCR_TXUIC, SAI_INTCR_TXUIC); 288 regmap_update_bits(sai->regmap, SAI_INTCR, 289 SAI_INTCR_TXUIE_MASK, 290 SAI_INTCR_TXUIE(en)); 291 } else { 292 /* clear irq status which was asserted before RXOIE enabled */ 293 regmap_update_bits(sai->regmap, SAI_INTCR, 294 SAI_INTCR_RXOIC, SAI_INTCR_RXOIC); 295 regmap_update_bits(sai->regmap, SAI_INTCR, 296 SAI_INTCR_RXOIE_MASK, 297 SAI_INTCR_RXOIE(en)); 298 } 299 } 300 301 static void rockchip_sai_dma_ctrl(struct rk_sai_dev *sai, 302 int stream, bool en) 303 { 304 if (!en) 305 rockchip_sai_fifo_xrun_detect(sai, stream, 0); 306 307 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 308 regmap_update_bits(sai->regmap, SAI_DMACR, 309 SAI_DMACR_TDE_MASK, 310 SAI_DMACR_TDE(en)); 311 } else { 312 regmap_update_bits(sai->regmap, SAI_DMACR, 313 SAI_DMACR_RDE_MASK, 314 SAI_DMACR_RDE(en)); 315 } 316 317 if (en) 318 rockchip_sai_fifo_xrun_detect(sai, stream, 1); 319 } 320 321 static void rockchip_sai_reset(struct rk_sai_dev *sai) 322 { 323 /* 324 * It is advised to reset the hclk domain before resetting the mclk 325 * domain, especially in slave mode without a clock input. 326 * 327 * To deal with the aforementioned case of slave mode without a clock 328 * input, we work around a potential issue by resetting the whole 329 * controller, bringing it back into master mode, and then recovering 330 * the controller configuration in the regmap. 331 */ 332 reset_control_assert(sai->rst_h); 333 udelay(10); 334 reset_control_deassert(sai->rst_h); 335 udelay(10); 336 reset_control_assert(sai->rst_m); 337 udelay(10); 338 reset_control_deassert(sai->rst_m); 339 udelay(10); 340 341 /* recover regmap config */ 342 regcache_mark_dirty(sai->regmap); 343 regcache_sync(sai->regmap); 344 } 345 346 static int rockchip_sai_clear(struct rk_sai_dev *sai, unsigned int clr) 347 { 348 unsigned int val = 0; 349 int ret = 0; 350 351 regmap_update_bits(sai->regmap, SAI_CLR, clr, clr); 352 ret = regmap_read_poll_timeout_atomic(sai->regmap, SAI_CLR, val, 353 !(val & clr), 10, TIMEOUT_US); 354 if (ret < 0) { 355 dev_warn(sai->dev, "Failed to clear %u\n", clr); 356 rockchip_sai_reset(sai); 357 } 358 359 return ret; 360 } 361 362 static void rockchip_sai_xfer_start(struct rk_sai_dev *sai, int stream) 363 { 364 unsigned int msk, val; 365 366 if (stream == SNDRV_PCM_STREAM_PLAYBACK) { 367 msk = SAI_XFER_TXS_MASK; 368 val = SAI_XFER_TXS_EN; 369 370 } else { 371 msk = SAI_XFER_RXS_MASK; 372 val = SAI_XFER_RXS_EN; 373 } 374 375 regmap_update_bits(sai->regmap, SAI_XFER, msk, val); 376 } 377 378 static void rockchip_sai_xfer_stop(struct rk_sai_dev *sai, int stream) 379 { 380 unsigned int msk = 0, val = 0, clr = 0; 381 bool capture = stream == SNDRV_PCM_STREAM_CAPTURE || stream < 0; 382 bool playback = stream == SNDRV_PCM_STREAM_PLAYBACK || stream < 0; 383 /* could be <= 0 but we don't want to depend on enum values */ 384 385 if (playback) { 386 msk |= SAI_XFER_TXS_MASK; 387 val |= SAI_XFER_TXS_DIS; 388 clr |= SAI_CLR_TXC; 389 } 390 if (capture) { 391 msk |= SAI_XFER_RXS_MASK; 392 val |= SAI_XFER_RXS_DIS; 393 clr |= SAI_CLR_RXC; 394 } 395 396 regmap_update_bits(sai->regmap, SAI_XFER, msk, val); 397 rockchip_sai_poll_stream_idle(sai, playback, capture); 398 399 rockchip_sai_clear(sai, clr); 400 } 401 402 static void rockchip_sai_start(struct rk_sai_dev *sai, int stream) 403 { 404 rockchip_sai_dma_ctrl(sai, stream, 1); 405 rockchip_sai_xfer_start(sai, stream); 406 } 407 408 static void rockchip_sai_stop(struct rk_sai_dev *sai, int stream) 409 { 410 rockchip_sai_dma_ctrl(sai, stream, 0); 411 rockchip_sai_xfer_stop(sai, stream); 412 } 413 414 static void rockchip_sai_fmt_create(struct rk_sai_dev *sai, unsigned int fmt) 415 { 416 unsigned int xcr_mask = 0, xcr_val = 0, xsft_mask = 0, xsft_val = 0; 417 unsigned int fscr_mask = 0, fscr_val = 0; 418 419 assert_spin_locked(&sai->xfer_lock); 420 421 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 422 case SND_SOC_DAIFMT_RIGHT_J: 423 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK; 424 xcr_val = SAI_XCR_VDJ_R | SAI_XCR_EDGE_SHIFT_0; 425 xsft_mask = SAI_XSHIFT_RIGHT_MASK; 426 xsft_val = SAI_XSHIFT_RIGHT(0); 427 fscr_mask = SAI_FSCR_EDGE_MASK; 428 fscr_val = SAI_FSCR_EDGE_DUAL; 429 sai->fpw = FPW_HALF_FRAME_WIDTH; 430 break; 431 case SND_SOC_DAIFMT_LEFT_J: 432 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK; 433 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0; 434 xsft_mask = SAI_XSHIFT_RIGHT_MASK; 435 xsft_val = SAI_XSHIFT_RIGHT(0); 436 fscr_mask = SAI_FSCR_EDGE_MASK; 437 fscr_val = SAI_FSCR_EDGE_DUAL; 438 sai->fpw = FPW_HALF_FRAME_WIDTH; 439 break; 440 case SND_SOC_DAIFMT_I2S: 441 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK; 442 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_1; 443 xsft_mask = SAI_XSHIFT_RIGHT_MASK; 444 if (sai->is_tdm) 445 xsft_val = SAI_XSHIFT_RIGHT(1); 446 else 447 xsft_val = SAI_XSHIFT_RIGHT(2); 448 fscr_mask = SAI_FSCR_EDGE_MASK; 449 fscr_val = SAI_FSCR_EDGE_DUAL; 450 sai->fpw = FPW_HALF_FRAME_WIDTH; 451 break; 452 case SND_SOC_DAIFMT_DSP_A: 453 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK; 454 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0; 455 xsft_mask = SAI_XSHIFT_RIGHT_MASK; 456 xsft_val = SAI_XSHIFT_RIGHT(2); 457 fscr_mask = SAI_FSCR_EDGE_MASK; 458 fscr_val = SAI_FSCR_EDGE_RISING; 459 sai->fpw = FPW_ONE_BCLK_WIDTH; 460 break; 461 case SND_SOC_DAIFMT_DSP_B: 462 xcr_mask = SAI_XCR_VDJ_MASK | SAI_XCR_EDGE_SHIFT_MASK; 463 xcr_val = SAI_XCR_VDJ_L | SAI_XCR_EDGE_SHIFT_0; 464 xsft_mask = SAI_XSHIFT_RIGHT_MASK; 465 xsft_val = SAI_XSHIFT_RIGHT(0); 466 fscr_mask = SAI_FSCR_EDGE_MASK; 467 fscr_val = SAI_FSCR_EDGE_RISING; 468 sai->fpw = FPW_ONE_BCLK_WIDTH; 469 break; 470 default: 471 dev_err(sai->dev, "Unsupported fmt %u\n", fmt); 472 break; 473 } 474 475 regmap_update_bits(sai->regmap, SAI_TXCR, xcr_mask, xcr_val); 476 regmap_update_bits(sai->regmap, SAI_RXCR, xcr_mask, xcr_val); 477 regmap_update_bits(sai->regmap, SAI_TX_SHIFT, xsft_mask, xsft_val); 478 regmap_update_bits(sai->regmap, SAI_RX_SHIFT, xsft_mask, xsft_val); 479 regmap_update_bits(sai->regmap, SAI_FSCR, fscr_mask, fscr_val); 480 } 481 482 static int rockchip_sai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 483 { 484 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 485 unsigned int mask = 0, val = 0; 486 unsigned int clk_gates; 487 unsigned long flags; 488 int ret = 0; 489 490 ret = pm_runtime_resume_and_get(dai->dev); 491 if (ret) 492 return ret; 493 494 mask = SAI_CKR_MSS_MASK; 495 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 496 case SND_SOC_DAIFMT_BP_FP: 497 val = SAI_CKR_MSS_MASTER; 498 sai->is_master_mode = true; 499 break; 500 case SND_SOC_DAIFMT_BC_FC: 501 val = SAI_CKR_MSS_SLAVE; 502 sai->is_master_mode = false; 503 break; 504 default: 505 ret = -EINVAL; 506 goto err_pm_put; 507 } 508 509 spin_lock_irqsave(&sai->xfer_lock, flags); 510 rockchip_sai_xfer_clk_stop_and_wait(sai, &clk_gates); 511 if (sai->initialized) { 512 if (sai->has_capture && sai->has_playback) 513 rockchip_sai_xfer_stop(sai, -1); 514 else if (sai->has_capture) 515 rockchip_sai_xfer_stop(sai, SNDRV_PCM_STREAM_CAPTURE); 516 else 517 rockchip_sai_xfer_stop(sai, SNDRV_PCM_STREAM_PLAYBACK); 518 } else { 519 rockchip_sai_clear(sai, 0); 520 sai->initialized = true; 521 } 522 523 regmap_update_bits(sai->regmap, SAI_CKR, mask, val); 524 525 mask = SAI_CKR_CKP_MASK | SAI_CKR_FSP_MASK; 526 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 527 case SND_SOC_DAIFMT_NB_NF: 528 val = SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_NORMAL; 529 break; 530 case SND_SOC_DAIFMT_NB_IF: 531 val = SAI_CKR_CKP_NORMAL | SAI_CKR_FSP_INVERTED; 532 break; 533 case SND_SOC_DAIFMT_IB_NF: 534 val = SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_NORMAL; 535 break; 536 case SND_SOC_DAIFMT_IB_IF: 537 val = SAI_CKR_CKP_INVERTED | SAI_CKR_FSP_INVERTED; 538 break; 539 default: 540 ret = -EINVAL; 541 goto err_xfer_unlock; 542 } 543 544 regmap_update_bits(sai->regmap, SAI_CKR, mask, val); 545 546 rockchip_sai_fmt_create(sai, fmt); 547 548 err_xfer_unlock: 549 if (clk_gates) 550 regmap_update_bits(sai->regmap, SAI_XFER, 551 SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK, 552 clk_gates); 553 spin_unlock_irqrestore(&sai->xfer_lock, flags); 554 err_pm_put: 555 pm_runtime_put(dai->dev); 556 557 return ret; 558 } 559 560 static int rockchip_sai_hw_params(struct snd_pcm_substream *substream, 561 struct snd_pcm_hw_params *params, 562 struct snd_soc_dai *dai) 563 { 564 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 565 struct snd_dmaengine_dai_dma_data *dma_data; 566 unsigned int mclk_rate, mclk_req_rate, bclk_rate, div_bclk; 567 unsigned int ch_per_lane, slot_width; 568 unsigned int val, fscr, reg; 569 unsigned int lanes, req_lanes; 570 unsigned long flags; 571 int ret = 0; 572 573 if (!rockchip_sai_stream_valid(substream, dai)) 574 return 0; 575 576 dma_data = snd_soc_dai_get_dma_data(dai, substream); 577 dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2; 578 579 pm_runtime_get_sync(sai->dev); 580 581 regmap_read(sai->regmap, SAI_DMACR, &val); 582 583 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 584 reg = SAI_TXCR; 585 lanes = sai->tx_lanes; 586 } else { 587 reg = SAI_RXCR; 588 lanes = sai->rx_lanes; 589 } 590 591 if (!sai->is_tdm) { 592 req_lanes = DIV_ROUND_UP(params_channels(params), 2); 593 if (lanes < req_lanes) { 594 dev_err(sai->dev, "not enough lanes (%d) for requested number of %s channels (%d)\n", 595 lanes, reg == SAI_TXCR ? "playback" : "capture", 596 params_channels(params)); 597 ret = -EINVAL; 598 goto err_pm_put; 599 } else { 600 lanes = req_lanes; 601 } 602 } 603 604 dev_dbg(sai->dev, "using %d lanes totalling %d%s channels for %s\n", 605 lanes, params_channels(params), sai->is_tdm ? " (TDM)" : "", 606 reg == SAI_TXCR ? "playback" : "capture"); 607 608 switch (params_format(params)) { 609 case SNDRV_PCM_FORMAT_S8: 610 case SNDRV_PCM_FORMAT_U8: 611 val = SAI_XCR_VDW(8); 612 break; 613 case SNDRV_PCM_FORMAT_S16_LE: 614 val = SAI_XCR_VDW(16); 615 break; 616 case SNDRV_PCM_FORMAT_S24_LE: 617 val = SAI_XCR_VDW(24); 618 break; 619 case SNDRV_PCM_FORMAT_S32_LE: 620 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: 621 val = SAI_XCR_VDW(32); 622 break; 623 default: 624 ret = -EINVAL; 625 goto err_pm_put; 626 } 627 628 val |= SAI_XCR_CSR(lanes); 629 630 spin_lock_irqsave(&sai->xfer_lock, flags); 631 632 regmap_update_bits(sai->regmap, reg, SAI_XCR_VDW_MASK | SAI_XCR_CSR_MASK, val); 633 634 if (!sai->is_tdm) 635 regmap_update_bits(sai->regmap, reg, SAI_XCR_SBW_MASK, 636 SAI_XCR_SBW(params_physical_width(params))); 637 638 regmap_read(sai->regmap, reg, &val); 639 640 slot_width = SAI_XCR_SBW_V(val); 641 ch_per_lane = params_channels(params) / lanes; 642 643 regmap_update_bits(sai->regmap, reg, SAI_XCR_SNB_MASK, 644 SAI_XCR_SNB(ch_per_lane)); 645 646 fscr = SAI_FSCR_FW(sai->fw_ratio * slot_width * ch_per_lane); 647 648 switch (sai->fpw) { 649 case FPW_ONE_BCLK_WIDTH: 650 fscr |= SAI_FSCR_FPW(1); 651 break; 652 case FPW_ONE_SLOT_WIDTH: 653 fscr |= SAI_FSCR_FPW(slot_width); 654 break; 655 case FPW_HALF_FRAME_WIDTH: 656 fscr |= SAI_FSCR_FPW(sai->fw_ratio * slot_width * ch_per_lane / 2); 657 break; 658 default: 659 dev_err(sai->dev, "Invalid Frame Pulse Width %d\n", sai->fpw); 660 ret = -EINVAL; 661 goto err_xfer_unlock; 662 } 663 664 regmap_update_bits(sai->regmap, SAI_FSCR, 665 SAI_FSCR_FW_MASK | SAI_FSCR_FPW_MASK, fscr); 666 667 if (sai->is_master_mode) { 668 bclk_rate = sai->fw_ratio * slot_width * ch_per_lane * params_rate(params); 669 ret = clk_set_rate(sai->mclk, sai->mclk_rate); 670 if (ret) { 671 dev_err(sai->dev, "Failed to set mclk to %u: %pe\n", 672 sai->mclk_rate, ERR_PTR(ret)); 673 goto err_xfer_unlock; 674 } 675 676 mclk_rate = clk_get_rate(sai->mclk); 677 if (mclk_rate < bclk_rate) { 678 dev_err(sai->dev, "Mismatch mclk: %u, at least %u\n", 679 mclk_rate, bclk_rate); 680 ret = -EINVAL; 681 goto err_xfer_unlock; 682 } 683 684 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); 685 mclk_req_rate = bclk_rate * div_bclk; 686 687 if (mclk_rate < mclk_req_rate - CLK_SHIFT_RATE_HZ_MAX || 688 mclk_rate > mclk_req_rate + CLK_SHIFT_RATE_HZ_MAX) { 689 dev_err(sai->dev, "Mismatch mclk: %u, expected %u (+/- %dHz)\n", 690 mclk_rate, mclk_req_rate, CLK_SHIFT_RATE_HZ_MAX); 691 ret = -EINVAL; 692 goto err_xfer_unlock; 693 } 694 695 regmap_update_bits(sai->regmap, SAI_CKR, SAI_CKR_MDIV_MASK, 696 SAI_CKR_MDIV(div_bclk)); 697 } 698 699 err_xfer_unlock: 700 spin_unlock_irqrestore(&sai->xfer_lock, flags); 701 err_pm_put: 702 pm_runtime_put(sai->dev); 703 704 return ret; 705 } 706 707 static int rockchip_sai_prepare(struct snd_pcm_substream *substream, 708 struct snd_soc_dai *dai) 709 { 710 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 711 unsigned long flags; 712 713 if (!rockchip_sai_stream_valid(substream, dai)) 714 return 0; 715 716 if (sai->is_master_mode) { 717 /* 718 * We should wait for the first BCLK pulse to have definitely 719 * occurred after any DIV settings have potentially been 720 * changed in order to guarantee a clean clock signal once we 721 * ungate the clock. 722 * 723 * Ideally, this would be done depending on the samplerate, but 724 * for the sake of simplicity, we'll just delay for the maximum 725 * possible clock offset time, which is quite a small value. 726 * 727 * The maximum BCLK offset is 15.6us @ 8K-8Bit (64kHz BCLK). We 728 * wait for 20us in order to give us a safety margin in case 729 * udelay falls short. 730 */ 731 udelay(20); 732 spin_lock_irqsave(&sai->xfer_lock, flags); 733 regmap_update_bits(sai->regmap, SAI_XFER, 734 SAI_XFER_CLK_MASK | 735 SAI_XFER_FSS_MASK, 736 SAI_XFER_CLK_EN | 737 SAI_XFER_FSS_EN); 738 spin_unlock_irqrestore(&sai->xfer_lock, flags); 739 } 740 741 rockchip_sai_fsync_lost_detect(sai, 1); 742 rockchip_sai_fsync_err_detect(sai, 1); 743 744 return 0; 745 } 746 747 static void rockchip_sai_path_config(struct rk_sai_dev *sai, 748 int num, bool is_rx) 749 { 750 int i; 751 752 if (is_rx) 753 for (i = 0; i < num; i++) 754 regmap_update_bits(sai->regmap, SAI_PATH_SEL, 755 SAI_RX_PATH_MASK(i), 756 SAI_RX_PATH(i, sai->sdi[i])); 757 else 758 for (i = 0; i < num; i++) 759 regmap_update_bits(sai->regmap, SAI_PATH_SEL, 760 SAI_TX_PATH_MASK(i), 761 SAI_TX_PATH(i, sai->sdo[i])); 762 } 763 764 static int rockchip_sai_path_prepare(struct rk_sai_dev *sai, 765 struct device_node *np, 766 bool is_rx) 767 { 768 const char *path_prop; 769 unsigned int *data; 770 unsigned int *lanes; 771 int i, num, ret; 772 773 if (is_rx) { 774 path_prop = "rockchip,sai-rx-route"; 775 data = sai->sdi; 776 lanes = &sai->rx_lanes; 777 } else { 778 path_prop = "rockchip,sai-tx-route"; 779 data = sai->sdo; 780 lanes = &sai->tx_lanes; 781 } 782 783 num = of_count_phandle_with_args(np, path_prop, NULL); 784 if (num == -ENOENT) { 785 return 0; 786 } else if (num > MAX_LANES || num == 0) { 787 dev_err(sai->dev, "found %d entries in %s, outside of range 1 to %d\n", 788 num, path_prop, MAX_LANES); 789 return -EINVAL; 790 } else if (num < 0) { 791 dev_err(sai->dev, "error in %s property: %pe\n", path_prop, 792 ERR_PTR(num)); 793 return num; 794 } 795 796 *lanes = num; 797 ret = device_property_read_u32_array(sai->dev, path_prop, data, num); 798 if (ret < 0) { 799 dev_err(sai->dev, "failed to read property '%s': %pe\n", 800 path_prop, ERR_PTR(ret)); 801 return ret; 802 } 803 804 for (i = 0; i < num; i++) { 805 if (data[i] >= MAX_LANES) { 806 dev_err(sai->dev, "%s[%d] is %d, should be less than %d\n", 807 path_prop, i, data[i], MAX_LANES); 808 return -EINVAL; 809 } 810 } 811 812 rockchip_sai_path_config(sai, num, is_rx); 813 814 return 0; 815 } 816 817 static int rockchip_sai_parse_paths(struct rk_sai_dev *sai, 818 struct device_node *np) 819 { 820 int ret; 821 822 if (sai->has_playback) { 823 sai->tx_lanes = 1; 824 ret = rockchip_sai_path_prepare(sai, np, false); 825 if (ret < 0) { 826 dev_err(sai->dev, "Failed to prepare TX path: %pe\n", 827 ERR_PTR(ret)); 828 return ret; 829 } 830 } 831 832 if (sai->has_capture) { 833 sai->rx_lanes = 1; 834 ret = rockchip_sai_path_prepare(sai, np, true); 835 if (ret < 0) { 836 dev_err(sai->dev, "Failed to prepare RX path: %pe\n", 837 ERR_PTR(ret)); 838 return ret; 839 } 840 } 841 842 return 0; 843 } 844 845 static int rockchip_sai_trigger(struct snd_pcm_substream *substream, 846 int cmd, struct snd_soc_dai *dai) 847 { 848 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 849 int ret = 0; 850 851 if (!rockchip_sai_stream_valid(substream, dai)) 852 return 0; 853 854 switch (cmd) { 855 case SNDRV_PCM_TRIGGER_START: 856 case SNDRV_PCM_TRIGGER_RESUME: 857 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 858 rockchip_sai_start(sai, substream->stream); 859 break; 860 case SNDRV_PCM_TRIGGER_SUSPEND: 861 case SNDRV_PCM_TRIGGER_STOP: 862 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 863 rockchip_sai_stop(sai, substream->stream); 864 break; 865 default: 866 ret = -EINVAL; 867 break; 868 } 869 870 return ret; 871 } 872 873 874 static int rockchip_sai_dai_probe(struct snd_soc_dai *dai) 875 { 876 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 877 878 snd_soc_dai_init_dma_data(dai, 879 sai->has_playback ? &sai->playback_dma_data : NULL, 880 sai->has_capture ? &sai->capture_dma_data : NULL); 881 882 return 0; 883 } 884 885 static int rockchip_sai_startup(struct snd_pcm_substream *substream, 886 struct snd_soc_dai *dai) 887 { 888 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 889 int stream = substream->stream; 890 891 if (!rockchip_sai_stream_valid(substream, dai)) 892 return 0; 893 894 if (sai->substreams[stream]) 895 return -EBUSY; 896 897 if (sai->wait_time[stream]) 898 substream->wait_time = sai->wait_time[stream]; 899 900 sai->substreams[stream] = substream; 901 902 return 0; 903 } 904 905 static void rockchip_sai_shutdown(struct snd_pcm_substream *substream, 906 struct snd_soc_dai *dai) 907 { 908 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 909 910 if (!rockchip_sai_stream_valid(substream, dai)) 911 return; 912 913 sai->substreams[substream->stream] = NULL; 914 } 915 916 static int rockchip_sai_set_tdm_slot(struct snd_soc_dai *dai, 917 unsigned int tx_mask, unsigned int rx_mask, 918 int slots, int slot_width) 919 { 920 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 921 unsigned long flags; 922 unsigned int clk_gates; 923 int sw = slot_width; 924 925 if (!slots) { 926 /* Disabling TDM, set slot width back to 32 bits */ 927 sai->is_tdm = false; 928 sw = 32; 929 } else { 930 sai->is_tdm = true; 931 } 932 933 if (sw < 16 || sw > 32) 934 return -EINVAL; 935 936 pm_runtime_get_sync(dai->dev); 937 spin_lock_irqsave(&sai->xfer_lock, flags); 938 rockchip_sai_xfer_clk_stop_and_wait(sai, &clk_gates); 939 regmap_update_bits(sai->regmap, SAI_TXCR, SAI_XCR_SBW_MASK, 940 SAI_XCR_SBW(sw)); 941 regmap_update_bits(sai->regmap, SAI_RXCR, SAI_XCR_SBW_MASK, 942 SAI_XCR_SBW(sw)); 943 regmap_update_bits(sai->regmap, SAI_XFER, 944 SAI_XFER_CLK_MASK | SAI_XFER_FSS_MASK, 945 clk_gates); 946 spin_unlock_irqrestore(&sai->xfer_lock, flags); 947 pm_runtime_put(dai->dev); 948 949 return 0; 950 } 951 952 static int rockchip_sai_set_sysclk(struct snd_soc_dai *dai, int stream, 953 unsigned int freq, int dir) 954 { 955 struct rk_sai_dev *sai = snd_soc_dai_get_drvdata(dai); 956 957 sai->mclk_rate = freq; 958 959 return 0; 960 } 961 962 static const u64 rockchip_sai_selectable_formats = 963 SND_SOC_POSSIBLE_DAIFMT_I2S | 964 SND_SOC_POSSIBLE_DAIFMT_RIGHT_J | 965 SND_SOC_POSSIBLE_DAIFMT_LEFT_J | 966 SND_SOC_POSSIBLE_DAIFMT_DSP_A | 967 SND_SOC_POSSIBLE_DAIFMT_DSP_B | 968 SND_SOC_POSSIBLE_DAIFMT_NB_NF | 969 SND_SOC_POSSIBLE_DAIFMT_NB_IF | 970 SND_SOC_POSSIBLE_DAIFMT_IB_NF | 971 SND_SOC_POSSIBLE_DAIFMT_IB_IF; 972 973 static const struct snd_soc_dai_ops rockchip_sai_dai_ops = { 974 .probe = rockchip_sai_dai_probe, 975 .startup = rockchip_sai_startup, 976 .shutdown = rockchip_sai_shutdown, 977 .hw_params = rockchip_sai_hw_params, 978 .set_fmt = rockchip_sai_set_fmt, 979 .set_sysclk = rockchip_sai_set_sysclk, 980 .prepare = rockchip_sai_prepare, 981 .trigger = rockchip_sai_trigger, 982 .set_tdm_slot = rockchip_sai_set_tdm_slot, 983 .auto_selectable_formats = &rockchip_sai_selectable_formats, 984 .num_auto_selectable_formats = 1, 985 }; 986 987 static const struct snd_soc_dai_driver rockchip_sai_dai = { 988 .ops = &rockchip_sai_dai_ops, 989 .symmetric_rate = 1, 990 }; 991 992 static bool rockchip_sai_wr_reg(struct device *dev, unsigned int reg) 993 { 994 switch (reg) { 995 case SAI_TXCR: 996 case SAI_FSCR: 997 case SAI_RXCR: 998 case SAI_MONO_CR: 999 case SAI_XFER: 1000 case SAI_CLR: 1001 case SAI_CKR: 1002 case SAI_DMACR: 1003 case SAI_INTCR: 1004 case SAI_TXDR: 1005 case SAI_PATH_SEL: 1006 case SAI_TX_SLOT_MASK0: 1007 case SAI_TX_SLOT_MASK1: 1008 case SAI_TX_SLOT_MASK2: 1009 case SAI_TX_SLOT_MASK3: 1010 case SAI_RX_SLOT_MASK0: 1011 case SAI_RX_SLOT_MASK1: 1012 case SAI_RX_SLOT_MASK2: 1013 case SAI_RX_SLOT_MASK3: 1014 case SAI_TX_SHIFT: 1015 case SAI_RX_SHIFT: 1016 case SAI_FSXN: 1017 case SAI_FS_TIMEOUT: 1018 case SAI_LOOPBACK_LR: 1019 return true; 1020 default: 1021 return false; 1022 } 1023 } 1024 1025 static bool rockchip_sai_rd_reg(struct device *dev, unsigned int reg) 1026 { 1027 switch (reg) { 1028 case SAI_TXCR: 1029 case SAI_FSCR: 1030 case SAI_RXCR: 1031 case SAI_MONO_CR: 1032 case SAI_XFER: 1033 case SAI_CLR: 1034 case SAI_CKR: 1035 case SAI_TXFIFOLR: 1036 case SAI_RXFIFOLR: 1037 case SAI_DMACR: 1038 case SAI_INTCR: 1039 case SAI_INTSR: 1040 case SAI_TXDR: 1041 case SAI_RXDR: 1042 case SAI_PATH_SEL: 1043 case SAI_TX_SLOT_MASK0: 1044 case SAI_TX_SLOT_MASK1: 1045 case SAI_TX_SLOT_MASK2: 1046 case SAI_TX_SLOT_MASK3: 1047 case SAI_RX_SLOT_MASK0: 1048 case SAI_RX_SLOT_MASK1: 1049 case SAI_RX_SLOT_MASK2: 1050 case SAI_RX_SLOT_MASK3: 1051 case SAI_TX_DATA_CNT: 1052 case SAI_RX_DATA_CNT: 1053 case SAI_TX_SHIFT: 1054 case SAI_RX_SHIFT: 1055 case SAI_STATUS: 1056 case SAI_VERSION: 1057 case SAI_FSXN: 1058 case SAI_FS_TIMEOUT: 1059 case SAI_LOOPBACK_LR: 1060 return true; 1061 default: 1062 return false; 1063 } 1064 } 1065 1066 static bool rockchip_sai_volatile_reg(struct device *dev, unsigned int reg) 1067 { 1068 switch (reg) { 1069 case SAI_XFER: 1070 case SAI_INTCR: 1071 case SAI_INTSR: 1072 case SAI_CLR: 1073 case SAI_TXFIFOLR: 1074 case SAI_RXFIFOLR: 1075 case SAI_TXDR: 1076 case SAI_RXDR: 1077 case SAI_TX_DATA_CNT: 1078 case SAI_RX_DATA_CNT: 1079 case SAI_STATUS: 1080 case SAI_VERSION: 1081 return true; 1082 default: 1083 return false; 1084 } 1085 } 1086 1087 static bool rockchip_sai_precious_reg(struct device *dev, unsigned int reg) 1088 { 1089 switch (reg) { 1090 case SAI_RXDR: 1091 return true; 1092 default: 1093 return false; 1094 } 1095 } 1096 1097 static const struct reg_default rockchip_sai_reg_defaults[] = { 1098 { SAI_TXCR, 0x00000bff }, 1099 { SAI_FSCR, 0x0001f03f }, 1100 { SAI_RXCR, 0x00000bff }, 1101 { SAI_PATH_SEL, 0x0000e4e4 }, 1102 }; 1103 1104 static const struct regmap_config rockchip_sai_regmap_config = { 1105 .reg_bits = 32, 1106 .reg_stride = 4, 1107 .val_bits = 32, 1108 .max_register = SAI_LOOPBACK_LR, 1109 .reg_defaults = rockchip_sai_reg_defaults, 1110 .num_reg_defaults = ARRAY_SIZE(rockchip_sai_reg_defaults), 1111 .writeable_reg = rockchip_sai_wr_reg, 1112 .readable_reg = rockchip_sai_rd_reg, 1113 .volatile_reg = rockchip_sai_volatile_reg, 1114 .precious_reg = rockchip_sai_precious_reg, 1115 .cache_type = REGCACHE_FLAT, 1116 }; 1117 1118 static int rockchip_sai_init_dai(struct rk_sai_dev *sai, struct resource *res, 1119 struct snd_soc_dai_driver **dp) 1120 { 1121 struct device_node *node = sai->dev->of_node; 1122 struct snd_soc_dai_driver *dai; 1123 struct property *dma_names; 1124 const char *dma_name; 1125 1126 of_property_for_each_string(node, "dma-names", dma_names, dma_name) { 1127 if (!strcmp(dma_name, "tx")) 1128 sai->has_playback = true; 1129 if (!strcmp(dma_name, "rx")) 1130 sai->has_capture = true; 1131 } 1132 1133 dai = devm_kmemdup(sai->dev, &rockchip_sai_dai, 1134 sizeof(*dai), GFP_KERNEL); 1135 if (!dai) 1136 return -ENOMEM; 1137 1138 if (sai->has_playback) { 1139 dai->playback.stream_name = "Playback"; 1140 dai->playback.channels_min = 1; 1141 dai->playback.channels_max = 512; 1142 dai->playback.rates = SNDRV_PCM_RATE_8000_384000; 1143 dai->playback.formats = SNDRV_PCM_FMTBIT_S8 | 1144 SNDRV_PCM_FMTBIT_S16_LE | 1145 SNDRV_PCM_FMTBIT_S24_LE | 1146 SNDRV_PCM_FMTBIT_S32_LE | 1147 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; 1148 1149 sai->playback_dma_data.addr = res->start + SAI_TXDR; 1150 sai->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1151 sai->playback_dma_data.maxburst = MAXBURST_PER_FIFO; 1152 } 1153 1154 if (sai->has_capture) { 1155 dai->capture.stream_name = "Capture"; 1156 dai->capture.channels_min = 1; 1157 dai->capture.channels_max = 512; 1158 dai->capture.rates = SNDRV_PCM_RATE_8000_384000; 1159 dai->capture.formats = SNDRV_PCM_FMTBIT_S8 | 1160 SNDRV_PCM_FMTBIT_S16_LE | 1161 SNDRV_PCM_FMTBIT_S24_LE | 1162 SNDRV_PCM_FMTBIT_S32_LE | 1163 SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE; 1164 1165 sai->capture_dma_data.addr = res->start + SAI_RXDR; 1166 sai->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1167 sai->capture_dma_data.maxburst = MAXBURST_PER_FIFO; 1168 } 1169 1170 regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_TDL_MASK, 1171 SAI_DMACR_TDL(16)); 1172 regmap_update_bits(sai->regmap, SAI_DMACR, SAI_DMACR_RDL_MASK, 1173 SAI_DMACR_RDL(16)); 1174 1175 if (dp) 1176 *dp = dai; 1177 1178 return 0; 1179 } 1180 1181 static const char * const mono_text[] = { "Disable", "Enable" }; 1182 1183 static DECLARE_TLV_DB_SCALE(rmss_tlv, 0, 128, 0); 1184 1185 static const char * const lplrc_text[] = { "L:MIC R:LP", "L:LP R:MIC" }; 1186 static const char * const lplr_text[] = { "Disable", "Enable" }; 1187 1188 static const char * const lpx_text[] = { 1189 "From SDO0", "From SDO1", "From SDO2", "From SDO3" }; 1190 1191 static const char * const lps_text[] = { "Disable", "Enable" }; 1192 static const char * const sync_out_text[] = { "From CRU", "From IO" }; 1193 static const char * const sync_in_text[] = { "From IO", "From Sync Port" }; 1194 1195 static const char * const rpaths_text[] = { 1196 "From SDI0", "From SDI1", "From SDI2", "From SDI3" }; 1197 1198 static const char * const tpaths_text[] = { 1199 "From PATH0", "From PATH1", "From PATH2", "From PATH3" }; 1200 1201 /* MONO_CR */ 1202 static SOC_ENUM_SINGLE_DECL(rmono_switch, SAI_MONO_CR, 1, mono_text); 1203 static SOC_ENUM_SINGLE_DECL(tmono_switch, SAI_MONO_CR, 0, mono_text); 1204 1205 /* PATH_SEL */ 1206 static SOC_ENUM_SINGLE_DECL(lp3_enum, SAI_PATH_SEL, 28, lpx_text); 1207 static SOC_ENUM_SINGLE_DECL(lp2_enum, SAI_PATH_SEL, 26, lpx_text); 1208 static SOC_ENUM_SINGLE_DECL(lp1_enum, SAI_PATH_SEL, 24, lpx_text); 1209 static SOC_ENUM_SINGLE_DECL(lp0_enum, SAI_PATH_SEL, 22, lpx_text); 1210 static SOC_ENUM_SINGLE_DECL(lp3_switch, SAI_PATH_SEL, 21, lps_text); 1211 static SOC_ENUM_SINGLE_DECL(lp2_switch, SAI_PATH_SEL, 20, lps_text); 1212 static SOC_ENUM_SINGLE_DECL(lp1_switch, SAI_PATH_SEL, 19, lps_text); 1213 static SOC_ENUM_SINGLE_DECL(lp0_switch, SAI_PATH_SEL, 18, lps_text); 1214 static SOC_ENUM_SINGLE_DECL(sync_out_switch, SAI_PATH_SEL, 17, sync_out_text); 1215 static SOC_ENUM_SINGLE_DECL(sync_in_switch, SAI_PATH_SEL, 16, sync_in_text); 1216 static SOC_ENUM_SINGLE_DECL(rpath3_enum, SAI_PATH_SEL, 14, rpaths_text); 1217 static SOC_ENUM_SINGLE_DECL(rpath2_enum, SAI_PATH_SEL, 12, rpaths_text); 1218 static SOC_ENUM_SINGLE_DECL(rpath1_enum, SAI_PATH_SEL, 10, rpaths_text); 1219 static SOC_ENUM_SINGLE_DECL(rpath0_enum, SAI_PATH_SEL, 8, rpaths_text); 1220 static SOC_ENUM_SINGLE_DECL(tpath3_enum, SAI_PATH_SEL, 6, tpaths_text); 1221 static SOC_ENUM_SINGLE_DECL(tpath2_enum, SAI_PATH_SEL, 4, tpaths_text); 1222 static SOC_ENUM_SINGLE_DECL(tpath1_enum, SAI_PATH_SEL, 2, tpaths_text); 1223 static SOC_ENUM_SINGLE_DECL(tpath0_enum, SAI_PATH_SEL, 0, tpaths_text); 1224 1225 /* LOOPBACK_LR */ 1226 static SOC_ENUM_SINGLE_DECL(lp3lrc_enum, SAI_LOOPBACK_LR, 7, lplrc_text); 1227 static SOC_ENUM_SINGLE_DECL(lp2lrc_enum, SAI_LOOPBACK_LR, 6, lplrc_text); 1228 static SOC_ENUM_SINGLE_DECL(lp1lrc_enum, SAI_LOOPBACK_LR, 5, lplrc_text); 1229 static SOC_ENUM_SINGLE_DECL(lp0lrc_enum, SAI_LOOPBACK_LR, 4, lplrc_text); 1230 static SOC_ENUM_SINGLE_DECL(lp3lr_switch, SAI_LOOPBACK_LR, 3, lplr_text); 1231 static SOC_ENUM_SINGLE_DECL(lp2lr_switch, SAI_LOOPBACK_LR, 2, lplr_text); 1232 static SOC_ENUM_SINGLE_DECL(lp1lr_switch, SAI_LOOPBACK_LR, 1, lplr_text); 1233 static SOC_ENUM_SINGLE_DECL(lp0lr_switch, SAI_LOOPBACK_LR, 0, lplr_text); 1234 1235 static int rockchip_sai_wait_time_info(struct snd_kcontrol *kcontrol, 1236 struct snd_ctl_elem_info *uinfo) 1237 { 1238 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER; 1239 uinfo->count = 1; 1240 uinfo->value.integer.min = 0; 1241 uinfo->value.integer.max = WAIT_TIME_MS_MAX; 1242 uinfo->value.integer.step = 1; 1243 1244 return 0; 1245 } 1246 1247 static int rockchip_sai_rd_wait_time_get(struct snd_kcontrol *kcontrol, 1248 struct snd_ctl_elem_value *ucontrol) 1249 { 1250 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1251 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component); 1252 1253 ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_CAPTURE]; 1254 1255 return 0; 1256 } 1257 1258 static int rockchip_sai_rd_wait_time_put(struct snd_kcontrol *kcontrol, 1259 struct snd_ctl_elem_value *ucontrol) 1260 { 1261 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1262 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component); 1263 1264 if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX) 1265 return -EINVAL; 1266 1267 sai->wait_time[SNDRV_PCM_STREAM_CAPTURE] = ucontrol->value.integer.value[0]; 1268 1269 return 1; 1270 } 1271 1272 static int rockchip_sai_wr_wait_time_get(struct snd_kcontrol *kcontrol, 1273 struct snd_ctl_elem_value *ucontrol) 1274 { 1275 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1276 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component); 1277 1278 ucontrol->value.integer.value[0] = sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK]; 1279 1280 return 0; 1281 } 1282 1283 static int rockchip_sai_wr_wait_time_put(struct snd_kcontrol *kcontrol, 1284 struct snd_ctl_elem_value *ucontrol) 1285 { 1286 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1287 struct rk_sai_dev *sai = snd_soc_component_get_drvdata(component); 1288 1289 if (ucontrol->value.integer.value[0] > WAIT_TIME_MS_MAX) 1290 return -EINVAL; 1291 1292 sai->wait_time[SNDRV_PCM_STREAM_PLAYBACK] = ucontrol->value.integer.value[0]; 1293 1294 return 1; 1295 } 1296 1297 #define SAI_PCM_WAIT_TIME(xname, xhandler_get, xhandler_put) \ 1298 { .iface = SNDRV_CTL_ELEM_IFACE_PCM, .name = xname, \ 1299 .info = rockchip_sai_wait_time_info, \ 1300 .get = xhandler_get, .put = xhandler_put } 1301 1302 static const struct snd_kcontrol_new rockchip_sai_controls[] = { 1303 SOC_SINGLE_TLV("Receive Mono Slot Select", SAI_MONO_CR, 1304 2, 128, 0, rmss_tlv), 1305 SOC_ENUM("Receive Mono Switch", rmono_switch), 1306 SOC_ENUM("Transmit Mono Switch", tmono_switch), 1307 1308 SOC_ENUM("SDI3 Loopback I2S LR Channel Sel", lp3lrc_enum), 1309 SOC_ENUM("SDI2 Loopback I2S LR Channel Sel", lp2lrc_enum), 1310 SOC_ENUM("SDI1 Loopback I2S LR Channel Sel", lp1lrc_enum), 1311 SOC_ENUM("SDI0 Loopback I2S LR Channel Sel", lp0lrc_enum), 1312 SOC_ENUM("SDI3 Loopback I2S LR Switch", lp3lr_switch), 1313 SOC_ENUM("SDI2 Loopback I2S LR Switch", lp2lr_switch), 1314 SOC_ENUM("SDI1 Loopback I2S LR Switch", lp1lr_switch), 1315 SOC_ENUM("SDI0 Loopback I2S LR Switch", lp0lr_switch), 1316 1317 SOC_ENUM("SDI3 Loopback Src Select", lp3_enum), 1318 SOC_ENUM("SDI2 Loopback Src Select", lp2_enum), 1319 SOC_ENUM("SDI1 Loopback Src Select", lp1_enum), 1320 SOC_ENUM("SDI0 Loopback Src Select", lp0_enum), 1321 SOC_ENUM("SDI3 Loopback Switch", lp3_switch), 1322 SOC_ENUM("SDI2 Loopback Switch", lp2_switch), 1323 SOC_ENUM("SDI1 Loopback Switch", lp1_switch), 1324 SOC_ENUM("SDI0 Loopback Switch", lp0_switch), 1325 SOC_ENUM("Sync Out Switch", sync_out_switch), 1326 SOC_ENUM("Sync In Switch", sync_in_switch), 1327 SOC_ENUM("Receive PATH3 Source Select", rpath3_enum), 1328 SOC_ENUM("Receive PATH2 Source Select", rpath2_enum), 1329 SOC_ENUM("Receive PATH1 Source Select", rpath1_enum), 1330 SOC_ENUM("Receive PATH0 Source Select", rpath0_enum), 1331 SOC_ENUM("Transmit SDO3 Source Select", tpath3_enum), 1332 SOC_ENUM("Transmit SDO2 Source Select", tpath2_enum), 1333 SOC_ENUM("Transmit SDO1 Source Select", tpath1_enum), 1334 SOC_ENUM("Transmit SDO0 Source Select", tpath0_enum), 1335 1336 SAI_PCM_WAIT_TIME("PCM Read Wait Time MS", 1337 rockchip_sai_rd_wait_time_get, 1338 rockchip_sai_rd_wait_time_put), 1339 SAI_PCM_WAIT_TIME("PCM Write Wait Time MS", 1340 rockchip_sai_wr_wait_time_get, 1341 rockchip_sai_wr_wait_time_put), 1342 }; 1343 1344 static const struct snd_soc_component_driver rockchip_sai_component = { 1345 .name = DRV_NAME, 1346 .controls = rockchip_sai_controls, 1347 .num_controls = ARRAY_SIZE(rockchip_sai_controls), 1348 .legacy_dai_naming = 1, 1349 }; 1350 1351 static irqreturn_t rockchip_sai_isr(int irq, void *devid) 1352 { 1353 struct rk_sai_dev *sai = (struct rk_sai_dev *)devid; 1354 struct snd_pcm_substream *substream; 1355 u32 val; 1356 1357 regmap_read(sai->regmap, SAI_INTSR, &val); 1358 if (val & SAI_INTSR_TXUI_ACT) { 1359 dev_warn_ratelimited(sai->dev, "TX FIFO Underrun\n"); 1360 regmap_update_bits(sai->regmap, SAI_INTCR, 1361 SAI_INTCR_TXUIC, SAI_INTCR_TXUIC); 1362 regmap_update_bits(sai->regmap, SAI_INTCR, 1363 SAI_INTCR_TXUIE_MASK, 1364 SAI_INTCR_TXUIE(0)); 1365 substream = sai->substreams[SNDRV_PCM_STREAM_PLAYBACK]; 1366 if (substream) 1367 snd_pcm_stop_xrun(substream); 1368 } 1369 1370 if (val & SAI_INTSR_RXOI_ACT) { 1371 dev_warn_ratelimited(sai->dev, "RX FIFO Overrun\n"); 1372 regmap_update_bits(sai->regmap, SAI_INTCR, 1373 SAI_INTCR_RXOIC, SAI_INTCR_RXOIC); 1374 regmap_update_bits(sai->regmap, SAI_INTCR, 1375 SAI_INTCR_RXOIE_MASK, 1376 SAI_INTCR_RXOIE(0)); 1377 substream = sai->substreams[SNDRV_PCM_STREAM_CAPTURE]; 1378 if (substream) 1379 snd_pcm_stop_xrun(substream); 1380 } 1381 1382 if (val & SAI_INTSR_FSERRI_ACT) { 1383 dev_warn_ratelimited(sai->dev, "Frame Sync Error\n"); 1384 regmap_update_bits(sai->regmap, SAI_INTCR, 1385 SAI_INTCR_FSERRC, SAI_INTCR_FSERRC); 1386 regmap_update_bits(sai->regmap, SAI_INTCR, 1387 SAI_INTCR_FSERR_MASK, 1388 SAI_INTCR_FSERR(0)); 1389 } 1390 1391 if (val & SAI_INTSR_FSLOSTI_ACT) { 1392 dev_warn_ratelimited(sai->dev, "Frame Sync Lost\n"); 1393 regmap_update_bits(sai->regmap, SAI_INTCR, 1394 SAI_INTCR_FSLOSTC, SAI_INTCR_FSLOSTC); 1395 regmap_update_bits(sai->regmap, SAI_INTCR, 1396 SAI_INTCR_FSLOST_MASK, 1397 SAI_INTCR_FSLOST(0)); 1398 } 1399 1400 return IRQ_HANDLED; 1401 } 1402 1403 static int rockchip_sai_probe(struct platform_device *pdev) 1404 { 1405 struct device_node *node = pdev->dev.of_node; 1406 struct rk_sai_dev *sai; 1407 struct snd_soc_dai_driver *dai; 1408 struct resource *res; 1409 void __iomem *regs; 1410 int ret, irq; 1411 1412 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL); 1413 if (!sai) 1414 return -ENOMEM; 1415 1416 sai->dev = &pdev->dev; 1417 sai->fw_ratio = 1; 1418 /* match to register default */ 1419 sai->is_master_mode = true; 1420 dev_set_drvdata(&pdev->dev, sai); 1421 1422 spin_lock_init(&sai->xfer_lock); 1423 1424 sai->rst_h = devm_reset_control_get_optional_exclusive(&pdev->dev, "h"); 1425 if (IS_ERR(sai->rst_h)) 1426 return dev_err_probe(&pdev->dev, PTR_ERR(sai->rst_h), 1427 "Error in 'h' reset control\n"); 1428 1429 sai->rst_m = devm_reset_control_get_optional_exclusive(&pdev->dev, "m"); 1430 if (IS_ERR(sai->rst_m)) 1431 return dev_err_probe(&pdev->dev, PTR_ERR(sai->rst_m), 1432 "Error in 'm' reset control\n"); 1433 1434 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1435 if (IS_ERR(regs)) 1436 return dev_err_probe(&pdev->dev, PTR_ERR(regs), 1437 "Failed to get and ioremap resource\n"); 1438 1439 sai->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1440 &rockchip_sai_regmap_config); 1441 if (IS_ERR(sai->regmap)) 1442 return dev_err_probe(&pdev->dev, PTR_ERR(sai->regmap), 1443 "Failed to initialize regmap\n"); 1444 1445 irq = platform_get_irq_optional(pdev, 0); 1446 if (irq == -EPROBE_DEFER) 1447 return irq; 1448 if (irq > 0) { 1449 ret = devm_request_irq(&pdev->dev, irq, rockchip_sai_isr, 1450 IRQF_SHARED, node->name, sai); 1451 if (ret) 1452 return ret; 1453 } else { 1454 dev_dbg(&pdev->dev, "Asked for an IRQ but got %d\n", irq); 1455 } 1456 1457 sai->mclk = devm_clk_get(&pdev->dev, "mclk"); 1458 if (IS_ERR(sai->mclk)) 1459 return dev_err_probe(&pdev->dev, PTR_ERR(sai->mclk), 1460 "Failed to get mclk\n"); 1461 1462 sai->hclk = devm_clk_get_enabled(&pdev->dev, "hclk"); 1463 if (IS_ERR(sai->hclk)) 1464 return dev_err_probe(&pdev->dev, PTR_ERR(sai->hclk), 1465 "Failed to get hclk\n"); 1466 1467 regmap_read(sai->regmap, SAI_VERSION, &sai->version); 1468 1469 ret = rockchip_sai_init_dai(sai, res, &dai); 1470 if (ret) 1471 return dev_err_probe(&pdev->dev, ret, "Failed to initialize DAI\n"); 1472 1473 ret = rockchip_sai_parse_paths(sai, node); 1474 if (ret) 1475 return ret; 1476 1477 /* 1478 * From here on, all register accesses need to be wrapped in 1479 * pm_runtime_get_sync/pm_runtime_put calls 1480 * 1481 * NB: we don't rely on _resume_and_get in case of !CONFIG_PM 1482 */ 1483 devm_pm_runtime_enable(&pdev->dev); 1484 pm_runtime_get_noresume(&pdev->dev); 1485 ret = rockchip_sai_runtime_resume(&pdev->dev); 1486 if (ret) 1487 return dev_err_probe(&pdev->dev, ret, "Failed to resume device\n"); 1488 1489 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1490 if (ret) 1491 goto err_runtime_suspend; 1492 1493 ret = devm_snd_soc_register_component(&pdev->dev, 1494 &rockchip_sai_component, 1495 dai, 1); 1496 if (ret) 1497 goto err_runtime_suspend; 1498 1499 pm_runtime_use_autosuspend(&pdev->dev); 1500 pm_runtime_put(&pdev->dev); 1501 1502 clk_disable_unprepare(sai->hclk); 1503 1504 return 0; 1505 1506 err_runtime_suspend: 1507 if (IS_ENABLED(CONFIG_PM)) 1508 pm_runtime_put(&pdev->dev); 1509 else 1510 rockchip_sai_runtime_suspend(&pdev->dev); 1511 1512 return ret; 1513 } 1514 1515 static void rockchip_sai_remove(struct platform_device *pdev) 1516 { 1517 #ifndef CONFIG_PM 1518 rockchip_sai_runtime_suspend(&pdev->dev); 1519 #endif 1520 } 1521 1522 static const struct dev_pm_ops rockchip_sai_pm_ops = { 1523 SET_RUNTIME_PM_OPS(rockchip_sai_runtime_suspend, rockchip_sai_runtime_resume, NULL) 1524 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1525 }; 1526 1527 static const struct of_device_id rockchip_sai_match[] = { 1528 { .compatible = "rockchip,rk3576-sai", }, 1529 {}, 1530 }; 1531 MODULE_DEVICE_TABLE(of, rockchip_sai_match); 1532 1533 static struct platform_driver rockchip_sai_driver = { 1534 .probe = rockchip_sai_probe, 1535 .remove = rockchip_sai_remove, 1536 .driver = { 1537 .name = DRV_NAME, 1538 .of_match_table = rockchip_sai_match, 1539 .pm = &rockchip_sai_pm_ops, 1540 }, 1541 }; 1542 module_platform_driver(rockchip_sai_driver); 1543 1544 MODULE_DESCRIPTION("Rockchip SAI ASoC Interface"); 1545 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>"); 1546 MODULE_AUTHOR("Nicolas Frattaroli <nicolas.frattaroli@collabora.com>"); 1547 MODULE_LICENSE("GPL"); 1548