1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2019 Intel Corporation.
3
4 #include <linux/acpi.h>
5 #include <linux/clk.h>
6 #include <linux/delay.h>
7 #include <linux/gpio/consumer.h>
8 #include <linux/i2c.h>
9 #include <linux/module.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regulator/consumer.h>
12 #include <linux/unaligned.h>
13
14 #include <media/v4l2-ctrls.h>
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-fwnode.h>
17
18 #define OV5675_REG_VALUE_08BIT 1
19 #define OV5675_REG_VALUE_16BIT 2
20 #define OV5675_REG_VALUE_24BIT 3
21
22 #define OV5675_LINK_FREQ_450MHZ 450000000ULL
23 #define OV5675_SCLK 90000000LL
24 #define OV5675_XVCLK_19_2 19200000
25 #define OV5675_DATA_LANES 2
26 #define OV5675_RGB_DEPTH 10
27
28 #define OV5675_REG_CHIP_ID 0x300a
29 #define OV5675_CHIP_ID 0x5675
30
31 #define OV5675_REG_MODE_SELECT 0x0100
32 #define OV5675_MODE_STANDBY 0x00
33 #define OV5675_MODE_STREAMING 0x01
34
35 /* vertical-timings from sensor */
36 #define OV5675_REG_VTS 0x380e
37 #define OV5675_VTS_30FPS 0x07e4
38 #define OV5675_VTS_30FPS_MIN 0x07e4
39 #define OV5675_VTS_MAX 0x7fff
40
41 /* horizontal-timings from sensor */
42 #define OV5675_REG_HTS 0x380c
43
44 /* Exposure controls from sensor */
45 #define OV5675_REG_EXPOSURE 0x3500
46 #define OV5675_EXPOSURE_MIN 4
47 #define OV5675_EXPOSURE_MAX_MARGIN 4
48 #define OV5675_EXPOSURE_STEP 1
49
50 /* Analog gain controls from sensor */
51 #define OV5675_REG_ANALOG_GAIN 0x3508
52 #define OV5675_ANAL_GAIN_MIN 128
53 #define OV5675_ANAL_GAIN_MAX 2047
54 #define OV5675_ANAL_GAIN_STEP 1
55
56 /* Digital gain controls from sensor */
57 #define OV5675_REG_DIGITAL_GAIN 0x350a
58 #define OV5675_REG_MWB_R_GAIN 0x5019
59 #define OV5675_REG_MWB_G_GAIN 0x501b
60 #define OV5675_REG_MWB_B_GAIN 0x501d
61 #define OV5675_DGTL_GAIN_MIN 1024
62 #define OV5675_DGTL_GAIN_MAX 4095
63 #define OV5675_DGTL_GAIN_STEP 1
64 #define OV5675_DGTL_GAIN_DEFAULT 1024
65
66 /* Group Access */
67 #define OV5675_REG_GROUP_ACCESS 0x3208
68 #define OV5675_GROUP_HOLD_START 0x0
69 #define OV5675_GROUP_HOLD_END 0x10
70 #define OV5675_GROUP_HOLD_LAUNCH 0xa0
71
72 /* Test Pattern Control */
73 #define OV5675_REG_TEST_PATTERN 0x4503
74 #define OV5675_TEST_PATTERN_ENABLE BIT(7)
75 #define OV5675_TEST_PATTERN_BAR_SHIFT 2
76
77 /* Flip Mirror Controls from sensor */
78 #define OV5675_REG_FORMAT1 0x3820
79 #define OV5675_REG_FORMAT2 0x373d
80
81 #define to_ov5675(_sd) container_of(_sd, struct ov5675, sd)
82
83 static const char * const ov5675_supply_names[] = {
84 "avdd", /* Analog power */
85 "dovdd", /* Digital I/O power */
86 "dvdd", /* Digital core power */
87 };
88
89 #define OV5675_NUM_SUPPLIES ARRAY_SIZE(ov5675_supply_names)
90
91 enum {
92 OV5675_LINK_FREQ_900MBPS,
93 };
94
95 struct ov5675_reg {
96 u16 address;
97 u8 val;
98 };
99
100 struct ov5675_reg_list {
101 u32 num_of_regs;
102 const struct ov5675_reg *regs;
103 };
104
105 struct ov5675_link_freq_config {
106 const struct ov5675_reg_list reg_list;
107 };
108
109 struct ov5675_mode {
110 /* Frame width in pixels */
111 u32 width;
112
113 /* Frame height in pixels */
114 u32 height;
115
116 /* Horizontal timining size */
117 u32 hts;
118
119 /* Default vertical timining size */
120 u32 vts_def;
121
122 /* Min vertical timining size */
123 u32 vts_min;
124
125 /* Link frequency needed for this resolution */
126 u32 link_freq_index;
127
128 /* Sensor register settings for this resolution */
129 const struct ov5675_reg_list reg_list;
130 };
131
132 static const struct ov5675_reg mipi_data_rate_900mbps[] = {
133 {0x0103, 0x01},
134 {0x0100, 0x00},
135 {0x0300, 0x04},
136 {0x0302, 0x8d},
137 {0x0303, 0x00},
138 {0x030d, 0x26},
139 };
140
141 static const struct ov5675_reg mode_2592x1944_regs[] = {
142 {0x3002, 0x21},
143 {0x3107, 0x23},
144 {0x3501, 0x20},
145 {0x3503, 0x0c},
146 {0x3508, 0x03},
147 {0x3509, 0x00},
148 {0x3600, 0x66},
149 {0x3602, 0x30},
150 {0x3610, 0xa5},
151 {0x3612, 0x93},
152 {0x3620, 0x80},
153 {0x3642, 0x0e},
154 {0x3661, 0x00},
155 {0x3662, 0x10},
156 {0x3664, 0xf3},
157 {0x3665, 0x9e},
158 {0x3667, 0xa5},
159 {0x366e, 0x55},
160 {0x366f, 0x55},
161 {0x3670, 0x11},
162 {0x3671, 0x11},
163 {0x3672, 0x11},
164 {0x3673, 0x11},
165 {0x3714, 0x24},
166 {0x371a, 0x3e},
167 {0x3733, 0x10},
168 {0x3734, 0x00},
169 {0x373d, 0x24},
170 {0x3764, 0x20},
171 {0x3765, 0x20},
172 {0x3766, 0x12},
173 {0x37a1, 0x14},
174 {0x37a8, 0x1c},
175 {0x37ab, 0x0f},
176 {0x37c2, 0x04},
177 {0x37cb, 0x00},
178 {0x37cc, 0x00},
179 {0x37cd, 0x00},
180 {0x37ce, 0x00},
181 {0x37d8, 0x02},
182 {0x37d9, 0x08},
183 {0x37dc, 0x04},
184 {0x3800, 0x00},
185 {0x3801, 0x00},
186 {0x3802, 0x00},
187 {0x3803, 0x04},
188 {0x3804, 0x0a},
189 {0x3805, 0x3f},
190 {0x3806, 0x07},
191 {0x3807, 0xb3},
192 {0x3808, 0x0a},
193 {0x3809, 0x20},
194 {0x380a, 0x07},
195 {0x380b, 0x98},
196 {0x380c, 0x02},
197 {0x380d, 0xee},
198 {0x380e, 0x07},
199 {0x380f, 0xe4},
200 {0x3811, 0x10},
201 {0x3813, 0x0d},
202 {0x3814, 0x01},
203 {0x3815, 0x01},
204 {0x3816, 0x01},
205 {0x3817, 0x01},
206 {0x381e, 0x02},
207 {0x3820, 0x88},
208 {0x3821, 0x01},
209 {0x3832, 0x04},
210 {0x3c80, 0x01},
211 {0x3c82, 0x00},
212 {0x3c83, 0xc8},
213 {0x3c8c, 0x0f},
214 {0x3c8d, 0xa0},
215 {0x3c90, 0x07},
216 {0x3c91, 0x00},
217 {0x3c92, 0x00},
218 {0x3c93, 0x00},
219 {0x3c94, 0xd0},
220 {0x3c95, 0x50},
221 {0x3c96, 0x35},
222 {0x3c97, 0x00},
223 {0x4001, 0xe0},
224 {0x4008, 0x02},
225 {0x4009, 0x0d},
226 {0x400f, 0x80},
227 {0x4013, 0x02},
228 {0x4040, 0x00},
229 {0x4041, 0x07},
230 {0x404c, 0x50},
231 {0x404e, 0x20},
232 {0x4500, 0x06},
233 {0x4503, 0x00},
234 {0x450a, 0x04},
235 {0x4809, 0x04},
236 {0x480c, 0x12},
237 {0x4819, 0x70},
238 {0x4825, 0x32},
239 {0x4826, 0x32},
240 {0x482a, 0x06},
241 {0x4833, 0x08},
242 {0x4837, 0x0d},
243 {0x5000, 0x77},
244 {0x5b00, 0x01},
245 {0x5b01, 0x10},
246 {0x5b02, 0x01},
247 {0x5b03, 0xdb},
248 {0x5b05, 0x6c},
249 {0x5e10, 0xfc},
250 {0x3500, 0x00},
251 {0x3501, 0x3E},
252 {0x3502, 0x60},
253 {0x3503, 0x08},
254 {0x3508, 0x04},
255 {0x3509, 0x00},
256 {0x3832, 0x48},
257 {0x5780, 0x3e},
258 {0x5781, 0x0f},
259 {0x5782, 0x44},
260 {0x5783, 0x02},
261 {0x5784, 0x01},
262 {0x5785, 0x01},
263 {0x5786, 0x00},
264 {0x5787, 0x04},
265 {0x5788, 0x02},
266 {0x5789, 0x0f},
267 {0x578a, 0xfd},
268 {0x578b, 0xf5},
269 {0x578c, 0xf5},
270 {0x578d, 0x03},
271 {0x578e, 0x08},
272 {0x578f, 0x0c},
273 {0x5790, 0x08},
274 {0x5791, 0x06},
275 {0x5792, 0x00},
276 {0x5793, 0x52},
277 {0x5794, 0xa3},
278 {0x4003, 0x40},
279 {0x3107, 0x01},
280 {0x3c80, 0x08},
281 {0x3c83, 0xb1},
282 {0x3c8c, 0x10},
283 {0x3c8d, 0x00},
284 {0x3c90, 0x00},
285 {0x3c94, 0x00},
286 {0x3c95, 0x00},
287 {0x3c96, 0x00},
288 {0x37cb, 0x09},
289 {0x37cc, 0x15},
290 {0x37cd, 0x1f},
291 {0x37ce, 0x1f},
292 };
293
294 static const struct ov5675_reg mode_1296x972_regs[] = {
295 {0x3002, 0x21},
296 {0x3107, 0x23},
297 {0x3501, 0x20},
298 {0x3503, 0x0c},
299 {0x3508, 0x03},
300 {0x3509, 0x00},
301 {0x3600, 0x66},
302 {0x3602, 0x30},
303 {0x3610, 0xa5},
304 {0x3612, 0x93},
305 {0x3620, 0x80},
306 {0x3642, 0x0e},
307 {0x3661, 0x00},
308 {0x3662, 0x08},
309 {0x3664, 0xf3},
310 {0x3665, 0x9e},
311 {0x3667, 0xa5},
312 {0x366e, 0x55},
313 {0x366f, 0x55},
314 {0x3670, 0x11},
315 {0x3671, 0x11},
316 {0x3672, 0x11},
317 {0x3673, 0x11},
318 {0x3714, 0x28},
319 {0x371a, 0x3e},
320 {0x3733, 0x10},
321 {0x3734, 0x00},
322 {0x373d, 0x24},
323 {0x3764, 0x20},
324 {0x3765, 0x20},
325 {0x3766, 0x12},
326 {0x37a1, 0x14},
327 {0x37a8, 0x1c},
328 {0x37ab, 0x0f},
329 {0x37c2, 0x14},
330 {0x37cb, 0x00},
331 {0x37cc, 0x00},
332 {0x37cd, 0x00},
333 {0x37ce, 0x00},
334 {0x37d8, 0x02},
335 {0x37d9, 0x04},
336 {0x37dc, 0x04},
337 {0x3800, 0x00},
338 {0x3801, 0x00},
339 {0x3802, 0x00},
340 {0x3803, 0x00},
341 {0x3804, 0x0a},
342 {0x3805, 0x3f},
343 {0x3806, 0x07},
344 {0x3807, 0xb7},
345 {0x3808, 0x05},
346 {0x3809, 0x10},
347 {0x380a, 0x03},
348 {0x380b, 0xcc},
349 {0x380c, 0x02},
350 {0x380d, 0xee},
351 {0x380e, 0x07},
352 {0x380f, 0xd0},
353 {0x3811, 0x08},
354 {0x3813, 0x0d},
355 {0x3814, 0x03},
356 {0x3815, 0x01},
357 {0x3816, 0x03},
358 {0x3817, 0x01},
359 {0x381e, 0x02},
360 {0x3820, 0x8b},
361 {0x3821, 0x01},
362 {0x3832, 0x04},
363 {0x3c80, 0x01},
364 {0x3c82, 0x00},
365 {0x3c83, 0xc8},
366 {0x3c8c, 0x0f},
367 {0x3c8d, 0xa0},
368 {0x3c90, 0x07},
369 {0x3c91, 0x00},
370 {0x3c92, 0x00},
371 {0x3c93, 0x00},
372 {0x3c94, 0xd0},
373 {0x3c95, 0x50},
374 {0x3c96, 0x35},
375 {0x3c97, 0x00},
376 {0x4001, 0xe0},
377 {0x4008, 0x00},
378 {0x4009, 0x07},
379 {0x400f, 0x80},
380 {0x4013, 0x02},
381 {0x4040, 0x00},
382 {0x4041, 0x03},
383 {0x404c, 0x50},
384 {0x404e, 0x20},
385 {0x4500, 0x06},
386 {0x4503, 0x00},
387 {0x450a, 0x04},
388 {0x4809, 0x04},
389 {0x480c, 0x12},
390 {0x4819, 0x70},
391 {0x4825, 0x32},
392 {0x4826, 0x32},
393 {0x482a, 0x06},
394 {0x4833, 0x08},
395 {0x4837, 0x0d},
396 {0x5000, 0x77},
397 {0x5b00, 0x01},
398 {0x5b01, 0x10},
399 {0x5b02, 0x01},
400 {0x5b03, 0xdb},
401 {0x5b05, 0x6c},
402 {0x5e10, 0xfc},
403 {0x3500, 0x00},
404 {0x3501, 0x1F},
405 {0x3502, 0x20},
406 {0x3503, 0x08},
407 {0x3508, 0x04},
408 {0x3509, 0x00},
409 {0x3832, 0x48},
410 {0x5780, 0x3e},
411 {0x5781, 0x0f},
412 {0x5782, 0x44},
413 {0x5783, 0x02},
414 {0x5784, 0x01},
415 {0x5785, 0x01},
416 {0x5786, 0x00},
417 {0x5787, 0x04},
418 {0x5788, 0x02},
419 {0x5789, 0x0f},
420 {0x578a, 0xfd},
421 {0x578b, 0xf5},
422 {0x578c, 0xf5},
423 {0x578d, 0x03},
424 {0x578e, 0x08},
425 {0x578f, 0x0c},
426 {0x5790, 0x08},
427 {0x5791, 0x06},
428 {0x5792, 0x00},
429 {0x5793, 0x52},
430 {0x5794, 0xa3},
431 {0x4003, 0x40},
432 {0x3107, 0x01},
433 {0x3c80, 0x08},
434 {0x3c83, 0xb1},
435 {0x3c8c, 0x10},
436 {0x3c8d, 0x00},
437 {0x3c90, 0x00},
438 {0x3c94, 0x00},
439 {0x3c95, 0x00},
440 {0x3c96, 0x00},
441 {0x37cb, 0x09},
442 {0x37cc, 0x15},
443 {0x37cd, 0x1f},
444 {0x37ce, 0x1f},
445 };
446
447 static const char * const ov5675_test_pattern_menu[] = {
448 "Disabled",
449 "Standard Color Bar",
450 "Top-Bottom Darker Color Bar",
451 "Right-Left Darker Color Bar",
452 "Bottom-Top Darker Color Bar"
453 };
454
455 static const s64 link_freq_menu_items[] = {
456 OV5675_LINK_FREQ_450MHZ,
457 };
458
459 static const struct ov5675_link_freq_config link_freq_configs[] = {
460 [OV5675_LINK_FREQ_900MBPS] = {
461 .reg_list = {
462 .num_of_regs = ARRAY_SIZE(mipi_data_rate_900mbps),
463 .regs = mipi_data_rate_900mbps,
464 }
465 }
466 };
467
468 static const struct ov5675_mode supported_modes[] = {
469 {
470 .width = 2592,
471 .height = 1944,
472 .hts = 1500,
473 .vts_def = OV5675_VTS_30FPS,
474 .vts_min = OV5675_VTS_30FPS_MIN,
475 .reg_list = {
476 .num_of_regs = ARRAY_SIZE(mode_2592x1944_regs),
477 .regs = mode_2592x1944_regs,
478 },
479 .link_freq_index = OV5675_LINK_FREQ_900MBPS,
480 },
481 {
482 .width = 1296,
483 .height = 972,
484 .hts = 1500,
485 .vts_def = OV5675_VTS_30FPS,
486 .vts_min = OV5675_VTS_30FPS_MIN,
487 .reg_list = {
488 .num_of_regs = ARRAY_SIZE(mode_1296x972_regs),
489 .regs = mode_1296x972_regs,
490 },
491 .link_freq_index = OV5675_LINK_FREQ_900MBPS,
492 }
493 };
494
495 struct ov5675 {
496 struct device *dev;
497
498 struct v4l2_subdev sd;
499 struct media_pad pad;
500 struct v4l2_ctrl_handler ctrl_handler;
501 struct clk *xvclk;
502 struct gpio_desc *reset_gpio;
503 struct regulator_bulk_data supplies[OV5675_NUM_SUPPLIES];
504
505 /* V4L2 Controls */
506 struct v4l2_ctrl *link_freq;
507 struct v4l2_ctrl *pixel_rate;
508 struct v4l2_ctrl *vblank;
509 struct v4l2_ctrl *hblank;
510 struct v4l2_ctrl *exposure;
511
512 /* Current mode */
513 const struct ov5675_mode *cur_mode;
514
515 /* To serialize asynchronous callbacks */
516 struct mutex mutex;
517
518 /* True if the device has been identified */
519 bool identified;
520 };
521
to_pixel_rate(u32 f_index)522 static u64 to_pixel_rate(u32 f_index)
523 {
524 u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV5675_DATA_LANES;
525
526 do_div(pixel_rate, OV5675_RGB_DEPTH);
527
528 return pixel_rate;
529 }
530
to_pixels_per_line(u32 hts,u32 f_index)531 static u64 to_pixels_per_line(u32 hts, u32 f_index)
532 {
533 u64 ppl = hts * to_pixel_rate(f_index);
534
535 do_div(ppl, OV5675_SCLK);
536
537 return ppl;
538 }
539
ov5675_read_reg(struct ov5675 * ov5675,u16 reg,u16 len,u32 * val)540 static int ov5675_read_reg(struct ov5675 *ov5675, u16 reg, u16 len, u32 *val)
541 {
542 struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
543 struct i2c_msg msgs[2];
544 u8 addr_buf[2];
545 u8 data_buf[4] = {0};
546 int ret;
547
548 if (len > 4)
549 return -EINVAL;
550
551 put_unaligned_be16(reg, addr_buf);
552 msgs[0].addr = client->addr;
553 msgs[0].flags = 0;
554 msgs[0].len = sizeof(addr_buf);
555 msgs[0].buf = addr_buf;
556 msgs[1].addr = client->addr;
557 msgs[1].flags = I2C_M_RD;
558 msgs[1].len = len;
559 msgs[1].buf = &data_buf[4 - len];
560
561 ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
562 if (ret != ARRAY_SIZE(msgs))
563 return -EIO;
564
565 *val = get_unaligned_be32(data_buf);
566
567 return 0;
568 }
569
ov5675_write_reg(struct ov5675 * ov5675,u16 reg,u16 len,u32 val)570 static int ov5675_write_reg(struct ov5675 *ov5675, u16 reg, u16 len, u32 val)
571 {
572 struct i2c_client *client = v4l2_get_subdevdata(&ov5675->sd);
573 u8 buf[6];
574
575 if (len > 4)
576 return -EINVAL;
577
578 put_unaligned_be16(reg, buf);
579 put_unaligned_be32(val << 8 * (4 - len), buf + 2);
580 if (i2c_master_send(client, buf, len + 2) != len + 2)
581 return -EIO;
582
583 return 0;
584 }
585
ov5675_write_reg_list(struct ov5675 * ov5675,const struct ov5675_reg_list * r_list)586 static int ov5675_write_reg_list(struct ov5675 *ov5675,
587 const struct ov5675_reg_list *r_list)
588 {
589 unsigned int i;
590 int ret;
591
592 for (i = 0; i < r_list->num_of_regs; i++) {
593 ret = ov5675_write_reg(ov5675, r_list->regs[i].address, 1,
594 r_list->regs[i].val);
595 if (ret) {
596 dev_err_ratelimited(ov5675->dev,
597 "failed to write reg 0x%4.4x. error = %d",
598 r_list->regs[i].address, ret);
599 return ret;
600 }
601 }
602
603 return 0;
604 }
605
ov5675_update_digital_gain(struct ov5675 * ov5675,u32 d_gain)606 static int ov5675_update_digital_gain(struct ov5675 *ov5675, u32 d_gain)
607 {
608 int ret;
609
610 ret = ov5675_write_reg(ov5675, OV5675_REG_GROUP_ACCESS,
611 OV5675_REG_VALUE_08BIT,
612 OV5675_GROUP_HOLD_START);
613 if (ret)
614 return ret;
615
616 ret = ov5675_write_reg(ov5675, OV5675_REG_MWB_R_GAIN,
617 OV5675_REG_VALUE_16BIT, d_gain);
618 if (ret)
619 return ret;
620
621 ret = ov5675_write_reg(ov5675, OV5675_REG_MWB_G_GAIN,
622 OV5675_REG_VALUE_16BIT, d_gain);
623 if (ret)
624 return ret;
625
626 ret = ov5675_write_reg(ov5675, OV5675_REG_MWB_B_GAIN,
627 OV5675_REG_VALUE_16BIT, d_gain);
628 if (ret)
629 return ret;
630
631 ret = ov5675_write_reg(ov5675, OV5675_REG_GROUP_ACCESS,
632 OV5675_REG_VALUE_08BIT,
633 OV5675_GROUP_HOLD_END);
634 if (ret)
635 return ret;
636
637 ret = ov5675_write_reg(ov5675, OV5675_REG_GROUP_ACCESS,
638 OV5675_REG_VALUE_08BIT,
639 OV5675_GROUP_HOLD_LAUNCH);
640 return ret;
641 }
642
ov5675_test_pattern(struct ov5675 * ov5675,u32 pattern)643 static int ov5675_test_pattern(struct ov5675 *ov5675, u32 pattern)
644 {
645 if (pattern)
646 pattern = (pattern - 1) << OV5675_TEST_PATTERN_BAR_SHIFT |
647 OV5675_TEST_PATTERN_ENABLE;
648
649 return ov5675_write_reg(ov5675, OV5675_REG_TEST_PATTERN,
650 OV5675_REG_VALUE_08BIT, pattern);
651 }
652
653 /*
654 * OV5675 supports keeping the pixel order by mirror and flip function
655 * The Bayer order isn't affected by the flip controls
656 */
ov5675_set_ctrl_hflip(struct ov5675 * ov5675,u32 ctrl_val)657 static int ov5675_set_ctrl_hflip(struct ov5675 *ov5675, u32 ctrl_val)
658 {
659 int ret;
660 u32 val;
661
662 ret = ov5675_read_reg(ov5675, OV5675_REG_FORMAT1,
663 OV5675_REG_VALUE_08BIT, &val);
664 if (ret)
665 return ret;
666
667 return ov5675_write_reg(ov5675, OV5675_REG_FORMAT1,
668 OV5675_REG_VALUE_08BIT,
669 ctrl_val ? val & ~BIT(3) : val | BIT(3));
670 }
671
ov5675_set_ctrl_vflip(struct ov5675 * ov5675,u8 ctrl_val)672 static int ov5675_set_ctrl_vflip(struct ov5675 *ov5675, u8 ctrl_val)
673 {
674 int ret;
675 u32 val;
676
677 ret = ov5675_read_reg(ov5675, OV5675_REG_FORMAT1,
678 OV5675_REG_VALUE_08BIT, &val);
679 if (ret)
680 return ret;
681
682 ret = ov5675_write_reg(ov5675, OV5675_REG_FORMAT1,
683 OV5675_REG_VALUE_08BIT,
684 ctrl_val ? val | BIT(4) | BIT(5) : val & ~BIT(4) & ~BIT(5));
685
686 if (ret)
687 return ret;
688
689 ret = ov5675_read_reg(ov5675, OV5675_REG_FORMAT2,
690 OV5675_REG_VALUE_08BIT, &val);
691
692 if (ret)
693 return ret;
694
695 return ov5675_write_reg(ov5675, OV5675_REG_FORMAT2,
696 OV5675_REG_VALUE_08BIT,
697 ctrl_val ? val | BIT(1) : val & ~BIT(1));
698 }
699
ov5675_set_ctrl(struct v4l2_ctrl * ctrl)700 static int ov5675_set_ctrl(struct v4l2_ctrl *ctrl)
701 {
702 struct ov5675 *ov5675 = container_of(ctrl->handler,
703 struct ov5675, ctrl_handler);
704 s64 exposure_max;
705 int ret = 0;
706
707 /* Propagate change of current control to all related controls */
708 if (ctrl->id == V4L2_CID_VBLANK) {
709 /* Update max exposure while meeting expected vblanking */
710 exposure_max = ov5675->cur_mode->height + ctrl->val -
711 OV5675_EXPOSURE_MAX_MARGIN;
712 __v4l2_ctrl_modify_range(ov5675->exposure,
713 ov5675->exposure->minimum,
714 exposure_max, ov5675->exposure->step,
715 exposure_max);
716 }
717
718 /* V4L2 controls values will be applied only when power is already up */
719 if (!pm_runtime_get_if_in_use(ov5675->dev))
720 return 0;
721
722 switch (ctrl->id) {
723 case V4L2_CID_ANALOGUE_GAIN:
724 ret = ov5675_write_reg(ov5675, OV5675_REG_ANALOG_GAIN,
725 OV5675_REG_VALUE_16BIT, ctrl->val);
726 break;
727
728 case V4L2_CID_DIGITAL_GAIN:
729 ret = ov5675_update_digital_gain(ov5675, ctrl->val);
730 break;
731
732 case V4L2_CID_EXPOSURE:
733 /* 4 least significant bits of expsoure are fractional part
734 * val = val << 4
735 * for ov5675, the unit of exposure is different from other
736 * OmniVision sensors, its exposure value is twice of the
737 * register value, the exposure should be divided by 2 before
738 * set register, e.g. val << 3.
739 */
740 ret = ov5675_write_reg(ov5675, OV5675_REG_EXPOSURE,
741 OV5675_REG_VALUE_24BIT, ctrl->val << 3);
742 break;
743
744 case V4L2_CID_VBLANK:
745 ret = ov5675_write_reg(ov5675, OV5675_REG_VTS,
746 OV5675_REG_VALUE_16BIT,
747 ov5675->cur_mode->height + ctrl->val +
748 10);
749 break;
750
751 case V4L2_CID_TEST_PATTERN:
752 ret = ov5675_test_pattern(ov5675, ctrl->val);
753 break;
754
755 case V4L2_CID_HFLIP:
756 ov5675_set_ctrl_hflip(ov5675, ctrl->val);
757 break;
758
759 case V4L2_CID_VFLIP:
760 ov5675_set_ctrl_vflip(ov5675, ctrl->val);
761 break;
762
763 default:
764 ret = -EINVAL;
765 break;
766 }
767
768 pm_runtime_put(ov5675->dev);
769
770 return ret;
771 }
772
773 static const struct v4l2_ctrl_ops ov5675_ctrl_ops = {
774 .s_ctrl = ov5675_set_ctrl,
775 };
776
ov5675_init_controls(struct ov5675 * ov5675)777 static int ov5675_init_controls(struct ov5675 *ov5675)
778 {
779 struct v4l2_fwnode_device_properties props;
780 struct v4l2_ctrl_handler *ctrl_hdlr;
781 s64 exposure_max, h_blank;
782 int ret;
783
784 ctrl_hdlr = &ov5675->ctrl_handler;
785 ret = v4l2_ctrl_handler_init(ctrl_hdlr, 10);
786 if (ret)
787 return ret;
788
789 ctrl_hdlr->lock = &ov5675->mutex;
790 ov5675->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov5675_ctrl_ops,
791 V4L2_CID_LINK_FREQ,
792 ARRAY_SIZE(link_freq_menu_items) - 1,
793 0, link_freq_menu_items);
794 if (ov5675->link_freq)
795 ov5675->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
796
797 ov5675->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
798 V4L2_CID_PIXEL_RATE, 0,
799 to_pixel_rate(OV5675_LINK_FREQ_900MBPS),
800 1,
801 to_pixel_rate(OV5675_LINK_FREQ_900MBPS));
802 ov5675->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
803 V4L2_CID_VBLANK,
804 ov5675->cur_mode->vts_min - ov5675->cur_mode->height,
805 OV5675_VTS_MAX - ov5675->cur_mode->height, 1,
806 ov5675->cur_mode->vts_def - ov5675->cur_mode->height);
807 h_blank = to_pixels_per_line(ov5675->cur_mode->hts,
808 ov5675->cur_mode->link_freq_index) - ov5675->cur_mode->width;
809 ov5675->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
810 V4L2_CID_HBLANK, h_blank, h_blank, 1,
811 h_blank);
812 if (ov5675->hblank)
813 ov5675->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
814
815 v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
816 OV5675_ANAL_GAIN_MIN, OV5675_ANAL_GAIN_MAX,
817 OV5675_ANAL_GAIN_STEP, OV5675_ANAL_GAIN_MIN);
818 v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
819 OV5675_DGTL_GAIN_MIN, OV5675_DGTL_GAIN_MAX,
820 OV5675_DGTL_GAIN_STEP, OV5675_DGTL_GAIN_DEFAULT);
821 exposure_max = (ov5675->cur_mode->vts_def - OV5675_EXPOSURE_MAX_MARGIN);
822 ov5675->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
823 V4L2_CID_EXPOSURE,
824 OV5675_EXPOSURE_MIN, exposure_max,
825 OV5675_EXPOSURE_STEP,
826 exposure_max);
827 v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov5675_ctrl_ops,
828 V4L2_CID_TEST_PATTERN,
829 ARRAY_SIZE(ov5675_test_pattern_menu) - 1,
830 0, 0, ov5675_test_pattern_menu);
831 v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
832 V4L2_CID_HFLIP, 0, 1, 1, 0);
833 v4l2_ctrl_new_std(ctrl_hdlr, &ov5675_ctrl_ops,
834 V4L2_CID_VFLIP, 0, 1, 1, 0);
835
836 if (ctrl_hdlr->error) {
837 v4l2_ctrl_handler_free(ctrl_hdlr);
838 return ctrl_hdlr->error;
839 }
840
841 ret = v4l2_fwnode_device_parse(ov5675->dev, &props);
842 if (ret)
843 goto error;
844
845 ret = v4l2_ctrl_new_fwnode_properties(ctrl_hdlr, &ov5675_ctrl_ops,
846 &props);
847 if (ret)
848 goto error;
849
850 ov5675->sd.ctrl_handler = ctrl_hdlr;
851
852 return 0;
853
854 error:
855 v4l2_ctrl_handler_free(ctrl_hdlr);
856
857 return ret;
858 }
859
ov5675_update_pad_format(const struct ov5675_mode * mode,struct v4l2_mbus_framefmt * fmt)860 static void ov5675_update_pad_format(const struct ov5675_mode *mode,
861 struct v4l2_mbus_framefmt *fmt)
862 {
863 fmt->width = mode->width;
864 fmt->height = mode->height;
865 fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
866 fmt->field = V4L2_FIELD_NONE;
867 }
868
ov5675_identify_module(struct ov5675 * ov5675)869 static int ov5675_identify_module(struct ov5675 *ov5675)
870 {
871 int ret;
872 u32 val;
873
874 if (ov5675->identified)
875 return 0;
876
877 ret = ov5675_read_reg(ov5675, OV5675_REG_CHIP_ID,
878 OV5675_REG_VALUE_24BIT, &val);
879 if (ret)
880 return ret;
881
882 if (val != OV5675_CHIP_ID) {
883 dev_err(ov5675->dev, "chip id mismatch: %x!=%x",
884 OV5675_CHIP_ID, val);
885 return -ENXIO;
886 }
887
888 ov5675->identified = true;
889
890 return 0;
891 }
892
ov5675_start_streaming(struct ov5675 * ov5675)893 static int ov5675_start_streaming(struct ov5675 *ov5675)
894 {
895 const struct ov5675_reg_list *reg_list;
896 int link_freq_index, ret;
897
898 ret = ov5675_identify_module(ov5675);
899 if (ret)
900 return ret;
901
902 link_freq_index = ov5675->cur_mode->link_freq_index;
903 reg_list = &link_freq_configs[link_freq_index].reg_list;
904 ret = ov5675_write_reg_list(ov5675, reg_list);
905 if (ret) {
906 dev_err(ov5675->dev, "failed to set plls");
907 return ret;
908 }
909
910 reg_list = &ov5675->cur_mode->reg_list;
911 ret = ov5675_write_reg_list(ov5675, reg_list);
912 if (ret) {
913 dev_err(ov5675->dev, "failed to set mode");
914 return ret;
915 }
916
917 ret = __v4l2_ctrl_handler_setup(ov5675->sd.ctrl_handler);
918 if (ret)
919 return ret;
920
921 ret = ov5675_write_reg(ov5675, OV5675_REG_MODE_SELECT,
922 OV5675_REG_VALUE_08BIT, OV5675_MODE_STREAMING);
923 if (ret) {
924 dev_err(ov5675->dev, "failed to set stream");
925 return ret;
926 }
927
928 return 0;
929 }
930
ov5675_stop_streaming(struct ov5675 * ov5675)931 static void ov5675_stop_streaming(struct ov5675 *ov5675)
932 {
933 if (ov5675_write_reg(ov5675, OV5675_REG_MODE_SELECT,
934 OV5675_REG_VALUE_08BIT, OV5675_MODE_STANDBY))
935 dev_err(ov5675->dev, "failed to set stream");
936 }
937
ov5675_set_stream(struct v4l2_subdev * sd,int enable)938 static int ov5675_set_stream(struct v4l2_subdev *sd, int enable)
939 {
940 struct ov5675 *ov5675 = to_ov5675(sd);
941 int ret = 0;
942
943 mutex_lock(&ov5675->mutex);
944 if (enable) {
945 ret = pm_runtime_resume_and_get(ov5675->dev);
946 if (ret < 0) {
947 mutex_unlock(&ov5675->mutex);
948 return ret;
949 }
950
951 ret = ov5675_start_streaming(ov5675);
952 if (ret) {
953 enable = 0;
954 ov5675_stop_streaming(ov5675);
955 pm_runtime_put(ov5675->dev);
956 }
957 } else {
958 ov5675_stop_streaming(ov5675);
959 pm_runtime_put(ov5675->dev);
960 }
961
962 mutex_unlock(&ov5675->mutex);
963
964 return ret;
965 }
966
ov5675_power_off(struct device * dev)967 static int ov5675_power_off(struct device *dev)
968 {
969 struct v4l2_subdev *sd = dev_get_drvdata(dev);
970 struct ov5675 *ov5675 = to_ov5675(sd);
971
972 usleep_range(90, 100);
973
974 clk_disable_unprepare(ov5675->xvclk);
975 gpiod_set_value_cansleep(ov5675->reset_gpio, 1);
976 regulator_bulk_disable(OV5675_NUM_SUPPLIES, ov5675->supplies);
977
978 return 0;
979 }
980
ov5675_power_on(struct device * dev)981 static int ov5675_power_on(struct device *dev)
982 {
983 struct v4l2_subdev *sd = dev_get_drvdata(dev);
984 struct ov5675 *ov5675 = to_ov5675(sd);
985 int ret;
986
987 ret = clk_prepare_enable(ov5675->xvclk);
988 if (ret < 0) {
989 dev_err(dev, "failed to enable xvclk: %d\n", ret);
990 return ret;
991 }
992
993 gpiod_set_value_cansleep(ov5675->reset_gpio, 1);
994
995 ret = regulator_bulk_enable(OV5675_NUM_SUPPLIES, ov5675->supplies);
996 if (ret) {
997 clk_disable_unprepare(ov5675->xvclk);
998 return ret;
999 }
1000
1001 /* Reset pulse should be at least 2ms and reset gpio released only once
1002 * regulators are stable.
1003 */
1004 usleep_range(2000, 2200);
1005
1006 gpiod_set_value_cansleep(ov5675->reset_gpio, 0);
1007
1008 /* Worst case quiesence gap is 1.365 milliseconds @ 6MHz XVCLK
1009 * Add an additional threshold grace period to ensure reset
1010 * completion before initiating our first I2C transaction.
1011 */
1012 usleep_range(1500, 1600);
1013
1014 return 0;
1015 }
1016
ov5675_set_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)1017 static int ov5675_set_format(struct v4l2_subdev *sd,
1018 struct v4l2_subdev_state *sd_state,
1019 struct v4l2_subdev_format *fmt)
1020 {
1021 struct ov5675 *ov5675 = to_ov5675(sd);
1022 const struct ov5675_mode *mode;
1023 s32 vblank_def, h_blank;
1024
1025 mode = v4l2_find_nearest_size(supported_modes,
1026 ARRAY_SIZE(supported_modes), width,
1027 height, fmt->format.width,
1028 fmt->format.height);
1029
1030 mutex_lock(&ov5675->mutex);
1031 ov5675_update_pad_format(mode, &fmt->format);
1032 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
1033 *v4l2_subdev_state_get_format(sd_state, fmt->pad) = fmt->format;
1034 } else {
1035 ov5675->cur_mode = mode;
1036 __v4l2_ctrl_s_ctrl(ov5675->link_freq, mode->link_freq_index);
1037 __v4l2_ctrl_s_ctrl_int64(ov5675->pixel_rate,
1038 to_pixel_rate(mode->link_freq_index));
1039
1040 /* Update limits and set FPS to default */
1041 vblank_def = mode->vts_def - mode->height;
1042 __v4l2_ctrl_modify_range(ov5675->vblank,
1043 mode->vts_min - mode->height,
1044 OV5675_VTS_MAX - mode->height, 1,
1045 vblank_def);
1046 __v4l2_ctrl_s_ctrl(ov5675->vblank, vblank_def);
1047 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
1048 mode->width;
1049 __v4l2_ctrl_modify_range(ov5675->hblank, h_blank, h_blank, 1,
1050 h_blank);
1051 }
1052
1053 mutex_unlock(&ov5675->mutex);
1054
1055 return 0;
1056 }
1057
ov5675_get_format(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * fmt)1058 static int ov5675_get_format(struct v4l2_subdev *sd,
1059 struct v4l2_subdev_state *sd_state,
1060 struct v4l2_subdev_format *fmt)
1061 {
1062 struct ov5675 *ov5675 = to_ov5675(sd);
1063
1064 mutex_lock(&ov5675->mutex);
1065 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
1066 fmt->format = *v4l2_subdev_state_get_format(sd_state,
1067 fmt->pad);
1068 else
1069 ov5675_update_pad_format(ov5675->cur_mode, &fmt->format);
1070
1071 mutex_unlock(&ov5675->mutex);
1072
1073 return 0;
1074 }
1075
ov5675_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_state * state,struct v4l2_subdev_selection * sel)1076 static int ov5675_get_selection(struct v4l2_subdev *sd,
1077 struct v4l2_subdev_state *state,
1078 struct v4l2_subdev_selection *sel)
1079 {
1080 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1081 return -EINVAL;
1082
1083 switch (sel->target) {
1084 case V4L2_SEL_TGT_CROP_BOUNDS:
1085 sel->r.top = 0;
1086 sel->r.left = 0;
1087 sel->r.width = 2624;
1088 sel->r.height = 2000;
1089 return 0;
1090 case V4L2_SEL_TGT_CROP:
1091 case V4L2_SEL_TGT_CROP_DEFAULT:
1092 sel->r.top = 16;
1093 sel->r.left = 16;
1094 sel->r.width = 2592;
1095 sel->r.height = 1944;
1096 return 0;
1097 }
1098 return -EINVAL;
1099 }
1100
ov5675_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)1101 static int ov5675_enum_mbus_code(struct v4l2_subdev *sd,
1102 struct v4l2_subdev_state *sd_state,
1103 struct v4l2_subdev_mbus_code_enum *code)
1104 {
1105 if (code->index > 0)
1106 return -EINVAL;
1107
1108 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
1109
1110 return 0;
1111 }
1112
ov5675_enum_frame_size(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_frame_size_enum * fse)1113 static int ov5675_enum_frame_size(struct v4l2_subdev *sd,
1114 struct v4l2_subdev_state *sd_state,
1115 struct v4l2_subdev_frame_size_enum *fse)
1116 {
1117 if (fse->index >= ARRAY_SIZE(supported_modes))
1118 return -EINVAL;
1119
1120 if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
1121 return -EINVAL;
1122
1123 fse->min_width = supported_modes[fse->index].width;
1124 fse->max_width = fse->min_width;
1125 fse->min_height = supported_modes[fse->index].height;
1126 fse->max_height = fse->min_height;
1127
1128 return 0;
1129 }
1130
ov5675_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)1131 static int ov5675_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1132 {
1133 struct ov5675 *ov5675 = to_ov5675(sd);
1134
1135 mutex_lock(&ov5675->mutex);
1136 ov5675_update_pad_format(&supported_modes[0],
1137 v4l2_subdev_state_get_format(fh->state, 0));
1138 mutex_unlock(&ov5675->mutex);
1139
1140 return 0;
1141 }
1142
1143 static const struct v4l2_subdev_video_ops ov5675_video_ops = {
1144 .s_stream = ov5675_set_stream,
1145 };
1146
1147 static const struct v4l2_subdev_pad_ops ov5675_pad_ops = {
1148 .set_fmt = ov5675_set_format,
1149 .get_fmt = ov5675_get_format,
1150 .get_selection = ov5675_get_selection,
1151 .enum_mbus_code = ov5675_enum_mbus_code,
1152 .enum_frame_size = ov5675_enum_frame_size,
1153 };
1154
1155 static const struct v4l2_subdev_ops ov5675_subdev_ops = {
1156 .video = &ov5675_video_ops,
1157 .pad = &ov5675_pad_ops,
1158 };
1159
1160 static const struct media_entity_operations ov5675_subdev_entity_ops = {
1161 .link_validate = v4l2_subdev_link_validate,
1162 };
1163
1164 static const struct v4l2_subdev_internal_ops ov5675_internal_ops = {
1165 .open = ov5675_open,
1166 };
1167
ov5675_get_hwcfg(struct ov5675 * ov5675)1168 static int ov5675_get_hwcfg(struct ov5675 *ov5675)
1169 {
1170 struct device *dev = ov5675->dev;
1171 struct fwnode_handle *ep;
1172 struct fwnode_handle *fwnode = dev_fwnode(dev);
1173 struct v4l2_fwnode_endpoint bus_cfg = {
1174 .bus_type = V4L2_MBUS_CSI2_DPHY
1175 };
1176 u32 xvclk_rate;
1177 int ret;
1178 unsigned int i, j;
1179
1180 if (!fwnode)
1181 return -ENXIO;
1182
1183 ep = fwnode_graph_get_endpoint_by_id(fwnode, 0, 0,
1184 FWNODE_GRAPH_ENDPOINT_NEXT);
1185 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1186 fwnode_handle_put(ep);
1187 if (ret)
1188 return ret;
1189
1190 ov5675->xvclk = devm_v4l2_sensor_clk_get(dev, NULL);
1191 if (IS_ERR(ov5675->xvclk)) {
1192 ret = dev_err_probe(dev, PTR_ERR(ov5675->xvclk),
1193 "failed to get xvclk\n");
1194 goto check_hwcfg_error;
1195 }
1196
1197 xvclk_rate = clk_get_rate(ov5675->xvclk);
1198 if (xvclk_rate != OV5675_XVCLK_19_2) {
1199 dev_err(dev, "external clock rate %u is unsupported",
1200 xvclk_rate);
1201 ret = -EINVAL;
1202 goto check_hwcfg_error;
1203 }
1204
1205 ov5675->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1206 GPIOD_OUT_HIGH);
1207 if (IS_ERR(ov5675->reset_gpio)) {
1208 ret = PTR_ERR(ov5675->reset_gpio);
1209 dev_err(dev, "failed to get reset-gpios: %d\n", ret);
1210 goto check_hwcfg_error;
1211 }
1212
1213 for (i = 0; i < OV5675_NUM_SUPPLIES; i++)
1214 ov5675->supplies[i].supply = ov5675_supply_names[i];
1215
1216 ret = devm_regulator_bulk_get(dev, OV5675_NUM_SUPPLIES,
1217 ov5675->supplies);
1218 if (ret)
1219 goto check_hwcfg_error;
1220
1221 if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV5675_DATA_LANES) {
1222 dev_err(dev, "number of CSI2 data lanes %d is not supported",
1223 bus_cfg.bus.mipi_csi2.num_data_lanes);
1224 ret = -EINVAL;
1225 goto check_hwcfg_error;
1226 }
1227
1228 if (!bus_cfg.nr_of_link_frequencies) {
1229 dev_err(dev, "no link frequencies defined");
1230 ret = -EINVAL;
1231 goto check_hwcfg_error;
1232 }
1233
1234 for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1235 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1236 if (link_freq_menu_items[i] ==
1237 bus_cfg.link_frequencies[j])
1238 break;
1239 }
1240
1241 if (j == bus_cfg.nr_of_link_frequencies) {
1242 dev_err(dev, "no link frequency %lld supported",
1243 link_freq_menu_items[i]);
1244 ret = -EINVAL;
1245 goto check_hwcfg_error;
1246 }
1247 }
1248
1249 check_hwcfg_error:
1250 v4l2_fwnode_endpoint_free(&bus_cfg);
1251
1252 return ret;
1253 }
1254
ov5675_remove(struct i2c_client * client)1255 static void ov5675_remove(struct i2c_client *client)
1256 {
1257 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1258 struct ov5675 *ov5675 = to_ov5675(sd);
1259
1260 v4l2_async_unregister_subdev(sd);
1261 media_entity_cleanup(&sd->entity);
1262 v4l2_ctrl_handler_free(sd->ctrl_handler);
1263 pm_runtime_disable(ov5675->dev);
1264 mutex_destroy(&ov5675->mutex);
1265
1266 if (!pm_runtime_status_suspended(ov5675->dev))
1267 ov5675_power_off(ov5675->dev);
1268 pm_runtime_set_suspended(ov5675->dev);
1269 }
1270
ov5675_probe(struct i2c_client * client)1271 static int ov5675_probe(struct i2c_client *client)
1272 {
1273 struct ov5675 *ov5675;
1274 bool full_power;
1275 int ret;
1276
1277 ov5675 = devm_kzalloc(&client->dev, sizeof(*ov5675), GFP_KERNEL);
1278 if (!ov5675)
1279 return -ENOMEM;
1280
1281 ov5675->dev = &client->dev;
1282
1283 ret = ov5675_get_hwcfg(ov5675);
1284 if (ret)
1285 return ret;
1286
1287 v4l2_i2c_subdev_init(&ov5675->sd, client, &ov5675_subdev_ops);
1288
1289 ret = ov5675_power_on(ov5675->dev);
1290 if (ret) {
1291 dev_err(ov5675->dev, "failed to power on: %d\n", ret);
1292 return ret;
1293 }
1294
1295 full_power = acpi_dev_state_d0(ov5675->dev);
1296 if (full_power) {
1297 ret = ov5675_identify_module(ov5675);
1298 if (ret) {
1299 dev_err(ov5675->dev, "failed to find sensor: %d", ret);
1300 goto probe_power_off;
1301 }
1302 }
1303
1304 mutex_init(&ov5675->mutex);
1305 ov5675->cur_mode = &supported_modes[0];
1306 ret = ov5675_init_controls(ov5675);
1307 if (ret) {
1308 dev_err(ov5675->dev, "failed to init controls: %d", ret);
1309 goto probe_error_v4l2_ctrl_handler_free;
1310 }
1311
1312 ov5675->sd.internal_ops = &ov5675_internal_ops;
1313 ov5675->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1314 ov5675->sd.entity.ops = &ov5675_subdev_entity_ops;
1315 ov5675->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1316 ov5675->pad.flags = MEDIA_PAD_FL_SOURCE;
1317 ret = media_entity_pads_init(&ov5675->sd.entity, 1, &ov5675->pad);
1318 if (ret) {
1319 dev_err(ov5675->dev, "failed to init entity pads: %d", ret);
1320 goto probe_error_v4l2_ctrl_handler_free;
1321 }
1322
1323 ret = v4l2_async_register_subdev_sensor(&ov5675->sd);
1324 if (ret < 0) {
1325 dev_err(ov5675->dev, "failed to register V4L2 subdev: %d",
1326 ret);
1327 goto probe_error_media_entity_cleanup;
1328 }
1329
1330 /* Set the device's state to active if it's in D0 state. */
1331 if (full_power)
1332 pm_runtime_set_active(ov5675->dev);
1333 pm_runtime_enable(ov5675->dev);
1334 pm_runtime_idle(ov5675->dev);
1335
1336 return 0;
1337
1338 probe_error_media_entity_cleanup:
1339 media_entity_cleanup(&ov5675->sd.entity);
1340
1341 probe_error_v4l2_ctrl_handler_free:
1342 v4l2_ctrl_handler_free(ov5675->sd.ctrl_handler);
1343 mutex_destroy(&ov5675->mutex);
1344 probe_power_off:
1345 ov5675_power_off(ov5675->dev);
1346
1347 return ret;
1348 }
1349
1350 static const struct dev_pm_ops ov5675_pm_ops = {
1351 SET_RUNTIME_PM_OPS(ov5675_power_off, ov5675_power_on, NULL)
1352 };
1353
1354 #ifdef CONFIG_ACPI
1355 static const struct acpi_device_id ov5675_acpi_ids[] = {
1356 {"OVTI5675"},
1357 {}
1358 };
1359
1360 MODULE_DEVICE_TABLE(acpi, ov5675_acpi_ids);
1361 #endif
1362
1363 static const struct of_device_id ov5675_of_match[] = {
1364 { .compatible = "ovti,ov5675", },
1365 { /* sentinel */ },
1366 };
1367 MODULE_DEVICE_TABLE(of, ov5675_of_match);
1368
1369 static struct i2c_driver ov5675_i2c_driver = {
1370 .driver = {
1371 .name = "ov5675",
1372 .pm = &ov5675_pm_ops,
1373 .acpi_match_table = ACPI_PTR(ov5675_acpi_ids),
1374 .of_match_table = ov5675_of_match,
1375 },
1376 .probe = ov5675_probe,
1377 .remove = ov5675_remove,
1378 .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
1379 };
1380
1381 module_i2c_driver(ov5675_i2c_driver);
1382
1383 MODULE_AUTHOR("Shawn Tu");
1384 MODULE_DESCRIPTION("OmniVision OV5675 sensor driver");
1385 MODULE_LICENSE("GPL v2");
1386