1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2023 Nuvoton Technology Corp.
4 * Author: Chi-Fang Li <cfli0@nuvoton.com>
5 */
6
7 #include <linux/clk-provider.h>
8 #include <linux/device.h>
9 #include <linux/regmap.h>
10 #include <linux/spinlock.h>
11
12 #include "clk-ma35d1.h"
13
14 struct ma35d1_adc_clk_div {
15 struct clk_hw hw;
16 void __iomem *reg;
17 u8 shift;
18 u8 width;
19 u32 mask;
20 const struct clk_div_table *table;
21 /* protects concurrent access to clock divider registers */
22 spinlock_t *lock;
23 };
24
to_ma35d1_adc_clk_div(struct clk_hw * _hw)25 static inline struct ma35d1_adc_clk_div *to_ma35d1_adc_clk_div(struct clk_hw *_hw)
26 {
27 return container_of(_hw, struct ma35d1_adc_clk_div, hw);
28 }
29
ma35d1_clkdiv_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)30 static unsigned long ma35d1_clkdiv_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
31 {
32 unsigned int val;
33 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);
34
35 val = readl_relaxed(dclk->reg) >> dclk->shift;
36 val &= clk_div_mask(dclk->width);
37 val += 1;
38 return divider_recalc_rate(hw, parent_rate, val, dclk->table,
39 CLK_DIVIDER_ROUND_CLOSEST, dclk->width);
40 }
41
ma35d1_clkdiv_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)42 static int ma35d1_clkdiv_determine_rate(struct clk_hw *hw,
43 struct clk_rate_request *req)
44 {
45 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);
46
47 req->rate = divider_round_rate(hw, req->rate, &req->best_parent_rate,
48 dclk->table, dclk->width,
49 CLK_DIVIDER_ROUND_CLOSEST);
50
51 return 0;
52 }
53
ma35d1_clkdiv_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)54 static int ma35d1_clkdiv_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate)
55 {
56 int value;
57 unsigned long flags = 0;
58 u32 data;
59 struct ma35d1_adc_clk_div *dclk = to_ma35d1_adc_clk_div(hw);
60
61 value = divider_get_val(rate, parent_rate, dclk->table,
62 dclk->width, CLK_DIVIDER_ROUND_CLOSEST);
63
64 spin_lock_irqsave(dclk->lock, flags);
65
66 data = readl_relaxed(dclk->reg);
67 data &= ~(clk_div_mask(dclk->width) << dclk->shift);
68 data |= (value - 1) << dclk->shift;
69 data |= dclk->mask;
70 writel_relaxed(data, dclk->reg);
71
72 spin_unlock_irqrestore(dclk->lock, flags);
73 return 0;
74 }
75
76 static const struct clk_ops ma35d1_adc_clkdiv_ops = {
77 .recalc_rate = ma35d1_clkdiv_recalc_rate,
78 .determine_rate = ma35d1_clkdiv_determine_rate,
79 .set_rate = ma35d1_clkdiv_set_rate,
80 };
81
ma35d1_reg_adc_clkdiv(struct device * dev,const char * name,struct clk_hw * parent_hw,spinlock_t * lock,unsigned long flags,void __iomem * reg,u8 shift,u8 width,u32 mask_bit)82 struct clk_hw *ma35d1_reg_adc_clkdiv(struct device *dev, const char *name,
83 struct clk_hw *parent_hw, spinlock_t *lock,
84 unsigned long flags, void __iomem *reg,
85 u8 shift, u8 width, u32 mask_bit)
86 {
87 struct ma35d1_adc_clk_div *div;
88 struct clk_init_data init;
89 struct clk_div_table *table;
90 struct clk_parent_data pdata = { .index = 0 };
91 u32 max_div, min_div;
92 struct clk_hw *hw;
93 int ret;
94 int i;
95
96 div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
97 if (!div)
98 return ERR_PTR(-ENOMEM);
99
100 max_div = clk_div_mask(width) + 1;
101 min_div = 1;
102
103 table = devm_kcalloc(dev, max_div + 1, sizeof(*table), GFP_KERNEL);
104 if (!table)
105 return ERR_PTR(-ENOMEM);
106
107 for (i = 0; i < max_div; i++) {
108 table[i].val = min_div + i;
109 table[i].div = 2 * table[i].val;
110 }
111 table[max_div].val = 0;
112 table[max_div].div = 0;
113
114 memset(&init, 0, sizeof(init));
115 init.name = name;
116 init.ops = &ma35d1_adc_clkdiv_ops;
117 init.flags |= flags;
118 pdata.hw = parent_hw;
119 init.parent_data = &pdata;
120 init.num_parents = 1;
121
122 div->reg = reg;
123 div->shift = shift;
124 div->width = width;
125 div->mask = mask_bit ? BIT(mask_bit) : 0;
126 div->lock = lock;
127 div->hw.init = &init;
128 div->table = table;
129
130 hw = &div->hw;
131 ret = devm_clk_hw_register(dev, hw);
132 if (ret)
133 return ERR_PTR(ret);
134 return hw;
135 }
136 EXPORT_SYMBOL_GPL(ma35d1_reg_adc_clkdiv);
137