1 /* 2 * Copyright 2018-2024 Advanced Micro Devices, Inc. All rights reserved. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #include <linux/firmware.h> 25 #include <linux/kernfs.h> 26 27 #include "amdgpu.h" 28 #include "amdgpu_discovery.h" 29 #include "amdgpu_ualink.h" 30 #include "soc15_hw_ip.h" 31 #include "discovery.h" 32 #include "amdgpu_ras.h" 33 34 #include "soc15.h" 35 #include "gfx_v9_0.h" 36 #include "gfx_v9_4_3.h" 37 #include "gmc_v9_0.h" 38 #include "df_v1_7.h" 39 #include "df_v3_6.h" 40 #include "df_v4_3.h" 41 #include "df_v4_6_2.h" 42 #include "df_v4_15.h" 43 #include "nbio_v6_1.h" 44 #include "nbio_v7_0.h" 45 #include "nbio_v7_4.h" 46 #include "nbio_v7_9.h" 47 #include "nbio_v7_11.h" 48 #include "nbio_v7_11_5.h" 49 #include "hdp_v4_0.h" 50 #include "vega10_ih.h" 51 #include "vega20_ih.h" 52 #include "sdma_v4_0.h" 53 #include "sdma_v4_4_2.h" 54 #include "uvd_v7_0.h" 55 #include "vce_v4_0.h" 56 #include "vcn_v1_0.h" 57 #include "vcn_v2_5.h" 58 #include "jpeg_v2_5.h" 59 #include "smuio_v9_0.h" 60 #include "gmc_v10_0.h" 61 #include "gmc_v11_0.h" 62 #include "gmc_v12_0.h" 63 #include "gfxhub_v2_0.h" 64 #include "mmhub_v2_0.h" 65 #include "nbio_v2_3.h" 66 #include "nbio_v4_3.h" 67 #include "nbio_v7_2.h" 68 #include "nbio_v7_7.h" 69 #include "nbif_v6_3_1.h" 70 #include "nbio_v6_3_2.h" 71 #include "nbif_v7_10.h" 72 #include "hdp_v5_0.h" 73 #include "hdp_v5_2.h" 74 #include "hdp_v6_0.h" 75 #include "hdp_v7_0.h" 76 #include "hdp_v8_0.h" 77 #include "nv.h" 78 #include "soc21.h" 79 #include "soc24.h" 80 #include "soc_v1_0.h" 81 #include "navi10_ih.h" 82 #include "ih_v6_0.h" 83 #include "ih_v6_1.h" 84 #include "ih_v7_0.h" 85 #include "ih_v8_0.h" 86 #include "gfx_v10_0.h" 87 #include "gfx_v11_0.h" 88 #include "gfx_v12_0.h" 89 #include "gfx_v12_1.h" 90 #include "sdma_v5_0.h" 91 #include "sdma_v5_2.h" 92 #include "sdma_v6_0.h" 93 #include "sdma_v7_0.h" 94 #include "sdma_v7_1.h" 95 #include "lsdma_v6_0.h" 96 #include "lsdma_v7_0.h" 97 #include "lsdma_v7_1.h" 98 #include "lsdma_v8_0.h" 99 #include "vcn_v2_0.h" 100 #include "jpeg_v2_0.h" 101 #include "vcn_v3_0.h" 102 #include "jpeg_v3_0.h" 103 #include "vcn_v4_0.h" 104 #include "jpeg_v4_0.h" 105 #include "vcn_v4_0_3.h" 106 #include "jpeg_v4_0_3.h" 107 #include "vcn_v4_0_5.h" 108 #include "jpeg_v4_0_5.h" 109 #include "amdgpu_vkms.h" 110 #include "mes_v11_0.h" 111 #include "mes_v12_0.h" 112 #include "mes_v12_1.h" 113 #include "smuio_v11_0.h" 114 #include "smuio_v11_0_6.h" 115 #include "smuio_v13_0.h" 116 #include "smuio_v13_0_3.h" 117 #include "smuio_v13_0_6.h" 118 #include "smuio_v14_0_2.h" 119 #include "smuio_v15_0_0.h" 120 #include "smuio_v15_0_3.h" 121 #include "smuio_v15_0_8.h" 122 #include "vcn_v5_0_0.h" 123 #include "vcn_v5_0_1.h" 124 #include "vcn_v5_0_2.h" 125 #include "jpeg_v5_0_0.h" 126 #include "jpeg_v5_0_1.h" 127 #include "jpeg_v5_0_2.h" 128 #include "jpeg_v5_3_0.h" 129 130 #include "amdgpu_ras_mgr.h" 131 132 #include "amdgpu_vpe.h" 133 #if defined(CONFIG_DRM_AMD_ISP) 134 #include "amdgpu_isp.h" 135 #endif 136 137 MODULE_FIRMWARE("amdgpu/ip_discovery.bin"); 138 MODULE_FIRMWARE("amdgpu/vega10_ip_discovery.bin"); 139 MODULE_FIRMWARE("amdgpu/vega12_ip_discovery.bin"); 140 MODULE_FIRMWARE("amdgpu/vega20_ip_discovery.bin"); 141 MODULE_FIRMWARE("amdgpu/raven_ip_discovery.bin"); 142 MODULE_FIRMWARE("amdgpu/raven2_ip_discovery.bin"); 143 MODULE_FIRMWARE("amdgpu/picasso_ip_discovery.bin"); 144 MODULE_FIRMWARE("amdgpu/arcturus_ip_discovery.bin"); 145 MODULE_FIRMWARE("amdgpu/aldebaran_ip_discovery.bin"); 146 147 /* Note: These registers are consistent across all the SOCs */ 148 #define mmIP_DISCOVERY_VERSION 0x16A00 149 #define mmRCC_CONFIG_MEMSIZE 0xde3 150 #define mmRCC_HW_DEBUG 0x10c01 151 #define mmMP0_SMN_C2PMSG_33 0x16061 152 #define mmMM_INDEX 0x0 153 #define mmMM_INDEX_HI 0x6 154 #define mmMM_DATA 0x1 155 156 #define mmDRIVER_SCRATCH_0 0x94 157 #define mmDRIVER_SCRATCH_1 0x95 158 #define mmDRIVER_SCRATCH_2 0x96 159 160 struct ip_discovery_top { 161 struct kobject kobj; 162 struct kset die_kset; 163 struct pci_dev *pdev; 164 struct amdgpu_device *adev; 165 uint8_t *discovery_bin; 166 uint32_t bin_size; 167 bool standalone_mode; 168 }; 169 170 /* List to track early-initialized ip_discovery_top entries */ 171 struct early_ip_discovery { 172 struct list_head list; 173 struct pci_dev *pdev; 174 struct ip_discovery_top *ip_top; 175 }; 176 177 static LIST_HEAD(early_ip_discovery_list); 178 static DEFINE_MUTEX(early_ip_discovery_mutex); 179 180 static const char *hw_id_names[HW_ID_MAX] = { 181 [MP1_HWID] = "MP1", 182 [MP2_HWID] = "MP2", 183 [THM_HWID] = "THM", 184 [SMUIO_HWID] = "SMUIO", 185 [FUSE_HWID] = "FUSE", 186 [CLKA_HWID] = "CLKA", 187 [PWR_HWID] = "PWR", 188 [GC_HWID] = "GC", 189 [UVD_HWID] = "UVD", 190 [AUDIO_AZ_HWID] = "AUDIO_AZ", 191 [ACP_HWID] = "ACP", 192 [DCI_HWID] = "DCI", 193 [DMU_HWID] = "DMU", 194 [DCO_HWID] = "DCO", 195 [DIO_HWID] = "DIO", 196 [XDMA_HWID] = "XDMA", 197 [DCEAZ_HWID] = "DCEAZ", 198 [DAZ_HWID] = "DAZ", 199 [SDPMUX_HWID] = "SDPMUX", 200 [NTB_HWID] = "NTB", 201 [IOHC_HWID] = "IOHC", 202 [L2IMU_HWID] = "L2IMU", 203 [VCE_HWID] = "VCE", 204 [MMHUB_HWID] = "MMHUB", 205 [ATHUB_HWID] = "ATHUB", 206 [DBGU_NBIO_HWID] = "DBGU_NBIO", 207 [DFX_HWID] = "DFX", 208 [DBGU0_HWID] = "DBGU0", 209 [DBGU1_HWID] = "DBGU1", 210 [OSSSYS_HWID] = "OSSSYS", 211 [HDP_HWID] = "HDP", 212 [SDMA0_HWID] = "SDMA0", 213 [SDMA1_HWID] = "SDMA1", 214 [SDMA2_HWID] = "SDMA2", 215 [SDMA3_HWID] = "SDMA3", 216 [LSDMA_HWID] = "LSDMA", 217 [ISP_HWID] = "ISP", 218 [DBGU_IO_HWID] = "DBGU_IO", 219 [DF_HWID] = "DF", 220 [CLKB_HWID] = "CLKB", 221 [FCH_HWID] = "FCH", 222 [DFX_DAP_HWID] = "DFX_DAP", 223 [L1IMU_PCIE_HWID] = "L1IMU_PCIE", 224 [L1IMU_NBIF_HWID] = "L1IMU_NBIF", 225 [L1IMU_IOAGR_HWID] = "L1IMU_IOAGR", 226 [L1IMU3_HWID] = "L1IMU3", 227 [L1IMU4_HWID] = "L1IMU4", 228 [L1IMU5_HWID] = "L1IMU5", 229 [L1IMU6_HWID] = "L1IMU6", 230 [L1IMU7_HWID] = "L1IMU7", 231 [L1IMU8_HWID] = "L1IMU8", 232 [L1IMU9_HWID] = "L1IMU9", 233 [L1IMU10_HWID] = "L1IMU10", 234 [L1IMU11_HWID] = "L1IMU11", 235 [L1IMU12_HWID] = "L1IMU12", 236 [L1IMU13_HWID] = "L1IMU13", 237 [L1IMU14_HWID] = "L1IMU14", 238 [L1IMU15_HWID] = "L1IMU15", 239 [WAFLC_HWID] = "WAFLC", 240 [FCH_USB_PD_HWID] = "FCH_USB_PD", 241 [PCIE_HWID] = "PCIE", 242 [PCS_HWID] = "PCS", 243 [DDCL_HWID] = "DDCL", 244 [SST_HWID] = "SST", 245 [IOAGR_HWID] = "IOAGR", 246 [NBIF_HWID] = "NBIF", 247 [IOAPIC_HWID] = "IOAPIC", 248 [SYSTEMHUB_HWID] = "SYSTEMHUB", 249 [NTBCCP_HWID] = "NTBCCP", 250 [UMC_HWID] = "UMC", 251 [SATA_HWID] = "SATA", 252 [USB_HWID] = "USB", 253 [CCXSEC_HWID] = "CCXSEC", 254 [XGMI_HWID] = "XGMI", 255 [XGBE_HWID] = "XGBE", 256 [MP0_HWID] = "MP0", 257 [VPE_HWID] = "VPE", 258 [UMSCH_HWID] = "UMSCH", 259 [ATU_HWID] = "ATU", 260 [AIGC_HWID] = "AIGC", 261 }; 262 263 static int hw_id_map[MAX_HWIP] = { 264 [GC_HWIP] = GC_HWID, 265 [HDP_HWIP] = HDP_HWID, 266 [SDMA0_HWIP] = SDMA0_HWID, 267 [SDMA1_HWIP] = SDMA1_HWID, 268 [SDMA2_HWIP] = SDMA2_HWID, 269 [SDMA3_HWIP] = SDMA3_HWID, 270 [LSDMA_HWIP] = LSDMA_HWID, 271 [MMHUB_HWIP] = MMHUB_HWID, 272 [ATHUB_HWIP] = ATHUB_HWID, 273 [NBIO_HWIP] = NBIF_HWID, 274 [MP0_HWIP] = MP0_HWID, 275 [MP1_HWIP] = MP1_HWID, 276 [UVD_HWIP] = UVD_HWID, 277 [VCE_HWIP] = VCE_HWID, 278 [DF_HWIP] = DF_HWID, 279 [DCE_HWIP] = DMU_HWID, 280 [OSSSYS_HWIP] = OSSSYS_HWID, 281 [SMUIO_HWIP] = SMUIO_HWID, 282 [PWR_HWIP] = PWR_HWID, 283 [NBIF_HWIP] = NBIF_HWID, 284 [THM_HWIP] = THM_HWID, 285 [CLK_HWIP] = CLKA_HWID, 286 [UMC_HWIP] = UMC_HWID, 287 [XGMI_HWIP] = XGMI_HWID, 288 [DCI_HWIP] = DCI_HWID, 289 [PCIE_HWIP] = PCIE_HWID, 290 [VPE_HWIP] = VPE_HWID, 291 [UMSCH_HWIP] = UMSCH_HWID, 292 [ISP_HWIP] = ISP_HWID, 293 [ATU_HWIP] = ATU_HWID, 294 }; 295 296 static u32 amdgpu_discovery_get_config_memsize(struct amdgpu_device *adev) 297 { 298 u32 memsize = RREG32(mmRCC_CONFIG_MEMSIZE); 299 300 /* Fall back to RCC_HW_DEBUG when RCC_CONFIG_MEMSIZE reads 0 on a VF. */ 301 if (!memsize && amdgpu_sriov_vf(adev)) 302 memsize = RREG32(mmRCC_HW_DEBUG); 303 304 return memsize; 305 } 306 307 static int amdgpu_discovery_get_tmr_info(struct amdgpu_device *adev, 308 bool *is_tmr_in_sysmem) 309 { 310 u64 vram_size, tmr_offset, tmr_size; 311 u32 msg, tmr_offset_lo, tmr_offset_hi; 312 int i, ret; 313 314 if (!amdgpu_sriov_vf(adev)) { 315 /* It can take up to two second for IFWI init to complete on some dGPUs, 316 * but generally it should be in the 60-100ms range. Normally this starts 317 * as soon as the device gets power so by the time the OS loads this has long 318 * completed. However, when a card is hotplugged via e.g., USB4, we need to 319 * wait for this to complete. Once the C2PMSG is updated, we can 320 * continue. 321 */ 322 323 for (i = 0; i < 2000; i++) { 324 msg = RREG32(mmMP0_SMN_C2PMSG_33); 325 if (msg & 0x80000000) 326 break; 327 msleep(1); 328 } 329 } 330 331 vram_size = amdgpu_discovery_get_config_memsize(adev); 332 if (vram_size == U32_MAX) 333 return -ENXIO; 334 else if (!vram_size) 335 *is_tmr_in_sysmem = true; 336 else 337 *is_tmr_in_sysmem = false; 338 339 /* init the default tmr size and offset */ 340 adev->discovery.size = DISCOVERY_TMR_SIZE; 341 if (vram_size) 342 adev->discovery.offset = (vram_size << 20) - DISCOVERY_TMR_OFFSET; 343 344 if (amdgpu_sriov_vf(adev)) { 345 if (adev->virt.is_dynamic_crit_regn_enabled) { 346 adev->discovery.offset = 347 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].offset; 348 adev->discovery.size = 349 adev->virt.crit_regn_tbl[AMD_SRIOV_MSG_IPD_TABLE_ID].size_kb << 10; 350 if (!adev->discovery.size) 351 return -EINVAL; 352 } else { 353 goto out; 354 } 355 } else { 356 if (adev->discovery.offset) { 357 u32 signature; 358 359 /* If VRAM holds a valid discovery signature at the default 360 * discovery offset, use it as-is. 361 */ 362 amdgpu_device_vram_access(adev, adev->discovery.offset, 363 &signature, sizeof(signature), 364 false); 365 if (le32_to_cpu(signature) == BINARY_SIGNATURE) 366 goto out; 367 } 368 369 tmr_size = RREG32(mmDRIVER_SCRATCH_2); 370 if (tmr_size) { 371 /* It's preferred to transition to PSP mailbox reg interface 372 * for both bare-metal and passthrough if available */ 373 adev->discovery.size = (u32)tmr_size; 374 tmr_offset_lo = RREG32(mmDRIVER_SCRATCH_0); 375 tmr_offset_hi = RREG32(mmDRIVER_SCRATCH_1); 376 adev->discovery.offset = ((u64)le32_to_cpu(tmr_offset_hi) << 32 | 377 le32_to_cpu(tmr_offset_lo)); 378 adev->discovery.reserve_tmr = true; 379 } else if (!vram_size) { 380 /* fall back to apci approach to query tmr offset if vram_size is 0 */ 381 ret = amdgpu_acpi_get_tmr_info(adev, &tmr_offset, &tmr_size); 382 if (ret) 383 return ret; 384 adev->discovery.size = DISCOVERY_TMR_SIZE; 385 adev->discovery.offset = tmr_offset + tmr_size - DISCOVERY_TMR_OFFSET; 386 } 387 } 388 out: 389 adev->discovery.bin = kzalloc(adev->discovery.size, GFP_KERNEL); 390 if (!adev->discovery.bin) 391 return -ENOMEM; 392 adev->discovery.debugfs_blob.data = adev->discovery.bin; 393 adev->discovery.debugfs_blob.size = adev->discovery.size; 394 395 return 0; 396 } 397 398 static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) 399 { 400 void *discv_regn; 401 402 /* This region is read-only and reserved from system use */ 403 discv_regn = memremap(adev->discovery.offset, adev->discovery.size, MEMREMAP_WC); 404 if (discv_regn) { 405 memcpy(binary, discv_regn, adev->discovery.size); 406 memunmap(discv_regn); 407 return 0; 408 } 409 410 return -ENOENT; 411 } 412 413 #define IP_DISCOVERY_V2 2 414 #define IP_DISCOVERY_V4 4 415 416 static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, 417 uint8_t *binary, 418 bool is_tmr_in_sysmem) 419 { 420 int ret = 0; 421 422 if (!is_tmr_in_sysmem) { 423 if (amdgpu_sriov_vf(adev) && 424 amdgpu_sriov_xgmi_connected_to_cpu(adev)) { 425 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 426 } else { 427 amdgpu_device_vram_access(adev, adev->discovery.offset, 428 (uint32_t *)binary, 429 adev->discovery.size, false); 430 adev->discovery.reserve_tmr = true; 431 } 432 } else { 433 ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); 434 } 435 436 return ret; 437 } 438 439 static int amdgpu_discovery_read_binary_from_file(struct amdgpu_device *adev, 440 uint8_t *binary, 441 const char *fw_name) 442 { 443 const struct firmware *fw; 444 int r; 445 446 r = firmware_request_nowarn(&fw, fw_name, adev->dev); 447 if (r) { 448 if (amdgpu_discovery == 2) 449 dev_err(adev->dev, "can't load firmware \"%s\"\n", fw_name); 450 else 451 drm_info(&adev->ddev, "Optional firmware \"%s\" was not found\n", fw_name); 452 return r; 453 } 454 455 if (fw->size > adev->discovery.size) { 456 dev_err(adev->dev, 457 "ip discovery firmware \"%s\" too large (%zu > %u)\n", 458 fw_name, fw->size, adev->discovery.size); 459 release_firmware(fw); 460 return -EINVAL; 461 } 462 463 /* Ensure the firmware is at least large enough to contain the 464 * binary header fields. 465 */ 466 if (fw->size < offsetof(struct binary_header, binary_size) + 467 sizeof(((struct binary_header *)0)->binary_size)) { 468 dev_err(adev->dev, 469 "ip discovery firmware \"%s\" too small (%zu)\n", 470 fw_name, fw->size); 471 release_firmware(fw); 472 return -EINVAL; 473 } 474 475 memcpy((u8 *)binary, (u8 *)fw->data, fw->size); 476 release_firmware(fw); 477 478 return 0; 479 } 480 481 static uint16_t amdgpu_discovery_calculate_checksum(uint8_t *data, uint32_t size) 482 { 483 uint16_t checksum = 0; 484 int i; 485 486 for (i = 0; i < size; i++) 487 checksum += data[i]; 488 489 return checksum; 490 } 491 492 static inline bool amdgpu_discovery_verify_checksum(struct amdgpu_device *adev, 493 uint8_t *data, uint32_t size, 494 uint16_t expected) 495 { 496 uint16_t calculated; 497 498 calculated = amdgpu_discovery_calculate_checksum(data, size); 499 500 if (calculated != expected) { 501 dev_err(adev->dev, "Discovery checksum failed: calc 0x%04x != exp 0x%04x, size %u.\n", 502 calculated, expected, size); 503 return false; 504 } 505 506 return true; 507 } 508 509 static inline bool amdgpu_discovery_verify_binary_signature(uint8_t *binary) 510 { 511 struct binary_header *bhdr; 512 bhdr = (struct binary_header *)binary; 513 514 return (le32_to_cpu(bhdr->binary_signature) == BINARY_SIGNATURE); 515 } 516 517 static void amdgpu_discovery_harvest_config_quirk(struct amdgpu_device *adev) 518 { 519 /* 520 * So far, apply this quirk only on those Navy Flounder boards which 521 * have a bad harvest table of VCN config. 522 */ 523 if ((amdgpu_ip_version(adev, UVD_HWIP, 1) == IP_VERSION(3, 0, 1)) && 524 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 2))) { 525 switch (adev->pdev->revision) { 526 case 0xC1: 527 case 0xC2: 528 case 0xC3: 529 case 0xC5: 530 case 0xC7: 531 case 0xCF: 532 case 0xDF: 533 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 534 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; 535 break; 536 default: 537 break; 538 } 539 } 540 } 541 542 static int amdgpu_discovery_verify_npsinfo(struct amdgpu_device *adev, 543 struct table_info *info) 544 { 545 uint8_t *discovery_bin = adev->discovery.bin; 546 uint16_t checksum; 547 uint16_t offset; 548 549 offset = le16_to_cpu(info->offset); 550 checksum = le16_to_cpu(info->checksum); 551 552 struct nps_info_header *nhdr = 553 (struct nps_info_header *)(discovery_bin + offset); 554 555 if (le32_to_cpu(nhdr->table_id) != NPS_INFO_TABLE_ID) { 556 dev_dbg(adev->dev, "invalid ip discovery nps info table id\n"); 557 return -EINVAL; 558 } 559 560 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 561 le32_to_cpu(nhdr->size_bytes), 562 checksum)) { 563 dev_dbg(adev->dev, "invalid nps info data table checksum\n"); 564 return -EINVAL; 565 } 566 567 return 0; 568 } 569 570 static const char *amdgpu_discovery_get_fw_name(struct amdgpu_device *adev) 571 { 572 if (amdgpu_discovery == 2) { 573 /* Assume there is valid discovery TMR in VRAM even if binary is sideloaded */ 574 adev->discovery.reserve_tmr = true; 575 return "amdgpu/ip_discovery.bin"; 576 } 577 578 switch (adev->asic_type) { 579 case CHIP_VEGA10: 580 return "amdgpu/vega10_ip_discovery.bin"; 581 case CHIP_VEGA12: 582 return "amdgpu/vega12_ip_discovery.bin"; 583 case CHIP_RAVEN: 584 if (adev->apu_flags & AMD_APU_IS_RAVEN2) 585 return "amdgpu/raven2_ip_discovery.bin"; 586 else if (adev->apu_flags & AMD_APU_IS_PICASSO) 587 return "amdgpu/picasso_ip_discovery.bin"; 588 else 589 return "amdgpu/raven_ip_discovery.bin"; 590 case CHIP_VEGA20: 591 return "amdgpu/vega20_ip_discovery.bin"; 592 case CHIP_ARCTURUS: 593 return "amdgpu/arcturus_ip_discovery.bin"; 594 case CHIP_ALDEBARAN: 595 return "amdgpu/aldebaran_ip_discovery.bin"; 596 default: 597 return NULL; 598 } 599 } 600 601 static struct table_info * 602 amdgpu_discovery_get_table_info_from_bin(uint8_t *discovery_bin, 603 uint16_t table_id) 604 { 605 struct binary_header *bhdr = (struct binary_header *)discovery_bin; 606 struct binary_header_v2 *bhdrv2; 607 608 switch (bhdr->version_major) { 609 case 2: 610 bhdrv2 = (struct binary_header_v2 *)discovery_bin; 611 return &bhdrv2->table_list[table_id]; 612 case 1: 613 case 0: 614 return &bhdr->table_list[table_id]; 615 default: 616 return NULL; 617 } 618 } 619 620 static int amdgpu_discovery_get_table_info(struct amdgpu_device *adev, 621 struct table_info **info, 622 uint16_t table_id) 623 { 624 struct binary_header *bhdr = 625 (struct binary_header *)adev->discovery.bin; 626 627 *info = amdgpu_discovery_get_table_info_from_bin(adev->discovery.bin, 628 table_id); 629 if (!*info) { 630 dev_err(adev->dev, "Invalid ip discovery table version %d\n", 631 bhdr->version_major); 632 return -EINVAL; 633 } 634 635 return 0; 636 } 637 638 static int amdgpu_discovery_table_check(struct amdgpu_device *adev, 639 uint8_t *discovery_bin, 640 uint16_t table_id) 641 { 642 int r, act_val, exp_val, table_size; 643 uint16_t offset, checksum; 644 struct table_info *info; 645 bool check_table = true; 646 char *table_name; 647 648 r = amdgpu_discovery_get_table_info(adev, &info, table_id); 649 if (r) 650 return r; 651 offset = le16_to_cpu(info->offset); 652 checksum = le16_to_cpu(info->checksum); 653 654 switch (table_id) { 655 case IP_DISCOVERY: { 656 struct ip_discovery_header *ihdr = 657 (struct ip_discovery_header *)(discovery_bin + offset); 658 act_val = le32_to_cpu(ihdr->signature); 659 exp_val = DISCOVERY_TABLE_SIGNATURE; 660 table_size = le16_to_cpu(ihdr->size); 661 table_name = "data table"; 662 break; 663 } 664 case GC: { 665 struct gpu_info_header *ghdr = 666 (struct gpu_info_header *)(discovery_bin + offset); 667 act_val = le32_to_cpu(ghdr->table_id); 668 exp_val = GC_TABLE_ID; 669 table_size = le16_to_cpu(ghdr->size); 670 table_name = "gc table"; 671 break; 672 } 673 case HARVEST_INFO: { 674 struct harvest_info_header *hhdr = 675 (struct harvest_info_header *)(discovery_bin + offset); 676 act_val = le32_to_cpu(hhdr->signature); 677 exp_val = HARVEST_TABLE_SIGNATURE; 678 table_size = sizeof(struct harvest_table); 679 table_name = "harvest table"; 680 break; 681 } 682 case VCN_INFO: { 683 struct vcn_info_header *vhdr = 684 (struct vcn_info_header *)(discovery_bin + offset); 685 act_val = le32_to_cpu(vhdr->table_id); 686 exp_val = VCN_INFO_TABLE_ID; 687 table_size = le32_to_cpu(vhdr->size_bytes); 688 table_name = "vcn table"; 689 break; 690 } 691 case MALL_INFO: { 692 struct mall_info_header *mhdr = 693 (struct mall_info_header *)(discovery_bin + offset); 694 act_val = le32_to_cpu(mhdr->table_id); 695 exp_val = MALL_INFO_TABLE_ID; 696 table_size = le32_to_cpu(mhdr->size_bytes); 697 table_name = "mall table"; 698 check_table = false; 699 break; 700 } 701 case NPS_INFO: { 702 table_name = "nps table"; 703 check_table = false; 704 break; 705 } 706 case MEM_RESERVED_INFO: 707 /* Optional table; signature is validated in get_mem_reserved_info_table(). */ 708 table_name = "mem_reserved table"; 709 check_table = false; 710 break; 711 default: 712 dev_err(adev->dev, "invalid ip discovery table id %d specified\n", table_id); 713 check_table = false; 714 break; 715 } 716 717 if (check_table && offset && table_size) { 718 if (act_val != exp_val) { 719 dev_err(adev->dev, "invalid ip discovery %s signature\n", table_name); 720 return -EINVAL; 721 } 722 723 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, 724 table_size, checksum)) { 725 dev_err(adev->dev, "invalid ip discovery %s checksum\n", table_name); 726 return -EINVAL; 727 } 728 } 729 730 return 0; 731 } 732 733 static void amdgpu_discovery_dump_mem_reserved_info_table(struct amdgpu_device *adev, 734 struct mem_reserved_info_table_v1_0 *table); 735 736 static void amdgpu_discovery_log_bad_signature(struct amdgpu_device *adev, 737 uint8_t *discovery_bin, 738 const char *fw_name) 739 { 740 dev_err(adev->dev, 741 "get invalid ip discovery binary signature: got 0x%08x, expected 0x%08x (source=%s)\n", 742 le32_to_cpu(((struct binary_header *)discovery_bin)->binary_signature), 743 BINARY_SIGNATURE, fw_name ? "file" : "mem"); 744 print_hex_dump(KERN_ERR, "ip_discovery head: ", DUMP_PREFIX_OFFSET, 745 16, 1, discovery_bin, 64, false); 746 } 747 748 static int amdgpu_discovery_init(struct amdgpu_device *adev) 749 { 750 struct binary_header *bhdr; 751 uint8_t *discovery_bin; 752 const char *fw_name; 753 uint16_t offset; 754 uint16_t size; 755 uint16_t checksum; 756 uint16_t table_id; 757 bool is_tmr_in_sysmem; 758 int r; 759 760 r = amdgpu_discovery_get_tmr_info(adev, &is_tmr_in_sysmem); 761 if (r) 762 return r; 763 764 discovery_bin = adev->discovery.bin; 765 /* Read from file if it is the preferred option */ 766 fw_name = amdgpu_discovery_get_fw_name(adev); 767 if (fw_name != NULL) { 768 drm_dbg(&adev->ddev, "use ip discovery information from file\n"); 769 r = amdgpu_discovery_read_binary_from_file(adev, discovery_bin, 770 fw_name); 771 if (r) 772 goto out; 773 } else { 774 drm_dbg(&adev->ddev, "use ip discovery information from memory\n"); 775 r = amdgpu_discovery_read_binary_from_mem(adev, discovery_bin, 776 is_tmr_in_sysmem); 777 if (r) 778 goto out; 779 } 780 781 /* check the ip discovery binary signature */ 782 if (!amdgpu_discovery_verify_binary_signature(discovery_bin)) { 783 amdgpu_discovery_log_bad_signature(adev, discovery_bin, fw_name); 784 r = -EINVAL; 785 goto out; 786 } 787 788 bhdr = (struct binary_header *)discovery_bin; 789 790 offset = offsetof(struct binary_header, binary_checksum) + 791 sizeof(bhdr->binary_checksum); 792 size = le16_to_cpu(bhdr->binary_size) - offset; 793 checksum = le16_to_cpu(bhdr->binary_checksum); 794 795 if (!amdgpu_discovery_verify_checksum(adev, discovery_bin + offset, size, 796 checksum)) { 797 dev_err(adev->dev, "invalid ip discovery binary checksum\n"); 798 r = -EINVAL; 799 goto out; 800 } 801 802 for (table_id = 0; table_id < TOTAL_TABLES; table_id++) { 803 r = amdgpu_discovery_table_check(adev, discovery_bin, table_id); 804 if (r) 805 goto out; 806 } 807 808 /* 809 * Resolve and dump the MEM_RESERVED_INFO table once at init time. 810 * The table is optional, so missing it is not a fatal error. 811 */ 812 if (!amdgpu_discovery_get_mem_reserved_info_table(adev)) 813 amdgpu_discovery_dump_mem_reserved_info_table(adev, 814 adev->discovery.mem_reserved_table); 815 816 return 0; 817 818 out: 819 kfree(adev->discovery.bin); 820 adev->discovery.bin = NULL; 821 if ((amdgpu_discovery != 2) && 822 (RREG32(mmIP_DISCOVERY_VERSION) == 4)) 823 amdgpu_ras_query_boot_status(adev, 4); 824 return r; 825 } 826 827 void amdgpu_discovery_fini(struct amdgpu_device *adev) 828 { 829 if (adev->discovery.ip_top && !adev->discovery.ip_top->standalone_mode) 830 amdgpu_discovery_sysfs_fini(adev); 831 832 kfree(adev->discovery.bin); 833 adev->discovery.bin = NULL; 834 /* Cached pointer lives inside discovery.bin; drop it to avoid UAF. */ 835 adev->discovery.mem_reserved_table = NULL; 836 } 837 838 static int amdgpu_discovery_validate_ip(struct amdgpu_device *adev, 839 uint8_t instance, uint16_t hw_id) 840 { 841 if (instance >= HWIP_MAX_INSTANCE) { 842 if (adev) 843 dev_err(adev->dev, 844 "Unexpected instance_number (%d) from ip discovery blob\n", 845 instance); 846 return -EINVAL; 847 } 848 if (hw_id >= HW_ID_MAX) { 849 if (adev) 850 dev_err(adev->dev, 851 "Unexpected hw_id (%d) from ip discovery blob\n", 852 hw_id); 853 return -EINVAL; 854 } 855 856 return 0; 857 } 858 859 static void amdgpu_discovery_read_harvest_bit_per_ip(struct amdgpu_device *adev, 860 uint32_t *vcn_harvest_count) 861 { 862 uint8_t *discovery_bin = adev->discovery.bin; 863 struct binary_header *bhdr; 864 struct ip_discovery_header *ihdr; 865 struct die_header *dhdr; 866 struct ip *ip; 867 uint16_t die_offset, ip_offset, num_dies, num_ips; 868 uint16_t hw_id; 869 uint8_t inst; 870 int i, j; 871 872 bhdr = (struct binary_header *)discovery_bin; 873 ihdr = (struct ip_discovery_header 874 *)(discovery_bin + 875 le16_to_cpu(bhdr->table_list[IP_DISCOVERY].offset)); 876 num_dies = le16_to_cpu(ihdr->num_dies); 877 878 /* scan harvest bit of all IP data structures */ 879 for (i = 0; i < num_dies; i++) { 880 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 881 dhdr = (struct die_header *)(discovery_bin + die_offset); 882 num_ips = le16_to_cpu(dhdr->num_ips); 883 ip_offset = die_offset + sizeof(*dhdr); 884 885 for (j = 0; j < num_ips; j++) { 886 ip = (struct ip *)(discovery_bin + ip_offset); 887 inst = ip->number_instance; 888 hw_id = le16_to_cpu(ip->hw_id); 889 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 890 goto next_ip; 891 892 if (ip->harvest == 1) { 893 switch (hw_id) { 894 case VCN_HWID: 895 (*vcn_harvest_count)++; 896 if (inst == 0) { 897 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN0; 898 adev->vcn.inst_mask &= 899 ~AMDGPU_VCN_HARVEST_VCN0; 900 adev->jpeg.inst_mask &= 901 ~AMDGPU_VCN_HARVEST_VCN0; 902 } else { 903 adev->vcn.harvest_config |= AMDGPU_VCN_HARVEST_VCN1; 904 adev->vcn.inst_mask &= 905 ~AMDGPU_VCN_HARVEST_VCN1; 906 adev->jpeg.inst_mask &= 907 ~AMDGPU_VCN_HARVEST_VCN1; 908 } 909 break; 910 case DMU_HWID: 911 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 912 break; 913 default: 914 break; 915 } 916 } 917 next_ip: 918 ip_offset += struct_size(ip, base_address, 919 ip->num_base_address); 920 } 921 } 922 } 923 924 static void amdgpu_discovery_read_from_harvest_table(struct amdgpu_device *adev, 925 uint32_t *vcn_harvest_count, 926 uint32_t *umc_harvest_count) 927 { 928 uint8_t *discovery_bin = adev->discovery.bin; 929 struct table_info *info; 930 struct harvest_table *harvest_info; 931 u16 offset; 932 int i; 933 u64 umc_harvest_config = 0; 934 935 if (amdgpu_discovery_get_table_info(adev, &info, HARVEST_INFO)) 936 return; 937 offset = le16_to_cpu(info->offset); 938 939 if (!offset) { 940 dev_err(adev->dev, "invalid harvest table offset\n"); 941 return; 942 } 943 944 harvest_info = (struct harvest_table *)(discovery_bin + offset); 945 946 for (i = 0; i < 32; i++) { 947 u16 hw_id = le16_to_cpu(harvest_info->list[i].hw_id); 948 u8 inst = harvest_info->list[i].number_instance; 949 950 if (hw_id == 0) 951 break; 952 953 if (inst >= 32) { 954 dev_warn(adev->dev, 955 "bogus harvest instance %u for hw_id %u\n", 956 inst, hw_id); 957 continue; 958 } 959 960 switch (hw_id) { 961 case VCN_HWID: 962 (*vcn_harvest_count)++; 963 adev->vcn.harvest_config |= BIT(inst); 964 adev->jpeg.harvest_config |= BIT(inst); 965 966 adev->vcn.inst_mask &= ~BIT(inst); 967 adev->jpeg.inst_mask &= ~BIT(inst); 968 break; 969 case DMU_HWID: 970 adev->harvest_ip_mask |= AMD_HARVEST_IP_DMU_MASK; 971 break; 972 case UMC_HWID: 973 umc_harvest_config |= BIT_ULL(inst); 974 (*umc_harvest_count)++; 975 break; 976 case GC_HWID: 977 adev->gfx.xcc_mask &= ~BIT(inst); 978 break; 979 case SDMA0_HWID: 980 adev->sdma.sdma_mask &= ~BIT(inst); 981 break; 982 case MMHUB_HWID: 983 adev->mmhub.inst_mask &= ~BIT(inst); 984 break; 985 case LSDMA_HWID: 986 adev->lsdma.inst_mask &= ~BIT(inst); 987 break; 988 #if defined(CONFIG_DRM_AMD_ISP) 989 case ISP_HWID: 990 adev->isp.harvest_config |= ~BIT(inst); 991 break; 992 #endif 993 default: 994 break; 995 } 996 } 997 998 adev->umc.active_mask = ((1ULL << adev->umc.node_inst_num) - 1ULL) & 999 ~umc_harvest_config; 1000 } 1001 1002 /* ================================================== */ 1003 1004 struct ip_hw_instance { 1005 struct kobject kobj; /* ip_discovery/die/#die/#hw_id/#instance/<attrs...> */ 1006 1007 int hw_id; 1008 u8 num_instance; 1009 u8 major, minor, revision; 1010 u8 harvest; 1011 1012 int num_base_addresses; 1013 u32 base_addr[] __counted_by(num_base_addresses); 1014 }; 1015 1016 struct ip_hw_id { 1017 struct kset hw_id_kset; /* ip_discovery/die/#die/#hw_id/, contains ip_hw_instance */ 1018 int hw_id; 1019 }; 1020 1021 struct ip_die_entry { 1022 struct kset ip_kset; /* ip_discovery/die/#die/, contains ip_hw_id */ 1023 u16 num_ips; 1024 }; 1025 1026 /* -------------------------------------------------- */ 1027 1028 struct ip_hw_instance_attr { 1029 struct attribute attr; 1030 ssize_t (*show)(struct ip_hw_instance *ip_hw_instance, char *buf); 1031 }; 1032 1033 static ssize_t hw_id_show(struct ip_hw_instance *ip_hw_instance, char *buf) 1034 { 1035 return sysfs_emit(buf, "%d\n", ip_hw_instance->hw_id); 1036 } 1037 1038 static ssize_t num_instance_show(struct ip_hw_instance *ip_hw_instance, char *buf) 1039 { 1040 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_instance); 1041 } 1042 1043 static ssize_t major_show(struct ip_hw_instance *ip_hw_instance, char *buf) 1044 { 1045 return sysfs_emit(buf, "%d\n", ip_hw_instance->major); 1046 } 1047 1048 static ssize_t minor_show(struct ip_hw_instance *ip_hw_instance, char *buf) 1049 { 1050 return sysfs_emit(buf, "%d\n", ip_hw_instance->minor); 1051 } 1052 1053 static ssize_t revision_show(struct ip_hw_instance *ip_hw_instance, char *buf) 1054 { 1055 return sysfs_emit(buf, "%d\n", ip_hw_instance->revision); 1056 } 1057 1058 static ssize_t harvest_show(struct ip_hw_instance *ip_hw_instance, char *buf) 1059 { 1060 return sysfs_emit(buf, "0x%01X\n", ip_hw_instance->harvest); 1061 } 1062 1063 static ssize_t num_base_addresses_show(struct ip_hw_instance *ip_hw_instance, char *buf) 1064 { 1065 return sysfs_emit(buf, "%d\n", ip_hw_instance->num_base_addresses); 1066 } 1067 1068 static ssize_t base_addr_show(struct ip_hw_instance *ip_hw_instance, char *buf) 1069 { 1070 ssize_t at; 1071 int ii; 1072 1073 for (at = ii = 0; ii < ip_hw_instance->num_base_addresses; ii++) { 1074 /* Here we satisfy the condition that, at + size <= PAGE_SIZE. 1075 */ 1076 if (at + 12 > PAGE_SIZE) 1077 break; 1078 at += sysfs_emit_at(buf, at, "0x%08X\n", 1079 ip_hw_instance->base_addr[ii]); 1080 } 1081 1082 return at; 1083 } 1084 1085 static struct ip_hw_instance_attr ip_hw_attr[] = { 1086 __ATTR_RO(hw_id), 1087 __ATTR_RO(num_instance), 1088 __ATTR_RO(major), 1089 __ATTR_RO(minor), 1090 __ATTR_RO(revision), 1091 __ATTR_RO(harvest), 1092 __ATTR_RO(num_base_addresses), 1093 __ATTR_RO(base_addr), 1094 }; 1095 1096 static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; 1097 ATTRIBUTE_GROUPS(ip_hw_instance); 1098 1099 #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) 1100 #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) 1101 1102 static ssize_t ip_hw_instance_attr_show(struct kobject *kobj, 1103 struct attribute *attr, 1104 char *buf) 1105 { 1106 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 1107 struct ip_hw_instance_attr *ip_hw_attr = to_ip_hw_instance_attr(attr); 1108 1109 if (!ip_hw_attr->show) 1110 return -EIO; 1111 1112 return ip_hw_attr->show(ip_hw_instance, buf); 1113 } 1114 1115 static const struct sysfs_ops ip_hw_instance_sysfs_ops = { 1116 .show = ip_hw_instance_attr_show, 1117 }; 1118 1119 static void ip_hw_instance_release(struct kobject *kobj) 1120 { 1121 struct ip_hw_instance *ip_hw_instance = to_ip_hw_instance(kobj); 1122 1123 kfree(ip_hw_instance); 1124 } 1125 1126 static const struct kobj_type ip_hw_instance_ktype = { 1127 .release = ip_hw_instance_release, 1128 .sysfs_ops = &ip_hw_instance_sysfs_ops, 1129 .default_groups = ip_hw_instance_groups, 1130 }; 1131 1132 /* -------------------------------------------------- */ 1133 1134 #define to_ip_hw_id(x) container_of(to_kset(x), struct ip_hw_id, hw_id_kset) 1135 1136 static void ip_hw_id_release(struct kobject *kobj) 1137 { 1138 struct ip_hw_id *ip_hw_id = to_ip_hw_id(kobj); 1139 1140 if (!list_empty(&ip_hw_id->hw_id_kset.list)) 1141 DRM_ERROR("ip_hw_id->hw_id_kset is not empty"); 1142 kfree(ip_hw_id); 1143 } 1144 1145 static const struct kobj_type ip_hw_id_ktype = { 1146 .release = ip_hw_id_release, 1147 .sysfs_ops = &kobj_sysfs_ops, 1148 }; 1149 1150 /* -------------------------------------------------- */ 1151 1152 static void die_kobj_release(struct kobject *kobj); 1153 static void ip_disc_release(struct kobject *kobj); 1154 1155 struct ip_die_entry_attribute { 1156 struct attribute attr; 1157 ssize_t (*show)(struct ip_die_entry *ip_die_entry, char *buf); 1158 }; 1159 1160 #define to_ip_die_entry_attr(x) container_of(x, struct ip_die_entry_attribute, attr) 1161 1162 static ssize_t num_ips_show(struct ip_die_entry *ip_die_entry, char *buf) 1163 { 1164 return sysfs_emit(buf, "%d\n", ip_die_entry->num_ips); 1165 } 1166 1167 /* If there are more ip_die_entry attrs, other than the number of IPs, 1168 * we can make this intro an array of attrs, and then initialize 1169 * ip_die_entry_attrs in a loop. 1170 */ 1171 static struct ip_die_entry_attribute num_ips_attr = 1172 __ATTR_RO(num_ips); 1173 1174 static struct attribute *ip_die_entry_attrs[] = { 1175 &num_ips_attr.attr, 1176 NULL, 1177 }; 1178 ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ 1179 1180 #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) 1181 1182 static ssize_t ip_die_entry_attr_show(struct kobject *kobj, 1183 struct attribute *attr, 1184 char *buf) 1185 { 1186 struct ip_die_entry_attribute *ip_die_entry_attr = to_ip_die_entry_attr(attr); 1187 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1188 1189 if (!ip_die_entry_attr->show) 1190 return -EIO; 1191 1192 return ip_die_entry_attr->show(ip_die_entry, buf); 1193 } 1194 1195 static void ip_die_entry_release(struct kobject *kobj) 1196 { 1197 struct ip_die_entry *ip_die_entry = to_ip_die_entry(kobj); 1198 1199 if (!list_empty(&ip_die_entry->ip_kset.list)) 1200 DRM_ERROR("ip_die_entry->ip_kset is not empty"); 1201 kfree(ip_die_entry); 1202 } 1203 1204 static const struct sysfs_ops ip_die_entry_sysfs_ops = { 1205 .show = ip_die_entry_attr_show, 1206 }; 1207 1208 static const struct kobj_type ip_die_entry_ktype = { 1209 .release = ip_die_entry_release, 1210 .sysfs_ops = &ip_die_entry_sysfs_ops, 1211 .default_groups = ip_die_entry_groups, 1212 }; 1213 1214 static const struct kobj_type die_kobj_ktype = { 1215 .release = die_kobj_release, 1216 .sysfs_ops = &kobj_sysfs_ops, 1217 }; 1218 1219 static const struct kobj_type ip_discovery_ktype = { 1220 .release = ip_disc_release, 1221 .sysfs_ops = &kobj_sysfs_ops, 1222 }; 1223 1224 static void die_kobj_release(struct kobject *kobj) 1225 { 1226 struct ip_discovery_top *ip_top = container_of(to_kset(kobj), 1227 struct ip_discovery_top, 1228 die_kset); 1229 if (!list_empty(&ip_top->die_kset.list)) 1230 DRM_ERROR("ip_top->die_kset is not empty"); 1231 } 1232 1233 static void ip_disc_release(struct kobject *kobj) 1234 { 1235 struct ip_discovery_top *ip_top = container_of(kobj, struct ip_discovery_top, 1236 kobj); 1237 struct amdgpu_device *adev = ip_top->adev; 1238 1239 /* In standalone mode, discovery_bin is managed by devm and will be 1240 * freed automatically when the PCI device is removed. Do not manually 1241 * free it here to avoid double-free. 1242 */ 1243 1244 kfree(ip_top); 1245 if (adev) 1246 adev->discovery.ip_top = NULL; 1247 } 1248 1249 static uint8_t amdgpu_discovery_get_harvest_info(struct amdgpu_device *adev, 1250 uint16_t hw_id, uint8_t inst) 1251 { 1252 uint8_t harvest = 0; 1253 1254 /* In early init mode (adev == NULL), harvest info is not available */ 1255 if (!adev) 1256 return 0; 1257 1258 /* Until a uniform way is figured, get mask based on hwid */ 1259 switch (hw_id) { 1260 case VCN_HWID: 1261 /* VCN vs UVD+VCE */ 1262 if (!amdgpu_ip_version(adev, VCE_HWIP, 0)) 1263 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; 1264 break; 1265 case DMU_HWID: 1266 if (adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK) 1267 harvest = 0x1; 1268 break; 1269 case UMC_HWID: 1270 /* TODO: It needs another parsing; for now, ignore.*/ 1271 break; 1272 case GC_HWID: 1273 harvest = ((1 << inst) & adev->gfx.xcc_mask) == 0; 1274 break; 1275 case SDMA0_HWID: 1276 harvest = ((1 << inst) & adev->sdma.sdma_mask) == 0; 1277 break; 1278 case MMHUB_HWID: 1279 harvest = (BIT(inst) & adev->mmhub.inst_mask) == 0; 1280 break; 1281 case LSDMA_HWID: 1282 harvest = (BIT(inst) & adev->lsdma.inst_mask) == 0; 1283 break; 1284 default: 1285 break; 1286 } 1287 1288 return harvest; 1289 } 1290 1291 static int amdgpu_discovery_sysfs_ips(struct amdgpu_device *adev, 1292 struct ip_discovery_top *ip_top, 1293 struct ip_die_entry *ip_die_entry, 1294 const size_t _ip_offset, const int num_ips, 1295 bool reg_base_64) 1296 { 1297 uint8_t *discovery_bin = ip_top->standalone_mode ? 1298 ip_top->discovery_bin : 1299 adev->discovery.bin; 1300 int ii, jj, kk, res; 1301 uint16_t hw_id; 1302 uint8_t inst; 1303 1304 DRM_DEBUG("num_ips:%d", num_ips); 1305 1306 /* Find all IPs of a given HW ID, and add their instance to 1307 * #die/#hw_id/#instance/<attributes> 1308 */ 1309 for (ii = 0; ii < HW_ID_MAX; ii++) { 1310 struct ip_hw_id *ip_hw_id = NULL; 1311 size_t ip_offset = _ip_offset; 1312 1313 for (jj = 0; jj < num_ips; jj++) { 1314 struct ip_v4 *ip; 1315 struct ip_hw_instance *ip_hw_instance; 1316 1317 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1318 inst = ip->instance_number; 1319 hw_id = le16_to_cpu(ip->hw_id); 1320 if (amdgpu_discovery_validate_ip(adev, inst, hw_id) || 1321 hw_id != ii) 1322 goto next_ip; 1323 1324 DRM_DEBUG("match:%d @ ip_offset:%zu", ii, ip_offset); 1325 1326 /* We have a hw_id match; register the hw 1327 * block if not yet registered. 1328 */ 1329 if (!ip_hw_id) { 1330 ip_hw_id = kzalloc_obj(*ip_hw_id); 1331 if (!ip_hw_id) 1332 return -ENOMEM; 1333 ip_hw_id->hw_id = ii; 1334 1335 kobject_set_name(&ip_hw_id->hw_id_kset.kobj, "%d", ii); 1336 ip_hw_id->hw_id_kset.kobj.kset = &ip_die_entry->ip_kset; 1337 ip_hw_id->hw_id_kset.kobj.ktype = &ip_hw_id_ktype; 1338 res = kset_register(&ip_hw_id->hw_id_kset); 1339 if (res) { 1340 DRM_ERROR("Couldn't register ip_hw_id kset"); 1341 kfree(ip_hw_id); 1342 return res; 1343 } 1344 if (hw_id_names[ii]) { 1345 res = sysfs_create_link(&ip_die_entry->ip_kset.kobj, 1346 &ip_hw_id->hw_id_kset.kobj, 1347 hw_id_names[ii]); 1348 if (res) { 1349 DRM_ERROR("Couldn't create IP link %s in IP Die:%s\n", 1350 hw_id_names[ii], 1351 kobject_name(&ip_die_entry->ip_kset.kobj)); 1352 } 1353 } 1354 } 1355 1356 /* Now register its instance. 1357 */ 1358 ip_hw_instance = kzalloc_flex(*ip_hw_instance, 1359 base_addr, 1360 ip->num_base_address); 1361 if (!ip_hw_instance) { 1362 DRM_ERROR("no memory for ip_hw_instance"); 1363 return -ENOMEM; 1364 } 1365 ip_hw_instance->hw_id = le16_to_cpu(ip->hw_id); /* == ii */ 1366 ip_hw_instance->num_instance = ip->instance_number; 1367 ip_hw_instance->major = ip->major; 1368 ip_hw_instance->minor = ip->minor; 1369 ip_hw_instance->revision = ip->revision; 1370 ip_hw_instance->harvest = 1371 amdgpu_discovery_get_harvest_info( 1372 adev, ip_hw_instance->hw_id, 1373 ip_hw_instance->num_instance); 1374 ip_hw_instance->num_base_addresses = ip->num_base_address; 1375 1376 for (kk = 0; kk < ip_hw_instance->num_base_addresses; kk++) { 1377 /* 1378 * Standalone mode uses a raw copy of the discovery 1379 * binary; decode 64-bit addresses here. The shared 1380 * bin is already collapsed to 32-bit in place. 1381 */ 1382 if (reg_base_64 && ip_top->standalone_mode) 1383 ip_hw_instance->base_addr[kk] = 1384 lower_32_bits(le64_to_cpu(ip->base_address_64[kk])) & 0x3FFFFFFF; 1385 else 1386 ip_hw_instance->base_addr[kk] = 1387 le32_to_cpu(ip->base_address[kk]); 1388 } 1389 1390 kobject_init(&ip_hw_instance->kobj, &ip_hw_instance_ktype); 1391 ip_hw_instance->kobj.kset = &ip_hw_id->hw_id_kset; 1392 res = kobject_add(&ip_hw_instance->kobj, NULL, 1393 "%d", ip_hw_instance->num_instance); 1394 if (res) 1395 kobject_put(&ip_hw_instance->kobj); 1396 next_ip: 1397 if (reg_base_64) 1398 ip_offset += struct_size(ip, base_address_64, 1399 ip->num_base_address); 1400 else 1401 ip_offset += struct_size(ip, base_address, 1402 ip->num_base_address); 1403 } 1404 } 1405 1406 return 0; 1407 } 1408 1409 static int amdgpu_discovery_sysfs_recurse(struct amdgpu_device *adev, 1410 struct ip_discovery_top *ip_top) 1411 { 1412 uint8_t *discovery_bin = ip_top->standalone_mode ? 1413 ip_top->discovery_bin : 1414 adev->discovery.bin; 1415 struct table_info *info; 1416 struct ip_discovery_header *ihdr; 1417 struct die_header *dhdr; 1418 struct kset *die_kset = &ip_top->die_kset; 1419 u16 num_dies, die_offset, num_ips; 1420 size_t ip_offset; 1421 int ii, res; 1422 1423 info = amdgpu_discovery_get_table_info_from_bin(discovery_bin, 1424 IP_DISCOVERY); 1425 if (!info) 1426 return -EINVAL; 1427 ihdr = (struct ip_discovery_header 1428 *)(discovery_bin + 1429 le16_to_cpu(info->offset)); 1430 num_dies = le16_to_cpu(ihdr->num_dies); 1431 1432 DRM_DEBUG("number of dies: %d\n", num_dies); 1433 1434 for (ii = 0; ii < num_dies; ii++) { 1435 struct ip_die_entry *ip_die_entry; 1436 1437 die_offset = le16_to_cpu(ihdr->die_info[ii].die_offset); 1438 dhdr = (struct die_header *)(discovery_bin + die_offset); 1439 num_ips = le16_to_cpu(dhdr->num_ips); 1440 ip_offset = die_offset + sizeof(*dhdr); 1441 1442 /* Add the die to the kset. 1443 * 1444 * dhdr->die_id == ii, which was checked in 1445 * amdgpu_discovery_reg_base_init(). 1446 */ 1447 1448 ip_die_entry = kzalloc_obj(*ip_die_entry); 1449 if (!ip_die_entry) 1450 return -ENOMEM; 1451 1452 ip_die_entry->num_ips = num_ips; 1453 1454 kobject_set_name(&ip_die_entry->ip_kset.kobj, "%d", le16_to_cpu(dhdr->die_id)); 1455 ip_die_entry->ip_kset.kobj.kset = die_kset; 1456 ip_die_entry->ip_kset.kobj.ktype = &ip_die_entry_ktype; 1457 res = kset_register(&ip_die_entry->ip_kset); 1458 if (res) { 1459 DRM_ERROR("Couldn't register ip_die_entry kset"); 1460 kfree(ip_die_entry); 1461 return res; 1462 } 1463 1464 amdgpu_discovery_sysfs_ips(adev, ip_top, ip_die_entry, ip_offset, 1465 num_ips, !!ihdr->base_addr_64_bit); 1466 } 1467 1468 return 0; 1469 } 1470 1471 static int amdgpu_discovery_sysfs_init(struct amdgpu_device *adev) 1472 { 1473 uint8_t *discovery_bin = adev->discovery.bin; 1474 struct ip_discovery_top *ip_top; 1475 struct kset *die_kset; 1476 int res, ii; 1477 1478 if (!discovery_bin) 1479 return -EINVAL; 1480 1481 /* If early init already created sysfs in standalone mode, skip normal init */ 1482 if (adev->discovery.ip_top && adev->discovery.ip_top->standalone_mode) 1483 return 0; 1484 1485 ip_top = kzalloc_obj(*ip_top); 1486 if (!ip_top) 1487 return -ENOMEM; 1488 1489 ip_top->adev = adev; 1490 1491 /* Check if ip_discovery already exists before creating. 1492 * This shouldn't normally happen but handle it gracefully. 1493 */ 1494 if (adev->dev->kobj.sd) { 1495 struct kernfs_node *existing; 1496 1497 existing = kernfs_find_and_get(adev->dev->kobj.sd, "ip_discovery"); 1498 if (existing) { 1499 kernfs_put(existing); 1500 kfree(ip_top); 1501 return 0; 1502 } 1503 } 1504 1505 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1506 &adev->dev->kobj, "ip_discovery"); 1507 if (res) { 1508 DRM_ERROR("Couldn't init and add ip_discovery/"); 1509 goto Err; 1510 } 1511 1512 adev->discovery.ip_top = ip_top; 1513 1514 die_kset = &ip_top->die_kset; 1515 kobject_set_name(&die_kset->kobj, "%s", "die"); 1516 die_kset->kobj.parent = &ip_top->kobj; 1517 die_kset->kobj.ktype = &die_kobj_ktype; 1518 res = kset_register(&ip_top->die_kset); 1519 if (res) { 1520 DRM_ERROR("Couldn't register die_kset"); 1521 goto Err; 1522 } 1523 1524 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1525 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1526 ip_hw_instance_attrs[ii] = NULL; 1527 1528 res = amdgpu_discovery_sysfs_recurse(adev, ip_top); 1529 1530 return res; 1531 Err: 1532 kobject_put(&ip_top->kobj); 1533 return res; 1534 } 1535 1536 /* -------------------------------------------------- */ 1537 1538 #define list_to_kobj(el) container_of(el, struct kobject, entry) 1539 1540 static void amdgpu_discovery_sysfs_ip_hw_free(struct ip_hw_id *ip_hw_id) 1541 { 1542 struct list_head *el, *tmp; 1543 struct kset *hw_id_kset; 1544 1545 hw_id_kset = &ip_hw_id->hw_id_kset; 1546 spin_lock(&hw_id_kset->list_lock); 1547 list_for_each_prev_safe(el, tmp, &hw_id_kset->list) { 1548 list_del_init(el); 1549 spin_unlock(&hw_id_kset->list_lock); 1550 /* kobject is embedded in ip_hw_instance */ 1551 kobject_put(list_to_kobj(el)); 1552 spin_lock(&hw_id_kset->list_lock); 1553 } 1554 spin_unlock(&hw_id_kset->list_lock); 1555 kobject_put(&ip_hw_id->hw_id_kset.kobj); 1556 } 1557 1558 static void amdgpu_discovery_sysfs_die_free(struct ip_die_entry *ip_die_entry) 1559 { 1560 struct list_head *el, *tmp; 1561 struct kset *ip_kset; 1562 1563 ip_kset = &ip_die_entry->ip_kset; 1564 spin_lock(&ip_kset->list_lock); 1565 list_for_each_prev_safe(el, tmp, &ip_kset->list) { 1566 list_del_init(el); 1567 spin_unlock(&ip_kset->list_lock); 1568 amdgpu_discovery_sysfs_ip_hw_free(to_ip_hw_id(list_to_kobj(el))); 1569 spin_lock(&ip_kset->list_lock); 1570 } 1571 spin_unlock(&ip_kset->list_lock); 1572 kobject_put(&ip_die_entry->ip_kset.kobj); 1573 } 1574 1575 void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev) 1576 { 1577 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1578 struct list_head *el, *tmp; 1579 struct kset *die_kset; 1580 1581 if (!ip_top) 1582 return; 1583 1584 /* 1585 * In standalone mode the sysfs hierarchy is tied to the PCI device 1586 * lifetime and is torn down by amdgpu_discovery_sysfs_early_fini(). 1587 * Freeing it here would leave a dangling pointer in the early 1588 * discovery list, causing a use-after-free on driver unbind. 1589 */ 1590 if (ip_top->standalone_mode) 1591 return; 1592 1593 adev->discovery.ip_top = NULL; 1594 die_kset = &ip_top->die_kset; 1595 spin_lock(&die_kset->list_lock); 1596 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1597 list_del_init(el); 1598 spin_unlock(&die_kset->list_lock); 1599 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1600 spin_lock(&die_kset->list_lock); 1601 } 1602 spin_unlock(&die_kset->list_lock); 1603 kobject_put(&ip_top->die_kset.kobj); 1604 kobject_put(&ip_top->kobj); 1605 } 1606 1607 /* devcoredump support */ 1608 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p) 1609 { 1610 struct ip_discovery_top *ip_top = adev->discovery.ip_top; 1611 struct ip_die_entry *ip_die_entry; 1612 struct list_head *el_die, *el_hw_id, *el_hw_inst; 1613 struct ip_hw_id *hw_id; 1614 struct kset *die_kset; 1615 struct ip_hw_instance *ip_inst; 1616 int i = 0, j; 1617 1618 if (!ip_top) 1619 return; 1620 1621 die_kset = &ip_top->die_kset; 1622 1623 drm_printf(p, "\nHW IP Discovery\n"); 1624 1625 spin_lock(&die_kset->list_lock); 1626 list_for_each(el_die, &die_kset->list) { 1627 drm_printf(p, "die %d\n", i++); 1628 ip_die_entry = to_ip_die_entry(list_to_kobj(el_die)); 1629 1630 list_for_each(el_hw_id, &ip_die_entry->ip_kset.list) { 1631 hw_id = to_ip_hw_id(list_to_kobj(el_hw_id)); 1632 drm_printf(p, "hw_id %d %s\n", hw_id->hw_id, hw_id_names[hw_id->hw_id]); 1633 1634 list_for_each(el_hw_inst, &hw_id->hw_id_kset.list) { 1635 ip_inst = to_ip_hw_instance(list_to_kobj(el_hw_inst)); 1636 drm_printf(p, "\tinstance %d\n", ip_inst->num_instance); 1637 drm_printf(p, "\tmajor %d\n", ip_inst->major); 1638 drm_printf(p, "\tminor %d\n", ip_inst->minor); 1639 drm_printf(p, "\trevision %d\n", ip_inst->revision); 1640 drm_printf(p, "\tharvest 0x%01X\n", ip_inst->harvest); 1641 drm_printf(p, "\tnum_base_addresses %d\n", 1642 ip_inst->num_base_addresses); 1643 for (j = 0; j < ip_inst->num_base_addresses; j++) 1644 drm_printf(p, "\tbase_addr[%d] 0x%08X\n", 1645 j, ip_inst->base_addr[j]); 1646 } 1647 } 1648 } 1649 spin_unlock(&die_kset->list_lock); 1650 } 1651 1652 int amdgpu_discovery_sysfs_early_init(struct amdgpu_device *adev, struct pci_dev *pdev) 1653 { 1654 struct ip_discovery_top *ip_top; 1655 struct early_ip_discovery *early_entry, *tmp; 1656 struct kset *die_kset; 1657 uint8_t *discovery_bin; 1658 int res, ii; 1659 1660 if (!adev || !adev->discovery.bin) 1661 return -EINVAL; 1662 1663 if (adev->discovery.ip_top) 1664 return 0; 1665 1666 mutex_lock(&early_ip_discovery_mutex); 1667 list_for_each_entry_safe(early_entry, tmp, &early_ip_discovery_list, list) { 1668 if (early_entry->pdev == pdev) { 1669 adev->discovery.ip_top = early_entry->ip_top; 1670 early_entry->ip_top->adev = adev; 1671 mutex_unlock(&early_ip_discovery_mutex); 1672 return 0; 1673 } 1674 } 1675 mutex_unlock(&early_ip_discovery_mutex); 1676 1677 discovery_bin = adev->discovery.bin; 1678 1679 early_entry = kzalloc_obj(*early_entry); 1680 if (!early_entry) 1681 return -ENOMEM; 1682 1683 ip_top = kzalloc_obj(*ip_top); 1684 if (!ip_top) { 1685 kfree(early_entry); 1686 return -ENOMEM; 1687 } 1688 1689 ip_top->discovery_bin = devm_kmemdup(&pdev->dev, discovery_bin, 1690 DISCOVERY_TMR_SIZE, GFP_KERNEL); 1691 if (!ip_top->discovery_bin) { 1692 kfree(ip_top); 1693 kfree(early_entry); 1694 return -ENOMEM; 1695 } 1696 1697 ip_top->bin_size = DISCOVERY_TMR_SIZE; 1698 ip_top->pdev = pdev; 1699 ip_top->adev = adev; 1700 ip_top->standalone_mode = true; 1701 1702 /* Check if ip_discovery already exists (from previous probe attempt). 1703 * This can happen if the module was unloaded and reloaded but the 1704 * sysfs persisted (tied to PCI device lifetime). 1705 */ 1706 if (pdev->dev.kobj.sd) { 1707 struct kernfs_node *existing; 1708 1709 existing = kernfs_find_and_get(pdev->dev.kobj.sd, "ip_discovery"); 1710 if (existing) { 1711 kernfs_put(existing); 1712 kfree(ip_top); 1713 kfree(early_entry); 1714 return 0; 1715 } 1716 } 1717 1718 res = kobject_init_and_add(&ip_top->kobj, &ip_discovery_ktype, 1719 &pdev->dev.kobj, "ip_discovery"); 1720 if (res) 1721 goto err_put_kobj; 1722 1723 adev->discovery.ip_top = ip_top; 1724 1725 die_kset = &ip_top->die_kset; 1726 kobject_set_name(&die_kset->kobj, "%s", "die"); 1727 die_kset->kobj.parent = &ip_top->kobj; 1728 die_kset->kobj.ktype = &die_kobj_ktype; 1729 res = kset_register(&ip_top->die_kset); 1730 if (res) 1731 goto err_put_die_kset; 1732 1733 for (ii = 0; ii < ARRAY_SIZE(ip_hw_attr); ii++) 1734 ip_hw_instance_attrs[ii] = &ip_hw_attr[ii].attr; 1735 ip_hw_instance_attrs[ii] = NULL; 1736 1737 res = amdgpu_discovery_sysfs_recurse(NULL, ip_top); 1738 if (res) 1739 goto err_put_die_kset; 1740 1741 early_entry->pdev = pdev; 1742 early_entry->ip_top = ip_top; 1743 mutex_lock(&early_ip_discovery_mutex); 1744 list_add(&early_entry->list, &early_ip_discovery_list); 1745 mutex_unlock(&early_ip_discovery_mutex); 1746 1747 return 0; 1748 1749 err_put_die_kset: 1750 kobject_put(&ip_top->die_kset.kobj); 1751 err_put_kobj: 1752 kobject_put(&ip_top->kobj); 1753 kfree(early_entry); 1754 adev->discovery.ip_top = NULL; 1755 return res; 1756 } 1757 1758 void amdgpu_discovery_sysfs_early_fini(struct pci_dev *pdev) 1759 { 1760 struct early_ip_discovery *entry, *tmp_entry; 1761 struct ip_discovery_top *ip_top = NULL; 1762 struct list_head *el, *tmp; 1763 struct kset *die_kset; 1764 1765 /* Find the entry in our tracking list */ 1766 mutex_lock(&early_ip_discovery_mutex); 1767 list_for_each_entry_safe(entry, tmp_entry, &early_ip_discovery_list, list) { 1768 if (entry->pdev == pdev) { 1769 ip_top = entry->ip_top; 1770 list_del(&entry->list); 1771 kfree(entry); 1772 break; 1773 } 1774 } 1775 mutex_unlock(&early_ip_discovery_mutex); 1776 1777 if (!ip_top) 1778 return; 1779 1780 /* Clean up sysfs hierarchy */ 1781 die_kset = &ip_top->die_kset; 1782 1783 spin_lock(&die_kset->list_lock); 1784 list_for_each_prev_safe(el, tmp, &die_kset->list) { 1785 list_del_init(el); 1786 spin_unlock(&die_kset->list_lock); 1787 amdgpu_discovery_sysfs_die_free(to_ip_die_entry(list_to_kobj(el))); 1788 spin_lock(&die_kset->list_lock); 1789 } 1790 spin_unlock(&die_kset->list_lock); 1791 1792 kobject_put(&ip_top->die_kset.kobj); 1793 kobject_put(&ip_top->kobj); 1794 /* ip_top itself will be freed by kobject_put via ip_disc_release */ 1795 } 1796 1797 /* ================================================== */ 1798 1799 static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev) 1800 { 1801 uint8_t num_base_address, subrev, variant; 1802 struct table_info *info; 1803 struct ip_discovery_header *ihdr; 1804 struct die_header *dhdr; 1805 uint8_t *discovery_bin; 1806 struct ip_v4 *ip; 1807 uint16_t die_offset; 1808 uint16_t ip_offset; 1809 uint16_t num_dies; 1810 uint32_t wafl_ver; 1811 uint16_t num_ips; 1812 uint16_t hw_id; 1813 uint8_t inst; 1814 int hw_ip; 1815 int i, j, k; 1816 int r; 1817 1818 r = amdgpu_discovery_init(adev); 1819 if (r) 1820 return r; 1821 1822 amdgpu_discovery_sysfs_early_init(adev, adev->pdev); 1823 1824 discovery_bin = adev->discovery.bin; 1825 wafl_ver = 0; 1826 adev->gfx.xcc_mask = 0; 1827 adev->sdma.sdma_mask = 0; 1828 adev->vcn.inst_mask = 0; 1829 adev->jpeg.inst_mask = 0; 1830 adev->mmhub.inst_mask = 0; 1831 adev->lsdma.inst_mask = 0; 1832 r = amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY); 1833 if (r) 1834 return r; 1835 ihdr = (struct ip_discovery_header 1836 *)(discovery_bin + 1837 le16_to_cpu(info->offset)); 1838 num_dies = le16_to_cpu(ihdr->num_dies); 1839 1840 DRM_DEBUG("number of dies: %d\n", num_dies); 1841 1842 for (i = 0; i < num_dies; i++) { 1843 die_offset = le16_to_cpu(ihdr->die_info[i].die_offset); 1844 dhdr = (struct die_header *)(discovery_bin + die_offset); 1845 num_ips = le16_to_cpu(dhdr->num_ips); 1846 ip_offset = die_offset + sizeof(*dhdr); 1847 1848 if (le16_to_cpu(dhdr->die_id) != i) { 1849 DRM_ERROR("invalid die id %d, expected %d\n", 1850 le16_to_cpu(dhdr->die_id), i); 1851 return -EINVAL; 1852 } 1853 1854 DRM_DEBUG("number of hardware IPs on die%d: %d\n", 1855 le16_to_cpu(dhdr->die_id), num_ips); 1856 1857 for (j = 0; j < num_ips; j++) { 1858 ip = (struct ip_v4 *)(discovery_bin + ip_offset); 1859 1860 inst = ip->instance_number; 1861 hw_id = le16_to_cpu(ip->hw_id); 1862 if (amdgpu_discovery_validate_ip(adev, inst, hw_id)) 1863 goto next_ip; 1864 1865 num_base_address = ip->num_base_address; 1866 1867 DRM_DEBUG("%s(%d) #%d v%d.%d.%d:\n", 1868 hw_id_names[le16_to_cpu(ip->hw_id)], 1869 le16_to_cpu(ip->hw_id), 1870 ip->instance_number, 1871 ip->major, ip->minor, 1872 ip->revision); 1873 1874 if (le16_to_cpu(ip->hw_id) == VCN_HWID) { 1875 /* Bit [5:0]: original revision value 1876 * Bit [7:6]: en/decode capability: 1877 * 0b00 : VCN function normally 1878 * 0b10 : encode is disabled 1879 * 0b01 : decode is disabled 1880 */ 1881 if (adev->vcn.num_vcn_inst < 1882 AMDGPU_MAX_VCN_INSTANCES) { 1883 adev->vcn.inst[adev->vcn.num_vcn_inst].vcn_config = 1884 ip->revision & 0xc0; 1885 adev->vcn.num_vcn_inst++; 1886 adev->vcn.inst_mask |= 1887 (1U << ip->instance_number); 1888 adev->jpeg.inst_mask |= 1889 (1U << ip->instance_number); 1890 } else { 1891 dev_err(adev->dev, "Too many VCN instances: %d vs %d\n", 1892 adev->vcn.num_vcn_inst + 1, 1893 AMDGPU_MAX_VCN_INSTANCES); 1894 } 1895 ip->revision &= ~0xc0; 1896 } 1897 1898 if (le16_to_cpu(ip->hw_id) == MMHUB_HWID) { 1899 if (inst < AMDGPU_MAX_MMHUB_INSTANCES) 1900 adev->mmhub.inst_mask |= BIT(inst); 1901 else 1902 dev_err(adev->dev, "Too many MMHUB instances: %d vs %d\n", 1903 inst + 1, 1904 AMDGPU_MAX_MMHUB_INSTANCES); 1905 } 1906 1907 if (le16_to_cpu(ip->hw_id) == LSDMA_HWID) { 1908 if (inst < AMDGPU_MAX_LSDMA_INSTANCES) 1909 adev->lsdma.inst_mask |= BIT(inst); 1910 else 1911 dev_err(adev->dev, "Too many LSDMA instances: %d vs %d\n", 1912 inst + 1, 1913 AMDGPU_MAX_LSDMA_INSTANCES); 1914 } 1915 1916 if (le16_to_cpu(ip->hw_id) == SDMA0_HWID || 1917 le16_to_cpu(ip->hw_id) == SDMA1_HWID || 1918 le16_to_cpu(ip->hw_id) == SDMA2_HWID || 1919 le16_to_cpu(ip->hw_id) == SDMA3_HWID) { 1920 if (adev->sdma.num_instances < 1921 AMDGPU_MAX_SDMA_INSTANCES) { 1922 adev->sdma.num_instances++; 1923 adev->sdma.sdma_mask |= 1924 (1U << ip->instance_number); 1925 } else { 1926 dev_err(adev->dev, "Too many SDMA instances: %d vs %d\n", 1927 adev->sdma.num_instances + 1, 1928 AMDGPU_MAX_SDMA_INSTANCES); 1929 } 1930 } 1931 1932 if (le16_to_cpu(ip->hw_id) == VPE_HWID) { 1933 if (adev->vpe.num_instances < AMDGPU_MAX_VPE_INSTANCES) 1934 adev->vpe.num_instances++; 1935 else 1936 dev_err(adev->dev, "Too many VPE instances: %d vs %d\n", 1937 adev->vpe.num_instances + 1, 1938 AMDGPU_MAX_VPE_INSTANCES); 1939 } 1940 1941 if (le16_to_cpu(ip->hw_id) == UMC_HWID) { 1942 adev->gmc.num_umc++; 1943 adev->umc.node_inst_num++; 1944 } 1945 1946 if (le16_to_cpu(ip->hw_id) == GC_HWID) 1947 adev->gfx.xcc_mask |= 1948 (1U << ip->instance_number); 1949 1950 if (!wafl_ver && le16_to_cpu(ip->hw_id) == WAFLC_HWID) 1951 wafl_ver = IP_VERSION_FULL(ip->major, ip->minor, 1952 ip->revision, 0, 0); 1953 1954 for (k = 0; k < num_base_address; k++) { 1955 /* 1956 * convert the endianness of base addresses in place, 1957 * so that we don't need to convert them when accessing adev->reg_offset. 1958 */ 1959 if (ihdr->base_addr_64_bit) 1960 /* Truncate the 64bit base address from ip discovery 1961 * and only store lower 32bit ip base in reg_offset[]. 1962 * Bits > 32 follows ASIC specific format, thus just 1963 * discard them and handle it within specific ASIC. 1964 * By this way reg_offset[] and related helpers can 1965 * stay unchanged. 1966 * The base address is in dwords, thus clear the 1967 * highest 2 bits to store. 1968 */ 1969 ip->base_address[k] = 1970 lower_32_bits(le64_to_cpu(ip->base_address_64[k])) & 0x3FFFFFFF; 1971 else 1972 ip->base_address[k] = le32_to_cpu(ip->base_address[k]); 1973 DRM_DEBUG("\t0x%08x\n", ip->base_address[k]); 1974 } 1975 1976 for (hw_ip = 0; hw_ip < MAX_HWIP; hw_ip++) { 1977 if (hw_id_map[hw_ip] == le16_to_cpu(ip->hw_id) && 1978 hw_id_map[hw_ip] != 0) { 1979 DRM_DEBUG("set register base offset for %s\n", 1980 hw_id_names[le16_to_cpu(ip->hw_id)]); 1981 adev->reg_offset[hw_ip][ip->instance_number] = 1982 ip->base_address; 1983 /* Instance support is somewhat inconsistent. 1984 * SDMA is a good example. Sienna cichlid has 4 total 1985 * SDMA instances, each enumerated separately (HWIDs 1986 * 42, 43, 68, 69). Arcturus has 8 total SDMA instances, 1987 * but they are enumerated as multiple instances of the 1988 * same HWIDs (4x HWID 42, 4x HWID 43). UMC is another 1989 * example. On most chips there are multiple instances 1990 * with the same HWID. 1991 */ 1992 1993 if (ihdr->version < 3) { 1994 subrev = 0; 1995 variant = 0; 1996 } else { 1997 subrev = ip->sub_revision; 1998 variant = ip->variant; 1999 } 2000 2001 adev->ip_versions[hw_ip] 2002 [ip->instance_number] = 2003 IP_VERSION_FULL(ip->major, 2004 ip->minor, 2005 ip->revision, 2006 variant, 2007 subrev); 2008 } 2009 } 2010 2011 next_ip: 2012 if (ihdr->base_addr_64_bit) 2013 ip_offset += struct_size(ip, base_address_64, ip->num_base_address); 2014 else 2015 ip_offset += struct_size(ip, base_address, ip->num_base_address); 2016 } 2017 } 2018 2019 if (wafl_ver && !adev->ip_versions[XGMI_HWIP][0]) 2020 adev->ip_versions[XGMI_HWIP][0] = wafl_ver; 2021 2022 return 0; 2023 } 2024 2025 static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev) 2026 { 2027 uint8_t *discovery_bin = adev->discovery.bin; 2028 struct ip_discovery_header *ihdr; 2029 struct table_info *info; 2030 int vcn_harvest_count = 0; 2031 int umc_harvest_count = 0; 2032 uint16_t ihdr_ver; 2033 2034 if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY)) 2035 return; 2036 ihdr = (struct ip_discovery_header *)(discovery_bin + 2037 le16_to_cpu(info->offset)); 2038 ihdr_ver = le16_to_cpu(ihdr->version); 2039 /* 2040 * Harvest table does not fit Navi1x and legacy GPUs, 2041 * so read harvest bit per IP data structure to set 2042 * harvest configuration. 2043 */ 2044 if (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(10, 2, 0) && 2045 ihdr_ver <= 2) { 2046 if ((adev->pdev->device == 0x731E && 2047 (adev->pdev->revision == 0xC6 || 2048 adev->pdev->revision == 0xC7)) || 2049 (adev->pdev->device == 0x7340 && 2050 adev->pdev->revision == 0xC9) || 2051 (adev->pdev->device == 0x7360 && 2052 adev->pdev->revision == 0xC7)) 2053 amdgpu_discovery_read_harvest_bit_per_ip(adev, 2054 &vcn_harvest_count); 2055 } else { 2056 amdgpu_discovery_read_from_harvest_table(adev, 2057 &vcn_harvest_count, 2058 &umc_harvest_count); 2059 } 2060 2061 amdgpu_discovery_harvest_config_quirk(adev); 2062 2063 if (vcn_harvest_count == adev->vcn.num_vcn_inst) { 2064 adev->harvest_ip_mask |= AMD_HARVEST_IP_VCN_MASK; 2065 adev->harvest_ip_mask |= AMD_HARVEST_IP_JPEG_MASK; 2066 } 2067 2068 if (umc_harvest_count < adev->gmc.num_umc) { 2069 adev->gmc.num_umc -= umc_harvest_count; 2070 } 2071 } 2072 2073 union gc_info { 2074 struct gc_info_v1_0 v1; 2075 struct gc_info_v1_1 v1_1; 2076 struct gc_info_v1_2 v1_2; 2077 struct gc_info_v1_3 v1_3; 2078 struct gc_info_v1_4 v1_4; 2079 struct gc_info_v1_5 v1_5; 2080 struct gc_info_v2_0 v2; 2081 struct gc_info_v2_1 v2_1; 2082 }; 2083 2084 static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) 2085 { 2086 uint8_t *discovery_bin = adev->discovery.bin; 2087 struct table_info *info; 2088 union gc_info *gc_info; 2089 uint32_t num_wgps_per_sa, num_wgps_per_sa1; 2090 u16 offset; 2091 2092 if (!discovery_bin) { 2093 DRM_ERROR("ip discovery uninitialized\n"); 2094 return -EINVAL; 2095 } 2096 2097 if (amdgpu_discovery_get_table_info(adev, &info, GC)) 2098 return -EINVAL; 2099 offset = le16_to_cpu(info->offset); 2100 2101 if (!offset) 2102 return 0; 2103 2104 gc_info = (union gc_info *)(discovery_bin + offset); 2105 2106 switch (le16_to_cpu(gc_info->v1.header.version_major)) { 2107 case 1: 2108 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v1.gc_num_se); 2109 adev->gfx.config.max_cu_per_sh = 2 * (le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 2110 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa)); 2111 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 2112 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v1.gc_num_rb_per_se); 2113 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v1.gc_num_gl2c); 2114 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v1.gc_num_gprs); 2115 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v1.gc_num_max_gs_thds); 2116 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v1.gc_gs_table_depth); 2117 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v1.gc_gsprim_buff_depth); 2118 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v1.gc_double_offchip_lds_buffer); 2119 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v1.gc_wave_size); 2120 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v1.gc_max_waves_per_simd); 2121 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v1.gc_max_scratch_slots_per_cu); 2122 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v1.gc_lds_size); 2123 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v1.gc_num_sc_per_se) / 2124 le32_to_cpu(gc_info->v1.gc_num_sa_per_se); 2125 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v1.gc_num_packer_per_sc); 2126 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 1) { 2127 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v1_1.gc_num_tcp_per_sa); 2128 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v1_1.gc_num_sdp_interface); 2129 adev->gfx.config.gc_num_tcps = le32_to_cpu(gc_info->v1_1.gc_num_tcps); 2130 } 2131 if (le16_to_cpu(gc_info->v1.header.version_minor) >= 2) { 2132 adev->gfx.config.gc_num_tcp_per_wpg = le32_to_cpu(gc_info->v1_2.gc_num_tcp_per_wpg); 2133 adev->gfx.config.gc_tcp_l1_size = le32_to_cpu(gc_info->v1_2.gc_tcp_l1_size); 2134 adev->gfx.config.gc_num_sqc_per_wgp = le32_to_cpu(gc_info->v1_2.gc_num_sqc_per_wgp); 2135 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_instruction_cache_size_per_sqc); 2136 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_2.gc_l1_data_cache_size_per_sqc); 2137 adev->gfx.config.gc_gl1c_per_sa = le32_to_cpu(gc_info->v1_2.gc_gl1c_per_sa); 2138 adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); 2139 adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); 2140 } 2141 if (le16_to_cpu(gc_info->v1.header.version_minor) == 4) { 2142 num_wgps_per_sa = le32_to_cpu(gc_info->v1_4.gc_num_rwgp0_per_sa) + 2143 le32_to_cpu(gc_info->v1_4.gc_num_rwgp1_per_sa) + 2144 le32_to_cpu(gc_info->v1_4.gc_num_twgp0_per_sa) + 2145 le32_to_cpu(gc_info->v1_4.gc_num_twgp1_per_sa); 2146 num_wgps_per_sa1 = le32_to_cpu(gc_info->v1_4.gc_num_rwgp0_per_sa1) + 2147 le32_to_cpu(gc_info->v1_4.gc_num_rwgp1_per_sa1) + 2148 le32_to_cpu(gc_info->v1_4.gc_num_twgp0_per_sa1) + 2149 le32_to_cpu(gc_info->v1_4.gc_num_twgp1_per_sa1); 2150 adev->gfx.config.max_cu_per_sh = 2 * (num_wgps_per_sa >= num_wgps_per_sa1 ? 2151 num_wgps_per_sa : num_wgps_per_sa1); 2152 } else if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { 2153 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); 2154 adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); 2155 adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); 2156 adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); 2157 adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); 2158 adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); 2159 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); 2160 adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); 2161 } 2162 if (le16_to_cpu(gc_info->v1.header.version_minor) == 5) { 2163 adev->gfx.config.gc_max_num_residency_ways = le32_to_cpu(gc_info->v1_5.gc_max_num_residency_ways); 2164 adev->gfx.config.gc_cache_ways_size_in_bytes = le32_to_cpu(gc_info->v1_5.gc_cache_ways_size_in_bytes); 2165 adev->gfx.config.gc_reserved = le32_to_cpu(gc_info->v1_5.gc_reserved); 2166 2167 num_wgps_per_sa = le32_to_cpu(gc_info->v1.gc_num_wgp0_per_sa) + 2168 le32_to_cpu(gc_info->v1.gc_num_wgp1_per_sa); 2169 num_wgps_per_sa1 = le32_to_cpu(gc_info->v1_5.gc_num_wgp0_per_sa1) + 2170 le32_to_cpu(gc_info->v1_5.gc_num_wgp1_per_sa1); 2171 adev->gfx.config.max_cu_per_sh = num_wgps_per_sa >= num_wgps_per_sa1 ? 2172 num_wgps_per_sa : num_wgps_per_sa1; 2173 } 2174 break; 2175 case 2: 2176 adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); 2177 adev->gfx.config.max_cu_per_sh = le32_to_cpu(gc_info->v2.gc_num_cu_per_sh); 2178 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 2179 adev->gfx.config.max_backends_per_se = le32_to_cpu(gc_info->v2.gc_num_rb_per_se); 2180 adev->gfx.config.max_texture_channel_caches = le32_to_cpu(gc_info->v2.gc_num_tccs); 2181 adev->gfx.config.max_gprs = le32_to_cpu(gc_info->v2.gc_num_gprs); 2182 adev->gfx.config.max_gs_threads = le32_to_cpu(gc_info->v2.gc_num_max_gs_thds); 2183 adev->gfx.config.gs_vgt_table_depth = le32_to_cpu(gc_info->v2.gc_gs_table_depth); 2184 adev->gfx.config.gs_prim_buffer_depth = le32_to_cpu(gc_info->v2.gc_gsprim_buff_depth); 2185 adev->gfx.config.double_offchip_lds_buf = le32_to_cpu(gc_info->v2.gc_double_offchip_lds_buffer); 2186 adev->gfx.cu_info.wave_front_size = le32_to_cpu(gc_info->v2.gc_wave_size); 2187 adev->gfx.cu_info.max_waves_per_simd = le32_to_cpu(gc_info->v2.gc_max_waves_per_simd); 2188 adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gc_info->v2.gc_max_scratch_slots_per_cu); 2189 adev->gfx.cu_info.lds_size = le32_to_cpu(gc_info->v2.gc_lds_size); 2190 adev->gfx.config.num_sc_per_sh = le32_to_cpu(gc_info->v2.gc_num_sc_per_se) / 2191 le32_to_cpu(gc_info->v2.gc_num_sh_per_se); 2192 adev->gfx.config.num_packer_per_sc = le32_to_cpu(gc_info->v2.gc_num_packer_per_sc); 2193 if (le16_to_cpu(gc_info->v2.header.version_minor) == 1) { 2194 adev->gfx.config.gc_num_tcp_per_sa = le32_to_cpu(gc_info->v2_1.gc_num_tcp_per_sh); 2195 adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v2_1.gc_tcp_size_per_cu); 2196 adev->gfx.config.gc_num_sdp_interface = le32_to_cpu(gc_info->v2_1.gc_num_sdp_interface); /* per XCD */ 2197 adev->gfx.config.gc_num_cu_per_sqc = le32_to_cpu(gc_info->v2_1.gc_num_cu_per_sqc); 2198 adev->gfx.config.gc_l1_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_instruction_cache_size_per_sqc); 2199 adev->gfx.config.gc_l1_data_cache_size_per_sqc = le32_to_cpu(gc_info->v2_1.gc_scalar_data_cache_size_per_sqc); 2200 adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v2_1.gc_tcc_size); /* per XCD */ 2201 } 2202 break; 2203 default: 2204 dev_err(adev->dev, 2205 "Unhandled GC info table %d.%d\n", 2206 le16_to_cpu(gc_info->v1.header.version_major), 2207 le16_to_cpu(gc_info->v1.header.version_minor)); 2208 return -EINVAL; 2209 } 2210 return 0; 2211 } 2212 2213 union mall_info { 2214 struct mall_info_v1_0 v1; 2215 struct mall_info_v2_0 v2; 2216 }; 2217 2218 static int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev) 2219 { 2220 uint8_t *discovery_bin = adev->discovery.bin; 2221 struct table_info *info; 2222 union mall_info *mall_info; 2223 u32 u, mall_size_per_umc, m_s_present, half_use; 2224 u64 mall_size; 2225 u16 offset, size; 2226 2227 if (!discovery_bin) { 2228 DRM_ERROR("ip discovery uninitialized\n"); 2229 return -EINVAL; 2230 } 2231 2232 if (amdgpu_discovery_get_table_info(adev, &info, MALL_INFO)) 2233 return -EINVAL; 2234 offset = le16_to_cpu(info->offset); 2235 size = le16_to_cpu(info->size); 2236 2237 if (!offset || !size) 2238 return 0; 2239 2240 mall_info = (union mall_info *)(discovery_bin + offset); 2241 2242 switch (le16_to_cpu(mall_info->v1.header.version_major)) { 2243 case 1: 2244 mall_size = 0; 2245 mall_size_per_umc = le32_to_cpu(mall_info->v1.mall_size_per_m); 2246 m_s_present = le32_to_cpu(mall_info->v1.m_s_present); 2247 half_use = le32_to_cpu(mall_info->v1.m_half_use); 2248 for (u = 0; u < adev->gmc.num_umc; u++) { 2249 if (m_s_present & (1 << u)) 2250 mall_size += mall_size_per_umc * 2; 2251 else if (half_use & (1 << u)) 2252 mall_size += mall_size_per_umc / 2; 2253 else 2254 mall_size += mall_size_per_umc; 2255 } 2256 adev->gmc.mall_size = mall_size; 2257 adev->gmc.m_half_use = half_use; 2258 break; 2259 case 2: 2260 mall_size_per_umc = le32_to_cpu(mall_info->v2.mall_size_per_umc); 2261 adev->gmc.mall_size = (uint64_t)mall_size_per_umc * adev->gmc.num_umc; 2262 break; 2263 default: 2264 dev_err(adev->dev, 2265 "Unhandled MALL info table %d.%d\n", 2266 le16_to_cpu(mall_info->v1.header.version_major), 2267 le16_to_cpu(mall_info->v1.header.version_minor)); 2268 return -EINVAL; 2269 } 2270 return 0; 2271 } 2272 2273 union vcn_info { 2274 struct vcn_info_v1_0 v1; 2275 }; 2276 2277 static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev) 2278 { 2279 uint8_t *discovery_bin = adev->discovery.bin; 2280 struct table_info *info; 2281 union vcn_info *vcn_info; 2282 u16 offset, size; 2283 int v; 2284 2285 if (!discovery_bin) { 2286 DRM_ERROR("ip discovery uninitialized\n"); 2287 return -EINVAL; 2288 } 2289 2290 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 2291 * which is smaller than VCN_INFO_TABLE_MAX_NUM_INSTANCES 2292 * but that may change in the future with new GPUs so keep this 2293 * check for defensive purposes. 2294 */ 2295 if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) { 2296 dev_err(adev->dev, "invalid vcn instances\n"); 2297 return -EINVAL; 2298 } 2299 2300 if (amdgpu_discovery_get_table_info(adev, &info, VCN_INFO)) 2301 return -EINVAL; 2302 offset = le16_to_cpu(info->offset); 2303 size = le16_to_cpu(info->size); 2304 2305 if (!offset || !size) 2306 return 0; 2307 2308 vcn_info = (union vcn_info *)(discovery_bin + offset); 2309 2310 switch (le16_to_cpu(vcn_info->v1.header.version_major)) { 2311 case 1: 2312 /* num_vcn_inst is currently limited to AMDGPU_MAX_VCN_INSTANCES 2313 * so this won't overflow. 2314 */ 2315 for (v = 0; v < adev->vcn.num_vcn_inst; v++) { 2316 adev->vcn.inst[v].vcn_codec_disable_mask = 2317 le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits); 2318 } 2319 break; 2320 default: 2321 dev_err(adev->dev, 2322 "Unhandled VCN info table %d.%d\n", 2323 le16_to_cpu(vcn_info->v1.header.version_major), 2324 le16_to_cpu(vcn_info->v1.header.version_minor)); 2325 return -EINVAL; 2326 } 2327 return 0; 2328 } 2329 2330 union nps_info { 2331 struct nps_info_v1_0 v1; 2332 }; 2333 2334 static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, 2335 union nps_info *nps_data) 2336 { 2337 uint64_t vram_size, pos, offset; 2338 struct nps_info_header *nhdr; 2339 struct binary_header bhdr; 2340 struct binary_header_v2 bhdrv2; 2341 uint16_t checksum; 2342 2343 vram_size = (uint64_t)amdgpu_discovery_get_config_memsize(adev) << 20; 2344 pos = vram_size - DISCOVERY_TMR_OFFSET; 2345 amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); 2346 2347 switch (bhdr.version_major) { 2348 case 2: 2349 amdgpu_device_vram_access(adev, pos, &bhdrv2, sizeof(bhdrv2), false); 2350 offset = le16_to_cpu(bhdrv2.table_list[NPS_INFO].offset); 2351 checksum = le16_to_cpu(bhdrv2.table_list[NPS_INFO].checksum); 2352 break; 2353 case 1: 2354 offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); 2355 checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); 2356 break; 2357 default: 2358 return -EINVAL; 2359 } 2360 2361 amdgpu_device_vram_access(adev, (pos + offset), nps_data, 2362 sizeof(*nps_data), false); 2363 2364 nhdr = (struct nps_info_header *)(nps_data); 2365 if (!amdgpu_discovery_verify_checksum(adev, (uint8_t *)nps_data, 2366 le32_to_cpu(nhdr->size_bytes), 2367 checksum)) { 2368 dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); 2369 return -EINVAL; 2370 } 2371 2372 return 0; 2373 } 2374 2375 int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, 2376 uint32_t *nps_type, 2377 struct amdgpu_gmc_memrange *ranges, 2378 int *range_cnt, bool refresh) 2379 { 2380 uint8_t *discovery_bin = adev->discovery.bin; 2381 struct table_info *info; 2382 union nps_info *nps_info; 2383 union nps_info nps_data; 2384 u16 offset; 2385 int i, r; 2386 2387 if (!nps_type || !range_cnt || !ranges) 2388 return -EINVAL; 2389 2390 if (refresh) { 2391 r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); 2392 if (r) 2393 return r; 2394 nps_info = &nps_data; 2395 } else { 2396 if (!discovery_bin) { 2397 dev_err(adev->dev, 2398 "fetch mem range failed, ip discovery uninitialized\n"); 2399 return -EINVAL; 2400 } 2401 2402 if (amdgpu_discovery_get_table_info(adev, &info, NPS_INFO)) 2403 return -EINVAL; 2404 offset = le16_to_cpu(info->offset); 2405 2406 if (!offset) 2407 return -ENOENT; 2408 2409 /* If verification fails, return as if NPS table doesn't exist */ 2410 if (amdgpu_discovery_verify_npsinfo(adev, info)) 2411 return -ENOENT; 2412 2413 nps_info = (union nps_info *)(discovery_bin + offset); 2414 } 2415 2416 switch (le16_to_cpu(nps_info->v1.header.version_major)) { 2417 case 1: 2418 *nps_type = nps_info->v1.nps_type; 2419 if (*range_cnt < nps_info->v1.count) { 2420 dev_dbg(adev->dev, 2421 "not enough space for nps ranges: %d < %d\n", 2422 *range_cnt, nps_info->v1.count); 2423 return -ENOSPC; 2424 } 2425 *range_cnt = nps_info->v1.count; 2426 for (i = 0; i < *range_cnt; i++) { 2427 ranges[i].base_address = 2428 nps_info->v1.instance_info[i].base_address; 2429 ranges[i].limit_address = 2430 nps_info->v1.instance_info[i].limit_address; 2431 ranges[i].nid_mask = -1; 2432 ranges[i].flags = 0; 2433 } 2434 break; 2435 default: 2436 dev_err(adev->dev, "Unhandled NPS info table %d.%d\n", 2437 le16_to_cpu(nps_info->v1.header.version_major), 2438 le16_to_cpu(nps_info->v1.header.version_minor)); 2439 return -EINVAL; 2440 } 2441 2442 return 0; 2443 } 2444 2445 static const char *amdgpu_discovery_mem_reserved_region_name(u32 id) 2446 { 2447 switch (id) { 2448 case NO_RESERVED_REGION_ID: return "NO_RESERVED_REGION"; 2449 case PRE_OS_DISP_FW_REGION_ID: return "PRE_OS_DISP_FW"; 2450 case MASTER_DIE_UMF_REGION_ID: return "MASTER_DIE_UMF"; 2451 case DCC_META_DATA_REGION_ID: return "DCC_META_DATA"; 2452 case VM_PAGE_FAULT_REGION_ID: return "VM_PAGE_FAULT"; 2453 case G7_PSTATE_APERTURE1_ID: return "G7_PSTATE_APERTURE1"; 2454 case G7_PSTATE_APERTURE2_ID: return "G7_PSTATE_APERTURE2"; 2455 case G7_PSTATE_MIRROR_REGION_ID: return "G7_PSTATE_MIRROR"; 2456 case G7_TRAINING_DATA_REGION_ID: return "G7_TRAINING_DATA"; 2457 case SPECIFIC_PURPOSE_REGION_ID: return "SPECIFIC_PURPOSE"; 2458 default: return "UNKNOWN"; 2459 } 2460 } 2461 2462 /* Dump all the mem_reserved_info table entries for debugging */ 2463 static void amdgpu_discovery_dump_mem_reserved_info_table(struct amdgpu_device *adev, 2464 struct mem_reserved_info_table_v1_0 *table) 2465 { 2466 u32 list_num = min_t(u32, le32_to_cpu(table->list_num), MAX_MEM_REGION_NUM); 2467 u32 id, i; 2468 2469 dev_info(adev->dev, "MEM_RESERVED_INFO: list_num=%u\n", list_num); 2470 for (i = 0; i < list_num; i++) { 2471 id = le32_to_cpu(table->list[i].reserved_region_id); 2472 dev_info(adev->dev, " [%u] id=%u (%s) size=0x%llx start=0x%llx\n", 2473 i, id, 2474 amdgpu_discovery_mem_reserved_region_name(id), 2475 le64_to_cpu(table->list[i].reserved_region_size), 2476 le64_to_cpu(table->list[i].reserved_region_start)); 2477 } 2478 } 2479 2480 /** 2481 * Add READ-ONLY mem_reserved_info sysfs entry. 2482 * MEM_RESERVED_INFO table is parsed from the IP discovery binary. 2483 * The file mem_reserved_info dumps every entry as: 2484 * list_num=<N> 2485 * [<i>] id=<id> (<name>) size=<size> start=<start> 2486 */ 2487 static ssize_t mem_reserved_info_show(struct device *dev, 2488 struct device_attribute *attr, char *buf) 2489 { 2490 struct drm_device *ddev = dev_get_drvdata(dev); 2491 struct amdgpu_device *adev = drm_to_adev(ddev); 2492 struct mem_reserved_info_table_v1_0 *table; 2493 u32 list_num, id, i; 2494 ssize_t len = 0; 2495 2496 if (amdgpu_discovery_get_mem_reserved_info_table(adev)) 2497 return sysfs_emit(buf, "MEM_RESERVED_INFO table not available\n"); 2498 2499 table = adev->discovery.mem_reserved_table; 2500 list_num = min_t(u32, le32_to_cpu(table->list_num), MAX_MEM_REGION_NUM); 2501 2502 len += sysfs_emit_at(buf, len, "list_num=%u\n", list_num); 2503 for (i = 0; i < list_num; i++) { 2504 id = le32_to_cpu(table->list[i].reserved_region_id); 2505 len += sysfs_emit_at(buf, len, 2506 "[%u] id=%u (%s) size=0x%llx start=0x%llx\n", 2507 i, id, 2508 amdgpu_discovery_mem_reserved_region_name(id), 2509 le64_to_cpu(table->list[i].reserved_region_size), 2510 le64_to_cpu(table->list[i].reserved_region_start)); 2511 } 2512 2513 return len; 2514 } 2515 2516 static DEVICE_ATTR_RO(mem_reserved_info); 2517 2518 int amdgpu_discovery_mem_reserved_info_sysfs_init(struct amdgpu_device *adev) 2519 { 2520 if (!adev->discovery.mem_reserved_table) 2521 return 0; 2522 2523 return sysfs_create_file(&adev->dev->kobj, 2524 &dev_attr_mem_reserved_info.attr); 2525 } 2526 2527 void amdgpu_discovery_mem_reserved_info_sysfs_fini(struct amdgpu_device *adev) 2528 { 2529 if (!adev->discovery.mem_reserved_table) 2530 return; 2531 2532 sysfs_remove_file(&adev->dev->kobj, 2533 &dev_attr_mem_reserved_info.attr); 2534 } 2535 2536 /* 2537 * Resolve the MEM_RESERVED_INFO table from the IP discovery binary and 2538 * cache it in adev->discovery.mem_reserved_table. 2539 * Return: 0 on success, -ENOENT/-EINVAL if the table unavailable. 2540 */ 2541 int amdgpu_discovery_get_mem_reserved_info_table(struct amdgpu_device *adev) 2542 { 2543 uint8_t *discovery_bin = adev->discovery.bin; 2544 struct mem_reserved_info_header *mrhdr; 2545 struct binary_header *bhdr; 2546 struct table_info *info; 2547 u16 offset; 2548 2549 /* If already queried, do not query again. */ 2550 if (adev->discovery.mem_reserved_table) 2551 return 0; 2552 2553 if (!discovery_bin) { 2554 dev_err(adev->dev, "ip discovery uninitialized\n"); 2555 return -ENOENT; 2556 } 2557 2558 /* MEM_RESERVED_INFO only exists in binary_header >= v2. Skip populating it on v1 */ 2559 bhdr = (struct binary_header *)discovery_bin; 2560 if (le16_to_cpu(bhdr->version_major) < 2) { 2561 dev_dbg(adev->dev, "header version = %d\n", le16_to_cpu(bhdr->version_major)); 2562 return -ENOENT; 2563 } 2564 2565 if (amdgpu_discovery_get_table_info(adev, &info, MEM_RESERVED_INFO)) { 2566 dev_dbg(adev->dev, "MEM_RESERVED_INFO table entry not present\n"); 2567 return -EINVAL; 2568 } 2569 2570 offset = le16_to_cpu(info->offset); 2571 if (!offset) { 2572 dev_dbg(adev->dev, "MEM_RESERVED_INFO table offset is 0, invalid!\n"); 2573 return -EINVAL; 2574 } 2575 2576 /* 2577 * Only populated when the signature matches; skip ASICs whose 2578 * slot points to unrelated data. 2579 */ 2580 mrhdr = (struct mem_reserved_info_header *)(discovery_bin + offset); 2581 if (le32_to_cpu(mrhdr->signature) != MEM_RSV_TABLE_SIGNATURE) { 2582 dev_dbg(adev->dev, "MEM_RESERVED_INFO table signature mismatch, skipping\n"); 2583 return -ENOENT; 2584 } 2585 2586 /* Cache for subsequent lookups. */ 2587 adev->discovery.mem_reserved_table = 2588 (struct mem_reserved_info_table_v1_0 *)mrhdr; 2589 2590 dev_dbg(adev->dev, "MEM_RESERVED_INFO table exist\n"); 2591 return 0; 2592 } 2593 2594 /** 2595 * Query mem_reserved_info by region ID 2596 * 2597 * @reserved_region_id: MEM_RESERVED_REGION_ID to look up 2598 * @info: pass NULL to skip 2599 */ 2600 int amdgpu_discovery_get_mem_reserved_region_by_id(struct amdgpu_device *adev, 2601 u32 reserved_region_id, 2602 struct mem_reserved_info *info) 2603 { 2604 struct mem_reserved_info_table_v1_0 *table; 2605 u32 list_num, i; 2606 2607 if (!adev->discovery.mem_reserved_table) 2608 return -ENOENT; 2609 2610 table = adev->discovery.mem_reserved_table; 2611 list_num = min_t(u32, le32_to_cpu(table->list_num), MAX_MEM_REGION_NUM); 2612 2613 for (i = 0; i < list_num; i++) { 2614 if (le32_to_cpu(table->list[i].reserved_region_id) != reserved_region_id) 2615 continue; 2616 2617 if (info) { 2618 info->reserved_region_id = reserved_region_id; 2619 info->reserved_region_size = 2620 le64_to_cpu(table->list[i].reserved_region_size); 2621 info->reserved_region_start = 2622 le64_to_cpu(table->list[i].reserved_region_start); 2623 } 2624 dev_dbg(adev->dev, "Found reserved region: %s (id=%u)\n", 2625 amdgpu_discovery_mem_reserved_region_name(reserved_region_id), 2626 reserved_region_id); 2627 return 0; 2628 } 2629 return -ENOENT; 2630 } 2631 2632 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev) 2633 { 2634 /* what IP to use for this? */ 2635 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2636 case IP_VERSION(9, 0, 1): 2637 case IP_VERSION(9, 1, 0): 2638 case IP_VERSION(9, 2, 1): 2639 case IP_VERSION(9, 2, 2): 2640 case IP_VERSION(9, 3, 0): 2641 case IP_VERSION(9, 4, 0): 2642 case IP_VERSION(9, 4, 1): 2643 case IP_VERSION(9, 4, 2): 2644 case IP_VERSION(9, 4, 3): 2645 case IP_VERSION(9, 4, 4): 2646 case IP_VERSION(9, 5, 0): 2647 amdgpu_device_ip_block_add(adev, &vega10_common_ip_block); 2648 break; 2649 case IP_VERSION(10, 1, 10): 2650 case IP_VERSION(10, 1, 1): 2651 case IP_VERSION(10, 1, 2): 2652 case IP_VERSION(10, 1, 3): 2653 case IP_VERSION(10, 1, 4): 2654 case IP_VERSION(10, 3, 0): 2655 case IP_VERSION(10, 3, 1): 2656 case IP_VERSION(10, 3, 2): 2657 case IP_VERSION(10, 3, 3): 2658 case IP_VERSION(10, 3, 4): 2659 case IP_VERSION(10, 3, 5): 2660 case IP_VERSION(10, 3, 6): 2661 case IP_VERSION(10, 3, 7): 2662 amdgpu_device_ip_block_add(adev, &nv_common_ip_block); 2663 break; 2664 case IP_VERSION(11, 0, 0): 2665 case IP_VERSION(11, 0, 1): 2666 case IP_VERSION(11, 0, 2): 2667 case IP_VERSION(11, 0, 3): 2668 case IP_VERSION(11, 0, 4): 2669 case IP_VERSION(11, 5, 0): 2670 case IP_VERSION(11, 5, 1): 2671 case IP_VERSION(11, 5, 2): 2672 case IP_VERSION(11, 5, 3): 2673 case IP_VERSION(11, 5, 4): 2674 case IP_VERSION(11, 5, 6): 2675 case IP_VERSION(11, 7, 0): 2676 case IP_VERSION(11, 7, 1): 2677 amdgpu_device_ip_block_add(adev, &soc21_common_ip_block); 2678 break; 2679 case IP_VERSION(12, 0, 0): 2680 case IP_VERSION(12, 0, 1): 2681 amdgpu_device_ip_block_add(adev, &soc24_common_ip_block); 2682 break; 2683 case IP_VERSION(12, 1, 0): 2684 amdgpu_device_ip_block_add(adev, &soc_v1_0_common_ip_block); 2685 break; 2686 default: 2687 dev_err(adev->dev, 2688 "Failed to add common ip block(GC_HWIP:0x%x)\n", 2689 amdgpu_ip_version(adev, GC_HWIP, 0)); 2690 return -EINVAL; 2691 } 2692 return 0; 2693 } 2694 2695 static int amdgpu_discovery_set_gmc_ip_blocks(struct amdgpu_device *adev) 2696 { 2697 /* use GC or MMHUB IP version */ 2698 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 2699 case IP_VERSION(9, 0, 1): 2700 case IP_VERSION(9, 1, 0): 2701 case IP_VERSION(9, 2, 1): 2702 case IP_VERSION(9, 2, 2): 2703 case IP_VERSION(9, 3, 0): 2704 case IP_VERSION(9, 4, 0): 2705 case IP_VERSION(9, 4, 1): 2706 case IP_VERSION(9, 4, 2): 2707 case IP_VERSION(9, 4, 3): 2708 case IP_VERSION(9, 4, 4): 2709 case IP_VERSION(9, 5, 0): 2710 amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block); 2711 break; 2712 case IP_VERSION(10, 1, 10): 2713 case IP_VERSION(10, 1, 1): 2714 case IP_VERSION(10, 1, 2): 2715 case IP_VERSION(10, 1, 3): 2716 case IP_VERSION(10, 1, 4): 2717 case IP_VERSION(10, 3, 0): 2718 case IP_VERSION(10, 3, 1): 2719 case IP_VERSION(10, 3, 2): 2720 case IP_VERSION(10, 3, 3): 2721 case IP_VERSION(10, 3, 4): 2722 case IP_VERSION(10, 3, 5): 2723 case IP_VERSION(10, 3, 6): 2724 case IP_VERSION(10, 3, 7): 2725 amdgpu_device_ip_block_add(adev, &gmc_v10_0_ip_block); 2726 break; 2727 case IP_VERSION(11, 0, 0): 2728 case IP_VERSION(11, 0, 1): 2729 case IP_VERSION(11, 0, 2): 2730 case IP_VERSION(11, 0, 3): 2731 case IP_VERSION(11, 0, 4): 2732 case IP_VERSION(11, 5, 0): 2733 case IP_VERSION(11, 5, 1): 2734 case IP_VERSION(11, 5, 2): 2735 case IP_VERSION(11, 5, 3): 2736 case IP_VERSION(11, 5, 4): 2737 case IP_VERSION(11, 5, 6): 2738 case IP_VERSION(11, 7, 0): 2739 case IP_VERSION(11, 7, 1): 2740 amdgpu_device_ip_block_add(adev, &gmc_v11_0_ip_block); 2741 break; 2742 case IP_VERSION(12, 0, 0): 2743 case IP_VERSION(12, 0, 1): 2744 case IP_VERSION(12, 1, 0): 2745 amdgpu_device_ip_block_add(adev, &gmc_v12_0_ip_block); 2746 break; 2747 default: 2748 dev_err(adev->dev, "Failed to add gmc ip block(GC_HWIP:0x%x)\n", 2749 amdgpu_ip_version(adev, GC_HWIP, 0)); 2750 return -EINVAL; 2751 } 2752 return 0; 2753 } 2754 2755 static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev) 2756 { 2757 switch (amdgpu_ip_version(adev, OSSSYS_HWIP, 0)) { 2758 case IP_VERSION(4, 0, 0): 2759 case IP_VERSION(4, 0, 1): 2760 case IP_VERSION(4, 1, 0): 2761 case IP_VERSION(4, 1, 1): 2762 case IP_VERSION(4, 3, 0): 2763 amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block); 2764 break; 2765 case IP_VERSION(4, 2, 0): 2766 case IP_VERSION(4, 2, 1): 2767 case IP_VERSION(4, 4, 0): 2768 case IP_VERSION(4, 4, 2): 2769 case IP_VERSION(4, 4, 5): 2770 amdgpu_device_ip_block_add(adev, &vega20_ih_ip_block); 2771 break; 2772 case IP_VERSION(5, 0, 0): 2773 case IP_VERSION(5, 0, 1): 2774 case IP_VERSION(5, 0, 2): 2775 case IP_VERSION(5, 0, 3): 2776 case IP_VERSION(5, 2, 0): 2777 case IP_VERSION(5, 2, 1): 2778 amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block); 2779 break; 2780 case IP_VERSION(6, 0, 0): 2781 case IP_VERSION(6, 0, 1): 2782 case IP_VERSION(6, 0, 2): 2783 amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block); 2784 break; 2785 case IP_VERSION(6, 1, 0): 2786 case IP_VERSION(6, 1, 1): 2787 case IP_VERSION(6, 4, 0): 2788 amdgpu_device_ip_block_add(adev, &ih_v6_1_ip_block); 2789 break; 2790 case IP_VERSION(7, 0, 0): 2791 case IP_VERSION(7, 1, 0): 2792 amdgpu_device_ip_block_add(adev, &ih_v7_0_ip_block); 2793 break; 2794 case IP_VERSION(8, 0, 1): 2795 amdgpu_device_ip_block_add(adev, &ih_v8_0_ip_block); 2796 break; 2797 default: 2798 dev_err(adev->dev, 2799 "Failed to add ih ip block(OSSSYS_HWIP:0x%x)\n", 2800 amdgpu_ip_version(adev, OSSSYS_HWIP, 0)); 2801 return -EINVAL; 2802 } 2803 return 0; 2804 } 2805 2806 static int amdgpu_discovery_set_psp_ip_blocks(struct amdgpu_device *adev) 2807 { 2808 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 2809 case IP_VERSION(9, 0, 0): 2810 amdgpu_device_ip_block_add(adev, &psp_v3_1_ip_block); 2811 break; 2812 case IP_VERSION(10, 0, 0): 2813 case IP_VERSION(10, 0, 1): 2814 amdgpu_device_ip_block_add(adev, &psp_v10_0_ip_block); 2815 break; 2816 case IP_VERSION(11, 0, 0): 2817 case IP_VERSION(11, 0, 2): 2818 case IP_VERSION(11, 0, 4): 2819 case IP_VERSION(11, 0, 5): 2820 case IP_VERSION(11, 0, 9): 2821 case IP_VERSION(11, 0, 7): 2822 case IP_VERSION(11, 0, 11): 2823 case IP_VERSION(11, 0, 12): 2824 case IP_VERSION(11, 0, 13): 2825 case IP_VERSION(11, 5, 0): 2826 case IP_VERSION(11, 5, 2): 2827 amdgpu_device_ip_block_add(adev, &psp_v11_0_ip_block); 2828 break; 2829 case IP_VERSION(11, 0, 8): 2830 amdgpu_device_ip_block_add(adev, &psp_v11_0_8_ip_block); 2831 break; 2832 case IP_VERSION(11, 0, 3): 2833 case IP_VERSION(12, 0, 1): 2834 amdgpu_device_ip_block_add(adev, &psp_v12_0_ip_block); 2835 break; 2836 case IP_VERSION(13, 0, 0): 2837 case IP_VERSION(13, 0, 1): 2838 case IP_VERSION(13, 0, 2): 2839 case IP_VERSION(13, 0, 3): 2840 case IP_VERSION(13, 0, 5): 2841 case IP_VERSION(13, 0, 6): 2842 case IP_VERSION(13, 0, 7): 2843 case IP_VERSION(13, 0, 8): 2844 case IP_VERSION(13, 0, 10): 2845 case IP_VERSION(13, 0, 11): 2846 case IP_VERSION(13, 0, 12): 2847 case IP_VERSION(13, 0, 14): 2848 case IP_VERSION(13, 0, 15): 2849 case IP_VERSION(14, 0, 0): 2850 case IP_VERSION(14, 0, 1): 2851 case IP_VERSION(14, 0, 4): 2852 amdgpu_device_ip_block_add(adev, &psp_v13_0_ip_block); 2853 break; 2854 case IP_VERSION(13, 0, 4): 2855 amdgpu_device_ip_block_add(adev, &psp_v13_0_4_ip_block); 2856 break; 2857 case IP_VERSION(14, 0, 2): 2858 case IP_VERSION(14, 0, 3): 2859 case IP_VERSION(14, 0, 5): 2860 amdgpu_device_ip_block_add(adev, &psp_v14_0_ip_block); 2861 break; 2862 case IP_VERSION(15, 0, 0): 2863 case IP_VERSION(15, 0, 5): 2864 case IP_VERSION(15, 0, 9): 2865 amdgpu_device_ip_block_add(adev, &psp_v15_0_ip_block); 2866 break; 2867 case IP_VERSION(15, 0, 3): 2868 amdgpu_device_ip_block_add(adev, &psp_v15_0_3_ip_block); 2869 break; 2870 case IP_VERSION(15, 0, 8): 2871 amdgpu_device_ip_block_add(adev, &psp_v15_0_8_ip_block); 2872 break; 2873 default: 2874 dev_err(adev->dev, 2875 "Failed to add psp ip block(MP0_HWIP:0x%x)\n", 2876 amdgpu_ip_version(adev, MP0_HWIP, 0)); 2877 return -EINVAL; 2878 } 2879 return 0; 2880 } 2881 2882 static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev) 2883 { 2884 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) { 2885 case IP_VERSION(9, 0, 0): 2886 case IP_VERSION(10, 0, 0): 2887 case IP_VERSION(10, 0, 1): 2888 case IP_VERSION(11, 0, 2): 2889 if (adev->asic_type == CHIP_ARCTURUS) 2890 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2891 else 2892 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block); 2893 break; 2894 case IP_VERSION(11, 0, 0): 2895 case IP_VERSION(11, 0, 5): 2896 case IP_VERSION(11, 0, 9): 2897 case IP_VERSION(11, 0, 7): 2898 case IP_VERSION(11, 0, 11): 2899 case IP_VERSION(11, 0, 12): 2900 case IP_VERSION(11, 0, 13): 2901 case IP_VERSION(11, 5, 0): 2902 case IP_VERSION(11, 5, 2): 2903 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2904 break; 2905 case IP_VERSION(11, 0, 8): 2906 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) 2907 amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); 2908 break; 2909 case IP_VERSION(12, 0, 0): 2910 case IP_VERSION(12, 0, 1): 2911 amdgpu_device_ip_block_add(adev, &smu_v12_0_ip_block); 2912 break; 2913 case IP_VERSION(13, 0, 0): 2914 case IP_VERSION(13, 0, 1): 2915 case IP_VERSION(13, 0, 2): 2916 case IP_VERSION(13, 0, 3): 2917 case IP_VERSION(13, 0, 4): 2918 case IP_VERSION(13, 0, 5): 2919 case IP_VERSION(13, 0, 6): 2920 case IP_VERSION(13, 0, 7): 2921 case IP_VERSION(13, 0, 8): 2922 case IP_VERSION(13, 0, 10): 2923 case IP_VERSION(13, 0, 11): 2924 case IP_VERSION(13, 0, 14): 2925 case IP_VERSION(13, 0, 12): 2926 amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block); 2927 break; 2928 case IP_VERSION(14, 0, 0): 2929 case IP_VERSION(14, 0, 1): 2930 case IP_VERSION(14, 0, 2): 2931 case IP_VERSION(14, 0, 3): 2932 case IP_VERSION(14, 0, 4): 2933 case IP_VERSION(14, 0, 5): 2934 amdgpu_device_ip_block_add(adev, &smu_v14_0_ip_block); 2935 break; 2936 case IP_VERSION(15, 0, 0): 2937 case IP_VERSION(15, 0, 5): 2938 case IP_VERSION(15, 0, 8): 2939 case IP_VERSION(15, 0, 9): 2940 amdgpu_device_ip_block_add(adev, &smu_v15_0_ip_block); 2941 break; 2942 default: 2943 dev_err(adev->dev, 2944 "Failed to add smu ip block(MP1_HWIP:0x%x)\n", 2945 amdgpu_ip_version(adev, MP1_HWIP, 0)); 2946 return -EINVAL; 2947 } 2948 return 0; 2949 } 2950 2951 #if defined(CONFIG_DRM_AMD_DC) 2952 static void amdgpu_discovery_set_sriov_display(struct amdgpu_device *adev) 2953 { 2954 amdgpu_device_set_sriov_virtual_display(adev); 2955 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2956 } 2957 #endif 2958 2959 static int amdgpu_discovery_set_display_ip_blocks(struct amdgpu_device *adev) 2960 { 2961 if (adev->enable_virtual_display) { 2962 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block); 2963 return 0; 2964 } 2965 2966 if (!amdgpu_device_has_dc_support(adev)) 2967 return 0; 2968 2969 #if defined(CONFIG_DRM_AMD_DC) 2970 if (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2971 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { 2972 case IP_VERSION(1, 0, 0): 2973 case IP_VERSION(1, 0, 1): 2974 case IP_VERSION(2, 0, 2): 2975 case IP_VERSION(2, 0, 0): 2976 case IP_VERSION(2, 0, 3): 2977 case IP_VERSION(2, 1, 0): 2978 case IP_VERSION(3, 0, 0): 2979 case IP_VERSION(3, 0, 2): 2980 case IP_VERSION(3, 0, 3): 2981 case IP_VERSION(3, 0, 1): 2982 case IP_VERSION(3, 1, 2): 2983 case IP_VERSION(3, 1, 3): 2984 case IP_VERSION(3, 1, 4): 2985 case IP_VERSION(3, 1, 5): 2986 case IP_VERSION(3, 1, 6): 2987 case IP_VERSION(3, 2, 0): 2988 case IP_VERSION(3, 2, 1): 2989 case IP_VERSION(3, 5, 0): 2990 case IP_VERSION(3, 5, 1): 2991 case IP_VERSION(3, 6, 0): 2992 case IP_VERSION(4, 1, 0): 2993 case IP_VERSION(4, 2, 0): 2994 case IP_VERSION(4, 2, 1): 2995 case IP_VERSION(6, 0, 0): 2996 /* TODO: Fix IP version. DC code expects version 4.0.1 */ 2997 if (adev->ip_versions[DCE_HWIP][0] == IP_VERSION(4, 1, 0)) 2998 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(4, 0, 1); 2999 3000 if (amdgpu_sriov_vf(adev)) 3001 amdgpu_discovery_set_sriov_display(adev); 3002 else 3003 amdgpu_device_ip_block_add(adev, &dm_ip_block); 3004 break; 3005 default: 3006 dev_err(adev->dev, 3007 "Failed to add dm ip block(DCE_HWIP:0x%x)\n", 3008 amdgpu_ip_version(adev, DCE_HWIP, 0)); 3009 return -EINVAL; 3010 } 3011 } else if (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 3012 switch (amdgpu_ip_version(adev, DCI_HWIP, 0)) { 3013 case IP_VERSION(12, 0, 0): 3014 case IP_VERSION(12, 0, 1): 3015 case IP_VERSION(12, 1, 0): 3016 if (amdgpu_sriov_vf(adev)) 3017 amdgpu_discovery_set_sriov_display(adev); 3018 else 3019 amdgpu_device_ip_block_add(adev, &dm_ip_block); 3020 break; 3021 default: 3022 dev_err(adev->dev, 3023 "Failed to add dm ip block(DCI_HWIP:0x%x)\n", 3024 amdgpu_ip_version(adev, DCI_HWIP, 0)); 3025 return -EINVAL; 3026 } 3027 } 3028 #endif 3029 return 0; 3030 } 3031 3032 static int amdgpu_discovery_set_gc_ip_blocks(struct amdgpu_device *adev) 3033 { 3034 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3035 case IP_VERSION(9, 0, 1): 3036 case IP_VERSION(9, 1, 0): 3037 case IP_VERSION(9, 2, 1): 3038 case IP_VERSION(9, 2, 2): 3039 case IP_VERSION(9, 3, 0): 3040 case IP_VERSION(9, 4, 0): 3041 case IP_VERSION(9, 4, 1): 3042 case IP_VERSION(9, 4, 2): 3043 amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); 3044 break; 3045 case IP_VERSION(9, 4, 3): 3046 case IP_VERSION(9, 4, 4): 3047 case IP_VERSION(9, 5, 0): 3048 amdgpu_device_ip_block_add(adev, &gfx_v9_4_3_ip_block); 3049 break; 3050 case IP_VERSION(10, 1, 10): 3051 case IP_VERSION(10, 1, 2): 3052 case IP_VERSION(10, 1, 1): 3053 case IP_VERSION(10, 1, 3): 3054 case IP_VERSION(10, 1, 4): 3055 case IP_VERSION(10, 3, 0): 3056 case IP_VERSION(10, 3, 2): 3057 case IP_VERSION(10, 3, 1): 3058 case IP_VERSION(10, 3, 4): 3059 case IP_VERSION(10, 3, 5): 3060 case IP_VERSION(10, 3, 6): 3061 case IP_VERSION(10, 3, 3): 3062 case IP_VERSION(10, 3, 7): 3063 amdgpu_device_ip_block_add(adev, &gfx_v10_0_ip_block); 3064 break; 3065 case IP_VERSION(11, 0, 0): 3066 case IP_VERSION(11, 0, 1): 3067 case IP_VERSION(11, 0, 2): 3068 case IP_VERSION(11, 0, 3): 3069 case IP_VERSION(11, 0, 4): 3070 case IP_VERSION(11, 5, 0): 3071 case IP_VERSION(11, 5, 1): 3072 case IP_VERSION(11, 5, 2): 3073 case IP_VERSION(11, 5, 3): 3074 case IP_VERSION(11, 5, 4): 3075 case IP_VERSION(11, 5, 6): 3076 case IP_VERSION(11, 7, 0): 3077 case IP_VERSION(11, 7, 1): 3078 amdgpu_device_ip_block_add(adev, &gfx_v11_0_ip_block); 3079 break; 3080 case IP_VERSION(12, 0, 0): 3081 case IP_VERSION(12, 0, 1): 3082 amdgpu_device_ip_block_add(adev, &gfx_v12_0_ip_block); 3083 break; 3084 case IP_VERSION(12, 1, 0): 3085 amdgpu_device_ip_block_add(adev, &gfx_v12_1_ip_block); 3086 break; 3087 default: 3088 dev_err(adev->dev, "Failed to add gfx ip block(GC_HWIP:0x%x)\n", 3089 amdgpu_ip_version(adev, GC_HWIP, 0)); 3090 return -EINVAL; 3091 } 3092 return 0; 3093 } 3094 3095 static int amdgpu_discovery_set_sdma_ip_blocks(struct amdgpu_device *adev) 3096 { 3097 switch (amdgpu_ip_version(adev, SDMA0_HWIP, 0)) { 3098 case IP_VERSION(4, 0, 0): 3099 case IP_VERSION(4, 0, 1): 3100 case IP_VERSION(4, 1, 0): 3101 case IP_VERSION(4, 1, 1): 3102 case IP_VERSION(4, 1, 2): 3103 case IP_VERSION(4, 2, 0): 3104 case IP_VERSION(4, 2, 2): 3105 case IP_VERSION(4, 4, 0): 3106 amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); 3107 break; 3108 case IP_VERSION(4, 4, 2): 3109 case IP_VERSION(4, 4, 5): 3110 case IP_VERSION(4, 4, 4): 3111 amdgpu_device_ip_block_add(adev, &sdma_v4_4_2_ip_block); 3112 break; 3113 case IP_VERSION(5, 0, 0): 3114 case IP_VERSION(5, 0, 1): 3115 case IP_VERSION(5, 0, 2): 3116 case IP_VERSION(5, 0, 5): 3117 amdgpu_device_ip_block_add(adev, &sdma_v5_0_ip_block); 3118 break; 3119 case IP_VERSION(5, 2, 0): 3120 case IP_VERSION(5, 2, 2): 3121 case IP_VERSION(5, 2, 4): 3122 case IP_VERSION(5, 2, 5): 3123 case IP_VERSION(5, 2, 6): 3124 case IP_VERSION(5, 2, 3): 3125 case IP_VERSION(5, 2, 1): 3126 case IP_VERSION(5, 2, 7): 3127 amdgpu_device_ip_block_add(adev, &sdma_v5_2_ip_block); 3128 break; 3129 case IP_VERSION(6, 0, 0): 3130 case IP_VERSION(6, 0, 1): 3131 case IP_VERSION(6, 0, 2): 3132 case IP_VERSION(6, 0, 3): 3133 case IP_VERSION(6, 1, 0): 3134 case IP_VERSION(6, 1, 1): 3135 case IP_VERSION(6, 1, 2): 3136 case IP_VERSION(6, 1, 3): 3137 case IP_VERSION(6, 1, 4): 3138 case IP_VERSION(6, 4, 0): 3139 amdgpu_device_ip_block_add(adev, &sdma_v6_0_ip_block); 3140 break; 3141 case IP_VERSION(7, 0, 0): 3142 case IP_VERSION(7, 0, 1): 3143 amdgpu_device_ip_block_add(adev, &sdma_v7_0_ip_block); 3144 break; 3145 case IP_VERSION(7, 1, 0): 3146 amdgpu_device_ip_block_add(adev, &sdma_v7_1_ip_block); 3147 break; 3148 default: 3149 dev_err(adev->dev, 3150 "Failed to add sdma ip block(SDMA0_HWIP:0x%x)\n", 3151 amdgpu_ip_version(adev, SDMA0_HWIP, 0)); 3152 return -EINVAL; 3153 } 3154 3155 return 0; 3156 } 3157 3158 static int amdgpu_discovery_set_ras_ip_blocks(struct amdgpu_device *adev) 3159 { 3160 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) { 3161 case IP_VERSION(13, 0, 6): 3162 case IP_VERSION(13, 0, 12): 3163 case IP_VERSION(13, 0, 14): 3164 case IP_VERSION(13, 0, 15): 3165 case IP_VERSION(15, 0, 8): 3166 case IP_VERSION(15, 0, 3): 3167 amdgpu_device_ip_block_add(adev, &ras_v1_0_ip_block); 3168 break; 3169 default: 3170 break; 3171 } 3172 return 0; 3173 } 3174 3175 static int amdgpu_discovery_set_mm_ip_blocks(struct amdgpu_device *adev) 3176 { 3177 if (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 3178 switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { 3179 case IP_VERSION(7, 0, 0): 3180 case IP_VERSION(7, 2, 0): 3181 /* UVD is not supported on vega20 SR-IOV */ 3182 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 3183 amdgpu_device_ip_block_add(adev, &uvd_v7_0_ip_block); 3184 break; 3185 default: 3186 dev_err(adev->dev, 3187 "Failed to add uvd v7 ip block(UVD_HWIP:0x%x)\n", 3188 amdgpu_ip_version(adev, UVD_HWIP, 0)); 3189 return -EINVAL; 3190 } 3191 switch (amdgpu_ip_version(adev, VCE_HWIP, 0)) { 3192 case IP_VERSION(4, 0, 0): 3193 case IP_VERSION(4, 1, 0): 3194 /* VCE is not supported on vega20 SR-IOV */ 3195 if (!(adev->asic_type == CHIP_VEGA20 && amdgpu_sriov_vf(adev))) 3196 amdgpu_device_ip_block_add(adev, &vce_v4_0_ip_block); 3197 break; 3198 default: 3199 dev_err(adev->dev, 3200 "Failed to add VCE v4 ip block(VCE_HWIP:0x%x)\n", 3201 amdgpu_ip_version(adev, VCE_HWIP, 0)); 3202 return -EINVAL; 3203 } 3204 } else { 3205 uint32_t vcn_version = amdgpu_ip_version(adev, UVD_HWIP, 0); 3206 3207 /* no VCN discovered; nothing to add */ 3208 if (!vcn_version) 3209 return 0; 3210 switch (vcn_version) { 3211 case IP_VERSION(1, 0, 0): 3212 case IP_VERSION(1, 0, 1): 3213 amdgpu_device_ip_block_add(adev, &vcn_v1_0_ip_block); 3214 break; 3215 case IP_VERSION(2, 0, 0): 3216 case IP_VERSION(2, 0, 2): 3217 case IP_VERSION(2, 2, 0): 3218 amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block); 3219 if (!amdgpu_sriov_vf(adev)) 3220 amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block); 3221 break; 3222 case IP_VERSION(2, 0, 3): 3223 break; 3224 case IP_VERSION(2, 5, 0): 3225 amdgpu_device_ip_block_add(adev, &vcn_v2_5_ip_block); 3226 amdgpu_device_ip_block_add(adev, &jpeg_v2_5_ip_block); 3227 break; 3228 case IP_VERSION(2, 6, 0): 3229 amdgpu_device_ip_block_add(adev, &vcn_v2_6_ip_block); 3230 amdgpu_device_ip_block_add(adev, &jpeg_v2_6_ip_block); 3231 break; 3232 case IP_VERSION(3, 0, 0): 3233 case IP_VERSION(3, 0, 16): 3234 case IP_VERSION(3, 1, 1): 3235 case IP_VERSION(3, 1, 2): 3236 case IP_VERSION(3, 0, 2): 3237 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 3238 if (!amdgpu_sriov_vf(adev)) 3239 amdgpu_device_ip_block_add(adev, &jpeg_v3_0_ip_block); 3240 break; 3241 case IP_VERSION(3, 0, 33): 3242 amdgpu_device_ip_block_add(adev, &vcn_v3_0_ip_block); 3243 break; 3244 case IP_VERSION(4, 0, 0): 3245 case IP_VERSION(4, 0, 2): 3246 case IP_VERSION(4, 0, 4): 3247 amdgpu_device_ip_block_add(adev, &vcn_v4_0_ip_block); 3248 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_ip_block); 3249 break; 3250 case IP_VERSION(4, 0, 3): 3251 amdgpu_device_ip_block_add(adev, &vcn_v4_0_3_ip_block); 3252 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_3_ip_block); 3253 break; 3254 case IP_VERSION(4, 0, 5): 3255 case IP_VERSION(4, 0, 6): 3256 amdgpu_device_ip_block_add(adev, &vcn_v4_0_5_ip_block); 3257 amdgpu_device_ip_block_add(adev, &jpeg_v4_0_5_ip_block); 3258 break; 3259 case IP_VERSION(5, 0, 0): 3260 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 3261 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_0_ip_block); 3262 break; 3263 case IP_VERSION(5, 3, 0): 3264 amdgpu_device_ip_block_add(adev, &vcn_v5_0_0_ip_block); 3265 amdgpu_device_ip_block_add(adev, &jpeg_v5_3_0_ip_block); 3266 break; 3267 case IP_VERSION(5, 0, 1): 3268 amdgpu_device_ip_block_add(adev, &vcn_v5_0_1_ip_block); 3269 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_1_ip_block); 3270 break; 3271 case IP_VERSION(5, 0, 2): 3272 amdgpu_device_ip_block_add(adev, &vcn_v5_0_2_ip_block); 3273 amdgpu_device_ip_block_add(adev, &jpeg_v5_0_2_ip_block); 3274 break; 3275 default: 3276 dev_err(adev->dev, 3277 "Failed to add vcn/jpeg ip block(UVD_HWIP:0x%x)\n", 3278 vcn_version); 3279 return -EINVAL; 3280 } 3281 } 3282 return 0; 3283 } 3284 3285 static int amdgpu_discovery_set_mes_ip_blocks(struct amdgpu_device *adev) 3286 { 3287 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3288 case IP_VERSION(11, 0, 0): 3289 case IP_VERSION(11, 0, 1): 3290 case IP_VERSION(11, 0, 2): 3291 case IP_VERSION(11, 0, 3): 3292 case IP_VERSION(11, 0, 4): 3293 case IP_VERSION(11, 5, 0): 3294 case IP_VERSION(11, 5, 1): 3295 case IP_VERSION(11, 5, 2): 3296 case IP_VERSION(11, 5, 3): 3297 case IP_VERSION(11, 5, 4): 3298 case IP_VERSION(11, 5, 6): 3299 case IP_VERSION(11, 7, 0): 3300 case IP_VERSION(11, 7, 1): 3301 amdgpu_device_ip_block_add(adev, &mes_v11_0_ip_block); 3302 adev->enable_mes = true; 3303 adev->enable_mes_kiq = true; 3304 break; 3305 case IP_VERSION(12, 0, 0): 3306 case IP_VERSION(12, 0, 1): 3307 amdgpu_device_ip_block_add(adev, &mes_v12_0_ip_block); 3308 adev->enable_mes = true; 3309 adev->enable_mes_kiq = true; 3310 if (amdgpu_uni_mes) 3311 adev->enable_uni_mes = true; 3312 break; 3313 case IP_VERSION(12, 1, 0): 3314 amdgpu_device_ip_block_add(adev, &mes_v12_1_ip_block); 3315 adev->enable_mes = true; 3316 adev->enable_mes_kiq = true; 3317 adev->enable_uni_mes = true; 3318 break; 3319 default: 3320 break; 3321 } 3322 return 0; 3323 } 3324 3325 static void amdgpu_discovery_init_soc_config(struct amdgpu_device *adev) 3326 { 3327 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3328 case IP_VERSION(9, 4, 3): 3329 case IP_VERSION(9, 4, 4): 3330 case IP_VERSION(9, 5, 0): 3331 aqua_vanjaram_init_soc_config(adev); 3332 break; 3333 case IP_VERSION(12, 1, 0): 3334 soc_v1_0_init_soc_config(adev); 3335 break; 3336 default: 3337 break; 3338 } 3339 } 3340 3341 static int amdgpu_discovery_set_vpe_ip_blocks(struct amdgpu_device *adev) 3342 { 3343 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { 3344 case IP_VERSION(6, 1, 0): 3345 case IP_VERSION(6, 1, 1): 3346 case IP_VERSION(6, 1, 3): 3347 amdgpu_device_ip_block_add(adev, &vpe_v6_1_ip_block); 3348 break; 3349 case IP_VERSION(2, 0, 0): 3350 case IP_VERSION(2, 2, 0): 3351 amdgpu_device_ip_block_add(adev, &vpe_v2_0_ip_block); 3352 break; 3353 case IP_VERSION(3, 0, 0): 3354 case IP_VERSION(3, 0, 1): 3355 amdgpu_device_ip_block_add(adev, &vpe_v3_0_ip_block); 3356 break; 3357 default: 3358 break; 3359 } 3360 3361 return 0; 3362 } 3363 3364 static int amdgpu_discovery_set_umsch_mm_ip_blocks(struct amdgpu_device *adev) 3365 { 3366 switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { 3367 case IP_VERSION(4, 0, 5): 3368 case IP_VERSION(4, 0, 6): 3369 if (amdgpu_umsch_mm & 0x1) { 3370 amdgpu_device_ip_block_add(adev, &umsch_mm_v4_0_ip_block); 3371 adev->enable_umsch_mm = true; 3372 } 3373 break; 3374 default: 3375 break; 3376 } 3377 3378 return 0; 3379 } 3380 3381 static int amdgpu_discovery_set_isp_ip_blocks(struct amdgpu_device *adev) 3382 { 3383 #if defined(CONFIG_DRM_AMD_ISP) 3384 switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { 3385 case IP_VERSION(4, 1, 0): 3386 amdgpu_device_ip_block_add(adev, &isp_v4_1_0_ip_block); 3387 break; 3388 case IP_VERSION(4, 1, 1): 3389 amdgpu_device_ip_block_add(adev, &isp_v4_1_1_ip_block); 3390 break; 3391 default: 3392 break; 3393 } 3394 #endif 3395 3396 return 0; 3397 } 3398 3399 static int amdgpu_discovery_set_ualink_ip_blocks(struct amdgpu_device *adev) 3400 { 3401 /* TODO: no dedicated IP discovery version for UALink yet; key off the 3402 * GC IP version for now. 3403 */ 3404 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3405 case IP_VERSION(12, 1, 0): 3406 amdgpu_device_ip_block_add(adev, &ualink_v1_0_ip_block); 3407 break; 3408 default: 3409 break; 3410 } 3411 3412 return 0; 3413 } 3414 3415 int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev) 3416 { 3417 int r; 3418 3419 switch (adev->asic_type) { 3420 case CHIP_VEGA10: 3421 /* This is not fatal. We only need the discovery 3422 * binary for sysfs. We don't need it for a 3423 * functional system. 3424 */ 3425 amdgpu_discovery_init(adev); 3426 vega10_reg_base_init(adev); 3427 adev->sdma.num_instances = 2; 3428 adev->sdma.sdma_mask = 3; 3429 adev->gmc.num_umc = 4; 3430 adev->gfx.xcc_mask = 1; 3431 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); 3432 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0); 3433 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0); 3434 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 0); 3435 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 0); 3436 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 0); 3437 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 3438 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); 3439 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 0, 0); 3440 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 3441 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 3442 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 3443 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 0); 3444 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 0, 1); 3445 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 3446 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 3447 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 0); 3448 break; 3449 case CHIP_VEGA12: 3450 /* This is not fatal. We only need the discovery 3451 * binary for sysfs. We don't need it for a 3452 * functional system. 3453 */ 3454 amdgpu_discovery_init(adev); 3455 vega10_reg_base_init(adev); 3456 adev->sdma.num_instances = 2; 3457 adev->sdma.sdma_mask = 3; 3458 adev->gmc.num_umc = 4; 3459 adev->gfx.xcc_mask = 1; 3460 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); 3461 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0); 3462 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1); 3463 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 0, 1); 3464 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 0, 1); 3465 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 0, 1); 3466 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 5, 0); 3467 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); 3468 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 0); 3469 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(9, 0, 0); 3470 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(9, 0, 0); 3471 adev->ip_versions[THM_HWIP][0] = IP_VERSION(9, 0, 0); 3472 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(9, 0, 1); 3473 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 1); 3474 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 0, 0); 3475 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 0, 0); 3476 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 0, 1); 3477 break; 3478 case CHIP_RAVEN: 3479 /* This is not fatal. We only need the discovery 3480 * binary for sysfs. We don't need it for a 3481 * functional system. 3482 */ 3483 amdgpu_discovery_init(adev); 3484 vega10_reg_base_init(adev); 3485 adev->sdma.num_instances = 1; 3486 adev->sdma.sdma_mask = 1; 3487 adev->vcn.num_vcn_inst = 1; 3488 adev->gmc.num_umc = 2; 3489 adev->gfx.xcc_mask = 1; 3490 if (adev->apu_flags & AMD_APU_IS_RAVEN2) { 3491 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); 3492 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0); 3493 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 1); 3494 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 1); 3495 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 1); 3496 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 1); 3497 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); 3498 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 5, 0); 3499 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 1); 3500 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 1); 3501 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 1, 0); 3502 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 1); 3503 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 2, 2); 3504 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 1); 3505 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 1); 3506 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 3507 } else { 3508 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); 3509 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 1, 0); 3510 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 1, 0); 3511 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 1, 0); 3512 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 1, 0); 3513 adev->ip_versions[DF_HWIP][0] = IP_VERSION(2, 1, 0); 3514 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); 3515 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(7, 0, 0); 3516 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(10, 0, 0); 3517 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(10, 0, 0); 3518 adev->ip_versions[THM_HWIP][0] = IP_VERSION(10, 0, 0); 3519 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(10, 0, 0); 3520 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 1, 0); 3521 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(1, 0, 0); 3522 adev->ip_versions[DCE_HWIP][0] = IP_VERSION(1, 0, 0); 3523 adev->ip_versions[ISP_HWIP][0] = IP_VERSION(2, 0, 0); 3524 } 3525 break; 3526 case CHIP_VEGA20: 3527 /* This is not fatal. We only need the discovery 3528 * binary for sysfs. We don't need it for a 3529 * functional system. 3530 */ 3531 amdgpu_discovery_init(adev); 3532 vega20_reg_base_init(adev); 3533 adev->sdma.num_instances = 2; 3534 adev->sdma.sdma_mask = 3; 3535 adev->gmc.num_umc = 8; 3536 adev->gfx.xcc_mask = 1; 3537 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); 3538 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0); 3539 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0); 3540 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 0); 3541 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 0); 3542 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 0); 3543 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 0); 3544 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); 3545 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 1); 3546 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 2); 3547 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 3548 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 2); 3549 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 2); 3550 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 0); 3551 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(7, 2, 0); 3552 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(7, 2, 0); 3553 adev->ip_versions[VCE_HWIP][0] = IP_VERSION(4, 1, 0); 3554 adev->ip_versions[DCI_HWIP][0] = IP_VERSION(12, 1, 0); 3555 break; 3556 case CHIP_ARCTURUS: 3557 /* This is not fatal. We only need the discovery 3558 * binary for sysfs. We don't need it for a 3559 * functional system. 3560 */ 3561 amdgpu_discovery_init(adev); 3562 arct_reg_base_init(adev); 3563 adev->sdma.num_instances = 8; 3564 adev->sdma.sdma_mask = 0xff; 3565 adev->vcn.num_vcn_inst = 2; 3566 adev->gmc.num_umc = 8; 3567 adev->gfx.xcc_mask = 1; 3568 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); 3569 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1); 3570 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1); 3571 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 2, 1); 3572 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 2, 2); 3573 adev->ip_versions[SDMA1_HWIP][0] = IP_VERSION(4, 2, 2); 3574 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(4, 2, 2); 3575 adev->ip_versions[SDMA1_HWIP][2] = IP_VERSION(4, 2, 2); 3576 adev->ip_versions[SDMA1_HWIP][3] = IP_VERSION(4, 2, 2); 3577 adev->ip_versions[SDMA1_HWIP][4] = IP_VERSION(4, 2, 2); 3578 adev->ip_versions[SDMA1_HWIP][5] = IP_VERSION(4, 2, 2); 3579 adev->ip_versions[SDMA1_HWIP][6] = IP_VERSION(4, 2, 2); 3580 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 1); 3581 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); 3582 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 1, 2); 3583 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 4); 3584 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 2); 3585 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 3); 3586 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 3); 3587 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 1); 3588 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 5, 0); 3589 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 5, 0); 3590 break; 3591 case CHIP_ALDEBARAN: 3592 /* This is not fatal. We only need the discovery 3593 * binary for sysfs. We don't need it for a 3594 * functional system. 3595 */ 3596 amdgpu_discovery_init(adev); 3597 aldebaran_reg_base_init(adev); 3598 adev->sdma.num_instances = 5; 3599 adev->sdma.sdma_mask = 0x1f; 3600 adev->vcn.num_vcn_inst = 2; 3601 adev->gmc.num_umc = 4; 3602 adev->gfx.xcc_mask = 1; 3603 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); 3604 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2); 3605 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0); 3606 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(4, 4, 0); 3607 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(4, 4, 0); 3608 adev->ip_versions[SDMA0_HWIP][1] = IP_VERSION(4, 4, 0); 3609 adev->ip_versions[SDMA0_HWIP][2] = IP_VERSION(4, 4, 0); 3610 adev->ip_versions[SDMA0_HWIP][3] = IP_VERSION(4, 4, 0); 3611 adev->ip_versions[SDMA0_HWIP][4] = IP_VERSION(4, 4, 0); 3612 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 6, 2); 3613 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); 3614 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(6, 7, 0); 3615 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(13, 0, 2); 3616 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(13, 0, 2); 3617 adev->ip_versions[THM_HWIP][0] = IP_VERSION(13, 0, 2); 3618 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(13, 0, 2); 3619 adev->ip_versions[GC_HWIP][0] = IP_VERSION(9, 4, 2); 3620 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 6, 0); 3621 adev->ip_versions[UVD_HWIP][1] = IP_VERSION(2, 6, 0); 3622 adev->ip_versions[XGMI_HWIP][0] = IP_VERSION(6, 1, 0); 3623 break; 3624 case CHIP_CYAN_SKILLFISH: 3625 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) { 3626 r = amdgpu_discovery_reg_base_init(adev); 3627 if (r) 3628 return -EINVAL; 3629 3630 amdgpu_discovery_harvest_ip(adev); 3631 amdgpu_discovery_get_gfx_info(adev); 3632 amdgpu_discovery_get_mall_info(adev); 3633 amdgpu_discovery_get_vcn_info(adev); 3634 } else { 3635 cyan_skillfish_reg_base_init(adev); 3636 adev->sdma.num_instances = 2; 3637 adev->sdma.sdma_mask = 3; 3638 adev->gfx.xcc_mask = 1; 3639 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); 3640 adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(2, 0, 3); 3641 adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(5, 0, 1); 3642 adev->ip_versions[HDP_HWIP][0] = IP_VERSION(5, 0, 1); 3643 adev->ip_versions[SDMA0_HWIP][0] = IP_VERSION(5, 0, 1); 3644 adev->ip_versions[SDMA1_HWIP][1] = IP_VERSION(5, 0, 1); 3645 adev->ip_versions[DF_HWIP][0] = IP_VERSION(3, 5, 0); 3646 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); 3647 adev->ip_versions[UMC_HWIP][0] = IP_VERSION(8, 1, 1); 3648 adev->ip_versions[MP0_HWIP][0] = IP_VERSION(11, 0, 8); 3649 adev->ip_versions[MP1_HWIP][0] = IP_VERSION(11, 0, 8); 3650 adev->ip_versions[THM_HWIP][0] = IP_VERSION(11, 0, 1); 3651 adev->ip_versions[SMUIO_HWIP][0] = IP_VERSION(11, 0, 8); 3652 adev->ip_versions[GC_HWIP][0] = IP_VERSION(10, 1, 3); 3653 adev->ip_versions[UVD_HWIP][0] = IP_VERSION(2, 0, 3); 3654 } 3655 break; 3656 default: 3657 r = amdgpu_discovery_reg_base_init(adev); 3658 if (r) { 3659 drm_err(&adev->ddev, "discovery failed: %d\n", r); 3660 return r; 3661 } 3662 3663 amdgpu_discovery_harvest_ip(adev); 3664 amdgpu_discovery_get_gfx_info(adev); 3665 amdgpu_discovery_get_mall_info(adev); 3666 amdgpu_discovery_get_vcn_info(adev); 3667 break; 3668 } 3669 3670 amdgpu_discovery_init_soc_config(adev); 3671 amdgpu_discovery_sysfs_init(adev); 3672 3673 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3674 case IP_VERSION(9, 0, 1): 3675 case IP_VERSION(9, 2, 1): 3676 case IP_VERSION(9, 4, 0): 3677 case IP_VERSION(9, 4, 1): 3678 case IP_VERSION(9, 4, 2): 3679 case IP_VERSION(9, 4, 3): 3680 case IP_VERSION(9, 4, 4): 3681 case IP_VERSION(9, 5, 0): 3682 adev->family = AMDGPU_FAMILY_AI; 3683 break; 3684 case IP_VERSION(9, 1, 0): 3685 case IP_VERSION(9, 2, 2): 3686 case IP_VERSION(9, 3, 0): 3687 adev->family = AMDGPU_FAMILY_RV; 3688 break; 3689 case IP_VERSION(10, 1, 10): 3690 case IP_VERSION(10, 1, 1): 3691 case IP_VERSION(10, 1, 2): 3692 case IP_VERSION(10, 1, 3): 3693 case IP_VERSION(10, 1, 4): 3694 case IP_VERSION(10, 3, 0): 3695 case IP_VERSION(10, 3, 2): 3696 case IP_VERSION(10, 3, 4): 3697 case IP_VERSION(10, 3, 5): 3698 adev->family = AMDGPU_FAMILY_NV; 3699 break; 3700 case IP_VERSION(10, 3, 1): 3701 adev->family = AMDGPU_FAMILY_VGH; 3702 adev->apu_flags |= AMD_APU_IS_VANGOGH; 3703 break; 3704 case IP_VERSION(10, 3, 3): 3705 adev->family = AMDGPU_FAMILY_YC; 3706 break; 3707 case IP_VERSION(10, 3, 6): 3708 adev->family = AMDGPU_FAMILY_GC_10_3_6; 3709 break; 3710 case IP_VERSION(10, 3, 7): 3711 adev->family = AMDGPU_FAMILY_GC_10_3_7; 3712 break; 3713 case IP_VERSION(11, 0, 0): 3714 case IP_VERSION(11, 0, 2): 3715 case IP_VERSION(11, 0, 3): 3716 adev->family = AMDGPU_FAMILY_GC_11_0_0; 3717 break; 3718 case IP_VERSION(11, 0, 1): 3719 case IP_VERSION(11, 0, 4): 3720 adev->family = AMDGPU_FAMILY_GC_11_0_1; 3721 break; 3722 case IP_VERSION(11, 5, 0): 3723 case IP_VERSION(11, 5, 1): 3724 case IP_VERSION(11, 5, 2): 3725 case IP_VERSION(11, 5, 3): 3726 case IP_VERSION(11, 5, 4): 3727 case IP_VERSION(11, 5, 6): 3728 adev->family = AMDGPU_FAMILY_GC_11_5_0; 3729 break; 3730 case IP_VERSION(11, 7, 0): 3731 case IP_VERSION(11, 7, 1): 3732 adev->family = AMDGPU_FAMILY_GC_11_5_4; 3733 break; 3734 case IP_VERSION(12, 0, 0): 3735 case IP_VERSION(12, 0, 1): 3736 case IP_VERSION(12, 1, 0): 3737 adev->family = AMDGPU_FAMILY_GC_12_0_0; 3738 break; 3739 default: 3740 return -EINVAL; 3741 } 3742 3743 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 3744 case IP_VERSION(9, 1, 0): 3745 case IP_VERSION(9, 2, 2): 3746 case IP_VERSION(9, 3, 0): 3747 case IP_VERSION(10, 1, 3): 3748 case IP_VERSION(10, 1, 4): 3749 case IP_VERSION(10, 3, 1): 3750 case IP_VERSION(10, 3, 3): 3751 case IP_VERSION(10, 3, 6): 3752 case IP_VERSION(10, 3, 7): 3753 case IP_VERSION(11, 0, 1): 3754 case IP_VERSION(11, 0, 4): 3755 case IP_VERSION(11, 5, 0): 3756 case IP_VERSION(11, 5, 1): 3757 case IP_VERSION(11, 5, 2): 3758 case IP_VERSION(11, 5, 3): 3759 case IP_VERSION(11, 5, 4): 3760 case IP_VERSION(11, 5, 6): 3761 case IP_VERSION(11, 7, 0): 3762 case IP_VERSION(11, 7, 1): 3763 adev->flags |= AMD_IS_APU; 3764 break; 3765 default: 3766 break; 3767 } 3768 3769 /* set NBIO version */ 3770 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { 3771 case IP_VERSION(6, 1, 0): 3772 case IP_VERSION(6, 2, 0): 3773 adev->nbio.funcs = &nbio_v6_1_funcs; 3774 adev->nbio.hdp_flush_reg = &nbio_v6_1_hdp_flush_reg; 3775 break; 3776 case IP_VERSION(7, 0, 0): 3777 case IP_VERSION(7, 0, 1): 3778 case IP_VERSION(2, 5, 0): 3779 adev->nbio.funcs = &nbio_v7_0_funcs; 3780 adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg; 3781 break; 3782 case IP_VERSION(7, 4, 0): 3783 case IP_VERSION(7, 4, 1): 3784 case IP_VERSION(7, 4, 4): 3785 adev->nbio.funcs = &nbio_v7_4_funcs; 3786 adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg; 3787 break; 3788 case IP_VERSION(7, 9, 0): 3789 case IP_VERSION(7, 9, 1): 3790 adev->nbio.funcs = &nbio_v7_9_funcs; 3791 adev->nbio.hdp_flush_reg = &nbio_v7_9_hdp_flush_reg; 3792 break; 3793 case IP_VERSION(7, 11, 0): 3794 case IP_VERSION(7, 11, 1): 3795 case IP_VERSION(7, 11, 2): 3796 case IP_VERSION(7, 11, 3): 3797 adev->nbio.funcs = &nbio_v7_11_funcs; 3798 adev->nbio.hdp_flush_reg = &nbio_v7_11_hdp_flush_reg; 3799 break; 3800 case IP_VERSION(7, 2, 0): 3801 case IP_VERSION(7, 2, 1): 3802 case IP_VERSION(7, 3, 0): 3803 case IP_VERSION(7, 5, 0): 3804 case IP_VERSION(7, 5, 1): 3805 adev->nbio.funcs = &nbio_v7_2_funcs; 3806 adev->nbio.hdp_flush_reg = &nbio_v7_2_hdp_flush_reg; 3807 break; 3808 case IP_VERSION(2, 1, 1): 3809 case IP_VERSION(2, 3, 0): 3810 case IP_VERSION(2, 3, 1): 3811 case IP_VERSION(2, 3, 2): 3812 case IP_VERSION(3, 3, 0): 3813 case IP_VERSION(3, 3, 1): 3814 case IP_VERSION(3, 3, 2): 3815 case IP_VERSION(3, 3, 3): 3816 adev->nbio.funcs = &nbio_v2_3_funcs; 3817 adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg; 3818 break; 3819 case IP_VERSION(4, 3, 0): 3820 case IP_VERSION(4, 3, 1): 3821 if (amdgpu_sriov_vf(adev)) 3822 adev->nbio.funcs = &nbio_v4_3_sriov_funcs; 3823 else 3824 adev->nbio.funcs = &nbio_v4_3_funcs; 3825 adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg; 3826 break; 3827 case IP_VERSION(7, 7, 0): 3828 case IP_VERSION(7, 7, 1): 3829 adev->nbio.funcs = &nbio_v7_7_funcs; 3830 adev->nbio.hdp_flush_reg = &nbio_v7_7_hdp_flush_reg; 3831 break; 3832 case IP_VERSION(6, 3, 1): 3833 case IP_VERSION(7, 11, 4): 3834 adev->nbio.funcs = &nbif_v6_3_1_funcs; 3835 adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg; 3836 break; 3837 case IP_VERSION(7, 11, 5): 3838 adev->nbio.funcs = &nbio_v7_11_5_funcs; 3839 adev->nbio.hdp_flush_reg = &nbio_v7_11_5_hdp_flush_reg; 3840 break; 3841 case IP_VERSION(6, 3, 2): 3842 adev->nbio.funcs = &nbio_v6_3_2_funcs; 3843 break; 3844 case IP_VERSION(7, 10, 0): 3845 adev->nbio.funcs = &nbif_v7_10_funcs; 3846 adev->nbio.hdp_flush_reg = &nbif_v7_10_hdp_flush_reg; 3847 break; 3848 default: 3849 break; 3850 } 3851 3852 switch (amdgpu_ip_version(adev, HDP_HWIP, 0)) { 3853 case IP_VERSION(4, 0, 0): 3854 case IP_VERSION(4, 0, 1): 3855 case IP_VERSION(4, 1, 0): 3856 case IP_VERSION(4, 1, 1): 3857 case IP_VERSION(4, 1, 2): 3858 case IP_VERSION(4, 2, 0): 3859 case IP_VERSION(4, 2, 1): 3860 case IP_VERSION(4, 4, 0): 3861 case IP_VERSION(4, 4, 2): 3862 case IP_VERSION(4, 4, 5): 3863 adev->hdp.funcs = &hdp_v4_0_funcs; 3864 break; 3865 case IP_VERSION(5, 0, 0): 3866 case IP_VERSION(5, 0, 1): 3867 case IP_VERSION(5, 0, 2): 3868 case IP_VERSION(5, 0, 3): 3869 case IP_VERSION(5, 0, 4): 3870 case IP_VERSION(5, 2, 0): 3871 adev->hdp.funcs = &hdp_v5_0_funcs; 3872 break; 3873 case IP_VERSION(5, 2, 1): 3874 adev->hdp.funcs = &hdp_v5_2_funcs; 3875 break; 3876 case IP_VERSION(6, 0, 0): 3877 case IP_VERSION(6, 0, 1): 3878 case IP_VERSION(6, 1, 0): 3879 case IP_VERSION(6, 1, 1): 3880 case IP_VERSION(6, 4, 0): 3881 adev->hdp.funcs = &hdp_v6_0_funcs; 3882 break; 3883 case IP_VERSION(7, 0, 0): 3884 adev->hdp.funcs = &hdp_v7_0_funcs; 3885 break; 3886 case IP_VERSION(8, 0, 1): 3887 adev->hdp.funcs = &hdp_v8_0_funcs; 3888 break; 3889 default: 3890 break; 3891 } 3892 3893 switch (amdgpu_ip_version(adev, DF_HWIP, 0)) { 3894 case IP_VERSION(3, 6, 0): 3895 case IP_VERSION(3, 6, 1): 3896 case IP_VERSION(3, 6, 2): 3897 adev->df.funcs = &df_v3_6_funcs; 3898 break; 3899 case IP_VERSION(2, 1, 0): 3900 case IP_VERSION(2, 1, 1): 3901 case IP_VERSION(2, 5, 0): 3902 case IP_VERSION(3, 5, 1): 3903 case IP_VERSION(3, 5, 2): 3904 adev->df.funcs = &df_v1_7_funcs; 3905 break; 3906 case IP_VERSION(4, 3, 0): 3907 adev->df.funcs = &df_v4_3_funcs; 3908 break; 3909 case IP_VERSION(4, 6, 2): 3910 adev->df.funcs = &df_v4_6_2_funcs; 3911 break; 3912 case IP_VERSION(4, 15, 0): 3913 case IP_VERSION(4, 15, 1): 3914 case IP_VERSION(5, 0, 2): 3915 adev->df.funcs = &df_v4_15_funcs; 3916 break; 3917 default: 3918 break; 3919 } 3920 3921 switch (amdgpu_ip_version(adev, SMUIO_HWIP, 0)) { 3922 case IP_VERSION(9, 0, 0): 3923 case IP_VERSION(9, 0, 1): 3924 case IP_VERSION(10, 0, 0): 3925 case IP_VERSION(10, 0, 1): 3926 case IP_VERSION(10, 0, 2): 3927 adev->smuio.funcs = &smuio_v9_0_funcs; 3928 break; 3929 case IP_VERSION(11, 0, 0): 3930 case IP_VERSION(11, 0, 2): 3931 case IP_VERSION(11, 0, 3): 3932 case IP_VERSION(11, 0, 4): 3933 case IP_VERSION(11, 0, 7): 3934 case IP_VERSION(11, 0, 8): 3935 adev->smuio.funcs = &smuio_v11_0_funcs; 3936 break; 3937 case IP_VERSION(11, 0, 6): 3938 case IP_VERSION(11, 0, 10): 3939 case IP_VERSION(11, 0, 11): 3940 case IP_VERSION(11, 5, 0): 3941 case IP_VERSION(11, 5, 2): 3942 case IP_VERSION(13, 0, 1): 3943 case IP_VERSION(13, 0, 9): 3944 case IP_VERSION(13, 0, 10): 3945 adev->smuio.funcs = &smuio_v11_0_6_funcs; 3946 break; 3947 case IP_VERSION(13, 0, 2): 3948 adev->smuio.funcs = &smuio_v13_0_funcs; 3949 break; 3950 case IP_VERSION(13, 0, 3): 3951 case IP_VERSION(13, 0, 11): 3952 adev->smuio.funcs = &smuio_v13_0_3_funcs; 3953 if (adev->smuio.funcs->get_pkg_type(adev) == AMDGPU_PKG_TYPE_APU) { 3954 adev->flags |= AMD_IS_APU; 3955 } 3956 break; 3957 case IP_VERSION(13, 0, 6): 3958 case IP_VERSION(13, 0, 8): 3959 case IP_VERSION(14, 0, 0): 3960 case IP_VERSION(14, 0, 1): 3961 adev->smuio.funcs = &smuio_v13_0_6_funcs; 3962 break; 3963 case IP_VERSION(14, 0, 2): 3964 adev->smuio.funcs = &smuio_v14_0_2_funcs; 3965 break; 3966 case IP_VERSION(15, 0, 0): 3967 case IP_VERSION(15, 0, 5): 3968 adev->smuio.funcs = &smuio_v15_0_0_funcs; 3969 break; 3970 case IP_VERSION(15, 0, 3): 3971 adev->smuio.funcs = &smuio_v15_0_3_funcs; 3972 break; 3973 case IP_VERSION(15, 0, 8): 3974 adev->smuio.funcs = &smuio_v15_0_8_funcs; 3975 break; 3976 default: 3977 break; 3978 } 3979 3980 switch (amdgpu_ip_version(adev, LSDMA_HWIP, 0)) { 3981 case IP_VERSION(6, 0, 0): 3982 case IP_VERSION(6, 0, 1): 3983 case IP_VERSION(6, 0, 2): 3984 case IP_VERSION(6, 0, 3): 3985 adev->lsdma.funcs = &lsdma_v6_0_funcs; 3986 break; 3987 case IP_VERSION(7, 0, 0): 3988 case IP_VERSION(7, 0, 1): 3989 adev->lsdma.funcs = &lsdma_v7_0_funcs; 3990 break; 3991 case IP_VERSION(7, 1, 0): 3992 adev->lsdma.funcs = &lsdma_v7_1_funcs; 3993 break; 3994 case IP_VERSION(8, 0, 0): 3995 adev->lsdma.funcs = &lsdma_v8_0_funcs; 3996 break; 3997 default: 3998 break; 3999 } 4000 4001 r = amdgpu_discovery_set_common_ip_blocks(adev); 4002 if (r) 4003 return r; 4004 4005 r = amdgpu_discovery_set_gmc_ip_blocks(adev); 4006 if (r) 4007 return r; 4008 4009 /* For SR-IOV, PSP needs to be initialized before IH */ 4010 if (amdgpu_sriov_vf(adev)) { 4011 r = amdgpu_discovery_set_psp_ip_blocks(adev); 4012 if (r) 4013 return r; 4014 r = amdgpu_discovery_set_ih_ip_blocks(adev); 4015 if (r) 4016 return r; 4017 } else { 4018 r = amdgpu_discovery_set_ih_ip_blocks(adev); 4019 if (r) 4020 return r; 4021 4022 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4023 r = amdgpu_discovery_set_psp_ip_blocks(adev); 4024 if (r) 4025 return r; 4026 } 4027 } 4028 4029 if (likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 4030 r = amdgpu_discovery_set_smu_ip_blocks(adev); 4031 if (r) 4032 return r; 4033 } 4034 4035 r = amdgpu_discovery_set_display_ip_blocks(adev); 4036 if (r) 4037 return r; 4038 4039 r = amdgpu_discovery_set_gc_ip_blocks(adev); 4040 if (r) 4041 return r; 4042 4043 r = amdgpu_discovery_set_sdma_ip_blocks(adev); 4044 if (r) 4045 return r; 4046 4047 r = amdgpu_discovery_set_ras_ip_blocks(adev); 4048 if (r) 4049 return r; 4050 4051 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT && 4052 !amdgpu_sriov_vf(adev) && 4053 amdgpu_dpm == 1) || 4054 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && 4055 amdgpu_dpm == 1)) { 4056 r = amdgpu_discovery_set_smu_ip_blocks(adev); 4057 if (r) 4058 return r; 4059 } 4060 4061 r = amdgpu_discovery_set_mm_ip_blocks(adev); 4062 if (r) 4063 return r; 4064 4065 r = amdgpu_discovery_set_mes_ip_blocks(adev); 4066 if (r) 4067 return r; 4068 4069 r = amdgpu_discovery_set_vpe_ip_blocks(adev); 4070 if (r) 4071 return r; 4072 4073 r = amdgpu_discovery_set_umsch_mm_ip_blocks(adev); 4074 if (r) 4075 return r; 4076 4077 r = amdgpu_discovery_set_isp_ip_blocks(adev); 4078 if (r) 4079 return r; 4080 4081 r = amdgpu_discovery_set_ualink_ip_blocks(adev); 4082 if (r) 4083 return r; 4084 return 0; 4085 } 4086 4087 int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev, 4088 uint16_t *major, uint16_t *minor) 4089 { 4090 uint8_t *discovery_bin = adev->discovery.bin; 4091 struct table_info *info; 4092 union gc_info *gc_info; 4093 u16 offset; 4094 4095 if (!discovery_bin) 4096 return -EINVAL; 4097 if (amdgpu_discovery_get_table_info(adev, &info, GC)) 4098 return -EINVAL; 4099 4100 offset = le16_to_cpu(info->offset); 4101 if (!offset) 4102 return -EINVAL; 4103 4104 gc_info = (union gc_info *)(discovery_bin + offset); 4105 4106 if (major) 4107 *major = le16_to_cpu(gc_info->v1.header.version_major); 4108 if (minor) 4109 *minor = le16_to_cpu(gc_info->v1.header.version_minor); 4110 return 0; 4111 } 4112 4113 int amdgpu_discovery_get_die_rev_id(struct amdgpu_device *adev, 4114 uint16_t *die_rev_id) 4115 { 4116 uint8_t *discovery_bin = adev->discovery.bin; 4117 struct ip_discovery_header *ihdr; 4118 struct table_info *info; 4119 u16 offset; 4120 4121 if (!discovery_bin) 4122 return -EINVAL; 4123 if (amdgpu_discovery_get_table_info(adev, &info, IP_DISCOVERY)) 4124 return -EINVAL; 4125 4126 offset = le16_to_cpu(info->offset); 4127 if (!offset) 4128 return -EINVAL; 4129 4130 ihdr = (struct ip_discovery_header *)(discovery_bin + offset); 4131 4132 if (die_rev_id) 4133 *die_rev_id = le16_to_cpu(ihdr->die_info[0].die_id); 4134 return 0; 4135 } 4136