1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2014-2018 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
6 */
7
8 #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
9
10 #include <linux/debugfs.h>
11 #include <linux/dma-buf.h>
12
13 #include <drm/drm_atomic.h>
14 #include <drm/drm_atomic_uapi.h>
15 #include <drm/drm_blend.h>
16 #include <drm/drm_damage_helper.h>
17 #include <drm/drm_framebuffer.h>
18 #include <drm/drm_gem_atomic_helper.h>
19
20 #include "msm_drv.h"
21 #include "msm_mdss.h"
22 #include "dpu_kms.h"
23 #include "dpu_hw_sspp.h"
24 #include "dpu_hw_util.h"
25 #include "dpu_trace.h"
26 #include "dpu_crtc.h"
27 #include "dpu_vbif.h"
28 #include "dpu_plane.h"
29
30 #define DPU_DEBUG_PLANE(pl, fmt, ...) DRM_DEBUG_ATOMIC("plane%d " fmt,\
31 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
32
33 #define DPU_ERROR_PLANE(pl, fmt, ...) DPU_ERROR("plane%d " fmt,\
34 (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
35
36 #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
37 #define PHASE_STEP_SHIFT 21
38 #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
39 #define PHASE_RESIDUAL 15
40
41 #define SHARP_STRENGTH_DEFAULT 32
42 #define SHARP_EDGE_THR_DEFAULT 112
43 #define SHARP_SMOOTH_THR_DEFAULT 8
44 #define SHARP_NOISE_THR_DEFAULT 2
45
46 #define DPU_PLANE_COLOR_FILL_FLAG BIT(31)
47 #define DPU_ZPOS_MAX 255
48
49 /*
50 * Default Preload Values
51 */
52 #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4
53 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3
54 #define DPU_QSEED4_DEFAULT_PRELOAD_V 0x2
55 #define DPU_QSEED4_DEFAULT_PRELOAD_H 0x4
56
57 #define DEFAULT_REFRESH_RATE 60
58
59 static const uint32_t qcom_compressed_supported_formats[] = {
60 DRM_FORMAT_ABGR8888,
61 DRM_FORMAT_ARGB8888,
62 DRM_FORMAT_XBGR8888,
63 DRM_FORMAT_XRGB8888,
64 DRM_FORMAT_ARGB2101010,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_BGR565,
67
68 DRM_FORMAT_NV12,
69 DRM_FORMAT_P010,
70 };
71
72 /*
73 * struct dpu_plane - local dpu plane structure
74 * @aspace: address space pointer
75 * @csc_ptr: Points to dpu_csc_cfg structure to use for current
76 * @catalog: Points to dpu catalog structure
77 * @revalidate: force revalidation of all the plane properties
78 */
79 struct dpu_plane {
80 struct drm_plane base;
81
82 enum dpu_sspp pipe;
83
84 uint32_t color_fill;
85 bool is_error;
86 bool is_rt_pipe;
87 const struct dpu_mdss_cfg *catalog;
88 };
89
90 static const uint64_t supported_format_modifiers[] = {
91 DRM_FORMAT_MOD_QCOM_COMPRESSED,
92 DRM_FORMAT_MOD_LINEAR,
93 DRM_FORMAT_MOD_INVALID
94 };
95
96 #define to_dpu_plane(x) container_of(x, struct dpu_plane, base)
97
_dpu_plane_get_kms(struct drm_plane * plane)98 static struct dpu_kms *_dpu_plane_get_kms(struct drm_plane *plane)
99 {
100 struct msm_drm_private *priv = plane->dev->dev_private;
101
102 return to_dpu_kms(priv->kms);
103 }
104
105 /**
106 * _dpu_plane_calc_bw - calculate bandwidth required for a plane
107 * @catalog: Points to dpu catalog structure
108 * @fmt: Pointer to source buffer format
109 * @mode: Pointer to drm display mode
110 * @pipe_cfg: Pointer to pipe configuration
111 * Result: Updates calculated bandwidth in the plane state.
112 * BW Equation: src_w * src_h * bpp * fps * (v_total / v_dest)
113 * Prefill BW Equation: line src bytes * line_time
114 */
_dpu_plane_calc_bw(const struct dpu_mdss_cfg * catalog,const struct msm_format * fmt,const struct drm_display_mode * mode,struct dpu_sw_pipe_cfg * pipe_cfg)115 static u64 _dpu_plane_calc_bw(const struct dpu_mdss_cfg *catalog,
116 const struct msm_format *fmt,
117 const struct drm_display_mode *mode,
118 struct dpu_sw_pipe_cfg *pipe_cfg)
119 {
120 int src_width, src_height, dst_height, fps;
121 u64 plane_pixel_rate, plane_bit_rate;
122 u64 plane_prefill_bw;
123 u64 plane_bw;
124 u32 hw_latency_lines;
125 u64 scale_factor;
126 int vbp, vpw, vfp;
127
128 src_width = drm_rect_width(&pipe_cfg->src_rect);
129 src_height = drm_rect_height(&pipe_cfg->src_rect);
130 dst_height = drm_rect_height(&pipe_cfg->dst_rect);
131 fps = drm_mode_vrefresh(mode);
132 vbp = mode->vtotal - mode->vsync_end;
133 vpw = mode->vsync_end - mode->vsync_start;
134 vfp = mode->vsync_start - mode->vdisplay;
135 hw_latency_lines = catalog->perf->min_prefill_lines;
136 scale_factor = src_height > dst_height ?
137 mult_frac(src_height, 1, dst_height) : 1;
138
139 plane_pixel_rate = src_width * mode->vtotal * fps;
140 plane_bit_rate = plane_pixel_rate * fmt->bpp;
141
142 plane_bw = plane_bit_rate * scale_factor;
143
144 plane_prefill_bw = plane_bw * hw_latency_lines;
145
146 if ((vbp+vpw) > hw_latency_lines)
147 do_div(plane_prefill_bw, (vbp+vpw));
148 else if ((vbp+vpw+vfp) < hw_latency_lines)
149 do_div(plane_prefill_bw, (vbp+vpw+vfp));
150 else
151 do_div(plane_prefill_bw, hw_latency_lines);
152
153
154 return max(plane_bw, plane_prefill_bw);
155 }
156
157 /**
158 * _dpu_plane_calc_clk - calculate clock required for a plane
159 * @mode: Pointer to drm display mode
160 * @pipe_cfg: Pointer to pipe configuration
161 * Result: Updates calculated clock in the plane state.
162 * Clock equation: dst_w * v_total * fps * (src_h / dst_h)
163 */
_dpu_plane_calc_clk(const struct drm_display_mode * mode,struct dpu_sw_pipe_cfg * pipe_cfg)164 static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode,
165 struct dpu_sw_pipe_cfg *pipe_cfg)
166 {
167 int dst_width, src_height, dst_height, fps;
168 u64 plane_clk;
169
170 src_height = drm_rect_height(&pipe_cfg->src_rect);
171 dst_width = drm_rect_width(&pipe_cfg->dst_rect);
172 dst_height = drm_rect_height(&pipe_cfg->dst_rect);
173 fps = drm_mode_vrefresh(mode);
174
175 plane_clk =
176 dst_width * mode->vtotal * fps;
177
178 if (src_height > dst_height) {
179 plane_clk *= src_height;
180 do_div(plane_clk, dst_height);
181 }
182
183 return plane_clk;
184 }
185
186 /**
187 * _dpu_plane_calc_fill_level - calculate fill level of the given source format
188 * @plane: Pointer to drm plane
189 * @pipe: Pointer to software pipe
190 * @lut_usage: LUT usecase
191 * @fmt: Pointer to source buffer format
192 * @src_width: width of source buffer
193 * Return: fill level corresponding to the source buffer/format or 0 if error
194 */
_dpu_plane_calc_fill_level(struct drm_plane * plane,struct dpu_sw_pipe * pipe,enum dpu_qos_lut_usage lut_usage,const struct msm_format * fmt,u32 src_width)195 static int _dpu_plane_calc_fill_level(struct drm_plane *plane,
196 struct dpu_sw_pipe *pipe,
197 enum dpu_qos_lut_usage lut_usage,
198 const struct msm_format *fmt, u32 src_width)
199 {
200 struct dpu_plane *pdpu;
201 u32 fixed_buff_size;
202 u32 total_fl;
203
204 if (!fmt || !pipe || !src_width || !fmt->bpp) {
205 DPU_ERROR("invalid arguments\n");
206 return 0;
207 }
208
209 if (lut_usage == DPU_QOS_LUT_USAGE_NRT)
210 return 0;
211
212 pdpu = to_dpu_plane(plane);
213 fixed_buff_size = pdpu->catalog->caps->pixel_ram_size;
214
215 /* FIXME: in multirect case account for the src_width of all the planes */
216
217 if (fmt->fetch_type == MDP_PLANE_PSEUDO_PLANAR) {
218 if (fmt->chroma_sample == CHROMA_420) {
219 /* NV12 */
220 total_fl = (fixed_buff_size / 2) /
221 ((src_width + 32) * fmt->bpp);
222 } else {
223 /* non NV12 */
224 total_fl = (fixed_buff_size / 2) * 2 /
225 ((src_width + 32) * fmt->bpp);
226 }
227 } else {
228 if (pipe->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
229 total_fl = (fixed_buff_size / 2) * 2 /
230 ((src_width + 32) * fmt->bpp);
231 } else {
232 total_fl = (fixed_buff_size) * 2 /
233 ((src_width + 32) * fmt->bpp);
234 }
235 }
236
237 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc w:%u fl:%u\n",
238 pipe->sspp->idx - SSPP_VIG0,
239 &fmt->pixel_format,
240 src_width, total_fl);
241
242 return total_fl;
243 }
244
245 /**
246 * _dpu_plane_set_qos_lut - set QoS LUT of the given plane
247 * @plane: Pointer to drm plane
248 * @pipe: Pointer to software pipe
249 * @fmt: Pointer to source buffer format
250 * @pipe_cfg: Pointer to pipe configuration
251 */
_dpu_plane_set_qos_lut(struct drm_plane * plane,struct dpu_sw_pipe * pipe,const struct msm_format * fmt,struct dpu_sw_pipe_cfg * pipe_cfg)252 static void _dpu_plane_set_qos_lut(struct drm_plane *plane,
253 struct dpu_sw_pipe *pipe,
254 const struct msm_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg)
255 {
256 struct dpu_plane *pdpu = to_dpu_plane(plane);
257 struct dpu_hw_qos_cfg cfg;
258 u32 total_fl, lut_usage;
259
260 if (!pdpu->is_rt_pipe) {
261 lut_usage = DPU_QOS_LUT_USAGE_NRT;
262 } else {
263 if (fmt && MSM_FORMAT_IS_LINEAR(fmt))
264 lut_usage = DPU_QOS_LUT_USAGE_LINEAR;
265 else
266 lut_usage = DPU_QOS_LUT_USAGE_MACROTILE;
267 }
268
269 total_fl = _dpu_plane_calc_fill_level(plane, pipe, lut_usage, fmt,
270 drm_rect_width(&pipe_cfg->src_rect));
271
272 cfg.creq_lut = _dpu_hw_get_qos_lut(&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl);
273 cfg.danger_lut = pdpu->catalog->perf->danger_lut_tbl[lut_usage];
274 cfg.safe_lut = pdpu->catalog->perf->safe_lut_tbl[lut_usage];
275
276 if (pipe->sspp->idx != SSPP_CURSOR0 &&
277 pipe->sspp->idx != SSPP_CURSOR1 &&
278 pdpu->is_rt_pipe)
279 cfg.danger_safe_en = true;
280
281 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n",
282 pdpu->pipe - SSPP_VIG0,
283 cfg.danger_safe_en,
284 pdpu->is_rt_pipe);
285
286 trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0,
287 (fmt) ? fmt->pixel_format : 0,
288 pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage);
289
290 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc rt:%d fl:%u lut:0x%llx\n",
291 pdpu->pipe - SSPP_VIG0,
292 fmt ? &fmt->pixel_format : NULL,
293 pdpu->is_rt_pipe, total_fl, cfg.creq_lut);
294
295 trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0,
296 (fmt) ? fmt->pixel_format : 0,
297 (fmt) ? fmt->fetch_mode : 0,
298 cfg.danger_lut,
299 cfg.safe_lut);
300
301 DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %p4cc mode:%d luts[0x%x, 0x%x]\n",
302 pdpu->pipe - SSPP_VIG0,
303 fmt ? &fmt->pixel_format : NULL,
304 fmt ? fmt->fetch_mode : -1,
305 cfg.danger_lut,
306 cfg.safe_lut);
307
308 pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg);
309 }
310
311 /**
312 * _dpu_plane_set_qos_ctrl - set QoS control of the given plane
313 * @plane: Pointer to drm plane
314 * @pipe: Pointer to software pipe
315 * @enable: true to enable QoS control
316 */
_dpu_plane_set_qos_ctrl(struct drm_plane * plane,struct dpu_sw_pipe * pipe,bool enable)317 static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane,
318 struct dpu_sw_pipe *pipe,
319 bool enable)
320 {
321 struct dpu_plane *pdpu = to_dpu_plane(plane);
322
323 if (!pdpu->is_rt_pipe)
324 enable = false;
325
326 DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n",
327 pdpu->pipe - SSPP_VIG0,
328 enable,
329 pdpu->is_rt_pipe);
330
331 pipe->sspp->ops.setup_qos_ctrl(pipe->sspp,
332 enable);
333 }
334
_dpu_plane_sspp_clk_force_ctrl(struct dpu_hw_sspp * sspp,struct dpu_hw_mdp * mdp,bool enable,bool * forced_on)335 static bool _dpu_plane_sspp_clk_force_ctrl(struct dpu_hw_sspp *sspp,
336 struct dpu_hw_mdp *mdp,
337 bool enable, bool *forced_on)
338 {
339 if (sspp->ops.setup_clk_force_ctrl) {
340 *forced_on = sspp->ops.setup_clk_force_ctrl(sspp, enable);
341 return true;
342 }
343
344 if (mdp->ops.setup_clk_force_ctrl) {
345 *forced_on = mdp->ops.setup_clk_force_ctrl(mdp, sspp->cap->clk_ctrl, enable);
346 return true;
347 }
348
349 return false;
350 }
351
352 /**
353 * _dpu_plane_set_ot_limit - set OT limit for the given plane
354 * @plane: Pointer to drm plane
355 * @pipe: Pointer to software pipe
356 * @pipe_cfg: Pointer to pipe configuration
357 * @frame_rate: CRTC's frame rate
358 */
_dpu_plane_set_ot_limit(struct drm_plane * plane,struct dpu_sw_pipe * pipe,struct dpu_sw_pipe_cfg * pipe_cfg,int frame_rate)359 static void _dpu_plane_set_ot_limit(struct drm_plane *plane,
360 struct dpu_sw_pipe *pipe,
361 struct dpu_sw_pipe_cfg *pipe_cfg,
362 int frame_rate)
363 {
364 struct dpu_plane *pdpu = to_dpu_plane(plane);
365 struct dpu_vbif_set_ot_params ot_params;
366 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
367 bool forced_on = false;
368
369 memset(&ot_params, 0, sizeof(ot_params));
370 ot_params.xin_id = pipe->sspp->cap->xin_id;
371 ot_params.num = pipe->sspp->idx - SSPP_NONE;
372 ot_params.width = drm_rect_width(&pipe_cfg->src_rect);
373 ot_params.height = drm_rect_height(&pipe_cfg->src_rect);
374 ot_params.is_wfd = !pdpu->is_rt_pipe;
375 ot_params.frame_rate = frame_rate;
376 ot_params.vbif_idx = VBIF_RT;
377 ot_params.rd = true;
378
379 if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,
380 true, &forced_on))
381 return;
382
383 dpu_vbif_set_ot_limit(dpu_kms, &ot_params);
384
385 if (forced_on)
386 _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,
387 false, &forced_on);
388 }
389
390 /**
391 * _dpu_plane_set_qos_remap - set vbif QoS for the given plane
392 * @plane: Pointer to drm plane
393 * @pipe: Pointer to software pipe
394 */
_dpu_plane_set_qos_remap(struct drm_plane * plane,struct dpu_sw_pipe * pipe)395 static void _dpu_plane_set_qos_remap(struct drm_plane *plane,
396 struct dpu_sw_pipe *pipe)
397 {
398 struct dpu_plane *pdpu = to_dpu_plane(plane);
399 struct dpu_vbif_set_qos_params qos_params;
400 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
401 bool forced_on = false;
402
403 memset(&qos_params, 0, sizeof(qos_params));
404 qos_params.vbif_idx = VBIF_RT;
405 qos_params.xin_id = pipe->sspp->cap->xin_id;
406 qos_params.num = pipe->sspp->idx - SSPP_VIG0;
407 qos_params.is_rt = pdpu->is_rt_pipe;
408
409 DPU_DEBUG_PLANE(pdpu, "pipe:%d vbif:%d xin:%d rt:%d\n",
410 qos_params.num,
411 qos_params.vbif_idx,
412 qos_params.xin_id, qos_params.is_rt);
413
414 if (!_dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,
415 true, &forced_on))
416 return;
417
418 dpu_vbif_set_qos_remap(dpu_kms, &qos_params);
419
420 if (forced_on)
421 _dpu_plane_sspp_clk_force_ctrl(pipe->sspp, dpu_kms->hw_mdp,
422 false, &forced_on);
423 }
424
_dpu_plane_setup_scaler3(struct dpu_hw_sspp * pipe_hw,uint32_t src_w,uint32_t src_h,uint32_t dst_w,uint32_t dst_h,struct dpu_hw_scaler3_cfg * scale_cfg,const struct msm_format * fmt,uint32_t chroma_subsmpl_h,uint32_t chroma_subsmpl_v,unsigned int rotation)425 static void _dpu_plane_setup_scaler3(struct dpu_hw_sspp *pipe_hw,
426 uint32_t src_w, uint32_t src_h, uint32_t dst_w, uint32_t dst_h,
427 struct dpu_hw_scaler3_cfg *scale_cfg,
428 const struct msm_format *fmt,
429 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v,
430 unsigned int rotation)
431 {
432 uint32_t i;
433 bool inline_rotation = rotation & DRM_MODE_ROTATE_90;
434
435 /*
436 * For inline rotation cases, scaler config is post-rotation,
437 * so swap the dimensions here. However, pixel extension will
438 * need pre-rotation settings.
439 */
440 if (inline_rotation)
441 swap(src_w, src_h);
442
443 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] =
444 mult_frac((1 << PHASE_STEP_SHIFT), src_w, dst_w);
445 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] =
446 mult_frac((1 << PHASE_STEP_SHIFT), src_h, dst_h);
447
448
449 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2] =
450 scale_cfg->phase_step_y[DPU_SSPP_COMP_0] / chroma_subsmpl_v;
451 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2] =
452 scale_cfg->phase_step_x[DPU_SSPP_COMP_0] / chroma_subsmpl_h;
453
454 scale_cfg->phase_step_x[DPU_SSPP_COMP_2] =
455 scale_cfg->phase_step_x[DPU_SSPP_COMP_1_2];
456 scale_cfg->phase_step_y[DPU_SSPP_COMP_2] =
457 scale_cfg->phase_step_y[DPU_SSPP_COMP_1_2];
458
459 scale_cfg->phase_step_x[DPU_SSPP_COMP_3] =
460 scale_cfg->phase_step_x[DPU_SSPP_COMP_0];
461 scale_cfg->phase_step_y[DPU_SSPP_COMP_3] =
462 scale_cfg->phase_step_y[DPU_SSPP_COMP_0];
463
464 for (i = 0; i < DPU_MAX_PLANES; i++) {
465 scale_cfg->src_width[i] = src_w;
466 scale_cfg->src_height[i] = src_h;
467 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
468 scale_cfg->src_width[i] /= chroma_subsmpl_h;
469 scale_cfg->src_height[i] /= chroma_subsmpl_v;
470 }
471
472 if (pipe_hw->cap->sblk->scaler_blk.version >= 0x3000) {
473 scale_cfg->preload_x[i] = DPU_QSEED4_DEFAULT_PRELOAD_H;
474 scale_cfg->preload_y[i] = DPU_QSEED4_DEFAULT_PRELOAD_V;
475 } else {
476 scale_cfg->preload_x[i] = DPU_QSEED3_DEFAULT_PRELOAD_H;
477 scale_cfg->preload_y[i] = DPU_QSEED3_DEFAULT_PRELOAD_V;
478 }
479 }
480 if (!(MSM_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
481 && (src_w == dst_w))
482 return;
483
484 scale_cfg->dst_width = dst_w;
485 scale_cfg->dst_height = dst_h;
486 scale_cfg->y_rgb_filter_cfg = DPU_SCALE_BIL;
487 scale_cfg->uv_filter_cfg = DPU_SCALE_BIL;
488 scale_cfg->alpha_filter_cfg = DPU_SCALE_ALPHA_BIL;
489 scale_cfg->lut_flag = 0;
490 scale_cfg->blend_cfg = 1;
491 scale_cfg->enable = 1;
492 }
493
_dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg * scale_cfg,struct dpu_hw_pixel_ext * pixel_ext,uint32_t src_w,uint32_t src_h,uint32_t chroma_subsmpl_h,uint32_t chroma_subsmpl_v)494 static void _dpu_plane_setup_pixel_ext(struct dpu_hw_scaler3_cfg *scale_cfg,
495 struct dpu_hw_pixel_ext *pixel_ext,
496 uint32_t src_w, uint32_t src_h,
497 uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
498 {
499 int i;
500
501 for (i = 0; i < DPU_MAX_PLANES; i++) {
502 if (i == DPU_SSPP_COMP_1_2 || i == DPU_SSPP_COMP_2) {
503 src_w /= chroma_subsmpl_h;
504 src_h /= chroma_subsmpl_v;
505 }
506
507 pixel_ext->num_ext_pxls_top[i] = src_h;
508 pixel_ext->num_ext_pxls_left[i] = src_w;
509 }
510 }
511
_dpu_plane_get_csc(struct dpu_sw_pipe * pipe,const struct msm_format * fmt)512 static const struct dpu_csc_cfg *_dpu_plane_get_csc(struct dpu_sw_pipe *pipe,
513 const struct msm_format *fmt)
514 {
515 const struct dpu_csc_cfg *csc_ptr;
516
517 if (!MSM_FORMAT_IS_YUV(fmt))
518 return NULL;
519
520 if (BIT(DPU_SSPP_CSC_10BIT) & pipe->sspp->cap->features)
521 csc_ptr = &dpu_csc10_YUV2RGB_601L;
522 else
523 csc_ptr = &dpu_csc_YUV2RGB_601L;
524
525 return csc_ptr;
526 }
527
_dpu_plane_setup_scaler(struct dpu_sw_pipe * pipe,const struct msm_format * fmt,bool color_fill,struct dpu_sw_pipe_cfg * pipe_cfg)528 static void _dpu_plane_setup_scaler(struct dpu_sw_pipe *pipe,
529 const struct msm_format *fmt, bool color_fill,
530 struct dpu_sw_pipe_cfg *pipe_cfg)
531 {
532 struct dpu_hw_sspp *pipe_hw = pipe->sspp;
533 const struct drm_format_info *info = drm_format_info(fmt->pixel_format);
534 struct dpu_hw_scaler3_cfg scaler3_cfg;
535 struct dpu_hw_pixel_ext pixel_ext;
536 u32 src_width = drm_rect_width(&pipe_cfg->src_rect);
537 u32 src_height = drm_rect_height(&pipe_cfg->src_rect);
538 u32 dst_width = drm_rect_width(&pipe_cfg->dst_rect);
539 u32 dst_height = drm_rect_height(&pipe_cfg->dst_rect);
540
541 memset(&scaler3_cfg, 0, sizeof(scaler3_cfg));
542 memset(&pixel_ext, 0, sizeof(pixel_ext));
543
544 /* don't chroma subsample if decimating */
545 /* update scaler. calculate default config for QSEED3 */
546 _dpu_plane_setup_scaler3(pipe_hw,
547 src_width,
548 src_height,
549 dst_width,
550 dst_height,
551 &scaler3_cfg, fmt,
552 info->hsub, info->vsub,
553 pipe_cfg->rotation);
554
555 /* configure pixel extension based on scalar config */
556 _dpu_plane_setup_pixel_ext(&scaler3_cfg, &pixel_ext,
557 src_width, src_height, info->hsub, info->vsub);
558
559 if (pipe_hw->ops.setup_pe)
560 pipe_hw->ops.setup_pe(pipe_hw,
561 &pixel_ext);
562
563 /**
564 * when programmed in multirect mode, scalar block will be
565 * bypassed. Still we need to update alpha and bitwidth
566 * ONLY for RECT0
567 */
568 if (pipe_hw->ops.setup_scaler &&
569 pipe->multirect_index != DPU_SSPP_RECT_1)
570 pipe_hw->ops.setup_scaler(pipe_hw,
571 &scaler3_cfg,
572 fmt);
573 }
574
_dpu_plane_color_fill_pipe(struct dpu_plane_state * pstate,struct dpu_sw_pipe * pipe,struct drm_rect * dst_rect,u32 fill_color,const struct msm_format * fmt)575 static void _dpu_plane_color_fill_pipe(struct dpu_plane_state *pstate,
576 struct dpu_sw_pipe *pipe,
577 struct drm_rect *dst_rect,
578 u32 fill_color,
579 const struct msm_format *fmt)
580 {
581 struct dpu_sw_pipe_cfg pipe_cfg;
582
583 /* update sspp */
584 if (!pipe->sspp->ops.setup_solidfill)
585 return;
586
587 pipe->sspp->ops.setup_solidfill(pipe, fill_color);
588
589 /* override scaler/decimation if solid fill */
590 pipe_cfg.dst_rect = *dst_rect;
591
592 pipe_cfg.src_rect.x1 = 0;
593 pipe_cfg.src_rect.y1 = 0;
594 pipe_cfg.src_rect.x2 =
595 drm_rect_width(&pipe_cfg.dst_rect);
596 pipe_cfg.src_rect.y2 =
597 drm_rect_height(&pipe_cfg.dst_rect);
598
599 if (pipe->sspp->ops.setup_format)
600 pipe->sspp->ops.setup_format(pipe, fmt, DPU_SSPP_SOLID_FILL);
601
602 if (pipe->sspp->ops.setup_rects)
603 pipe->sspp->ops.setup_rects(pipe, &pipe_cfg);
604
605 _dpu_plane_setup_scaler(pipe, fmt, true, &pipe_cfg);
606 }
607
608 /**
609 * _dpu_plane_color_fill - enables color fill on plane
610 * @pdpu: Pointer to DPU plane object
611 * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
612 * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
613 */
_dpu_plane_color_fill(struct dpu_plane * pdpu,uint32_t color,uint32_t alpha)614 static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
615 uint32_t color, uint32_t alpha)
616 {
617 const struct msm_format *fmt;
618 const struct drm_plane *plane = &pdpu->base;
619 struct msm_drm_private *priv = plane->dev->dev_private;
620 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
621 u32 fill_color = (color & 0xFFFFFF) | ((alpha & 0xFF) << 24);
622
623 DPU_DEBUG_PLANE(pdpu, "\n");
624
625 /*
626 * select fill format to match user property expectation,
627 * h/w only supports RGB variants
628 */
629 fmt = mdp_get_format(priv->kms, DRM_FORMAT_ABGR8888, 0);
630 /* should not happen ever */
631 if (!fmt)
632 return;
633
634 /* update sspp */
635 _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_rect,
636 fill_color, fmt);
637
638 if (pstate->r_pipe.sspp)
639 _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.dst_rect,
640 fill_color, fmt);
641 }
642
dpu_plane_prepare_fb(struct drm_plane * plane,struct drm_plane_state * new_state)643 static int dpu_plane_prepare_fb(struct drm_plane *plane,
644 struct drm_plane_state *new_state)
645 {
646 struct drm_framebuffer *fb = new_state->fb;
647 struct dpu_plane *pdpu = to_dpu_plane(plane);
648 struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
649 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
650 int ret;
651
652 if (!new_state->fb)
653 return 0;
654
655 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", fb->base.id);
656
657 /* cache aspace */
658 pstate->aspace = kms->base.aspace;
659
660 /*
661 * TODO: Need to sort out the msm_framebuffer_prepare() call below so
662 * we can use msm_atomic_prepare_fb() instead of doing the
663 * implicit fence and fb prepare by hand here.
664 */
665 drm_gem_plane_helper_prepare_fb(plane, new_state);
666
667 if (pstate->aspace) {
668 ret = msm_framebuffer_prepare(new_state->fb,
669 pstate->aspace, pstate->needs_dirtyfb);
670 if (ret) {
671 DPU_ERROR("failed to prepare framebuffer\n");
672 return ret;
673 }
674 }
675
676 return 0;
677 }
678
dpu_plane_cleanup_fb(struct drm_plane * plane,struct drm_plane_state * old_state)679 static void dpu_plane_cleanup_fb(struct drm_plane *plane,
680 struct drm_plane_state *old_state)
681 {
682 struct dpu_plane *pdpu = to_dpu_plane(plane);
683 struct dpu_plane_state *old_pstate;
684
685 if (!old_state || !old_state->fb)
686 return;
687
688 old_pstate = to_dpu_plane_state(old_state);
689
690 DPU_DEBUG_PLANE(pdpu, "FB[%u]\n", old_state->fb->base.id);
691
692 msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace,
693 old_pstate->needs_dirtyfb);
694 }
695
dpu_plane_check_inline_rotation(struct dpu_plane * pdpu,struct dpu_sw_pipe * pipe,struct drm_rect src,const struct msm_format * fmt)696 static int dpu_plane_check_inline_rotation(struct dpu_plane *pdpu,
697 struct dpu_sw_pipe *pipe,
698 struct drm_rect src,
699 const struct msm_format *fmt)
700 {
701 const struct dpu_sspp_sub_blks *sblk = pipe->sspp->cap->sblk;
702 size_t num_formats;
703 const u32 *supported_formats;
704
705 if (!test_bit(DPU_SSPP_INLINE_ROTATION, &pipe->sspp->cap->features))
706 return -EINVAL;
707
708 if (!sblk->rotation_cfg) {
709 DPU_ERROR("invalid rotation cfg\n");
710 return -EINVAL;
711 }
712
713 if (drm_rect_width(&src) > sblk->rotation_cfg->rot_maxheight) {
714 DPU_DEBUG_PLANE(pdpu, "invalid height for inline rot:%d max:%d\n",
715 src.y2, sblk->rotation_cfg->rot_maxheight);
716 return -EINVAL;
717 }
718
719 supported_formats = sblk->rotation_cfg->rot_format_list;
720 num_formats = sblk->rotation_cfg->rot_num_formats;
721
722 if (!MSM_FORMAT_IS_UBWC(fmt) ||
723 !dpu_find_format(fmt->pixel_format, supported_formats, num_formats))
724 return -EINVAL;
725
726 return 0;
727 }
728
dpu_plane_atomic_check_pipe(struct dpu_plane * pdpu,struct dpu_sw_pipe * pipe,struct dpu_sw_pipe_cfg * pipe_cfg,const struct msm_format * fmt,const struct drm_display_mode * mode)729 static int dpu_plane_atomic_check_pipe(struct dpu_plane *pdpu,
730 struct dpu_sw_pipe *pipe,
731 struct dpu_sw_pipe_cfg *pipe_cfg,
732 const struct msm_format *fmt,
733 const struct drm_display_mode *mode)
734 {
735 uint32_t min_src_size;
736 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
737 int ret;
738
739 min_src_size = MSM_FORMAT_IS_YUV(fmt) ? 2 : 1;
740
741 if (MSM_FORMAT_IS_YUV(fmt) &&
742 !pipe->sspp->cap->sblk->csc_blk.len) {
743 DPU_DEBUG_PLANE(pdpu,
744 "plane doesn't have csc for yuv\n");
745 return -EINVAL;
746 }
747
748 /* check src bounds */
749 if (drm_rect_width(&pipe_cfg->src_rect) < min_src_size ||
750 drm_rect_height(&pipe_cfg->src_rect) < min_src_size) {
751 DPU_DEBUG_PLANE(pdpu, "invalid source " DRM_RECT_FMT "\n",
752 DRM_RECT_ARG(&pipe_cfg->src_rect));
753 return -E2BIG;
754 }
755
756 /* valid yuv image */
757 if (MSM_FORMAT_IS_YUV(fmt) &&
758 (pipe_cfg->src_rect.x1 & 0x1 ||
759 pipe_cfg->src_rect.y1 & 0x1 ||
760 drm_rect_width(&pipe_cfg->src_rect) & 0x1 ||
761 drm_rect_height(&pipe_cfg->src_rect) & 0x1)) {
762 DPU_DEBUG_PLANE(pdpu, "invalid yuv source " DRM_RECT_FMT "\n",
763 DRM_RECT_ARG(&pipe_cfg->src_rect));
764 return -EINVAL;
765 }
766
767 /* min dst support */
768 if (drm_rect_width(&pipe_cfg->dst_rect) < 0x1 ||
769 drm_rect_height(&pipe_cfg->dst_rect) < 0x1) {
770 DPU_DEBUG_PLANE(pdpu, "invalid dest rect " DRM_RECT_FMT "\n",
771 DRM_RECT_ARG(&pipe_cfg->dst_rect));
772 return -EINVAL;
773 }
774
775 if (pipe_cfg->rotation & DRM_MODE_ROTATE_90) {
776 ret = dpu_plane_check_inline_rotation(pdpu, pipe, pipe_cfg->src_rect, fmt);
777 if (ret)
778 return ret;
779 }
780
781 /* max clk check */
782 if (_dpu_plane_calc_clk(mode, pipe_cfg) > kms->perf.max_core_clk_rate) {
783 DPU_DEBUG_PLANE(pdpu, "plane exceeds max mdp core clk limits\n");
784 return -E2BIG;
785 }
786
787 return 0;
788 }
789
790 #define MAX_UPSCALE_RATIO 20
791 #define MAX_DOWNSCALE_RATIO 4
792
dpu_plane_atomic_check_nosspp(struct drm_plane * plane,struct drm_plane_state * new_plane_state,const struct drm_crtc_state * crtc_state)793 static int dpu_plane_atomic_check_nosspp(struct drm_plane *plane,
794 struct drm_plane_state *new_plane_state,
795 const struct drm_crtc_state *crtc_state)
796 {
797 int i, ret = 0, min_scale, max_scale;
798 struct dpu_plane *pdpu = to_dpu_plane(plane);
799 struct dpu_kms *kms = _dpu_plane_get_kms(&pdpu->base);
800 u64 max_mdp_clk_rate = kms->perf.max_core_clk_rate;
801 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
802 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
803 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
804 struct drm_rect fb_rect = { 0 };
805 uint32_t max_linewidth;
806
807 min_scale = FRAC_16_16(1, MAX_UPSCALE_RATIO);
808 max_scale = MAX_DOWNSCALE_RATIO << 16;
809
810 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
811 min_scale,
812 max_scale,
813 true, true);
814 if (ret) {
815 DPU_DEBUG_PLANE(pdpu, "Check plane state failed (%d)\n", ret);
816 return ret;
817 }
818 if (!new_plane_state->visible)
819 return 0;
820
821 pstate->stage = DPU_STAGE_0 + pstate->base.normalized_zpos;
822 if (pstate->stage >= pdpu->catalog->caps->max_mixer_blendstages) {
823 DPU_ERROR("> %d plane stages assigned\n",
824 pdpu->catalog->caps->max_mixer_blendstages - DPU_STAGE_0);
825 return -EINVAL;
826 }
827
828 /* state->src is 16.16, src_rect is not */
829 drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src);
830
831 pipe_cfg->dst_rect = new_plane_state->dst;
832
833 fb_rect.x2 = new_plane_state->fb->width;
834 fb_rect.y2 = new_plane_state->fb->height;
835
836 /* Ensure fb size is supported */
837 if (drm_rect_width(&fb_rect) > DPU_MAX_IMG_WIDTH ||
838 drm_rect_height(&fb_rect) > DPU_MAX_IMG_HEIGHT) {
839 DPU_DEBUG_PLANE(pdpu, "invalid framebuffer " DRM_RECT_FMT "\n",
840 DRM_RECT_ARG(&fb_rect));
841 return -E2BIG;
842 }
843
844 ret = dpu_format_populate_plane_sizes(new_plane_state->fb, &pstate->layout);
845 if (ret) {
846 DPU_ERROR_PLANE(pdpu, "failed to get format plane sizes, %d\n", ret);
847 return ret;
848 }
849
850 for (i = 0; i < pstate->layout.num_planes; i++)
851 if (pstate->layout.plane_pitch[i] > DPU_SSPP_MAX_PITCH_SIZE)
852 return -E2BIG;
853
854 max_linewidth = pdpu->catalog->caps->max_linewidth;
855
856 drm_rect_rotate(&pipe_cfg->src_rect,
857 new_plane_state->fb->width, new_plane_state->fb->height,
858 new_plane_state->rotation);
859
860 if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) ||
861 _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_clk_rate) {
862 if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) {
863 DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n",
864 DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth);
865 return -E2BIG;
866 }
867
868 *r_pipe_cfg = *pipe_cfg;
869 pipe_cfg->src_rect.x2 = (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2) >> 1;
870 pipe_cfg->dst_rect.x2 = (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2) >> 1;
871 r_pipe_cfg->src_rect.x1 = pipe_cfg->src_rect.x2;
872 r_pipe_cfg->dst_rect.x1 = pipe_cfg->dst_rect.x2;
873 } else {
874 memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg));
875 }
876
877 drm_rect_rotate_inv(&pipe_cfg->src_rect,
878 new_plane_state->fb->width, new_plane_state->fb->height,
879 new_plane_state->rotation);
880 if (drm_rect_width(&r_pipe_cfg->src_rect) != 0)
881 drm_rect_rotate_inv(&r_pipe_cfg->src_rect,
882 new_plane_state->fb->width, new_plane_state->fb->height,
883 new_plane_state->rotation);
884
885 pstate->needs_qos_remap = drm_atomic_crtc_needs_modeset(crtc_state);
886
887 return 0;
888 }
889
dpu_plane_is_multirect_parallel_capable(struct dpu_hw_sspp * sspp,struct dpu_sw_pipe_cfg * pipe_cfg,const struct msm_format * fmt,uint32_t max_linewidth)890 static int dpu_plane_is_multirect_parallel_capable(struct dpu_hw_sspp *sspp,
891 struct dpu_sw_pipe_cfg *pipe_cfg,
892 const struct msm_format *fmt,
893 uint32_t max_linewidth)
894 {
895 if (drm_rect_width(&pipe_cfg->src_rect) != drm_rect_width(&pipe_cfg->dst_rect) ||
896 drm_rect_height(&pipe_cfg->src_rect) != drm_rect_height(&pipe_cfg->dst_rect))
897 return false;
898
899 if (pipe_cfg->rotation & DRM_MODE_ROTATE_90)
900 return false;
901
902 if (MSM_FORMAT_IS_YUV(fmt))
903 return false;
904
905 if (MSM_FORMAT_IS_UBWC(fmt) &&
906 drm_rect_width(&pipe_cfg->src_rect) > max_linewidth / 2)
907 return false;
908
909 if (!test_bit(DPU_SSPP_SMART_DMA_V1, &sspp->cap->features) &&
910 !test_bit(DPU_SSPP_SMART_DMA_V2, &sspp->cap->features))
911 return false;
912
913 return true;
914 }
915
dpu_plane_atomic_check_sspp(struct drm_plane * plane,struct drm_atomic_state * state,const struct drm_crtc_state * crtc_state)916 static int dpu_plane_atomic_check_sspp(struct drm_plane *plane,
917 struct drm_atomic_state *state,
918 const struct drm_crtc_state *crtc_state)
919 {
920 struct drm_plane_state *new_plane_state =
921 drm_atomic_get_new_plane_state(state, plane);
922 struct dpu_plane *pdpu = to_dpu_plane(plane);
923 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
924 struct dpu_sw_pipe *pipe = &pstate->pipe;
925 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
926 const struct msm_format *fmt;
927 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
928 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
929 uint32_t supported_rotations;
930 const struct dpu_sspp_cfg *pipe_hw_caps;
931 const struct dpu_sspp_sub_blks *sblk;
932 int ret = 0;
933
934 pipe_hw_caps = pipe->sspp->cap;
935 sblk = pipe->sspp->cap->sblk;
936
937 /*
938 * We already have verified scaling against platform limitations.
939 * Now check if the SSPP supports scaling at all.
940 */
941 if (!sblk->scaler_blk.len &&
942 ((drm_rect_width(&new_plane_state->src) >> 16 !=
943 drm_rect_width(&new_plane_state->dst)) ||
944 (drm_rect_height(&new_plane_state->src) >> 16 !=
945 drm_rect_height(&new_plane_state->dst))))
946 return -ERANGE;
947
948 fmt = msm_framebuffer_format(new_plane_state->fb);
949
950 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0;
951
952 if (pipe_hw_caps->features & BIT(DPU_SSPP_INLINE_ROTATION))
953 supported_rotations |= DRM_MODE_ROTATE_90;
954
955 pipe_cfg->rotation = drm_rotation_simplify(new_plane_state->rotation,
956 supported_rotations);
957 r_pipe_cfg->rotation = pipe_cfg->rotation;
958
959 ret = dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, fmt,
960 &crtc_state->adjusted_mode);
961 if (ret)
962 return ret;
963
964 if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) {
965 ret = dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, fmt,
966 &crtc_state->adjusted_mode);
967 if (ret)
968 return ret;
969 }
970
971 return 0;
972 }
973
dpu_plane_try_multirect_parallel(struct dpu_sw_pipe * pipe,struct dpu_sw_pipe_cfg * pipe_cfg,struct dpu_sw_pipe * r_pipe,struct dpu_sw_pipe_cfg * r_pipe_cfg,struct dpu_hw_sspp * sspp,const struct msm_format * fmt,uint32_t max_linewidth)974 static bool dpu_plane_try_multirect_parallel(struct dpu_sw_pipe *pipe, struct dpu_sw_pipe_cfg *pipe_cfg,
975 struct dpu_sw_pipe *r_pipe, struct dpu_sw_pipe_cfg *r_pipe_cfg,
976 struct dpu_hw_sspp *sspp, const struct msm_format *fmt,
977 uint32_t max_linewidth)
978 {
979 r_pipe->sspp = NULL;
980
981 pipe->multirect_index = DPU_SSPP_RECT_SOLO;
982 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
983
984 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
985 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
986
987 if (drm_rect_width(&r_pipe_cfg->src_rect) != 0) {
988 if (!dpu_plane_is_multirect_parallel_capable(pipe->sspp, pipe_cfg, fmt, max_linewidth) ||
989 !dpu_plane_is_multirect_parallel_capable(pipe->sspp, r_pipe_cfg, fmt, max_linewidth))
990 return false;
991
992 r_pipe->sspp = pipe->sspp;
993
994 pipe->multirect_index = DPU_SSPP_RECT_0;
995 pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
996
997 r_pipe->multirect_index = DPU_SSPP_RECT_1;
998 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
999 }
1000
1001 return true;
1002 }
1003
dpu_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)1004 static int dpu_plane_atomic_check(struct drm_plane *plane,
1005 struct drm_atomic_state *state)
1006 {
1007 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1008 plane);
1009 int ret = 0;
1010 struct dpu_plane *pdpu = to_dpu_plane(plane);
1011 struct dpu_plane_state *pstate = to_dpu_plane_state(new_plane_state);
1012 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1013 struct dpu_sw_pipe *pipe = &pstate->pipe;
1014 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1015 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1016 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
1017 const struct drm_crtc_state *crtc_state = NULL;
1018 uint32_t max_linewidth = dpu_kms->catalog->caps->max_linewidth;
1019
1020 if (new_plane_state->crtc)
1021 crtc_state = drm_atomic_get_new_crtc_state(state,
1022 new_plane_state->crtc);
1023
1024 pipe->sspp = dpu_rm_get_sspp(&dpu_kms->rm, pdpu->pipe);
1025
1026 if (!pipe->sspp)
1027 return -EINVAL;
1028
1029 ret = dpu_plane_atomic_check_nosspp(plane, new_plane_state, crtc_state);
1030 if (ret)
1031 return ret;
1032
1033 if (!new_plane_state->visible)
1034 return 0;
1035
1036 if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg,
1037 pipe->sspp,
1038 msm_framebuffer_format(new_plane_state->fb),
1039 max_linewidth)) {
1040 DPU_DEBUG_PLANE(pdpu, "invalid " DRM_RECT_FMT " /" DRM_RECT_FMT
1041 " max_line:%u, can't use split source\n",
1042 DRM_RECT_ARG(&pipe_cfg->src_rect),
1043 DRM_RECT_ARG(&r_pipe_cfg->src_rect),
1044 max_linewidth);
1045 return -E2BIG;
1046 }
1047
1048 return dpu_plane_atomic_check_sspp(plane, state, crtc_state);
1049 }
1050
dpu_plane_virtual_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)1051 static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
1052 struct drm_atomic_state *state)
1053 {
1054 struct drm_plane_state *plane_state =
1055 drm_atomic_get_plane_state(state, plane);
1056 struct drm_plane_state *old_plane_state =
1057 drm_atomic_get_old_plane_state(state, plane);
1058 struct dpu_plane_state *pstate = to_dpu_plane_state(plane_state);
1059 struct drm_crtc_state *crtc_state;
1060 int ret;
1061
1062 if (plane_state->crtc)
1063 crtc_state = drm_atomic_get_new_crtc_state(state,
1064 plane_state->crtc);
1065
1066 ret = dpu_plane_atomic_check_nosspp(plane, plane_state, crtc_state);
1067 if (ret)
1068 return ret;
1069
1070 if (!plane_state->visible) {
1071 /*
1072 * resources are freed by dpu_crtc_assign_plane_resources(),
1073 * but clean them here.
1074 */
1075 pstate->pipe.sspp = NULL;
1076 pstate->r_pipe.sspp = NULL;
1077
1078 return 0;
1079 }
1080
1081 /*
1082 * Force resource reallocation if the format of FB or src/dst have
1083 * changed. We might need to allocate different SSPP or SSPPs for this
1084 * plane than the one used previously.
1085 */
1086 if (!old_plane_state || !old_plane_state->fb ||
1087 old_plane_state->src_w != plane_state->src_w ||
1088 old_plane_state->src_h != plane_state->src_h ||
1089 old_plane_state->src_w != plane_state->src_w ||
1090 old_plane_state->crtc_h != plane_state->crtc_h ||
1091 msm_framebuffer_format(old_plane_state->fb) !=
1092 msm_framebuffer_format(plane_state->fb))
1093 crtc_state->planes_changed = true;
1094
1095 return 0;
1096 }
1097
dpu_plane_virtual_assign_resources(struct drm_crtc * crtc,struct dpu_global_state * global_state,struct drm_atomic_state * state,struct drm_plane_state * plane_state)1098 static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
1099 struct dpu_global_state *global_state,
1100 struct drm_atomic_state *state,
1101 struct drm_plane_state *plane_state)
1102 {
1103 const struct drm_crtc_state *crtc_state = NULL;
1104 struct drm_plane *plane = plane_state->plane;
1105 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1106 struct dpu_rm_sspp_requirements reqs;
1107 struct dpu_plane_state *pstate;
1108 struct dpu_sw_pipe *pipe;
1109 struct dpu_sw_pipe *r_pipe;
1110 struct dpu_sw_pipe_cfg *pipe_cfg;
1111 struct dpu_sw_pipe_cfg *r_pipe_cfg;
1112 const struct msm_format *fmt;
1113
1114 if (plane_state->crtc)
1115 crtc_state = drm_atomic_get_new_crtc_state(state,
1116 plane_state->crtc);
1117
1118 pstate = to_dpu_plane_state(plane_state);
1119 pipe = &pstate->pipe;
1120 r_pipe = &pstate->r_pipe;
1121 pipe_cfg = &pstate->pipe_cfg;
1122 r_pipe_cfg = &pstate->r_pipe_cfg;
1123
1124 pipe->sspp = NULL;
1125 r_pipe->sspp = NULL;
1126
1127 if (!plane_state->fb)
1128 return -EINVAL;
1129
1130 fmt = msm_framebuffer_format(plane_state->fb);
1131 reqs.yuv = MSM_FORMAT_IS_YUV(fmt);
1132 reqs.scale = (plane_state->src_w >> 16 != plane_state->crtc_w) ||
1133 (plane_state->src_h >> 16 != plane_state->crtc_h);
1134
1135 reqs.rot90 = drm_rotation_90_or_270(plane_state->rotation);
1136
1137 pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
1138 if (!pipe->sspp)
1139 return -ENODEV;
1140
1141 if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg,
1142 pipe->sspp,
1143 msm_framebuffer_format(plane_state->fb),
1144 dpu_kms->catalog->caps->max_linewidth)) {
1145 /* multirect is not possible, use two SSPP blocks */
1146 r_pipe->sspp = dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &reqs);
1147 if (!r_pipe->sspp)
1148 return -ENODEV;
1149
1150 pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1151 pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1152
1153 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1154 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1155 }
1156
1157 return dpu_plane_atomic_check_sspp(plane, state, crtc_state);
1158 }
1159
dpu_assign_plane_resources(struct dpu_global_state * global_state,struct drm_atomic_state * state,struct drm_crtc * crtc,struct drm_plane_state ** states,unsigned int num_planes)1160 int dpu_assign_plane_resources(struct dpu_global_state *global_state,
1161 struct drm_atomic_state *state,
1162 struct drm_crtc *crtc,
1163 struct drm_plane_state **states,
1164 unsigned int num_planes)
1165 {
1166 unsigned int i;
1167
1168 for (i = 0; i < num_planes; i++) {
1169 struct drm_plane_state *plane_state = states[i];
1170
1171 if (!plane_state ||
1172 !plane_state->visible)
1173 continue;
1174
1175 int ret = dpu_plane_virtual_assign_resources(crtc, global_state,
1176 state, plane_state);
1177 if (ret)
1178 return ret;
1179 }
1180
1181 return 0;
1182 }
1183
dpu_plane_flush_csc(struct dpu_plane * pdpu,struct dpu_sw_pipe * pipe)1184 static void dpu_plane_flush_csc(struct dpu_plane *pdpu, struct dpu_sw_pipe *pipe)
1185 {
1186 const struct msm_format *format =
1187 msm_framebuffer_format(pdpu->base.state->fb);
1188 const struct dpu_csc_cfg *csc_ptr;
1189
1190 if (!pipe->sspp || !pipe->sspp->ops.setup_csc)
1191 return;
1192
1193 csc_ptr = _dpu_plane_get_csc(pipe, format);
1194 if (!csc_ptr)
1195 return;
1196
1197 DPU_DEBUG_PLANE(pdpu, "using 0x%X 0x%X 0x%X...\n",
1198 csc_ptr->csc_mv[0],
1199 csc_ptr->csc_mv[1],
1200 csc_ptr->csc_mv[2]);
1201
1202 pipe->sspp->ops.setup_csc(pipe->sspp, csc_ptr);
1203
1204 }
1205
1206 /**
1207 * dpu_plane_flush - final plane operations before commit flush
1208 * @plane: Pointer to drm plane structure
1209 */
dpu_plane_flush(struct drm_plane * plane)1210 void dpu_plane_flush(struct drm_plane *plane)
1211 {
1212 struct dpu_plane *pdpu;
1213 struct dpu_plane_state *pstate;
1214
1215 if (!plane || !plane->state) {
1216 DPU_ERROR("invalid plane\n");
1217 return;
1218 }
1219
1220 pdpu = to_dpu_plane(plane);
1221 pstate = to_dpu_plane_state(plane->state);
1222
1223 /*
1224 * These updates have to be done immediately before the plane flush
1225 * timing, and may not be moved to the atomic_update/mode_set functions.
1226 */
1227 if (pdpu->is_error)
1228 /* force white frame with 100% alpha pipe output on error */
1229 _dpu_plane_color_fill(pdpu, 0xFFFFFF, 0xFF);
1230 else if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG)
1231 /* force 100% alpha */
1232 _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
1233 else {
1234 dpu_plane_flush_csc(pdpu, &pstate->pipe);
1235 dpu_plane_flush_csc(pdpu, &pstate->r_pipe);
1236 }
1237
1238 /* flag h/w flush complete */
1239 if (plane->state)
1240 pstate->pending = false;
1241 }
1242
1243 /**
1244 * dpu_plane_set_error: enable/disable error condition
1245 * @plane: pointer to drm_plane structure
1246 * @error: error value to set
1247 */
dpu_plane_set_error(struct drm_plane * plane,bool error)1248 void dpu_plane_set_error(struct drm_plane *plane, bool error)
1249 {
1250 struct dpu_plane *pdpu;
1251
1252 if (!plane)
1253 return;
1254
1255 pdpu = to_dpu_plane(plane);
1256 pdpu->is_error = error;
1257 }
1258
dpu_plane_sspp_update_pipe(struct drm_plane * plane,struct dpu_sw_pipe * pipe,struct dpu_sw_pipe_cfg * pipe_cfg,const struct msm_format * fmt,int frame_rate,struct dpu_hw_fmt_layout * layout)1259 static void dpu_plane_sspp_update_pipe(struct drm_plane *plane,
1260 struct dpu_sw_pipe *pipe,
1261 struct dpu_sw_pipe_cfg *pipe_cfg,
1262 const struct msm_format *fmt,
1263 int frame_rate,
1264 struct dpu_hw_fmt_layout *layout)
1265 {
1266 uint32_t src_flags;
1267 struct dpu_plane *pdpu = to_dpu_plane(plane);
1268 struct drm_plane_state *state = plane->state;
1269 struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1270
1271 if (layout && pipe->sspp->ops.setup_sourceaddress) {
1272 trace_dpu_plane_set_scanout(pipe, layout);
1273 pipe->sspp->ops.setup_sourceaddress(pipe, layout);
1274 }
1275
1276 /* override for color fill */
1277 if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) {
1278 _dpu_plane_set_qos_ctrl(plane, pipe, false);
1279
1280 /* skip remaining processing on color fill */
1281 return;
1282 }
1283
1284 if (pipe->sspp->ops.setup_rects) {
1285 pipe->sspp->ops.setup_rects(pipe,
1286 pipe_cfg);
1287 }
1288
1289 _dpu_plane_setup_scaler(pipe, fmt, false, pipe_cfg);
1290
1291 if (pipe->sspp->ops.setup_multirect)
1292 pipe->sspp->ops.setup_multirect(
1293 pipe);
1294
1295 if (pipe->sspp->ops.setup_format) {
1296 unsigned int rotation = pipe_cfg->rotation;
1297
1298 src_flags = 0x0;
1299
1300 if (rotation & DRM_MODE_REFLECT_X)
1301 src_flags |= DPU_SSPP_FLIP_LR;
1302
1303 if (rotation & DRM_MODE_REFLECT_Y)
1304 src_flags |= DPU_SSPP_FLIP_UD;
1305
1306 if (rotation & DRM_MODE_ROTATE_90)
1307 src_flags |= DPU_SSPP_ROT_90;
1308
1309 /* update format */
1310 pipe->sspp->ops.setup_format(pipe, fmt, src_flags);
1311
1312 if (pipe->sspp->ops.setup_cdp) {
1313 const struct dpu_perf_cfg *perf = pdpu->catalog->perf;
1314
1315 pipe->sspp->ops.setup_cdp(pipe, fmt,
1316 perf->cdp_cfg[DPU_PERF_CDP_USAGE_RT].rd_enable);
1317 }
1318 }
1319
1320 _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg);
1321
1322 if (pipe->sspp->idx != SSPP_CURSOR0 &&
1323 pipe->sspp->idx != SSPP_CURSOR1)
1324 _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate);
1325
1326 if (pstate->needs_qos_remap)
1327 _dpu_plane_set_qos_remap(plane, pipe);
1328 }
1329
dpu_plane_sspp_atomic_update(struct drm_plane * plane,struct drm_plane_state * new_state)1330 static void dpu_plane_sspp_atomic_update(struct drm_plane *plane,
1331 struct drm_plane_state *new_state)
1332 {
1333 struct dpu_plane *pdpu = to_dpu_plane(plane);
1334 struct drm_plane_state *state = plane->state;
1335 struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1336 struct dpu_sw_pipe *pipe = &pstate->pipe;
1337 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1338 struct drm_crtc *crtc = state->crtc;
1339 struct drm_framebuffer *fb = state->fb;
1340 bool is_rt_pipe;
1341 const struct msm_format *fmt =
1342 msm_framebuffer_format(fb);
1343 struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1344 struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
1345
1346 pstate->pending = true;
1347
1348 is_rt_pipe = (dpu_crtc_get_client_type(crtc) != NRT_CLIENT);
1349 pstate->needs_qos_remap |= (is_rt_pipe != pdpu->is_rt_pipe);
1350 pdpu->is_rt_pipe = is_rt_pipe;
1351
1352 dpu_format_populate_addrs(pstate->aspace, new_state->fb, &pstate->layout);
1353
1354 DPU_DEBUG_PLANE(pdpu, "FB[%u] " DRM_RECT_FP_FMT "->crtc%u " DRM_RECT_FMT
1355 ", %p4cc ubwc %d\n", fb->base.id, DRM_RECT_FP_ARG(&state->src),
1356 crtc->base.id, DRM_RECT_ARG(&state->dst),
1357 &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
1358
1359 dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt,
1360 drm_mode_vrefresh(&crtc->mode),
1361 &pstate->layout);
1362
1363 if (r_pipe->sspp) {
1364 dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt,
1365 drm_mode_vrefresh(&crtc->mode),
1366 &pstate->layout);
1367 }
1368
1369 if (pstate->needs_qos_remap)
1370 pstate->needs_qos_remap = false;
1371
1372 pstate->plane_fetch_bw = _dpu_plane_calc_bw(pdpu->catalog, fmt,
1373 &crtc->mode, pipe_cfg);
1374
1375 pstate->plane_clk = _dpu_plane_calc_clk(&crtc->mode, pipe_cfg);
1376
1377 if (r_pipe->sspp) {
1378 pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc->mode, r_pipe_cfg);
1379
1380 pstate->plane_clk = max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->mode, r_pipe_cfg));
1381 }
1382 }
1383
_dpu_plane_atomic_disable(struct drm_plane * plane)1384 static void _dpu_plane_atomic_disable(struct drm_plane *plane)
1385 {
1386 struct drm_plane_state *state = plane->state;
1387 struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1388 struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1389
1390 trace_dpu_plane_disable(DRMID(plane), false,
1391 pstate->pipe.multirect_mode);
1392
1393 if (r_pipe->sspp) {
1394 r_pipe->multirect_index = DPU_SSPP_RECT_SOLO;
1395 r_pipe->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
1396
1397 if (r_pipe->sspp->ops.setup_multirect)
1398 r_pipe->sspp->ops.setup_multirect(r_pipe);
1399 }
1400
1401 pstate->pending = true;
1402 }
1403
dpu_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)1404 static void dpu_plane_atomic_update(struct drm_plane *plane,
1405 struct drm_atomic_state *state)
1406 {
1407 struct dpu_plane *pdpu = to_dpu_plane(plane);
1408 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
1409 plane);
1410
1411 pdpu->is_error = false;
1412
1413 DPU_DEBUG_PLANE(pdpu, "\n");
1414
1415 if (!new_state->visible) {
1416 _dpu_plane_atomic_disable(plane);
1417 } else {
1418 dpu_plane_sspp_atomic_update(plane, new_state);
1419 }
1420 }
1421
dpu_plane_destroy_state(struct drm_plane * plane,struct drm_plane_state * state)1422 static void dpu_plane_destroy_state(struct drm_plane *plane,
1423 struct drm_plane_state *state)
1424 {
1425 __drm_atomic_helper_plane_destroy_state(state);
1426 kfree(to_dpu_plane_state(state));
1427 }
1428
1429 static struct drm_plane_state *
dpu_plane_duplicate_state(struct drm_plane * plane)1430 dpu_plane_duplicate_state(struct drm_plane *plane)
1431 {
1432 struct dpu_plane *pdpu;
1433 struct dpu_plane_state *pstate;
1434 struct dpu_plane_state *old_state;
1435
1436 if (!plane) {
1437 DPU_ERROR("invalid plane\n");
1438 return NULL;
1439 } else if (!plane->state) {
1440 DPU_ERROR("invalid plane state\n");
1441 return NULL;
1442 }
1443
1444 old_state = to_dpu_plane_state(plane->state);
1445 pdpu = to_dpu_plane(plane);
1446 pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
1447 if (!pstate) {
1448 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1449 return NULL;
1450 }
1451
1452 DPU_DEBUG_PLANE(pdpu, "\n");
1453
1454 pstate->pending = false;
1455
1456 __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
1457
1458 return &pstate->base;
1459 }
1460
1461 static const char * const multirect_mode_name[] = {
1462 [DPU_SSPP_MULTIRECT_NONE] = "none",
1463 [DPU_SSPP_MULTIRECT_PARALLEL] = "parallel",
1464 [DPU_SSPP_MULTIRECT_TIME_MX] = "time_mx",
1465 };
1466
1467 static const char * const multirect_index_name[] = {
1468 [DPU_SSPP_RECT_SOLO] = "solo",
1469 [DPU_SSPP_RECT_0] = "rect_0",
1470 [DPU_SSPP_RECT_1] = "rect_1",
1471 };
1472
dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode)1473 static const char *dpu_get_multirect_mode(enum dpu_sspp_multirect_mode mode)
1474 {
1475 if (WARN_ON(mode >= ARRAY_SIZE(multirect_mode_name)))
1476 return "unknown";
1477
1478 return multirect_mode_name[mode];
1479 }
1480
dpu_get_multirect_index(enum dpu_sspp_multirect_index index)1481 static const char *dpu_get_multirect_index(enum dpu_sspp_multirect_index index)
1482 {
1483 if (WARN_ON(index >= ARRAY_SIZE(multirect_index_name)))
1484 return "unknown";
1485
1486 return multirect_index_name[index];
1487 }
1488
dpu_plane_atomic_print_state(struct drm_printer * p,const struct drm_plane_state * state)1489 static void dpu_plane_atomic_print_state(struct drm_printer *p,
1490 const struct drm_plane_state *state)
1491 {
1492 const struct dpu_plane_state *pstate = to_dpu_plane_state(state);
1493 const struct dpu_sw_pipe *pipe = &pstate->pipe;
1494 const struct dpu_sw_pipe_cfg *pipe_cfg = &pstate->pipe_cfg;
1495 const struct dpu_sw_pipe *r_pipe = &pstate->r_pipe;
1496 const struct dpu_sw_pipe_cfg *r_pipe_cfg = &pstate->r_pipe_cfg;
1497
1498 drm_printf(p, "\tstage=%d\n", pstate->stage);
1499
1500 if (pipe->sspp) {
1501 drm_printf(p, "\tsspp[0]=%s\n", pipe->sspp->cap->name);
1502 drm_printf(p, "\tmultirect_mode[0]=%s\n",
1503 dpu_get_multirect_mode(pipe->multirect_mode));
1504 drm_printf(p, "\tmultirect_index[0]=%s\n",
1505 dpu_get_multirect_index(pipe->multirect_index));
1506 drm_printf(p, "\tsrc[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->src_rect));
1507 drm_printf(p, "\tdst[0]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->dst_rect));
1508 }
1509
1510 if (r_pipe->sspp) {
1511 drm_printf(p, "\tsspp[1]=%s\n", r_pipe->sspp->cap->name);
1512 drm_printf(p, "\tmultirect_mode[1]=%s\n",
1513 dpu_get_multirect_mode(r_pipe->multirect_mode));
1514 drm_printf(p, "\tmultirect_index[1]=%s\n",
1515 dpu_get_multirect_index(r_pipe->multirect_index));
1516 drm_printf(p, "\tsrc[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->src_rect));
1517 drm_printf(p, "\tdst[1]=" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg->dst_rect));
1518 }
1519 }
1520
dpu_plane_reset(struct drm_plane * plane)1521 static void dpu_plane_reset(struct drm_plane *plane)
1522 {
1523 struct dpu_plane *pdpu;
1524 struct dpu_plane_state *pstate;
1525
1526 if (!plane) {
1527 DPU_ERROR("invalid plane\n");
1528 return;
1529 }
1530
1531 pdpu = to_dpu_plane(plane);
1532 DPU_DEBUG_PLANE(pdpu, "\n");
1533
1534 /* remove previous state, if present */
1535 if (plane->state) {
1536 dpu_plane_destroy_state(plane, plane->state);
1537 plane->state = NULL;
1538 }
1539
1540 pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
1541 if (!pstate) {
1542 DPU_ERROR_PLANE(pdpu, "failed to allocate state\n");
1543 return;
1544 }
1545
1546 __drm_atomic_helper_plane_reset(plane, &pstate->base);
1547 }
1548
1549 #ifdef CONFIG_DEBUG_FS
dpu_plane_danger_signal_ctrl(struct drm_plane * plane,bool enable)1550 void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
1551 {
1552 struct dpu_plane *pdpu = to_dpu_plane(plane);
1553 struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
1554 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1555
1556 if (!pdpu->is_rt_pipe)
1557 return;
1558
1559 pm_runtime_get_sync(&dpu_kms->pdev->dev);
1560 _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable);
1561 if (pstate->r_pipe.sspp)
1562 _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable);
1563 pm_runtime_put_sync(&dpu_kms->pdev->dev);
1564 }
1565 #endif
1566
dpu_plane_format_mod_supported(struct drm_plane * plane,uint32_t format,uint64_t modifier)1567 static bool dpu_plane_format_mod_supported(struct drm_plane *plane,
1568 uint32_t format, uint64_t modifier)
1569 {
1570 struct dpu_kms *dpu_kms = _dpu_plane_get_kms(plane);
1571 bool has_no_ubwc = (dpu_kms->mdss->ubwc_enc_version == 0) &&
1572 (dpu_kms->mdss->ubwc_dec_version == 0);
1573
1574 if (modifier == DRM_FORMAT_MOD_LINEAR)
1575 return true;
1576
1577 if (modifier == DRM_FORMAT_MOD_QCOM_COMPRESSED && !has_no_ubwc)
1578 return dpu_find_format(format, qcom_compressed_supported_formats,
1579 ARRAY_SIZE(qcom_compressed_supported_formats));
1580
1581 return false;
1582 }
1583
1584 static const struct drm_plane_funcs dpu_plane_funcs = {
1585 .update_plane = drm_atomic_helper_update_plane,
1586 .disable_plane = drm_atomic_helper_disable_plane,
1587 .reset = dpu_plane_reset,
1588 .atomic_duplicate_state = dpu_plane_duplicate_state,
1589 .atomic_destroy_state = dpu_plane_destroy_state,
1590 .atomic_print_state = dpu_plane_atomic_print_state,
1591 .format_mod_supported = dpu_plane_format_mod_supported,
1592 };
1593
1594 static const struct drm_plane_helper_funcs dpu_plane_helper_funcs = {
1595 .prepare_fb = dpu_plane_prepare_fb,
1596 .cleanup_fb = dpu_plane_cleanup_fb,
1597 .atomic_check = dpu_plane_atomic_check,
1598 .atomic_update = dpu_plane_atomic_update,
1599 };
1600
1601 static const struct drm_plane_helper_funcs dpu_plane_virtual_helper_funcs = {
1602 .prepare_fb = dpu_plane_prepare_fb,
1603 .cleanup_fb = dpu_plane_cleanup_fb,
1604 .atomic_check = dpu_plane_virtual_atomic_check,
1605 .atomic_update = dpu_plane_atomic_update,
1606 };
1607
1608 /* initialize plane */
dpu_plane_init_common(struct drm_device * dev,enum drm_plane_type type,unsigned long possible_crtcs,bool inline_rotation,const uint32_t * format_list,uint32_t num_formats,enum dpu_sspp pipe)1609 static struct drm_plane *dpu_plane_init_common(struct drm_device *dev,
1610 enum drm_plane_type type,
1611 unsigned long possible_crtcs,
1612 bool inline_rotation,
1613 const uint32_t *format_list,
1614 uint32_t num_formats,
1615 enum dpu_sspp pipe)
1616 {
1617 struct drm_plane *plane = NULL;
1618 struct dpu_plane *pdpu;
1619 struct msm_drm_private *priv = dev->dev_private;
1620 struct dpu_kms *kms = to_dpu_kms(priv->kms);
1621 uint32_t supported_rotations;
1622 int ret;
1623
1624 pdpu = drmm_universal_plane_alloc(dev, struct dpu_plane, base,
1625 0xff, &dpu_plane_funcs,
1626 format_list, num_formats,
1627 supported_format_modifiers, type, NULL);
1628 if (IS_ERR(pdpu))
1629 return ERR_CAST(pdpu);
1630
1631 /* cache local stuff for later */
1632 plane = &pdpu->base;
1633 pdpu->pipe = pipe;
1634
1635 pdpu->catalog = kms->catalog;
1636
1637 ret = drm_plane_create_zpos_property(plane, 0, 0, DPU_ZPOS_MAX);
1638 if (ret)
1639 DPU_ERROR("failed to install zpos property, rc = %d\n", ret);
1640
1641 drm_plane_create_alpha_property(plane);
1642 drm_plane_create_blend_mode_property(plane,
1643 BIT(DRM_MODE_BLEND_PIXEL_NONE) |
1644 BIT(DRM_MODE_BLEND_PREMULTI) |
1645 BIT(DRM_MODE_BLEND_COVERAGE));
1646
1647 supported_rotations = DRM_MODE_REFLECT_MASK | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
1648
1649 if (inline_rotation)
1650 supported_rotations |= DRM_MODE_ROTATE_MASK;
1651
1652 drm_plane_create_rotation_property(plane,
1653 DRM_MODE_ROTATE_0, supported_rotations);
1654
1655 drm_plane_enable_fb_damage_clips(plane);
1656
1657 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name,
1658 pipe, plane->base.id);
1659 return plane;
1660 }
1661
1662 /**
1663 * dpu_plane_init - create new dpu plane for the given pipe
1664 * @dev: Pointer to DRM device
1665 * @pipe: dpu hardware pipe identifier
1666 * @type: Plane type - PRIMARY/OVERLAY/CURSOR
1667 * @possible_crtcs: bitmask of crtc that can be attached to the given pipe
1668 *
1669 * Initialize the plane.
1670 */
dpu_plane_init(struct drm_device * dev,uint32_t pipe,enum drm_plane_type type,unsigned long possible_crtcs)1671 struct drm_plane *dpu_plane_init(struct drm_device *dev,
1672 uint32_t pipe, enum drm_plane_type type,
1673 unsigned long possible_crtcs)
1674 {
1675 struct drm_plane *plane = NULL;
1676 struct msm_drm_private *priv = dev->dev_private;
1677 struct dpu_kms *kms = to_dpu_kms(priv->kms);
1678 struct dpu_hw_sspp *pipe_hw;
1679
1680 /* initialize underlying h/w driver */
1681 pipe_hw = dpu_rm_get_sspp(&kms->rm, pipe);
1682 if (!pipe_hw || !pipe_hw->cap || !pipe_hw->cap->sblk) {
1683 DPU_ERROR("[%u]SSPP is invalid\n", pipe);
1684 return ERR_PTR(-EINVAL);
1685 }
1686
1687
1688 plane = dpu_plane_init_common(dev, type, possible_crtcs,
1689 pipe_hw->cap->features & BIT(DPU_SSPP_INLINE_ROTATION),
1690 pipe_hw->cap->sblk->format_list,
1691 pipe_hw->cap->sblk->num_formats,
1692 pipe);
1693 if (IS_ERR(plane))
1694 return plane;
1695
1696 drm_plane_helper_add(plane, &dpu_plane_helper_funcs);
1697
1698 DPU_DEBUG("%s created for pipe:%u id:%u\n", plane->name,
1699 pipe, plane->base.id);
1700
1701 return plane;
1702 }
1703
1704 /**
1705 * dpu_plane_init_virtual - create new virtualized DPU plane
1706 * @dev: Pointer to DRM device
1707 * @type: Plane type - PRIMARY/OVERLAY/CURSOR
1708 * @possible_crtcs: bitmask of crtc that can be attached to the given pipe
1709 *
1710 * Initialize the virtual plane with no backing SSPP / pipe.
1711 */
dpu_plane_init_virtual(struct drm_device * dev,enum drm_plane_type type,unsigned long possible_crtcs)1712 struct drm_plane *dpu_plane_init_virtual(struct drm_device *dev,
1713 enum drm_plane_type type,
1714 unsigned long possible_crtcs)
1715 {
1716 struct drm_plane *plane = NULL;
1717 struct msm_drm_private *priv = dev->dev_private;
1718 struct dpu_kms *kms = to_dpu_kms(priv->kms);
1719 bool has_inline_rotation = false;
1720 const u32 *format_list = NULL;
1721 u32 num_formats = 0;
1722 int i;
1723
1724 /* Determine the largest configuration that we can implement */
1725 for (i = 0; i < kms->catalog->sspp_count; i++) {
1726 const struct dpu_sspp_cfg *cfg = &kms->catalog->sspp[i];
1727
1728 if (test_bit(DPU_SSPP_INLINE_ROTATION, &cfg->features))
1729 has_inline_rotation = true;
1730
1731 if (!format_list ||
1732 cfg->sblk->csc_blk.len) {
1733 format_list = cfg->sblk->format_list;
1734 num_formats = cfg->sblk->num_formats;
1735 }
1736 }
1737
1738 plane = dpu_plane_init_common(dev, type, possible_crtcs,
1739 has_inline_rotation,
1740 format_list,
1741 num_formats,
1742 SSPP_NONE);
1743 if (IS_ERR(plane))
1744 return plane;
1745
1746 drm_plane_helper_add(plane, &dpu_plane_virtual_helper_funcs);
1747
1748 DPU_DEBUG("%s created virtual id:%u\n", plane->name, plane->base.id);
1749
1750 return plane;
1751 }
1752