1 // SPDX-License-Identifier: GPL-2.0-only 2 // ALSA SoC Audio Layer - Rockchip I2S/TDM Controller driver 3 4 // Copyright (c) 2018 Rockchip Electronics Co. Ltd. 5 // Author: Sugar Zhang <sugar.zhang@rock-chips.com> 6 // Author: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 #include <linux/spinlock.h> 18 #include <sound/dmaengine_pcm.h> 19 #include <sound/pcm_params.h> 20 21 #include "rockchip_i2s_tdm.h" 22 23 #define DRV_NAME "rockchip-i2s-tdm" 24 25 #define DEFAULT_MCLK_FS 256 26 #define CH_GRP_MAX 4 /* The max channel 8 / 2 */ 27 #define MULTIPLEX_CH_MAX 10 28 29 #define TRCM_TXRX 0 30 #define TRCM_TX 1 31 #define TRCM_RX 2 32 33 struct txrx_config { 34 u32 addr; 35 u32 reg; 36 u32 txonly; 37 u32 rxonly; 38 }; 39 40 struct rk_i2s_soc_data { 41 u32 softrst_offset; 42 u32 grf_reg_offset; 43 u32 grf_shift; 44 int config_count; 45 const struct txrx_config *configs; 46 int (*init)(struct device *dev, u32 addr); 47 }; 48 49 struct rk_i2s_tdm_dev { 50 struct device *dev; 51 struct clk *hclk; 52 struct clk *mclk_tx; 53 struct clk *mclk_rx; 54 struct regmap *regmap; 55 struct regmap *grf; 56 struct snd_dmaengine_dai_dma_data capture_dma_data; 57 struct snd_dmaengine_dai_dma_data playback_dma_data; 58 struct reset_control *tx_reset; 59 struct reset_control *rx_reset; 60 const struct rk_i2s_soc_data *soc_data; 61 bool is_master_mode; 62 bool io_multiplex; 63 bool tdm_mode; 64 unsigned int frame_width; 65 unsigned int clk_trcm; 66 unsigned int i2s_sdis[CH_GRP_MAX]; 67 unsigned int i2s_sdos[CH_GRP_MAX]; 68 int refcount; 69 spinlock_t lock; /* xfer lock */ 70 bool has_playback; 71 bool has_capture; 72 struct snd_soc_dai_driver *dai; 73 unsigned int mclk_rx_freq; 74 unsigned int mclk_tx_freq; 75 }; 76 77 static int to_ch_num(unsigned int val) 78 { 79 switch (val) { 80 case I2S_CHN_4: 81 return 4; 82 case I2S_CHN_6: 83 return 6; 84 case I2S_CHN_8: 85 return 8; 86 default: 87 return 2; 88 } 89 } 90 91 static void i2s_tdm_disable_unprepare_mclk(struct rk_i2s_tdm_dev *i2s_tdm) 92 { 93 clk_disable_unprepare(i2s_tdm->mclk_tx); 94 clk_disable_unprepare(i2s_tdm->mclk_rx); 95 } 96 97 /** 98 * i2s_tdm_prepare_enable_mclk - prepare to enable all mclks, disable them on 99 * failure. 100 * @i2s_tdm: rk_i2s_tdm_dev struct 101 * 102 * This function attempts to enable all mclk clocks, but cleans up after 103 * itself on failure. Guarantees to balance its calls. 104 * 105 * Returns success (0) or negative errno. 106 */ 107 static int i2s_tdm_prepare_enable_mclk(struct rk_i2s_tdm_dev *i2s_tdm) 108 { 109 int ret = 0; 110 111 ret = clk_prepare_enable(i2s_tdm->mclk_tx); 112 if (ret) 113 goto err_mclk_tx; 114 ret = clk_prepare_enable(i2s_tdm->mclk_rx); 115 if (ret) 116 goto err_mclk_rx; 117 118 return 0; 119 120 err_mclk_rx: 121 clk_disable_unprepare(i2s_tdm->mclk_tx); 122 err_mclk_tx: 123 return ret; 124 } 125 126 static int i2s_tdm_runtime_suspend(struct device *dev) 127 { 128 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 129 130 regcache_cache_only(i2s_tdm->regmap, true); 131 i2s_tdm_disable_unprepare_mclk(i2s_tdm); 132 133 clk_disable_unprepare(i2s_tdm->hclk); 134 135 return 0; 136 } 137 138 static int i2s_tdm_runtime_resume(struct device *dev) 139 { 140 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 141 int ret; 142 143 ret = clk_prepare_enable(i2s_tdm->hclk); 144 if (ret) 145 goto err_hclk; 146 147 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm); 148 if (ret) 149 goto err_mclk; 150 151 regcache_cache_only(i2s_tdm->regmap, false); 152 regcache_mark_dirty(i2s_tdm->regmap); 153 154 ret = regcache_sync(i2s_tdm->regmap); 155 if (ret) 156 goto err_regcache; 157 158 return 0; 159 160 err_regcache: 161 i2s_tdm_disable_unprepare_mclk(i2s_tdm); 162 err_mclk: 163 clk_disable_unprepare(i2s_tdm->hclk); 164 err_hclk: 165 return ret; 166 } 167 168 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai) 169 { 170 return snd_soc_dai_get_drvdata(dai); 171 } 172 173 /* 174 * Makes sure that both tx and rx are reset at the same time to sync lrck 175 * when clk_trcm > 0. 176 */ 177 static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm) 178 { 179 /* This is technically race-y. 180 * 181 * In an ideal world, we could atomically assert both resets at the 182 * same time, through an atomic bulk reset API. This API however does 183 * not exist, so what the downstream vendor code used to do was 184 * implement half a reset controller here and require the CRU to be 185 * passed to the driver as a device tree node. Violating abstractions 186 * like that is bad, especially when it influences something like the 187 * bindings which are supposed to describe the hardware, not whatever 188 * workarounds the driver needs, so it was dropped. 189 * 190 * In practice, asserting the resets one by one appears to work just 191 * fine for playback. During duplex (playback + capture) operation, 192 * this might become an issue, but that should be solved by the 193 * implementation of the aforementioned API, not by shoving a reset 194 * controller into an audio driver. 195 */ 196 197 reset_control_assert(i2s_tdm->tx_reset); 198 reset_control_assert(i2s_tdm->rx_reset); 199 udelay(10); 200 reset_control_deassert(i2s_tdm->tx_reset); 201 reset_control_deassert(i2s_tdm->rx_reset); 202 udelay(10); 203 } 204 205 static void rockchip_snd_reset(struct reset_control *rc) 206 { 207 reset_control_assert(rc); 208 udelay(10); 209 reset_control_deassert(rc); 210 udelay(10); 211 } 212 213 static void rockchip_snd_xfer_clear(struct rk_i2s_tdm_dev *i2s_tdm, 214 unsigned int clr) 215 { 216 unsigned int xfer_mask = 0; 217 unsigned int xfer_val = 0; 218 unsigned int val; 219 int retry = 10; 220 bool tx = clr & I2S_CLR_TXC; 221 bool rx = clr & I2S_CLR_RXC; 222 223 if (!(rx || tx)) 224 return; 225 226 if (tx) { 227 xfer_mask = I2S_XFER_TXS_START; 228 xfer_val = I2S_XFER_TXS_STOP; 229 } 230 if (rx) { 231 xfer_mask |= I2S_XFER_RXS_START; 232 xfer_val |= I2S_XFER_RXS_STOP; 233 } 234 235 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, xfer_mask, xfer_val); 236 udelay(150); 237 regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr); 238 239 regmap_read(i2s_tdm->regmap, I2S_CLR, &val); 240 /* Wait on the clear operation to finish */ 241 while (val) { 242 udelay(15); 243 regmap_read(i2s_tdm->regmap, I2S_CLR, &val); 244 retry--; 245 if (!retry) { 246 dev_warn(i2s_tdm->dev, "clear failed, reset %s%s\n", 247 tx ? "tx" : "", rx ? "rx" : ""); 248 if (rx && tx) 249 rockchip_snd_xfer_sync_reset(i2s_tdm); 250 else if (tx) 251 rockchip_snd_reset(i2s_tdm->tx_reset); 252 else if (rx) 253 rockchip_snd_reset(i2s_tdm->rx_reset); 254 break; 255 } 256 } 257 } 258 259 static inline void rockchip_enable_tde(struct regmap *regmap) 260 { 261 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, 262 I2S_DMACR_TDE_ENABLE); 263 } 264 265 static inline void rockchip_disable_tde(struct regmap *regmap) 266 { 267 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_TDE_ENABLE, 268 I2S_DMACR_TDE_DISABLE); 269 } 270 271 static inline void rockchip_enable_rde(struct regmap *regmap) 272 { 273 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, 274 I2S_DMACR_RDE_ENABLE); 275 } 276 277 static inline void rockchip_disable_rde(struct regmap *regmap) 278 { 279 regmap_update_bits(regmap, I2S_DMACR, I2S_DMACR_RDE_ENABLE, 280 I2S_DMACR_RDE_DISABLE); 281 } 282 283 /* only used when clk_trcm > 0 */ 284 static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream, 285 struct snd_soc_dai *dai, int on) 286 { 287 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 288 289 guard(spinlock_irqsave)(&i2s_tdm->lock); 290 if (on) { 291 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 292 rockchip_enable_tde(i2s_tdm->regmap); 293 else 294 rockchip_enable_rde(i2s_tdm->regmap); 295 296 if (++i2s_tdm->refcount == 1) { 297 rockchip_snd_xfer_sync_reset(i2s_tdm); 298 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 299 I2S_XFER_TXS_START | 300 I2S_XFER_RXS_START, 301 I2S_XFER_TXS_START | 302 I2S_XFER_RXS_START); 303 } 304 } else { 305 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 306 rockchip_disable_tde(i2s_tdm->regmap); 307 else 308 rockchip_disable_rde(i2s_tdm->regmap); 309 310 if (--i2s_tdm->refcount == 0) { 311 rockchip_snd_xfer_clear(i2s_tdm, 312 I2S_CLR_TXC | I2S_CLR_RXC); 313 } 314 } 315 } 316 317 static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on) 318 { 319 if (on) { 320 rockchip_enable_tde(i2s_tdm->regmap); 321 322 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 323 I2S_XFER_TXS_START, 324 I2S_XFER_TXS_START); 325 } else { 326 rockchip_disable_tde(i2s_tdm->regmap); 327 328 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC); 329 } 330 } 331 332 static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on) 333 { 334 if (on) { 335 rockchip_enable_rde(i2s_tdm->regmap); 336 337 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 338 I2S_XFER_RXS_START, 339 I2S_XFER_RXS_START); 340 } else { 341 rockchip_disable_rde(i2s_tdm->regmap); 342 343 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_RXC); 344 } 345 } 346 347 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai, 348 unsigned int fmt) 349 { 350 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai); 351 unsigned int mask, val, tdm_val, txcr_val, rxcr_val; 352 int ret; 353 bool is_tdm = i2s_tdm->tdm_mode; 354 355 ret = pm_runtime_resume_and_get(cpu_dai->dev); 356 if (ret < 0 && ret != -EACCES) 357 return ret; 358 359 mask = I2S_CKR_MSS_MASK; 360 switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 361 case SND_SOC_DAIFMT_BP_FP: 362 val = I2S_CKR_MSS_MASTER; 363 i2s_tdm->is_master_mode = true; 364 break; 365 case SND_SOC_DAIFMT_BC_FC: 366 val = I2S_CKR_MSS_SLAVE; 367 i2s_tdm->is_master_mode = false; 368 break; 369 default: 370 ret = -EINVAL; 371 goto err_pm_put; 372 } 373 374 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val); 375 376 mask = I2S_CKR_CKP_MASK | I2S_CKR_TLP_MASK | I2S_CKR_RLP_MASK; 377 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 378 case SND_SOC_DAIFMT_NB_NF: 379 val = I2S_CKR_CKP_NORMAL | 380 I2S_CKR_TLP_NORMAL | 381 I2S_CKR_RLP_NORMAL; 382 break; 383 case SND_SOC_DAIFMT_NB_IF: 384 val = I2S_CKR_CKP_NORMAL | 385 I2S_CKR_TLP_INVERTED | 386 I2S_CKR_RLP_INVERTED; 387 break; 388 case SND_SOC_DAIFMT_IB_NF: 389 val = I2S_CKR_CKP_INVERTED | 390 I2S_CKR_TLP_NORMAL | 391 I2S_CKR_RLP_NORMAL; 392 break; 393 case SND_SOC_DAIFMT_IB_IF: 394 val = I2S_CKR_CKP_INVERTED | 395 I2S_CKR_TLP_INVERTED | 396 I2S_CKR_RLP_INVERTED; 397 break; 398 default: 399 ret = -EINVAL; 400 goto err_pm_put; 401 } 402 403 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, mask, val); 404 405 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 406 case SND_SOC_DAIFMT_RIGHT_J: 407 txcr_val = I2S_TXCR_IBM_RSJM; 408 rxcr_val = I2S_RXCR_IBM_RSJM; 409 break; 410 case SND_SOC_DAIFMT_LEFT_J: 411 txcr_val = I2S_TXCR_IBM_LSJM; 412 rxcr_val = I2S_RXCR_IBM_LSJM; 413 break; 414 case SND_SOC_DAIFMT_I2S: 415 txcr_val = I2S_TXCR_IBM_NORMAL; 416 rxcr_val = I2S_RXCR_IBM_NORMAL; 417 break; 418 case SND_SOC_DAIFMT_DSP_A: /* PCM delay 1 mode */ 419 txcr_val = I2S_TXCR_TFS_PCM | I2S_TXCR_PBM_MODE(1); 420 rxcr_val = I2S_RXCR_TFS_PCM | I2S_RXCR_PBM_MODE(1); 421 break; 422 case SND_SOC_DAIFMT_DSP_B: /* PCM no delay mode */ 423 txcr_val = I2S_TXCR_TFS_PCM; 424 rxcr_val = I2S_RXCR_TFS_PCM; 425 break; 426 default: 427 ret = -EINVAL; 428 goto err_pm_put; 429 } 430 431 mask = I2S_TXCR_IBM_MASK | I2S_TXCR_TFS_MASK | I2S_TXCR_PBM_MASK; 432 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, txcr_val); 433 434 mask = I2S_RXCR_IBM_MASK | I2S_RXCR_TFS_MASK | I2S_RXCR_PBM_MASK; 435 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, rxcr_val); 436 437 if (is_tdm) { 438 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 439 case SND_SOC_DAIFMT_RIGHT_J: 440 val = I2S_TXCR_TFS_TDM_I2S; 441 tdm_val = TDM_SHIFT_CTRL(2); 442 break; 443 case SND_SOC_DAIFMT_LEFT_J: 444 val = I2S_TXCR_TFS_TDM_I2S; 445 tdm_val = TDM_SHIFT_CTRL(1); 446 break; 447 case SND_SOC_DAIFMT_I2S: 448 val = I2S_TXCR_TFS_TDM_I2S; 449 tdm_val = TDM_SHIFT_CTRL(0); 450 break; 451 case SND_SOC_DAIFMT_DSP_A: 452 val = I2S_TXCR_TFS_TDM_PCM; 453 tdm_val = TDM_SHIFT_CTRL(2); 454 break; 455 case SND_SOC_DAIFMT_DSP_B: 456 val = I2S_TXCR_TFS_TDM_PCM; 457 tdm_val = TDM_SHIFT_CTRL(4); 458 break; 459 default: 460 ret = -EINVAL; 461 goto err_pm_put; 462 } 463 464 tdm_val |= TDM_FSYNC_WIDTH_SEL1(1); 465 tdm_val |= TDM_FSYNC_WIDTH_HALF_FRAME; 466 467 mask = I2S_TXCR_TFS_MASK; 468 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, mask, val); 469 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, mask, val); 470 471 mask = TDM_FSYNC_WIDTH_SEL1_MSK | TDM_FSYNC_WIDTH_SEL0_MSK | 472 TDM_SHIFT_CTRL_MSK; 473 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR, 474 mask, tdm_val); 475 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR, 476 mask, tdm_val); 477 } 478 479 err_pm_put: 480 pm_runtime_put(cpu_dai->dev); 481 482 return ret; 483 } 484 485 static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream, 486 struct rk_i2s_tdm_dev *i2s_tdm) 487 { 488 int stream; 489 490 stream = SNDRV_PCM_STREAM_LAST - substream->stream; 491 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 492 rockchip_disable_tde(i2s_tdm->regmap); 493 else 494 rockchip_disable_rde(i2s_tdm->regmap); 495 496 rockchip_snd_xfer_clear(i2s_tdm, I2S_CLR_TXC | I2S_CLR_RXC); 497 } 498 499 static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream, 500 struct rk_i2s_tdm_dev *i2s_tdm) 501 { 502 int stream; 503 504 stream = SNDRV_PCM_STREAM_LAST - substream->stream; 505 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 506 rockchip_enable_tde(i2s_tdm->regmap); 507 else 508 rockchip_enable_rde(i2s_tdm->regmap); 509 510 regmap_update_bits(i2s_tdm->regmap, I2S_XFER, 511 I2S_XFER_TXS_START | 512 I2S_XFER_RXS_START, 513 I2S_XFER_TXS_START | 514 I2S_XFER_RXS_START); 515 } 516 517 static int rockchip_i2s_io_multiplex(struct snd_pcm_substream *substream, 518 struct snd_soc_dai *dai) 519 { 520 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 521 int usable_chs = MULTIPLEX_CH_MAX; 522 unsigned int val = 0; 523 524 if (!i2s_tdm->io_multiplex) 525 return 0; 526 527 if (IS_ERR_OR_NULL(i2s_tdm->grf)) { 528 dev_err(i2s_tdm->dev, 529 "io multiplex not supported for this device\n"); 530 return -EINVAL; 531 } 532 533 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 534 struct snd_pcm_str *playback_str = 535 &substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK]; 536 537 if (playback_str->substream_opened) { 538 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val); 539 val &= I2S_TXCR_CSR_MASK; 540 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val); 541 } 542 543 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val); 544 val &= I2S_RXCR_CSR_MASK; 545 546 if (to_ch_num(val) > usable_chs) { 547 dev_err(i2s_tdm->dev, 548 "Capture channels (%d) > usable channels (%d)\n", 549 to_ch_num(val), usable_chs); 550 return -EINVAL; 551 } 552 553 } else { 554 struct snd_pcm_str *capture_str = 555 &substream->pcm->streams[SNDRV_PCM_STREAM_CAPTURE]; 556 557 if (capture_str->substream_opened) { 558 regmap_read(i2s_tdm->regmap, I2S_RXCR, &val); 559 val &= I2S_RXCR_CSR_MASK; 560 usable_chs = MULTIPLEX_CH_MAX - to_ch_num(val); 561 } 562 563 regmap_read(i2s_tdm->regmap, I2S_TXCR, &val); 564 val &= I2S_TXCR_CSR_MASK; 565 566 if (to_ch_num(val) > usable_chs) { 567 dev_err(i2s_tdm->dev, 568 "Playback channels (%d) > usable channels (%d)\n", 569 to_ch_num(val), usable_chs); 570 return -EINVAL; 571 } 572 } 573 574 val <<= i2s_tdm->soc_data->grf_shift; 575 val |= (I2S_IO_DIRECTION_MASK << i2s_tdm->soc_data->grf_shift) << 16; 576 regmap_write(i2s_tdm->grf, i2s_tdm->soc_data->grf_reg_offset, val); 577 578 return 0; 579 } 580 581 static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream, 582 struct snd_soc_dai *dai, 583 unsigned int div_bclk, 584 unsigned int div_lrck, 585 unsigned int fmt) 586 { 587 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 588 589 if (!i2s_tdm->clk_trcm) 590 return 0; 591 592 guard(spinlock_irqsave)(&i2s_tdm->lock); 593 if (i2s_tdm->refcount) 594 rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm); 595 596 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV, 597 I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK, 598 I2S_CLKDIV_TXM(div_bclk) | I2S_CLKDIV_RXM(div_bclk)); 599 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, 600 I2S_CKR_TSD_MASK | I2S_CKR_RSD_MASK, 601 I2S_CKR_TSD(div_lrck) | I2S_CKR_RSD(div_lrck)); 602 603 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 604 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, 605 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 606 fmt); 607 else 608 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, 609 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 610 fmt); 611 612 if (i2s_tdm->refcount) 613 rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm); 614 615 return 0; 616 } 617 618 static int rockchip_i2s_tdm_set_sysclk(struct snd_soc_dai *cpu_dai, int stream, 619 unsigned int freq, int dir) 620 { 621 struct rk_i2s_tdm_dev *i2s_tdm = to_info(cpu_dai); 622 623 if (i2s_tdm->clk_trcm) { 624 i2s_tdm->mclk_tx_freq = freq; 625 i2s_tdm->mclk_rx_freq = freq; 626 } else { 627 if (stream == SNDRV_PCM_STREAM_PLAYBACK) 628 i2s_tdm->mclk_tx_freq = freq; 629 else 630 i2s_tdm->mclk_rx_freq = freq; 631 } 632 633 dev_dbg(i2s_tdm->dev, "The target mclk_%s freq is: %d\n", 634 stream ? "rx" : "tx", freq); 635 636 return 0; 637 } 638 639 static int rockchip_i2s_tdm_hw_params(struct snd_pcm_substream *substream, 640 struct snd_pcm_hw_params *params, 641 struct snd_soc_dai *dai) 642 { 643 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 644 unsigned int val = 0; 645 unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64; 646 int err; 647 648 if (i2s_tdm->is_master_mode) { 649 struct clk *mclk; 650 651 if (i2s_tdm->clk_trcm == TRCM_TX) { 652 mclk = i2s_tdm->mclk_tx; 653 mclk_rate = i2s_tdm->mclk_tx_freq; 654 } else if (i2s_tdm->clk_trcm == TRCM_RX) { 655 mclk = i2s_tdm->mclk_rx; 656 mclk_rate = i2s_tdm->mclk_rx_freq; 657 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 658 mclk = i2s_tdm->mclk_tx; 659 mclk_rate = i2s_tdm->mclk_tx_freq; 660 } else { 661 mclk = i2s_tdm->mclk_rx; 662 mclk_rate = i2s_tdm->mclk_rx_freq; 663 } 664 665 /* 666 * When the dai/component driver doesn't need to set mclk-fs for a specific 667 * clock, it can skip the call to set_sysclk() for that clock. 668 * In that case, simply use the clock rate from the params and multiply it by 669 * the default mclk-fs value. 670 */ 671 if (!mclk_rate) 672 mclk_rate = DEFAULT_MCLK_FS * params_rate(params); 673 674 err = clk_set_rate(mclk, mclk_rate); 675 if (err) 676 return err; 677 678 mclk_rate = clk_get_rate(mclk); 679 bclk_rate = i2s_tdm->frame_width * params_rate(params); 680 if (!bclk_rate) 681 return -EINVAL; 682 683 div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate); 684 div_lrck = bclk_rate / params_rate(params); 685 } 686 687 switch (params_format(params)) { 688 case SNDRV_PCM_FORMAT_S8: 689 val |= I2S_TXCR_VDW(8); 690 break; 691 case SNDRV_PCM_FORMAT_S16_LE: 692 val |= I2S_TXCR_VDW(16); 693 break; 694 case SNDRV_PCM_FORMAT_S20_3LE: 695 val |= I2S_TXCR_VDW(20); 696 break; 697 case SNDRV_PCM_FORMAT_S24_LE: 698 val |= I2S_TXCR_VDW(24); 699 break; 700 case SNDRV_PCM_FORMAT_S32_LE: 701 val |= I2S_TXCR_VDW(32); 702 break; 703 default: 704 return -EINVAL; 705 } 706 707 switch (params_channels(params)) { 708 case 8: 709 val |= I2S_CHN_8; 710 break; 711 case 6: 712 val |= I2S_CHN_6; 713 break; 714 case 4: 715 val |= I2S_CHN_4; 716 break; 717 case 2: 718 val |= I2S_CHN_2; 719 break; 720 default: 721 return -EINVAL; 722 } 723 724 if (i2s_tdm->clk_trcm) { 725 rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val); 726 } else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { 727 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV, 728 I2S_CLKDIV_TXM_MASK, 729 I2S_CLKDIV_TXM(div_bclk)); 730 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, 731 I2S_CKR_TSD_MASK, 732 I2S_CKR_TSD(div_lrck)); 733 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, 734 I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK, 735 val); 736 } else { 737 regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV, 738 I2S_CLKDIV_RXM_MASK, 739 I2S_CLKDIV_RXM(div_bclk)); 740 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, 741 I2S_CKR_RSD_MASK, 742 I2S_CKR_RSD(div_lrck)); 743 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, 744 I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK, 745 val); 746 } 747 748 return rockchip_i2s_io_multiplex(substream, dai); 749 } 750 751 static int rockchip_i2s_tdm_trigger(struct snd_pcm_substream *substream, 752 int cmd, struct snd_soc_dai *dai) 753 { 754 struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai); 755 756 switch (cmd) { 757 case SNDRV_PCM_TRIGGER_START: 758 case SNDRV_PCM_TRIGGER_RESUME: 759 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 760 if (i2s_tdm->clk_trcm) 761 rockchip_snd_txrxctrl(substream, dai, 1); 762 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 763 rockchip_snd_rxctrl(i2s_tdm, 1); 764 else 765 rockchip_snd_txctrl(i2s_tdm, 1); 766 break; 767 case SNDRV_PCM_TRIGGER_SUSPEND: 768 case SNDRV_PCM_TRIGGER_STOP: 769 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 770 if (i2s_tdm->clk_trcm) 771 rockchip_snd_txrxctrl(substream, dai, 0); 772 else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) 773 rockchip_snd_rxctrl(i2s_tdm, 0); 774 else 775 rockchip_snd_txctrl(i2s_tdm, 0); 776 break; 777 default: 778 return -EINVAL; 779 } 780 781 return 0; 782 } 783 784 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai) 785 { 786 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); 787 788 if (i2s_tdm->has_capture) 789 snd_soc_dai_dma_data_set_capture(dai, &i2s_tdm->capture_dma_data); 790 if (i2s_tdm->has_playback) 791 snd_soc_dai_dma_data_set_playback(dai, &i2s_tdm->playback_dma_data); 792 793 return 0; 794 } 795 796 static int rockchip_dai_tdm_slot(struct snd_soc_dai *dai, 797 unsigned int tx_mask, unsigned int rx_mask, 798 int slots, int slot_width) 799 { 800 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); 801 unsigned int mask, val; 802 803 i2s_tdm->tdm_mode = true; 804 i2s_tdm->frame_width = slots * slot_width; 805 mask = TDM_SLOT_BIT_WIDTH_MSK | TDM_FRAME_WIDTH_MSK; 806 val = TDM_SLOT_BIT_WIDTH(slot_width) | 807 TDM_FRAME_WIDTH(slots * slot_width); 808 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_TXCR, 809 mask, val); 810 regmap_update_bits(i2s_tdm->regmap, I2S_TDM_RXCR, 811 mask, val); 812 813 return 0; 814 } 815 816 static int rockchip_i2s_tdm_set_bclk_ratio(struct snd_soc_dai *dai, 817 unsigned int ratio) 818 { 819 struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai); 820 821 if (ratio < 32 || ratio > 512 || ratio % 2 == 1) 822 return -EINVAL; 823 824 i2s_tdm->frame_width = ratio; 825 826 return 0; 827 } 828 829 static const u64 rockchip_dai_selectable_formats = 830 SND_SOC_POSSIBLE_DAIFMT_I2S | 831 SND_SOC_POSSIBLE_DAIFMT_RIGHT_J | 832 SND_SOC_POSSIBLE_DAIFMT_LEFT_J | 833 SND_SOC_POSSIBLE_DAIFMT_DSP_A | 834 SND_SOC_POSSIBLE_DAIFMT_DSP_B | 835 SND_SOC_POSSIBLE_DAIFMT_NB_NF | 836 SND_SOC_POSSIBLE_DAIFMT_NB_IF | 837 SND_SOC_POSSIBLE_DAIFMT_IB_NF | 838 SND_SOC_POSSIBLE_DAIFMT_IB_IF; 839 840 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = { 841 .probe = rockchip_i2s_tdm_dai_probe, 842 .hw_params = rockchip_i2s_tdm_hw_params, 843 .set_bclk_ratio = rockchip_i2s_tdm_set_bclk_ratio, 844 .set_fmt = rockchip_i2s_tdm_set_fmt, 845 .set_sysclk = rockchip_i2s_tdm_set_sysclk, 846 .set_tdm_slot = rockchip_dai_tdm_slot, 847 .trigger = rockchip_i2s_tdm_trigger, 848 .auto_selectable_formats = &rockchip_dai_selectable_formats, 849 .num_auto_selectable_formats = 1, 850 }; 851 852 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = { 853 .name = DRV_NAME, 854 .legacy_dai_naming = 1, 855 }; 856 857 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg) 858 { 859 switch (reg) { 860 case I2S_TXCR: 861 case I2S_RXCR: 862 case I2S_CKR: 863 case I2S_DMACR: 864 case I2S_INTCR: 865 case I2S_XFER: 866 case I2S_CLR: 867 case I2S_TXDR: 868 case I2S_TDM_TXCR: 869 case I2S_TDM_RXCR: 870 case I2S_CLKDIV: 871 return true; 872 default: 873 return false; 874 } 875 } 876 877 static bool rockchip_i2s_tdm_rd_reg(struct device *dev, unsigned int reg) 878 { 879 switch (reg) { 880 case I2S_TXCR: 881 case I2S_RXCR: 882 case I2S_CKR: 883 case I2S_DMACR: 884 case I2S_INTCR: 885 case I2S_XFER: 886 case I2S_CLR: 887 case I2S_TXDR: 888 case I2S_RXDR: 889 case I2S_TXFIFOLR: 890 case I2S_INTSR: 891 case I2S_RXFIFOLR: 892 case I2S_TDM_TXCR: 893 case I2S_TDM_RXCR: 894 case I2S_CLKDIV: 895 return true; 896 default: 897 return false; 898 } 899 } 900 901 static bool rockchip_i2s_tdm_volatile_reg(struct device *dev, unsigned int reg) 902 { 903 switch (reg) { 904 case I2S_TXFIFOLR: 905 case I2S_INTSR: 906 case I2S_CLR: 907 case I2S_TXDR: 908 case I2S_RXDR: 909 case I2S_RXFIFOLR: 910 return true; 911 default: 912 return false; 913 } 914 } 915 916 static bool rockchip_i2s_tdm_precious_reg(struct device *dev, unsigned int reg) 917 { 918 if (reg == I2S_RXDR) 919 return true; 920 return false; 921 } 922 923 static const struct reg_default rockchip_i2s_tdm_reg_defaults[] = { 924 {0x00, 0x7200000f}, 925 {0x04, 0x01c8000f}, 926 {0x08, 0x00001f1f}, 927 {0x10, 0x001f0000}, 928 {0x14, 0x01f00000}, 929 {0x30, 0x00003eff}, 930 {0x34, 0x00003eff}, 931 {0x38, 0x00000707}, 932 }; 933 934 static const struct regmap_config rockchip_i2s_tdm_regmap_config = { 935 .reg_bits = 32, 936 .reg_stride = 4, 937 .val_bits = 32, 938 .max_register = I2S_CLKDIV, 939 .reg_defaults = rockchip_i2s_tdm_reg_defaults, 940 .num_reg_defaults = ARRAY_SIZE(rockchip_i2s_tdm_reg_defaults), 941 .writeable_reg = rockchip_i2s_tdm_wr_reg, 942 .readable_reg = rockchip_i2s_tdm_rd_reg, 943 .volatile_reg = rockchip_i2s_tdm_volatile_reg, 944 .precious_reg = rockchip_i2s_tdm_precious_reg, 945 .cache_type = REGCACHE_FLAT, 946 }; 947 948 static int common_soc_init(struct device *dev, u32 addr) 949 { 950 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 951 const struct txrx_config *configs = i2s_tdm->soc_data->configs; 952 u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm; 953 int i; 954 955 if (trcm == TRCM_TXRX) 956 return 0; 957 958 if (IS_ERR_OR_NULL(i2s_tdm->grf)) { 959 dev_err(i2s_tdm->dev, 960 "no grf present but non-txrx TRCM specified\n"); 961 return -EINVAL; 962 } 963 964 for (i = 0; i < i2s_tdm->soc_data->config_count; i++) { 965 if (addr != configs[i].addr) 966 continue; 967 reg = configs[i].reg; 968 if (trcm == TRCM_TX) 969 val = configs[i].txonly; 970 else 971 val = configs[i].rxonly; 972 973 if (reg) 974 regmap_write(i2s_tdm->grf, reg, val); 975 } 976 977 return 0; 978 } 979 980 static const struct txrx_config px30_txrx_config[] = { 981 { 0xff060000, 0x184, PX30_I2S0_CLK_TXONLY, PX30_I2S0_CLK_RXONLY }, 982 }; 983 984 static const struct txrx_config rk1808_txrx_config[] = { 985 { 0xff7e0000, 0x190, RK1808_I2S0_CLK_TXONLY, RK1808_I2S0_CLK_RXONLY }, 986 }; 987 988 static const struct txrx_config rk3308_txrx_config[] = { 989 { 0xff300000, 0x308, RK3308_I2S0_CLK_TXONLY, RK3308_I2S0_CLK_RXONLY }, 990 { 0xff310000, 0x308, RK3308_I2S1_CLK_TXONLY, RK3308_I2S1_CLK_RXONLY }, 991 }; 992 993 static const struct txrx_config rk3568_txrx_config[] = { 994 { 0xfe410000, 0x504, RK3568_I2S1_CLK_TXONLY, RK3568_I2S1_CLK_RXONLY }, 995 { 0xfe410000, 0x508, RK3568_I2S1_MCLK_TX_OE, RK3568_I2S1_MCLK_RX_OE }, 996 { 0xfe420000, 0x508, RK3568_I2S2_MCLK_OE, RK3568_I2S2_MCLK_OE }, 997 { 0xfe430000, 0x504, RK3568_I2S3_CLK_TXONLY, RK3568_I2S3_CLK_RXONLY }, 998 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_TXONLY, RK3568_I2S3_MCLK_RXONLY }, 999 { 0xfe430000, 0x508, RK3568_I2S3_MCLK_OE, RK3568_I2S3_MCLK_OE }, 1000 }; 1001 1002 static const struct txrx_config rv1126_txrx_config[] = { 1003 { 0xff800000, 0x10260, RV1126_I2S0_CLK_TXONLY, RV1126_I2S0_CLK_RXONLY }, 1004 }; 1005 1006 static const struct rk_i2s_soc_data px30_i2s_soc_data = { 1007 .softrst_offset = 0x0300, 1008 .configs = px30_txrx_config, 1009 .config_count = ARRAY_SIZE(px30_txrx_config), 1010 .init = common_soc_init, 1011 }; 1012 1013 static const struct rk_i2s_soc_data rk1808_i2s_soc_data = { 1014 .softrst_offset = 0x0300, 1015 .configs = rk1808_txrx_config, 1016 .config_count = ARRAY_SIZE(rk1808_txrx_config), 1017 .init = common_soc_init, 1018 }; 1019 1020 static const struct rk_i2s_soc_data rk3308_i2s_soc_data = { 1021 .softrst_offset = 0x0400, 1022 .grf_reg_offset = 0x0308, 1023 .grf_shift = 5, 1024 .configs = rk3308_txrx_config, 1025 .config_count = ARRAY_SIZE(rk3308_txrx_config), 1026 .init = common_soc_init, 1027 }; 1028 1029 static const struct rk_i2s_soc_data rk3568_i2s_soc_data = { 1030 .softrst_offset = 0x0400, 1031 .configs = rk3568_txrx_config, 1032 .config_count = ARRAY_SIZE(rk3568_txrx_config), 1033 .init = common_soc_init, 1034 }; 1035 1036 static const struct rk_i2s_soc_data rv1126_i2s_soc_data = { 1037 .softrst_offset = 0x0300, 1038 .configs = rv1126_txrx_config, 1039 .config_count = ARRAY_SIZE(rv1126_txrx_config), 1040 .init = common_soc_init, 1041 }; 1042 1043 static const struct of_device_id rockchip_i2s_tdm_match[] = { 1044 { .compatible = "rockchip,px30-i2s-tdm", .data = &px30_i2s_soc_data }, 1045 { .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data }, 1046 { .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data }, 1047 { .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data }, 1048 { .compatible = "rockchip,rk3588-i2s-tdm" }, 1049 { .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data }, 1050 {}, 1051 }; 1052 MODULE_DEVICE_TABLE(of, rockchip_i2s_tdm_match); 1053 1054 static const struct snd_soc_dai_driver i2s_tdm_dai = { 1055 .ops = &rockchip_i2s_tdm_dai_ops, 1056 }; 1057 1058 static int rockchip_i2s_tdm_init_dai(struct rk_i2s_tdm_dev *i2s_tdm) 1059 { 1060 struct snd_soc_dai_driver *dai; 1061 struct property *dma_names; 1062 const char *dma_name; 1063 u64 formats = (SNDRV_PCM_FMTBIT_S8 | SNDRV_PCM_FMTBIT_S16_LE | 1064 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_LE | 1065 SNDRV_PCM_FMTBIT_S32_LE); 1066 struct device_node *node = i2s_tdm->dev->of_node; 1067 1068 of_property_for_each_string(node, "dma-names", dma_names, dma_name) { 1069 if (!strcmp(dma_name, "tx")) 1070 i2s_tdm->has_playback = true; 1071 if (!strcmp(dma_name, "rx")) 1072 i2s_tdm->has_capture = true; 1073 } 1074 1075 dai = devm_kmemdup(i2s_tdm->dev, &i2s_tdm_dai, 1076 sizeof(*dai), GFP_KERNEL); 1077 if (!dai) 1078 return -ENOMEM; 1079 1080 if (i2s_tdm->has_playback) { 1081 dai->playback.stream_name = "Playback"; 1082 dai->playback.channels_min = 2; 1083 dai->playback.channels_max = 8; 1084 dai->playback.rates = SNDRV_PCM_RATE_8000_192000; 1085 dai->playback.formats = formats; 1086 } 1087 1088 if (i2s_tdm->has_capture) { 1089 dai->capture.stream_name = "Capture"; 1090 dai->capture.channels_min = 2; 1091 dai->capture.channels_max = 8; 1092 dai->capture.rates = SNDRV_PCM_RATE_8000_192000; 1093 dai->capture.formats = formats; 1094 } 1095 1096 if (i2s_tdm->clk_trcm != TRCM_TXRX) 1097 dai->symmetric_rate = 1; 1098 1099 i2s_tdm->dai = dai; 1100 1101 return 0; 1102 } 1103 1104 static int rockchip_i2s_tdm_path_check(struct rk_i2s_tdm_dev *i2s_tdm, 1105 int num, 1106 bool is_rx_path) 1107 { 1108 unsigned int *i2s_data; 1109 int i, j; 1110 1111 if (is_rx_path) 1112 i2s_data = i2s_tdm->i2s_sdis; 1113 else 1114 i2s_data = i2s_tdm->i2s_sdos; 1115 1116 for (i = 0; i < num; i++) { 1117 if (i2s_data[i] > CH_GRP_MAX - 1) { 1118 dev_err(i2s_tdm->dev, 1119 "%s path i2s_data[%d]: %d is too high, max is: %d\n", 1120 is_rx_path ? "RX" : "TX", 1121 i, i2s_data[i], CH_GRP_MAX); 1122 return -EINVAL; 1123 } 1124 1125 for (j = 0; j < num; j++) { 1126 if (i == j) 1127 continue; 1128 1129 if (i2s_data[i] == i2s_data[j]) { 1130 dev_err(i2s_tdm->dev, 1131 "%s path invalid routed i2s_data: [%d]%d == [%d]%d\n", 1132 is_rx_path ? "RX" : "TX", 1133 i, i2s_data[i], 1134 j, i2s_data[j]); 1135 return -EINVAL; 1136 } 1137 } 1138 } 1139 1140 return 0; 1141 } 1142 1143 static void rockchip_i2s_tdm_tx_path_config(struct rk_i2s_tdm_dev *i2s_tdm, 1144 int num) 1145 { 1146 int idx; 1147 1148 for (idx = 0; idx < num; idx++) { 1149 regmap_update_bits(i2s_tdm->regmap, I2S_TXCR, 1150 I2S_TXCR_PATH_MASK(idx), 1151 I2S_TXCR_PATH(idx, i2s_tdm->i2s_sdos[idx])); 1152 } 1153 } 1154 1155 static void rockchip_i2s_tdm_rx_path_config(struct rk_i2s_tdm_dev *i2s_tdm, 1156 int num) 1157 { 1158 int idx; 1159 1160 for (idx = 0; idx < num; idx++) { 1161 regmap_update_bits(i2s_tdm->regmap, I2S_RXCR, 1162 I2S_RXCR_PATH_MASK(idx), 1163 I2S_RXCR_PATH(idx, i2s_tdm->i2s_sdis[idx])); 1164 } 1165 } 1166 1167 static void rockchip_i2s_tdm_path_config(struct rk_i2s_tdm_dev *i2s_tdm, 1168 int num, bool is_rx_path) 1169 { 1170 if (is_rx_path) 1171 rockchip_i2s_tdm_rx_path_config(i2s_tdm, num); 1172 else 1173 rockchip_i2s_tdm_tx_path_config(i2s_tdm, num); 1174 } 1175 1176 static int rockchip_i2s_tdm_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm, 1177 struct device_node *np, 1178 bool is_rx_path) 1179 { 1180 char *i2s_tx_path_prop = "rockchip,i2s-tx-route"; 1181 char *i2s_rx_path_prop = "rockchip,i2s-rx-route"; 1182 char *i2s_path_prop; 1183 unsigned int *i2s_data; 1184 int num, ret = 0; 1185 1186 if (is_rx_path) { 1187 i2s_path_prop = i2s_rx_path_prop; 1188 i2s_data = i2s_tdm->i2s_sdis; 1189 } else { 1190 i2s_path_prop = i2s_tx_path_prop; 1191 i2s_data = i2s_tdm->i2s_sdos; 1192 } 1193 1194 num = of_count_phandle_with_args(np, i2s_path_prop, NULL); 1195 if (num < 0) { 1196 if (num != -ENOENT) { 1197 dev_err(i2s_tdm->dev, 1198 "Failed to read '%s' num: %d\n", 1199 i2s_path_prop, num); 1200 ret = num; 1201 } 1202 return ret; 1203 } else if (num != CH_GRP_MAX) { 1204 dev_err(i2s_tdm->dev, 1205 "The num: %d should be: %d\n", num, CH_GRP_MAX); 1206 return -EINVAL; 1207 } 1208 1209 ret = of_property_read_u32_array(np, i2s_path_prop, 1210 i2s_data, num); 1211 if (ret < 0) { 1212 dev_err(i2s_tdm->dev, 1213 "Failed to read '%s': %d\n", 1214 i2s_path_prop, ret); 1215 return ret; 1216 } 1217 1218 ret = rockchip_i2s_tdm_path_check(i2s_tdm, num, is_rx_path); 1219 if (ret < 0) { 1220 dev_err(i2s_tdm->dev, 1221 "Failed to check i2s data bus: %d\n", ret); 1222 return ret; 1223 } 1224 1225 rockchip_i2s_tdm_path_config(i2s_tdm, num, is_rx_path); 1226 1227 return 0; 1228 } 1229 1230 static int rockchip_i2s_tdm_tx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm, 1231 struct device_node *np) 1232 { 1233 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 0); 1234 } 1235 1236 static int rockchip_i2s_tdm_rx_path_prepare(struct rk_i2s_tdm_dev *i2s_tdm, 1237 struct device_node *np) 1238 { 1239 return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1); 1240 } 1241 1242 static int rockchip_i2s_tdm_probe(struct platform_device *pdev) 1243 { 1244 struct device_node *node = pdev->dev.of_node; 1245 struct rk_i2s_tdm_dev *i2s_tdm; 1246 struct resource *res; 1247 void __iomem *regs; 1248 int ret; 1249 1250 i2s_tdm = devm_kzalloc(&pdev->dev, sizeof(*i2s_tdm), GFP_KERNEL); 1251 if (!i2s_tdm) 1252 return -ENOMEM; 1253 1254 i2s_tdm->dev = &pdev->dev; 1255 1256 spin_lock_init(&i2s_tdm->lock); 1257 i2s_tdm->soc_data = device_get_match_data(&pdev->dev); 1258 i2s_tdm->frame_width = 64; 1259 1260 i2s_tdm->clk_trcm = TRCM_TXRX; 1261 if (of_property_read_bool(node, "rockchip,trcm-sync-tx-only")) 1262 i2s_tdm->clk_trcm = TRCM_TX; 1263 if (of_property_read_bool(node, "rockchip,trcm-sync-rx-only")) { 1264 if (i2s_tdm->clk_trcm) { 1265 dev_err(i2s_tdm->dev, "invalid trcm-sync configuration\n"); 1266 return -EINVAL; 1267 } 1268 i2s_tdm->clk_trcm = TRCM_RX; 1269 } 1270 1271 ret = rockchip_i2s_tdm_init_dai(i2s_tdm); 1272 if (ret) 1273 return ret; 1274 1275 i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf"); 1276 i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1277 "tx-m"); 1278 if (IS_ERR(i2s_tdm->tx_reset)) { 1279 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->tx_reset), 1280 "Error in tx-m reset control\n"); 1281 } 1282 1283 i2s_tdm->rx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1284 "rx-m"); 1285 if (IS_ERR(i2s_tdm->rx_reset)) { 1286 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->rx_reset), 1287 "Error in rx-m reset control\n"); 1288 } 1289 1290 i2s_tdm->hclk = devm_clk_get(&pdev->dev, "hclk"); 1291 if (IS_ERR(i2s_tdm->hclk)) { 1292 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->hclk), 1293 "Failed to get clock hclk\n"); 1294 } 1295 1296 i2s_tdm->mclk_tx = devm_clk_get(&pdev->dev, "mclk_tx"); 1297 if (IS_ERR(i2s_tdm->mclk_tx)) { 1298 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_tx), 1299 "Failed to get clock mclk_tx\n"); 1300 } 1301 1302 i2s_tdm->mclk_rx = devm_clk_get(&pdev->dev, "mclk_rx"); 1303 if (IS_ERR(i2s_tdm->mclk_rx)) { 1304 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->mclk_rx), 1305 "Failed to get clock mclk_rx\n"); 1306 } 1307 1308 i2s_tdm->io_multiplex = 1309 of_property_read_bool(node, "rockchip,io-multiplex"); 1310 1311 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1312 if (IS_ERR(regs)) { 1313 return dev_err_probe(i2s_tdm->dev, PTR_ERR(regs), 1314 "Failed to get resource IORESOURCE_MEM\n"); 1315 } 1316 1317 i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 1318 &rockchip_i2s_tdm_regmap_config); 1319 if (IS_ERR(i2s_tdm->regmap)) { 1320 return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->regmap), 1321 "Failed to initialise regmap\n"); 1322 } 1323 1324 if (i2s_tdm->has_playback) { 1325 i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR; 1326 i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1327 i2s_tdm->playback_dma_data.maxburst = 8; 1328 } 1329 1330 if (i2s_tdm->has_capture) { 1331 i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR; 1332 i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1333 i2s_tdm->capture_dma_data.maxburst = 8; 1334 } 1335 1336 ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node); 1337 if (ret < 0) { 1338 dev_err(&pdev->dev, "I2S TX path prepare failed: %d\n", ret); 1339 return ret; 1340 } 1341 1342 ret = rockchip_i2s_tdm_rx_path_prepare(i2s_tdm, node); 1343 if (ret < 0) { 1344 dev_err(&pdev->dev, "I2S RX path prepare failed: %d\n", ret); 1345 return ret; 1346 } 1347 1348 dev_set_drvdata(&pdev->dev, i2s_tdm); 1349 1350 ret = clk_prepare_enable(i2s_tdm->hclk); 1351 if (ret) { 1352 return dev_err_probe(i2s_tdm->dev, ret, 1353 "Failed to enable clock hclk\n"); 1354 } 1355 1356 ret = i2s_tdm_prepare_enable_mclk(i2s_tdm); 1357 if (ret) { 1358 dev_err_probe(i2s_tdm->dev, ret, "Failed to enable one or more mclks\n"); 1359 goto err_disable_hclk; 1360 } 1361 1362 pm_runtime_enable(&pdev->dev); 1363 1364 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK, 1365 I2S_DMACR_TDL(16)); 1366 regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK, 1367 I2S_DMACR_RDL(16)); 1368 regmap_update_bits(i2s_tdm->regmap, I2S_CKR, I2S_CKR_TRCM_MASK, 1369 i2s_tdm->clk_trcm << I2S_CKR_TRCM_SHIFT); 1370 1371 if (i2s_tdm->soc_data && i2s_tdm->soc_data->init) 1372 i2s_tdm->soc_data->init(&pdev->dev, res->start); 1373 1374 ret = devm_snd_soc_register_component(&pdev->dev, 1375 &rockchip_i2s_tdm_component, 1376 i2s_tdm->dai, 1); 1377 if (ret) 1378 goto err_suspend; 1379 1380 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); 1381 if (ret) 1382 goto err_suspend; 1383 1384 return 0; 1385 1386 err_suspend: 1387 if (!pm_runtime_status_suspended(&pdev->dev)) 1388 i2s_tdm_runtime_suspend(&pdev->dev); 1389 pm_runtime_disable(&pdev->dev); 1390 1391 err_disable_hclk: 1392 clk_disable_unprepare(i2s_tdm->hclk); 1393 1394 return ret; 1395 } 1396 1397 static void rockchip_i2s_tdm_remove(struct platform_device *pdev) 1398 { 1399 if (!pm_runtime_status_suspended(&pdev->dev)) 1400 i2s_tdm_runtime_suspend(&pdev->dev); 1401 1402 pm_runtime_disable(&pdev->dev); 1403 } 1404 1405 static int rockchip_i2s_tdm_suspend(struct device *dev) 1406 { 1407 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 1408 1409 regcache_mark_dirty(i2s_tdm->regmap); 1410 1411 return 0; 1412 } 1413 1414 static int rockchip_i2s_tdm_resume(struct device *dev) 1415 { 1416 struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev); 1417 int ret; 1418 1419 ret = pm_runtime_resume_and_get(dev); 1420 if (ret < 0) 1421 return ret; 1422 ret = regcache_sync(i2s_tdm->regmap); 1423 pm_runtime_put(dev); 1424 1425 return ret; 1426 } 1427 1428 static const struct dev_pm_ops rockchip_i2s_tdm_pm_ops = { 1429 RUNTIME_PM_OPS(i2s_tdm_runtime_suspend, i2s_tdm_runtime_resume, NULL) 1430 SYSTEM_SLEEP_PM_OPS(rockchip_i2s_tdm_suspend, rockchip_i2s_tdm_resume) 1431 }; 1432 1433 static struct platform_driver rockchip_i2s_tdm_driver = { 1434 .probe = rockchip_i2s_tdm_probe, 1435 .remove = rockchip_i2s_tdm_remove, 1436 .driver = { 1437 .name = DRV_NAME, 1438 .of_match_table = rockchip_i2s_tdm_match, 1439 .pm = pm_ptr(&rockchip_i2s_tdm_pm_ops), 1440 }, 1441 }; 1442 module_platform_driver(rockchip_i2s_tdm_driver); 1443 1444 MODULE_DESCRIPTION("ROCKCHIP I2S/TDM ASoC Interface"); 1445 MODULE_AUTHOR("Sugar Zhang <sugar.zhang@rock-chips.com>"); 1446 MODULE_LICENSE("GPL v2"); 1447 MODULE_ALIAS("platform:" DRV_NAME); 1448