1 // SPDX-License-Identifier: (GPL-2.0-only)
2 /*
3 * Analog Devices Inc. AD7625 ADC driver
4 *
5 * Copyright 2024 Analog Devices Inc.
6 * Copyright 2024 BayLibre, SAS
7 *
8 * Note that this driver requires the AXI ADC IP block configured for
9 * LVDS to function. See Documentation/iio/ad7625.rst for more
10 * information.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/device.h>
15 #include <linux/err.h>
16 #include <linux/gpio/consumer.h>
17 #include <linux/iio/backend.h>
18 #include <linux/iio/iio.h>
19 #include <linux/kernel.h>
20 #include <linux/module.h>
21 #include <linux/platform_device.h>
22 #include <linux/pwm.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/units.h>
25
26 #define AD7625_INTERNAL_REF_MV 4096
27 #define AD7960_MAX_NBW_FREQ (2 * MEGA)
28
29 struct ad7625_timing_spec {
30 /* Max conversion high time (t_{CNVH}). */
31 unsigned int conv_high_ns;
32 /* Max conversion to MSB delay (t_{MSB}). */
33 unsigned int conv_msb_ns;
34 };
35
36 struct ad7625_chip_info {
37 const char *name;
38 const unsigned int max_sample_freq_hz;
39 const struct ad7625_timing_spec *timing_spec;
40 const struct iio_chan_spec chan_spec;
41 const bool has_power_down_state;
42 const bool has_bandwidth_control;
43 const bool has_internal_vref;
44 };
45
46 /* AD7625_CHAN_SPEC - Define a chan spec structure for a specific chip */
47 #define AD7625_CHAN_SPEC(_bits) { \
48 .type = IIO_VOLTAGE, \
49 .indexed = 1, \
50 .differential = 1, \
51 .channel = 0, \
52 .channel2 = 1, \
53 .info_mask_separate = BIT(IIO_CHAN_INFO_SCALE), \
54 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
55 .scan_index = 0, \
56 .scan_type.sign = 's', \
57 .scan_type.storagebits = (_bits) > 16 ? 32 : 16, \
58 .scan_type.realbits = (_bits), \
59 }
60
61 struct ad7625_state {
62 const struct ad7625_chip_info *info;
63 struct iio_backend *back;
64 /* rate of the clock gated by the "clk_gate" PWM */
65 u32 ref_clk_rate_hz;
66 /* PWM burst signal for transferring acquired data to the host */
67 struct pwm_device *clk_gate_pwm;
68 /*
69 * PWM control signal for initiating data conversion. Analog
70 * inputs are sampled beginning on this signal's rising edge.
71 */
72 struct pwm_device *cnv_pwm;
73 /*
74 * Waveforms containing the last-requested and rounded
75 * properties for the clk_gate and cnv PWMs
76 */
77 struct pwm_waveform clk_gate_wf;
78 struct pwm_waveform cnv_wf;
79 unsigned int vref_mv;
80 u32 sampling_freq_hz;
81 /*
82 * Optional GPIOs for controlling device state. EN0 and EN1
83 * determine voltage reference configuration and on/off state.
84 * EN2 controls the device -3dB bandwidth (and by extension, max
85 * sample rate). EN3 controls the VCM reference output. EN2 and
86 * EN3 are only present for the AD796x devices.
87 */
88 struct gpio_desc *en_gpios[4];
89 bool can_power_down;
90 bool can_refin;
91 bool can_ref_4v096;
92 /*
93 * Indicate whether the bandwidth can be narrow (9MHz).
94 * When true, device sample rate must also be < 2MSPS.
95 */
96 bool can_narrow_bandwidth;
97 /* Indicate whether the bandwidth can be wide (28MHz). */
98 bool can_wide_bandwidth;
99 bool can_ref_5v;
100 bool can_snooze;
101 bool can_test_pattern;
102 /* Indicate whether there is a REFIN supply connected */
103 bool have_refin;
104 };
105
106 static const struct ad7625_timing_spec ad7625_timing_spec = {
107 .conv_high_ns = 40,
108 .conv_msb_ns = 145,
109 };
110
111 static const struct ad7625_timing_spec ad7626_timing_spec = {
112 .conv_high_ns = 40,
113 .conv_msb_ns = 80,
114 };
115
116 /*
117 * conv_msb_ns is set to 0 instead of the datasheet maximum of 200ns to
118 * avoid exceeding the minimum conversion time, i.e. it is effectively
119 * modulo 200 and offset by a full period. Values greater than or equal
120 * to the period would be rejected by the PWM API.
121 */
122 static const struct ad7625_timing_spec ad7960_timing_spec = {
123 .conv_high_ns = 80,
124 .conv_msb_ns = 0,
125 };
126
127 static const struct ad7625_chip_info ad7625_chip_info = {
128 .name = "ad7625",
129 .max_sample_freq_hz = 6 * MEGA,
130 .timing_spec = &ad7625_timing_spec,
131 .chan_spec = AD7625_CHAN_SPEC(16),
132 .has_power_down_state = false,
133 .has_bandwidth_control = false,
134 .has_internal_vref = true,
135 };
136
137 static const struct ad7625_chip_info ad7626_chip_info = {
138 .name = "ad7626",
139 .max_sample_freq_hz = 10 * MEGA,
140 .timing_spec = &ad7626_timing_spec,
141 .chan_spec = AD7625_CHAN_SPEC(16),
142 .has_power_down_state = true,
143 .has_bandwidth_control = false,
144 .has_internal_vref = true,
145 };
146
147 static const struct ad7625_chip_info ad7960_chip_info = {
148 .name = "ad7960",
149 .max_sample_freq_hz = 5 * MEGA,
150 .timing_spec = &ad7960_timing_spec,
151 .chan_spec = AD7625_CHAN_SPEC(18),
152 .has_power_down_state = true,
153 .has_bandwidth_control = true,
154 .has_internal_vref = false,
155 };
156
157 static const struct ad7625_chip_info ad7961_chip_info = {
158 .name = "ad7961",
159 .max_sample_freq_hz = 5 * MEGA,
160 .timing_spec = &ad7960_timing_spec,
161 .chan_spec = AD7625_CHAN_SPEC(16),
162 .has_power_down_state = true,
163 .has_bandwidth_control = true,
164 .has_internal_vref = false,
165 };
166
167 enum ad7960_mode {
168 AD7960_MODE_POWER_DOWN,
169 AD7960_MODE_SNOOZE,
170 AD7960_MODE_NARROW_BANDWIDTH,
171 AD7960_MODE_WIDE_BANDWIDTH,
172 AD7960_MODE_TEST_PATTERN,
173 };
174
ad7625_set_sampling_freq(struct ad7625_state * st,u32 freq)175 static int ad7625_set_sampling_freq(struct ad7625_state *st, u32 freq)
176 {
177 struct pwm_waveform clk_gate_wf = { }, cnv_wf = { };
178 unsigned long target;
179 int ret;
180
181 target = DIV_ROUND_UP(NSEC_PER_SEC, freq);
182 cnv_wf.period_length_ns = clamp(target, 100UL, 10UL * NSEC_PER_USEC);
183
184 /*
185 * Use the maximum conversion time t_CNVH from the datasheet as
186 * the duty_cycle for ref_clk, cnv, and clk_gate
187 */
188 cnv_wf.duty_length_ns = st->info->timing_spec->conv_high_ns;
189
190 ret = pwm_round_waveform_might_sleep(st->cnv_pwm, &cnv_wf);
191 if (ret)
192 return ret;
193
194 /*
195 * Set up the burst signal for transferring data. period and
196 * offset should mirror the CNV signal
197 */
198 clk_gate_wf.period_length_ns = cnv_wf.period_length_ns;
199
200 clk_gate_wf.duty_length_ns = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC *
201 st->info->chan_spec.scan_type.realbits,
202 st->ref_clk_rate_hz);
203
204 /* max t_MSB from datasheet */
205 clk_gate_wf.duty_offset_ns = st->info->timing_spec->conv_msb_ns;
206
207 ret = pwm_round_waveform_might_sleep(st->clk_gate_pwm, &clk_gate_wf);
208 if (ret)
209 return ret;
210
211 st->cnv_wf = cnv_wf;
212 st->clk_gate_wf = clk_gate_wf;
213
214 /* TODO: Add a rounding API for PWMs that can simplify this */
215 target = DIV_ROUND_CLOSEST(st->ref_clk_rate_hz, freq);
216 st->sampling_freq_hz = DIV_ROUND_CLOSEST(st->ref_clk_rate_hz,
217 target);
218
219 return 0;
220 }
221
ad7625_read_raw(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,int * val,int * val2,long info)222 static int ad7625_read_raw(struct iio_dev *indio_dev,
223 const struct iio_chan_spec *chan,
224 int *val, int *val2, long info)
225 {
226 struct ad7625_state *st = iio_priv(indio_dev);
227
228 switch (info) {
229 case IIO_CHAN_INFO_SAMP_FREQ:
230 *val = st->sampling_freq_hz;
231
232 return IIO_VAL_INT;
233
234 case IIO_CHAN_INFO_SCALE:
235 *val = st->vref_mv;
236 *val2 = chan->scan_type.realbits - 1;
237
238 return IIO_VAL_FRACTIONAL_LOG2;
239
240 default:
241 return -EINVAL;
242 }
243 }
244
ad7625_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long info)245 static int ad7625_write_raw(struct iio_dev *indio_dev,
246 struct iio_chan_spec const *chan,
247 int val, int val2, long info)
248 {
249 struct ad7625_state *st = iio_priv(indio_dev);
250 int ret;
251
252 switch (info) {
253 case IIO_CHAN_INFO_SAMP_FREQ:
254 if (!iio_device_claim_direct(indio_dev))
255 return -EBUSY;
256 ret = ad7625_set_sampling_freq(st, val);
257 iio_device_release_direct(indio_dev);
258 return ret;
259 default:
260 return -EINVAL;
261 }
262 }
263
ad7625_parse_mode(struct device * dev,struct ad7625_state * st,int num_gpios)264 static int ad7625_parse_mode(struct device *dev, struct ad7625_state *st,
265 int num_gpios)
266 {
267 bool en_always_on[4], en_always_off[4];
268 bool en_may_be_on[4], en_may_be_off[4];
269 char en_gpio_buf[4];
270 char always_on_buf[18];
271 int i;
272
273 for (i = 0; i < num_gpios; i++) {
274 snprintf(en_gpio_buf, sizeof(en_gpio_buf), "en%d", i);
275 snprintf(always_on_buf, sizeof(always_on_buf),
276 "adi,en%d-always-on", i);
277 /* Set the device to 0b0000 (power-down mode) by default */
278 st->en_gpios[i] = devm_gpiod_get_optional(dev, en_gpio_buf,
279 GPIOD_OUT_LOW);
280 if (IS_ERR(st->en_gpios[i]))
281 return dev_err_probe(dev, PTR_ERR(st->en_gpios[i]),
282 "failed to get EN%d GPIO\n", i);
283
284 en_always_on[i] = device_property_read_bool(dev, always_on_buf);
285 if (st->en_gpios[i] && en_always_on[i])
286 return dev_err_probe(dev, -EINVAL,
287 "cannot have adi,en%d-always-on and en%d-gpios\n", i, i);
288
289 en_may_be_off[i] = !en_always_on[i];
290 en_may_be_on[i] = en_always_on[i] || st->en_gpios[i];
291 en_always_off[i] = !en_always_on[i] && !st->en_gpios[i];
292 }
293
294 /*
295 * Power down is mode 0bXX00, but not all devices have a valid
296 * power down state.
297 */
298 st->can_power_down = en_may_be_off[1] && en_may_be_off[0] &&
299 st->info->has_power_down_state;
300 /*
301 * The REFIN pin can take a 1.2V (AD762x) or 2.048V (AD796x)
302 * external reference when the mode is 0bXX01.
303 */
304 st->can_refin = en_may_be_off[1] && en_may_be_on[0];
305 /* 4.096V can be applied to REF when the EN mode is 0bXX10. */
306 st->can_ref_4v096 = en_may_be_on[1] && en_may_be_off[0];
307
308 /* Avoid AD796x-specific setup if the part is an AD762x */
309 if (num_gpios == 2)
310 return 0;
311
312 /* mode 0b1100 (AD796x) is invalid */
313 if (en_always_on[3] && en_always_on[2] &&
314 en_always_off[1] && en_always_off[0])
315 return dev_err_probe(dev, -EINVAL,
316 "EN GPIOs set to invalid mode 0b1100\n");
317 /*
318 * 5V can be applied to the AD796x REF pin when the EN mode is
319 * the same (0bX001 or 0bX101) as for can_refin, and REFIN is
320 * 0V.
321 */
322 st->can_ref_5v = st->can_refin;
323 /*
324 * Bandwidth (AD796x) is controlled solely by EN2. If it's
325 * specified and not hard-wired, then we can configure it to
326 * change the bandwidth between 28MHz and 9MHz.
327 */
328 st->can_narrow_bandwidth = en_may_be_on[2];
329 /* Wide bandwidth mode is possible if EN2 can be 0. */
330 st->can_wide_bandwidth = en_may_be_off[2];
331 /* Snooze mode (AD796x) is 0bXX11 when REFIN = 0V. */
332 st->can_snooze = en_may_be_on[1] && en_may_be_on[0];
333 /* Test pattern mode (AD796x) is 0b0100. */
334 st->can_test_pattern = en_may_be_off[3] && en_may_be_on[2] &&
335 en_may_be_off[1] && en_may_be_off[0];
336
337 return 0;
338 }
339
340 /* Set EN1 and EN0 based on reference voltage source */
ad7625_set_en_gpios_for_vref(struct ad7625_state * st,bool have_refin,int ref_mv)341 static void ad7625_set_en_gpios_for_vref(struct ad7625_state *st,
342 bool have_refin, int ref_mv)
343 {
344 if (have_refin || ref_mv == 5000) {
345 gpiod_set_value_cansleep(st->en_gpios[1], 0);
346 gpiod_set_value_cansleep(st->en_gpios[0], 1);
347 } else if (ref_mv == 4096) {
348 gpiod_set_value_cansleep(st->en_gpios[1], 1);
349 gpiod_set_value_cansleep(st->en_gpios[0], 0);
350 } else {
351 /*
352 * Unreachable by AD796x, since the driver will error if
353 * neither REF nor REFIN is provided
354 */
355 gpiod_set_value_cansleep(st->en_gpios[1], 1);
356 gpiod_set_value_cansleep(st->en_gpios[0], 1);
357 }
358 }
359
ad7960_set_mode(struct ad7625_state * st,enum ad7960_mode mode,bool have_refin,int ref_mv)360 static int ad7960_set_mode(struct ad7625_state *st, enum ad7960_mode mode,
361 bool have_refin, int ref_mv)
362 {
363 switch (mode) {
364 case AD7960_MODE_POWER_DOWN:
365 if (!st->can_power_down)
366 return -EINVAL;
367
368 gpiod_set_value_cansleep(st->en_gpios[2], 0);
369 gpiod_set_value_cansleep(st->en_gpios[1], 0);
370 gpiod_set_value_cansleep(st->en_gpios[0], 0);
371
372 return 0;
373
374 case AD7960_MODE_SNOOZE:
375 if (!st->can_snooze)
376 return -EINVAL;
377
378 gpiod_set_value_cansleep(st->en_gpios[1], 1);
379 gpiod_set_value_cansleep(st->en_gpios[0], 1);
380
381 return 0;
382
383 case AD7960_MODE_NARROW_BANDWIDTH:
384 if (!st->can_narrow_bandwidth)
385 return -EINVAL;
386
387 gpiod_set_value_cansleep(st->en_gpios[2], 1);
388 ad7625_set_en_gpios_for_vref(st, have_refin, ref_mv);
389
390 return 0;
391
392 case AD7960_MODE_WIDE_BANDWIDTH:
393 if (!st->can_wide_bandwidth)
394 return -EINVAL;
395
396 gpiod_set_value_cansleep(st->en_gpios[2], 0);
397 ad7625_set_en_gpios_for_vref(st, have_refin, ref_mv);
398
399 return 0;
400
401 case AD7960_MODE_TEST_PATTERN:
402 if (!st->can_test_pattern)
403 return -EINVAL;
404
405 gpiod_set_value_cansleep(st->en_gpios[3], 0);
406 gpiod_set_value_cansleep(st->en_gpios[2], 1);
407 gpiod_set_value_cansleep(st->en_gpios[1], 0);
408 gpiod_set_value_cansleep(st->en_gpios[0], 0);
409
410 return 0;
411
412 default:
413 return -EINVAL;
414 }
415 }
416
ad7625_buffer_preenable(struct iio_dev * indio_dev)417 static int ad7625_buffer_preenable(struct iio_dev *indio_dev)
418 {
419 struct ad7625_state *st = iio_priv(indio_dev);
420 int ret;
421
422 ret = pwm_set_waveform_might_sleep(st->cnv_pwm, &st->cnv_wf, false);
423 if (ret)
424 return ret;
425
426 ret = pwm_set_waveform_might_sleep(st->clk_gate_pwm,
427 &st->clk_gate_wf, false);
428 if (ret) {
429 /* Disable cnv PWM if clk_gate setup failed */
430 pwm_disable(st->cnv_pwm);
431 return ret;
432 }
433
434 return 0;
435 }
436
ad7625_buffer_postdisable(struct iio_dev * indio_dev)437 static int ad7625_buffer_postdisable(struct iio_dev *indio_dev)
438 {
439 struct ad7625_state *st = iio_priv(indio_dev);
440
441 pwm_disable(st->clk_gate_pwm);
442 pwm_disable(st->cnv_pwm);
443
444 return 0;
445 }
446
447 static const struct iio_info ad7625_info = {
448 .read_raw = ad7625_read_raw,
449 .write_raw = ad7625_write_raw,
450 };
451
452 static const struct iio_buffer_setup_ops ad7625_buffer_setup_ops = {
453 .preenable = &ad7625_buffer_preenable,
454 .postdisable = &ad7625_buffer_postdisable,
455 };
456
devm_ad7625_pwm_get(struct device * dev,struct ad7625_state * st)457 static int devm_ad7625_pwm_get(struct device *dev,
458 struct ad7625_state *st)
459 {
460 struct clk *ref_clk;
461 u32 ref_clk_rate_hz;
462
463 st->cnv_pwm = devm_pwm_get(dev, "cnv");
464 if (IS_ERR(st->cnv_pwm))
465 return dev_err_probe(dev, PTR_ERR(st->cnv_pwm),
466 "failed to get cnv pwm\n");
467
468 /* Preemptively disable the PWM in case it was enabled at boot */
469 pwm_disable(st->cnv_pwm);
470
471 st->clk_gate_pwm = devm_pwm_get(dev, "clk_gate");
472 if (IS_ERR(st->clk_gate_pwm))
473 return dev_err_probe(dev, PTR_ERR(st->clk_gate_pwm),
474 "failed to get clk_gate pwm\n");
475
476 /* Preemptively disable the PWM in case it was enabled at boot */
477 pwm_disable(st->clk_gate_pwm);
478
479 ref_clk = devm_clk_get_enabled(dev, NULL);
480 if (IS_ERR(ref_clk))
481 return dev_err_probe(dev, PTR_ERR(ref_clk),
482 "failed to get ref_clk\n");
483
484 ref_clk_rate_hz = clk_get_rate(ref_clk);
485 if (!ref_clk_rate_hz)
486 return dev_err_probe(dev, -EINVAL,
487 "failed to get ref_clk rate\n");
488
489 st->ref_clk_rate_hz = ref_clk_rate_hz;
490
491 return 0;
492 }
493
494 /*
495 * There are three required input voltages for each device, plus two
496 * conditionally-optional (depending on part) REF and REFIN voltages
497 * where their validity depends upon the EN pin configuration.
498 *
499 * Power-up info for the device says to bring up vio, then vdd2, then
500 * vdd1, so list them in that order in the regulator_names array.
501 *
502 * The reference voltage source is determined like so:
503 * - internal reference: neither REF or REFIN is connected (invalid for
504 * AD796x)
505 * - internal buffer, external reference: REF not connected, REFIN
506 * connected
507 * - external reference: REF connected, REFIN not connected
508 */
devm_ad7625_regulator_setup(struct device * dev,struct ad7625_state * st)509 static int devm_ad7625_regulator_setup(struct device *dev,
510 struct ad7625_state *st)
511 {
512 static const char * const regulator_names[] = { "vio", "vdd2", "vdd1" };
513 int ret, ref_mv;
514
515 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulator_names),
516 regulator_names);
517 if (ret)
518 return ret;
519
520 ret = devm_regulator_get_enable_read_voltage(dev, "ref");
521 if (ret < 0 && ret != -ENODEV)
522 return dev_err_probe(dev, ret, "failed to get REF voltage\n");
523
524 ref_mv = ret == -ENODEV ? 0 : ret / 1000;
525
526 ret = devm_regulator_get_enable_optional(dev, "refin");
527 if (ret < 0 && ret != -ENODEV)
528 return dev_err_probe(dev, ret, "failed to get REFIN voltage\n");
529
530 st->have_refin = ret != -ENODEV;
531
532 if (st->have_refin && !st->can_refin)
533 return dev_err_probe(dev, -EINVAL,
534 "REFIN provided in unsupported mode\n");
535
536 if (!st->info->has_internal_vref && !st->have_refin && !ref_mv)
537 return dev_err_probe(dev, -EINVAL,
538 "Need either REFIN or REF\n");
539
540 if (st->have_refin && ref_mv)
541 return dev_err_probe(dev, -EINVAL,
542 "cannot have both REFIN and REF supplies\n");
543
544 if (ref_mv == 4096 && !st->can_ref_4v096)
545 return dev_err_probe(dev, -EINVAL,
546 "REF is 4.096V in unsupported mode\n");
547
548 if (ref_mv == 5000 && !st->can_ref_5v)
549 return dev_err_probe(dev, -EINVAL,
550 "REF is 5V in unsupported mode\n");
551
552 st->vref_mv = ref_mv ?: AD7625_INTERNAL_REF_MV;
553
554 return 0;
555 }
556
ad7625_probe(struct platform_device * pdev)557 static int ad7625_probe(struct platform_device *pdev)
558 {
559 struct device *dev = &pdev->dev;
560 struct iio_dev *indio_dev;
561 struct ad7625_state *st;
562 int ret;
563 u32 default_sample_freq;
564
565 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
566 if (!indio_dev)
567 return -ENOMEM;
568
569 st = iio_priv(indio_dev);
570
571 st->info = device_get_match_data(dev);
572 if (!st->info)
573 return dev_err_probe(dev, -EINVAL, "no chip info\n");
574
575 if (device_property_read_bool(dev, "adi,no-dco"))
576 return dev_err_probe(dev, -EINVAL,
577 "self-clocked mode not supported\n");
578
579 if (st->info->has_bandwidth_control)
580 ret = ad7625_parse_mode(dev, st, 4);
581 else
582 ret = ad7625_parse_mode(dev, st, 2);
583
584 if (ret)
585 return ret;
586
587 ret = devm_ad7625_regulator_setup(dev, st);
588 if (ret)
589 return ret;
590
591 /* Set the device mode based on detected EN configuration. */
592 if (!st->info->has_bandwidth_control) {
593 ad7625_set_en_gpios_for_vref(st, st->have_refin, st->vref_mv);
594 } else {
595 /*
596 * If neither sampling mode is available, then report an error,
597 * since the other modes are not useful defaults.
598 */
599 if (st->can_wide_bandwidth) {
600 ret = ad7960_set_mode(st, AD7960_MODE_WIDE_BANDWIDTH,
601 st->have_refin, st->vref_mv);
602 } else if (st->can_narrow_bandwidth) {
603 ret = ad7960_set_mode(st, AD7960_MODE_NARROW_BANDWIDTH,
604 st->have_refin, st->vref_mv);
605 } else {
606 return dev_err_probe(dev, -EINVAL,
607 "couldn't set device to wide or narrow bandwidth modes\n");
608 }
609
610 if (ret)
611 return dev_err_probe(dev, -EINVAL,
612 "failed to set EN pins\n");
613 }
614
615 ret = devm_ad7625_pwm_get(dev, st);
616 if (ret)
617 return ret;
618
619 indio_dev->channels = &st->info->chan_spec;
620 indio_dev->num_channels = 1;
621 indio_dev->name = st->info->name;
622 indio_dev->info = &ad7625_info;
623 indio_dev->setup_ops = &ad7625_buffer_setup_ops;
624
625 st->back = devm_iio_backend_get(dev, NULL);
626 if (IS_ERR(st->back))
627 return dev_err_probe(dev, PTR_ERR(st->back),
628 "failed to get IIO backend\n");
629
630 ret = devm_iio_backend_request_buffer(dev, st->back, indio_dev);
631 if (ret)
632 return ret;
633
634 ret = devm_iio_backend_enable(dev, st->back);
635 if (ret)
636 return ret;
637
638 /*
639 * Set the initial sampling frequency to the maximum, unless the
640 * AD796x device is limited to narrow bandwidth by EN2 == 1, in
641 * which case the sampling frequency should be limited to 2MSPS
642 */
643 default_sample_freq = st->info->max_sample_freq_hz;
644 if (st->info->has_bandwidth_control && !st->can_wide_bandwidth)
645 default_sample_freq = AD7960_MAX_NBW_FREQ;
646
647 ret = ad7625_set_sampling_freq(st, default_sample_freq);
648 if (ret)
649 dev_err_probe(dev, ret,
650 "failed to set valid sampling frequency\n");
651
652 return devm_iio_device_register(dev, indio_dev);
653 }
654
655 static const struct of_device_id ad7625_of_match[] = {
656 { .compatible = "adi,ad7625", .data = &ad7625_chip_info },
657 { .compatible = "adi,ad7626", .data = &ad7626_chip_info },
658 { .compatible = "adi,ad7960", .data = &ad7960_chip_info },
659 { .compatible = "adi,ad7961", .data = &ad7961_chip_info },
660 { }
661 };
662 MODULE_DEVICE_TABLE(of, ad7625_of_match);
663
664 static const struct platform_device_id ad7625_device_ids[] = {
665 { .name = "ad7625", .driver_data = (kernel_ulong_t)&ad7625_chip_info },
666 { .name = "ad7626", .driver_data = (kernel_ulong_t)&ad7626_chip_info },
667 { .name = "ad7960", .driver_data = (kernel_ulong_t)&ad7960_chip_info },
668 { .name = "ad7961", .driver_data = (kernel_ulong_t)&ad7961_chip_info },
669 { }
670 };
671 MODULE_DEVICE_TABLE(platform, ad7625_device_ids);
672
673 static struct platform_driver ad7625_driver = {
674 .probe = ad7625_probe,
675 .driver = {
676 .name = "ad7625",
677 .of_match_table = ad7625_of_match,
678 },
679 .id_table = ad7625_device_ids,
680 };
681 module_platform_driver(ad7625_driver);
682
683 MODULE_AUTHOR("Trevor Gamblin <tgamblin@baylibre.com>");
684 MODULE_DESCRIPTION("Analog Devices AD7625 ADC");
685 MODULE_LICENSE("GPL");
686 MODULE_IMPORT_NS("IIO_BACKEND");
687