1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Probe module for 8250/16550-type PCI serial ports. 4 * 5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 6 * 7 * Copyright (C) 2001 Russell King, All Rights Reserved. 8 */ 9 #undef DEBUG 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/string.h> 13 #include <linux/kernel.h> 14 #include <linux/math.h> 15 #include <linux/slab.h> 16 #include <linux/delay.h> 17 #include <linux/tty.h> 18 #include <linux/serial_reg.h> 19 #include <linux/serial_core.h> 20 #include <linux/8250_pci.h> 21 #include <linux/bitops.h> 22 #include <linux/bitfield.h> 23 24 #include <asm/byteorder.h> 25 #include <asm/io.h> 26 27 #include "8250.h" 28 #include "8250_pcilib.h" 29 30 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B 31 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B 32 #define PCI_DEVICE_ID_OCTPRO 0x0001 33 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108 34 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208 35 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308 36 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408 37 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500 38 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530 39 #define PCI_VENDOR_ID_ADVANTECH 0x13fe 40 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66 41 #define PCI_DEVICE_ID_ADVANTECH_PCI1600 0x1600 42 #define PCI_DEVICE_ID_ADVANTECH_PCI1600_1611 0x1611 43 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620 44 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618 45 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618 46 #define PCI_DEVICE_ID_TITAN_200I 0x8028 47 #define PCI_DEVICE_ID_TITAN_400I 0x8048 48 #define PCI_DEVICE_ID_TITAN_800I 0x8088 49 #define PCI_DEVICE_ID_TITAN_800EH 0xA007 50 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008 51 #define PCI_DEVICE_ID_TITAN_400EH 0xA009 52 #define PCI_DEVICE_ID_TITAN_100E 0xA010 53 #define PCI_DEVICE_ID_TITAN_200E 0xA012 54 #define PCI_DEVICE_ID_TITAN_400E 0xA013 55 #define PCI_DEVICE_ID_TITAN_800E 0xA014 56 #define PCI_DEVICE_ID_TITAN_200EI 0xA016 57 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017 58 #define PCI_DEVICE_ID_TITAN_200V3 0xA306 59 #define PCI_DEVICE_ID_TITAN_400V3 0xA310 60 #define PCI_DEVICE_ID_TITAN_410V3 0xA312 61 #define PCI_DEVICE_ID_TITAN_800V3 0xA314 62 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315 63 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538 64 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6 65 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001 66 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d 67 68 #define PCI_DEVICE_ID_WCHCN_CH352_2S 0x3253 69 #define PCI_DEVICE_ID_WCHCN_CH355_4S 0x7173 70 71 #define PCI_VENDOR_ID_AGESTAR 0x5372 72 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872 73 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a 74 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e 75 76 #define PCI_DEVICE_ID_WCHIC_CH384_4S 0x3470 77 #define PCI_DEVICE_ID_WCHIC_CH384_8S 0x3853 78 79 #define PCI_DEVICE_ID_MOXA_CP102E 0x1024 80 #define PCI_DEVICE_ID_MOXA_CP102EL 0x1025 81 #define PCI_DEVICE_ID_MOXA_CP102N 0x1027 82 #define PCI_DEVICE_ID_MOXA_CP104EL_A 0x1045 83 #define PCI_DEVICE_ID_MOXA_CP104N 0x1046 84 #define PCI_DEVICE_ID_MOXA_CP112N 0x1121 85 #define PCI_DEVICE_ID_MOXA_CP114EL 0x1144 86 #define PCI_DEVICE_ID_MOXA_CP114N 0x1145 87 #define PCI_DEVICE_ID_MOXA_CP116E_A_A 0x1160 88 #define PCI_DEVICE_ID_MOXA_CP116E_A_B 0x1161 89 #define PCI_DEVICE_ID_MOXA_CP118EL_A 0x1182 90 #define PCI_DEVICE_ID_MOXA_CP118E_A_I 0x1183 91 #define PCI_DEVICE_ID_MOXA_CP132EL 0x1322 92 #define PCI_DEVICE_ID_MOXA_CP132N 0x1323 93 #define PCI_DEVICE_ID_MOXA_CP134EL_A 0x1342 94 #define PCI_DEVICE_ID_MOXA_CP134N 0x1343 95 #define PCI_DEVICE_ID_MOXA_CP138E_A 0x1381 96 #define PCI_DEVICE_ID_MOXA_CP168EL_A 0x1683 97 98 #define PCI_DEVICE_ID_ADDIDATA_CPCI7500 0x7003 99 #define PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG 0x7024 100 #define PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG 0x7025 101 #define PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG 0x7026 102 103 #define PCI_VENDOR_ID_SYSTEMBASE 0x14a1 104 105 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */ 106 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584 107 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588 108 109 /* 110 * init function returns: 111 * > 0 - number of ports 112 * = 0 - use board->num_ports 113 * < 0 - error 114 */ 115 struct pci_serial_quirk { 116 u32 vendor; 117 u32 device; 118 u32 subvendor; 119 u32 subdevice; 120 int (*probe)(struct pci_dev *dev); 121 int (*init)(struct pci_dev *dev); 122 int (*setup)(struct serial_private *, 123 const struct pciserial_board *, 124 struct uart_8250_port *, int); 125 void (*exit)(struct pci_dev *dev); 126 }; 127 128 struct f815xxa_data { 129 spinlock_t lock; 130 int idx; 131 }; 132 133 struct serial_private { 134 struct pci_dev *dev; 135 unsigned int nr; 136 struct pci_serial_quirk *quirk; 137 const struct pciserial_board *board; 138 int line[]; 139 }; 140 141 #define PCI_DEVICE_ID_HPE_PCI_SERIAL 0x37e 142 #define PCIE_VENDOR_ID_ASIX 0x125B 143 #define PCIE_DEVICE_ID_AX99100 0x9100 144 145 static const struct pci_device_id pci_use_msi[] = { 146 { PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9900, 147 0xA000, 0x1000) }, 148 { PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9912, 149 0xA000, 0x1000) }, 150 { PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9922, 151 0xA000, 0x1000) }, 152 { PCI_VDEVICE_SUB(ASIX, PCI_DEVICE_ID_ASIX_AX99100, 153 0xA000, 0x1000) }, 154 { PCI_VDEVICE(HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL) }, 155 { PCI_DEVICE_SUB(PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100, 156 0xA000, 0x1000) }, 157 { } 158 }; 159 160 static int pci_default_setup(struct serial_private*, 161 const struct pciserial_board*, struct uart_8250_port *, int); 162 163 static void moan_device(const char *str, struct pci_dev *dev) 164 { 165 pci_err(dev, "%s\n" 166 "Please send the output of lspci -vv, this\n" 167 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n" 168 "manufacturer and name of serial board or\n" 169 "modem board to <linux-serial@vger.kernel.org>.\n", 170 str, dev->vendor, dev->device, 171 dev->subsystem_vendor, dev->subsystem_device); 172 } 173 174 static int 175 setup_port(struct serial_private *priv, struct uart_8250_port *port, 176 u8 bar, unsigned int offset, int regshift) 177 { 178 void __iomem *iomem = NULL; 179 180 if (pci_resource_flags(priv->dev, bar) & IORESOURCE_MEM) { 181 iomem = pcim_iomap(priv->dev, bar, 0); 182 if (!iomem) 183 return -ENOMEM; 184 } 185 186 return serial8250_pci_setup_port(priv->dev, port, bar, offset, regshift, iomem); 187 } 188 189 /* 190 * ADDI-DATA GmbH communication cards <info@addi-data.com> 191 */ 192 static int addidata_apci7800_setup(struct serial_private *priv, 193 const struct pciserial_board *board, 194 struct uart_8250_port *port, int idx) 195 { 196 unsigned int bar = 0, offset = board->first_offset; 197 bar = FL_GET_BASE(board->flags); 198 199 if (idx < 2) { 200 offset += idx * board->uart_offset; 201 } else if ((idx >= 2) && (idx < 4)) { 202 bar += 1; 203 offset += ((idx - 2) * board->uart_offset); 204 } else if ((idx >= 4) && (idx < 6)) { 205 bar += 2; 206 offset += ((idx - 4) * board->uart_offset); 207 } else if (idx >= 6) { 208 bar += 3; 209 offset += ((idx - 6) * board->uart_offset); 210 } 211 212 return setup_port(priv, port, bar, offset, board->reg_shift); 213 } 214 215 /* 216 * AFAVLAB uses a different mixture of BARs and offsets 217 * Not that ugly ;) -- HW 218 */ 219 static int 220 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board, 221 struct uart_8250_port *port, int idx) 222 { 223 unsigned int bar, offset = board->first_offset; 224 225 bar = FL_GET_BASE(board->flags); 226 if (idx < 4) 227 bar += idx; 228 else { 229 bar = 4; 230 offset += (idx - 4) * board->uart_offset; 231 } 232 233 return setup_port(priv, port, bar, offset, board->reg_shift); 234 } 235 236 /* 237 * HP's Remote Management Console. The Diva chip came in several 238 * different versions. N-class, L2000 and A500 have two Diva chips, each 239 * with 3 UARTs (the third UART on the second chip is unused). Superdome 240 * and Keystone have one Diva chip with 3 UARTs. Some later machines have 241 * one Diva chip, but it has been expanded to 5 UARTs. 242 */ 243 static int pci_hp_diva_init(struct pci_dev *dev) 244 { 245 int rc = 0; 246 247 switch (dev->subsystem_device) { 248 case PCI_DEVICE_ID_HP_DIVA_TOSCA1: 249 case PCI_DEVICE_ID_HP_DIVA_HALFDOME: 250 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE: 251 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 252 rc = 3; 253 break; 254 case PCI_DEVICE_ID_HP_DIVA_TOSCA2: 255 rc = 2; 256 break; 257 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 258 rc = 4; 259 break; 260 case PCI_DEVICE_ID_HP_DIVA_POWERBAR: 261 case PCI_DEVICE_ID_HP_DIVA_HURRICANE: 262 rc = 1; 263 break; 264 } 265 266 return rc; 267 } 268 269 /* 270 * HP's Diva chip puts the 4th/5th serial port further out, and 271 * some serial ports are supposed to be hidden on certain models. 272 */ 273 static int 274 pci_hp_diva_setup(struct serial_private *priv, 275 const struct pciserial_board *board, 276 struct uart_8250_port *port, int idx) 277 { 278 unsigned int offset = board->first_offset; 279 unsigned int bar = FL_GET_BASE(board->flags); 280 281 switch (priv->dev->subsystem_device) { 282 case PCI_DEVICE_ID_HP_DIVA_MAESTRO: 283 if (idx == 3) 284 idx++; 285 break; 286 case PCI_DEVICE_ID_HP_DIVA_EVEREST: 287 if (idx > 0) 288 idx++; 289 if (idx > 2) 290 idx++; 291 break; 292 } 293 if (idx > 2) 294 offset = 0x18; 295 296 offset += idx * board->uart_offset; 297 298 return setup_port(priv, port, bar, offset, board->reg_shift); 299 } 300 301 /* 302 * Added for EKF Intel i960 serial boards 303 */ 304 static int pci_inteli960ni_init(struct pci_dev *dev) 305 { 306 u32 oldval; 307 308 if (!(dev->subsystem_device & 0x1000)) 309 return -ENODEV; 310 311 /* is firmware started? */ 312 pci_read_config_dword(dev, 0x44, &oldval); 313 if (oldval == 0x00001000L) { /* RESET value */ 314 pci_dbg(dev, "Local i960 firmware missing\n"); 315 return -ENODEV; 316 } 317 return 0; 318 } 319 320 /* 321 * Some PCI serial cards using the PLX 9050 PCI interface chip require 322 * that the card interrupt be explicitly enabled or disabled. This 323 * seems to be mainly needed on card using the PLX which also use I/O 324 * mapped memory. 325 */ 326 static int pci_plx9050_init(struct pci_dev *dev) 327 { 328 u8 irq_config; 329 void __iomem *p; 330 331 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) { 332 moan_device("no memory in bar 0", dev); 333 return 0; 334 } 335 336 irq_config = 0x41; 337 if (dev->vendor == PCI_VENDOR_ID_PANACOM || 338 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS) 339 irq_config = 0x43; 340 341 if ((dev->vendor == PCI_VENDOR_ID_PLX) && 342 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) 343 /* 344 * As the megawolf cards have the int pins active 345 * high, and have 2 UART chips, both ints must be 346 * enabled on the 9050. Also, the UARTS are set in 347 * 16450 mode by default, so we have to enable the 348 * 16C950 'enhanced' mode so that we can use the 349 * deep FIFOs 350 */ 351 irq_config = 0x5b; 352 /* 353 * enable/disable interrupts 354 */ 355 p = ioremap(pci_resource_start(dev, 0), 0x80); 356 if (p == NULL) 357 return -ENOMEM; 358 writel(irq_config, p + 0x4c); 359 360 /* 361 * Read the register back to ensure that it took effect. 362 */ 363 readl(p + 0x4c); 364 iounmap(p); 365 366 return 0; 367 } 368 369 static void pci_plx9050_exit(struct pci_dev *dev) 370 { 371 u8 __iomem *p; 372 373 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) 374 return; 375 376 /* 377 * disable interrupts 378 */ 379 p = ioremap(pci_resource_start(dev, 0), 0x80); 380 if (p != NULL) { 381 writel(0, p + 0x4c); 382 383 /* 384 * Read the register back to ensure that it took effect. 385 */ 386 readl(p + 0x4c); 387 iounmap(p); 388 } 389 } 390 391 #define NI8420_INT_ENABLE_REG 0x38 392 #define NI8420_INT_ENABLE_BIT 0x2000 393 394 static void pci_ni8420_exit(struct pci_dev *dev) 395 { 396 void __iomem *p; 397 unsigned int bar = 0; 398 399 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 400 moan_device("no memory in bar", dev); 401 return; 402 } 403 404 p = pci_ioremap_bar(dev, bar); 405 if (p == NULL) 406 return; 407 408 /* Disable the CPU Interrupt */ 409 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT), 410 p + NI8420_INT_ENABLE_REG); 411 iounmap(p); 412 } 413 414 415 /* MITE registers */ 416 #define MITE_IOWBSR1 0xc4 417 #define MITE_IOWCR1 0xf4 418 #define MITE_LCIMR1 0x08 419 #define MITE_LCIMR2 0x10 420 421 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30) 422 423 static void pci_ni8430_exit(struct pci_dev *dev) 424 { 425 void __iomem *p; 426 unsigned int bar = 0; 427 428 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 429 moan_device("no memory in bar", dev); 430 return; 431 } 432 433 p = pci_ioremap_bar(dev, bar); 434 if (p == NULL) 435 return; 436 437 /* Disable the CPU Interrupt */ 438 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2); 439 iounmap(p); 440 } 441 442 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */ 443 static int 444 sbs_setup(struct serial_private *priv, const struct pciserial_board *board, 445 struct uart_8250_port *port, int idx) 446 { 447 unsigned int bar, offset = board->first_offset; 448 449 bar = 0; 450 451 if (idx < 4) { 452 /* first four channels map to 0, 0x100, 0x200, 0x300 */ 453 offset += idx * board->uart_offset; 454 } else if (idx < 8) { 455 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */ 456 offset += idx * board->uart_offset + 0xC00; 457 } else /* we have only 8 ports on PMC-OCTALPRO */ 458 return 1; 459 460 return setup_port(priv, port, bar, offset, board->reg_shift); 461 } 462 463 /* 464 * This does initialization for PMC OCTALPRO cards: 465 * maps the device memory, resets the UARTs (needed, bc 466 * if the module is removed and inserted again, the card 467 * is in the sleep mode) and enables global interrupt. 468 */ 469 470 /* global control register offset for SBS PMC-OctalPro */ 471 #define OCT_REG_CR_OFF 0x500 472 473 static int sbs_init(struct pci_dev *dev) 474 { 475 u8 __iomem *p; 476 477 p = pci_ioremap_bar(dev, 0); 478 479 if (p == NULL) 480 return -ENOMEM; 481 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */ 482 writeb(0x10, p + OCT_REG_CR_OFF); 483 udelay(50); 484 writeb(0x0, p + OCT_REG_CR_OFF); 485 486 /* Set bit-2 (INTENABLE) of Control Register */ 487 writeb(0x4, p + OCT_REG_CR_OFF); 488 iounmap(p); 489 490 return 0; 491 } 492 493 /* 494 * Disables the global interrupt of PMC-OctalPro 495 */ 496 497 static void sbs_exit(struct pci_dev *dev) 498 { 499 u8 __iomem *p; 500 501 p = pci_ioremap_bar(dev, 0); 502 /* FIXME: What if resource_len < OCT_REG_CR_OFF */ 503 if (p != NULL) 504 writeb(0, p + OCT_REG_CR_OFF); 505 iounmap(p); 506 } 507 508 /* 509 * SIIG serial cards have an PCI interface chip which also controls 510 * the UART clocking frequency. Each UART can be clocked independently 511 * (except cards equipped with 4 UARTs) and initial clocking settings 512 * are stored in the EEPROM chip. It can cause problems because this 513 * version of serial driver doesn't support differently clocked UART's 514 * on single PCI card. To prevent this, initialization functions set 515 * high frequency clocking for all UART's on given card. It is safe (I 516 * hope) because it doesn't touch EEPROM settings to prevent conflicts 517 * with other OSes (like M$ DOS). 518 * 519 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999 520 * 521 * There is two family of SIIG serial cards with different PCI 522 * interface chip and different configuration methods: 523 * - 10x cards have control registers in IO and/or memory space; 524 * - 20x cards have control registers in standard PCI configuration space. 525 * 526 * Note: all 10x cards have PCI device ids 0x10.. 527 * all 20x cards have PCI device ids 0x20.. 528 * 529 * There are also Quartet Serial cards which use Oxford Semiconductor 530 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz. 531 * 532 * Note: some SIIG cards are probed by the parport_serial object. 533 */ 534 535 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc) 536 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8) 537 538 static int pci_siig10x_init(struct pci_dev *dev) 539 { 540 u16 data; 541 void __iomem *p; 542 543 switch (dev->device & 0xfff8) { 544 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */ 545 data = 0xffdf; 546 break; 547 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */ 548 data = 0xf7ff; 549 break; 550 default: /* 1S1P, 4S */ 551 data = 0xfffb; 552 break; 553 } 554 555 p = ioremap(pci_resource_start(dev, 0), 0x80); 556 if (p == NULL) 557 return -ENOMEM; 558 559 writew(readw(p + 0x28) & data, p + 0x28); 560 readw(p + 0x28); 561 iounmap(p); 562 return 0; 563 } 564 565 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc) 566 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc) 567 568 static int pci_siig20x_init(struct pci_dev *dev) 569 { 570 u8 data; 571 572 /* Change clock frequency for the first UART. */ 573 pci_read_config_byte(dev, 0x6f, &data); 574 pci_write_config_byte(dev, 0x6f, data & 0xef); 575 576 /* If this card has 2 UART, we have to do the same with second UART. */ 577 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) || 578 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) { 579 pci_read_config_byte(dev, 0x73, &data); 580 pci_write_config_byte(dev, 0x73, data & 0xef); 581 } 582 return 0; 583 } 584 585 static int pci_siig_init(struct pci_dev *dev) 586 { 587 unsigned int type = dev->device & 0xff00; 588 589 if (type == 0x1000) 590 return pci_siig10x_init(dev); 591 if (type == 0x2000) 592 return pci_siig20x_init(dev); 593 594 moan_device("Unknown SIIG card", dev); 595 return -ENODEV; 596 } 597 598 static int pci_siig_setup(struct serial_private *priv, 599 const struct pciserial_board *board, 600 struct uart_8250_port *port, int idx) 601 { 602 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0; 603 604 if (idx > 3) { 605 bar = 4; 606 offset = (idx - 4) * 8; 607 } 608 609 return setup_port(priv, port, bar, offset, 0); 610 } 611 612 /* 613 * Timedia has an explosion of boards, and to avoid the PCI table from 614 * growing *huge*, we use this function to collapse some 70 entries 615 * in the PCI table into one, for sanity's and compactness's sake. 616 */ 617 static const unsigned short timedia_single_port[] = { 618 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0 619 }; 620 621 static const unsigned short timedia_dual_port[] = { 622 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 623 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 624 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 625 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 626 0xD079, 0 627 }; 628 629 static const unsigned short timedia_quad_port[] = { 630 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 631 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 632 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 633 0xB157, 0 634 }; 635 636 static const unsigned short timedia_eight_port[] = { 637 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 638 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 639 }; 640 641 static const struct timedia_struct { 642 int num; 643 const unsigned short *ids; 644 } timedia_data[] = { 645 { 1, timedia_single_port }, 646 { 2, timedia_dual_port }, 647 { 4, timedia_quad_port }, 648 { 8, timedia_eight_port } 649 }; 650 651 /* 652 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of 653 * listing them individually, this driver merely grabs them all with 654 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port, 655 * and should be left free to be claimed by parport_serial instead. 656 */ 657 static int pci_timedia_probe(struct pci_dev *dev) 658 { 659 /* 660 * Check the third digit of the subdevice ID 661 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel) 662 */ 663 if ((dev->subsystem_device & 0x00f0) >= 0x70) { 664 pci_info(dev, "ignoring Timedia subdevice %04x for parport_serial\n", 665 dev->subsystem_device); 666 return -ENODEV; 667 } 668 669 return 0; 670 } 671 672 static int pci_timedia_init(struct pci_dev *dev) 673 { 674 const unsigned short *ids; 675 int i, j; 676 677 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) { 678 ids = timedia_data[i].ids; 679 for (j = 0; ids[j]; j++) 680 if (dev->subsystem_device == ids[j]) 681 return timedia_data[i].num; 682 } 683 return 0; 684 } 685 686 /* 687 * Timedia/SUNIX uses a mixture of BARs and offsets 688 * Ugh, this is ugly as all hell --- TYT 689 */ 690 static int 691 pci_timedia_setup(struct serial_private *priv, 692 const struct pciserial_board *board, 693 struct uart_8250_port *port, int idx) 694 { 695 unsigned int bar = 0, offset = board->first_offset; 696 697 switch (idx) { 698 case 0: 699 bar = 0; 700 break; 701 case 1: 702 offset = board->uart_offset; 703 bar = 0; 704 break; 705 case 2: 706 bar = 1; 707 break; 708 case 3: 709 offset = board->uart_offset; 710 fallthrough; 711 case 4: /* BAR 2 */ 712 case 5: /* BAR 3 */ 713 case 6: /* BAR 4 */ 714 case 7: /* BAR 5 */ 715 bar = idx - 2; 716 } 717 718 return setup_port(priv, port, bar, offset, board->reg_shift); 719 } 720 721 /* 722 * Some Titan cards are also a little weird 723 */ 724 static int 725 titan_400l_800l_setup(struct serial_private *priv, 726 const struct pciserial_board *board, 727 struct uart_8250_port *port, int idx) 728 { 729 unsigned int bar, offset = board->first_offset; 730 731 switch (idx) { 732 case 0: 733 bar = 1; 734 break; 735 case 1: 736 bar = 2; 737 break; 738 default: 739 bar = 4; 740 offset = (idx - 2) * board->uart_offset; 741 } 742 743 return setup_port(priv, port, bar, offset, board->reg_shift); 744 } 745 746 static int pci_xircom_init(struct pci_dev *dev) 747 { 748 msleep(100); 749 return 0; 750 } 751 752 static int pci_ni8420_init(struct pci_dev *dev) 753 { 754 void __iomem *p; 755 unsigned int bar = 0; 756 757 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 758 moan_device("no memory in bar", dev); 759 return 0; 760 } 761 762 p = pci_ioremap_bar(dev, bar); 763 if (p == NULL) 764 return -ENOMEM; 765 766 /* Enable CPU Interrupt */ 767 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT, 768 p + NI8420_INT_ENABLE_REG); 769 770 iounmap(p); 771 return 0; 772 } 773 774 #define MITE_IOWBSR1_WSIZE 0xa 775 #define MITE_IOWBSR1_WIN_OFFSET 0x800 776 #define MITE_IOWBSR1_WENAB (1 << 7) 777 #define MITE_LCIMR1_IO_IE_0 (1 << 24) 778 #define MITE_LCIMR2_SET_CPU_IE (1 << 31) 779 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe 780 781 static int pci_ni8430_init(struct pci_dev *dev) 782 { 783 void __iomem *p; 784 struct pci_bus_region region; 785 u32 device_window; 786 unsigned int bar = 0; 787 788 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) { 789 moan_device("no memory in bar", dev); 790 return 0; 791 } 792 793 p = pci_ioremap_bar(dev, bar); 794 if (p == NULL) 795 return -ENOMEM; 796 797 /* 798 * Set device window address and size in BAR0, while acknowledging that 799 * the resource structure may contain a translated address that differs 800 * from the address the device responds to. 801 */ 802 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]); 803 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00) 804 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE; 805 writel(device_window, p + MITE_IOWBSR1); 806 807 /* Set window access to go to RAMSEL IO address space */ 808 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK), 809 p + MITE_IOWCR1); 810 811 /* Enable IO Bus Interrupt 0 */ 812 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1); 813 814 /* Enable CPU Interrupt */ 815 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2); 816 817 iounmap(p); 818 return 0; 819 } 820 821 /* UART Port Control Register */ 822 #define NI8430_PORTCON 0x0f 823 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3) 824 825 static int 826 pci_ni8430_setup(struct serial_private *priv, 827 const struct pciserial_board *board, 828 struct uart_8250_port *port, int idx) 829 { 830 struct pci_dev *dev = priv->dev; 831 void __iomem *p; 832 unsigned int bar, offset = board->first_offset; 833 834 if (idx >= board->num_ports) 835 return 1; 836 837 bar = FL_GET_BASE(board->flags); 838 offset += idx * board->uart_offset; 839 840 p = pci_ioremap_bar(dev, bar); 841 if (!p) 842 return -ENOMEM; 843 844 /* enable the transceiver */ 845 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE, 846 p + offset + NI8430_PORTCON); 847 848 iounmap(p); 849 850 return setup_port(priv, port, bar, offset, board->reg_shift); 851 } 852 853 static int pci_netmos_9900_setup(struct serial_private *priv, 854 const struct pciserial_board *board, 855 struct uart_8250_port *port, int idx) 856 { 857 unsigned int bar; 858 859 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) && 860 (priv->dev->subsystem_device & 0xff00) == 0x3000) { 861 /* netmos apparently orders BARs by datasheet layout, so serial 862 * ports get BARs 0 and 3 (or 1 and 4 for memmapped) 863 */ 864 bar = 3 * idx; 865 866 return setup_port(priv, port, bar, 0, board->reg_shift); 867 } 868 869 return pci_default_setup(priv, board, port, idx); 870 } 871 872 /* the 99xx series comes with a range of device IDs and a variety 873 * of capabilities: 874 * 875 * 9900 has varying capabilities and can cascade to sub-controllers 876 * (cascading should be purely internal) 877 * 9904 is hardwired with 4 serial ports 878 * 9912 and 9922 are hardwired with 2 serial ports 879 */ 880 static int pci_netmos_9900_numports(struct pci_dev *dev) 881 { 882 unsigned int c = dev->class; 883 unsigned int pi; 884 unsigned short sub_serports; 885 886 pi = c & 0xff; 887 888 if (pi == 2) 889 return 1; 890 891 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) { 892 /* two possibilities: 0x30ps encodes number of parallel and 893 * serial ports, or 0x1000 indicates *something*. This is not 894 * immediately obvious, since the 2s1p+4s configuration seems 895 * to offer all functionality on functions 0..2, while still 896 * advertising the same function 3 as the 4s+2s1p config. 897 */ 898 sub_serports = dev->subsystem_device & 0xf; 899 if (sub_serports > 0) 900 return sub_serports; 901 902 pci_err(dev, "NetMos/Mostech serial driver ignoring port on ambiguous config.\n"); 903 return 0; 904 } 905 906 moan_device("unknown NetMos/Mostech program interface", dev); 907 return 0; 908 } 909 910 static int pci_netmos_init(struct pci_dev *dev) 911 { 912 /* subdevice 0x00PS means <P> parallel, <S> serial */ 913 unsigned int num_serial = dev->subsystem_device & 0xf; 914 915 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) || 916 (dev->device == PCI_DEVICE_ID_NETMOS_9865)) 917 return 0; 918 919 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 920 dev->subsystem_device == 0x0299) 921 return 0; 922 923 switch (dev->device) { /* FALLTHROUGH on all */ 924 case PCI_DEVICE_ID_NETMOS_9904: 925 case PCI_DEVICE_ID_NETMOS_9912: 926 case PCI_DEVICE_ID_NETMOS_9922: 927 case PCI_DEVICE_ID_NETMOS_9900: 928 case PCIE_DEVICE_ID_AX99100: 929 num_serial = pci_netmos_9900_numports(dev); 930 break; 931 932 default: 933 break; 934 } 935 936 if (num_serial == 0) { 937 moan_device("unknown NetMos/Mostech device", dev); 938 return -ENODEV; 939 } 940 941 return num_serial; 942 } 943 944 /* 945 * These chips are available with optionally one parallel port and up to 946 * two serial ports. Unfortunately they all have the same product id. 947 * 948 * Basic configuration is done over a region of 32 I/O ports. The base 949 * ioport is called INTA or INTC, depending on docs/other drivers. 950 * 951 * The region of the 32 I/O ports is configured in POSIO0R... 952 */ 953 954 /* registers */ 955 #define ITE_887x_MISCR 0x9c 956 #define ITE_887x_INTCBAR 0x78 957 #define ITE_887x_UARTBAR 0x7c 958 #define ITE_887x_PS0BAR 0x10 959 #define ITE_887x_POSIO0 0x60 960 961 /* I/O space size */ 962 #define ITE_887x_IOSIZE 32 963 /* I/O space size (bits 26-24; 8 bytes = 011b) */ 964 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24) 965 /* I/O space size (bits 26-24; 32 bytes = 101b) */ 966 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24) 967 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */ 968 #define ITE_887x_POSIO_SPEED (3 << 29) 969 /* enable IO_Space bit */ 970 #define ITE_887x_POSIO_ENABLE (1 << 31) 971 972 /* inta_addr are the configuration addresses of the ITE */ 973 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0, 0x200, 0x280 }; 974 static int pci_ite887x_init(struct pci_dev *dev) 975 { 976 int ret, i, type; 977 struct resource *iobase = NULL; 978 u32 miscr, uartbar, ioport; 979 980 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 981 return serial_8250_warn_need_ioport(dev); 982 983 /* search for the base-ioport */ 984 for (i = 0; i < ARRAY_SIZE(inta_addr); i++) { 985 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE, 986 "ite887x"); 987 if (iobase != NULL) { 988 /* write POSIO0R - speed | size | ioport */ 989 pci_write_config_dword(dev, ITE_887x_POSIO0, 990 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 991 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]); 992 /* write INTCBAR - ioport */ 993 pci_write_config_dword(dev, ITE_887x_INTCBAR, 994 inta_addr[i]); 995 ret = inb(inta_addr[i]); 996 if (ret != 0xff) { 997 /* ioport connected */ 998 break; 999 } 1000 release_region(iobase->start, ITE_887x_IOSIZE); 1001 } 1002 } 1003 1004 if (i == ARRAY_SIZE(inta_addr)) { 1005 pci_err(dev, "could not find iobase\n"); 1006 return -ENODEV; 1007 } 1008 1009 /* start of undocumented type checking (see parport_pc.c) */ 1010 type = inb(iobase->start + 0x18) & 0x0f; 1011 1012 switch (type) { 1013 case 0x2: /* ITE8871 (1P) */ 1014 case 0xa: /* ITE8875 (1P) */ 1015 ret = 0; 1016 break; 1017 case 0xe: /* ITE8872 (2S1P) */ 1018 ret = 2; 1019 break; 1020 case 0x6: /* ITE8873 (1S) */ 1021 ret = 1; 1022 break; 1023 case 0x8: /* ITE8874 (2S) */ 1024 ret = 2; 1025 break; 1026 default: 1027 moan_device("Unknown ITE887x", dev); 1028 ret = -ENODEV; 1029 } 1030 1031 /* configure all serial ports */ 1032 for (i = 0; i < ret; i++) { 1033 /* read the I/O port from the device */ 1034 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)), 1035 &ioport); 1036 ioport &= 0x0000FF00; /* the actual base address */ 1037 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)), 1038 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED | 1039 ITE_887x_POSIO_IOSIZE_8 | ioport); 1040 1041 /* write the ioport to the UARTBAR */ 1042 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar); 1043 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */ 1044 uartbar |= (ioport << (16 * i)); /* set the ioport */ 1045 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar); 1046 1047 /* get current config */ 1048 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr); 1049 /* disable interrupts (UARTx_Routing[3:0]) */ 1050 miscr &= ~(0xf << (12 - 4 * i)); 1051 /* activate the UART (UARTx_En) */ 1052 miscr |= 1 << (23 - i); 1053 /* write new config with activated UART */ 1054 pci_write_config_dword(dev, ITE_887x_MISCR, miscr); 1055 } 1056 1057 if (ret <= 0) { 1058 /* the device has no UARTs if we get here */ 1059 release_region(iobase->start, ITE_887x_IOSIZE); 1060 } 1061 1062 return ret; 1063 } 1064 1065 static void pci_ite887x_exit(struct pci_dev *dev) 1066 { 1067 u32 ioport; 1068 /* the ioport is bit 0-15 in POSIO0R */ 1069 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport); 1070 ioport &= 0xffff; 1071 release_region(ioport, ITE_887x_IOSIZE); 1072 } 1073 1074 /* 1075 * Oxford Semiconductor Inc. 1076 * Check if an OxSemi device is part of the Tornado range of devices. 1077 */ 1078 #define PCI_VENDOR_ID_ENDRUN 0x7401 1079 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100 1080 1081 static bool pci_oxsemi_tornado_p(struct pci_dev *dev) 1082 { 1083 /* OxSemi Tornado devices are all 0xCxxx */ 1084 if (dev->vendor == PCI_VENDOR_ID_OXSEMI && 1085 (dev->device & 0xf000) != 0xc000) 1086 return false; 1087 1088 /* EndRun devices are all 0xExxx */ 1089 if (dev->vendor == PCI_VENDOR_ID_ENDRUN && 1090 (dev->device & 0xf000) != 0xe000) 1091 return false; 1092 1093 return true; 1094 } 1095 1096 /* 1097 * Determine the number of ports available on a Tornado device. 1098 */ 1099 static int pci_oxsemi_tornado_init(struct pci_dev *dev) 1100 { 1101 u8 __iomem *p; 1102 unsigned long deviceID; 1103 unsigned int number_uarts = 0; 1104 1105 if (!pci_oxsemi_tornado_p(dev)) 1106 return 0; 1107 1108 p = pci_iomap(dev, 0, 5); 1109 if (p == NULL) 1110 return -ENOMEM; 1111 1112 deviceID = ioread32(p); 1113 /* Tornado device */ 1114 if (deviceID == 0x07000200) { 1115 number_uarts = ioread8(p + 4); 1116 pci_dbg(dev, "%d ports detected on %s PCI Express device\n", 1117 number_uarts, 1118 dev->vendor == PCI_VENDOR_ID_ENDRUN ? 1119 "EndRun" : "Oxford"); 1120 } 1121 pci_iounmap(dev, p); 1122 return number_uarts; 1123 } 1124 1125 /* Tornado-specific constants for the TCR and CPR registers; see below. */ 1126 #define OXSEMI_TORNADO_TCR_MASK 0xf 1127 #define OXSEMI_TORNADO_CPR_MASK 0x1ff 1128 #define OXSEMI_TORNADO_CPR_MIN 0x008 1129 #define OXSEMI_TORNADO_CPR_DEF 0x10f 1130 1131 /* 1132 * Determine the oversampling rate, the clock prescaler, and the clock 1133 * divisor for the requested baud rate. The clock rate is 62.5 MHz, 1134 * which is four times the baud base, and the prescaler increments in 1135 * steps of 1/8. Therefore to make calculations on integers we need 1136 * to use a scaled clock rate, which is the baud base multiplied by 32 1137 * (or our assumed UART clock rate multiplied by 2). 1138 * 1139 * The allowed oversampling rates are from 4 up to 16 inclusive (values 1140 * from 0 to 3 inclusive map to 16). Likewise the clock prescaler allows 1141 * values between 1.000 and 63.875 inclusive (operation for values from 1142 * 0.000 to 0.875 has not been specified). The clock divisor is the usual 1143 * unsigned 16-bit integer. 1144 * 1145 * For the most accurate baud rate we use a table of predetermined 1146 * oversampling rates and clock prescalers that records all possible 1147 * products of the two parameters in the range from 4 up to 255 inclusive, 1148 * and additionally 335 for the 1500000bps rate, with the prescaler scaled 1149 * by 8. The table is sorted by the decreasing value of the oversampling 1150 * rate and ties are resolved by sorting by the decreasing value of the 1151 * product. This way preference is given to higher oversampling rates. 1152 * 1153 * We iterate over the table and choose the product of an oversampling 1154 * rate and a clock prescaler that gives the lowest integer division 1155 * result deviation, or if an exact integer divider is found we stop 1156 * looking for it right away. We do some fixup if the resulting clock 1157 * divisor required would be out of its unsigned 16-bit integer range. 1158 * 1159 * Finally we abuse the supposed fractional part returned to encode the 1160 * 4-bit value of the oversampling rate and the 9-bit value of the clock 1161 * prescaler which will end up in the TCR and CPR/CPR2 registers. 1162 */ 1163 static unsigned int pci_oxsemi_tornado_get_divisor(struct uart_port *port, 1164 unsigned int baud, 1165 unsigned int *frac) 1166 { 1167 static u8 p[][2] = { 1168 { 16, 14, }, { 16, 13, }, { 16, 12, }, { 16, 11, }, 1169 { 16, 10, }, { 16, 9, }, { 16, 8, }, { 15, 17, }, 1170 { 15, 16, }, { 15, 15, }, { 15, 14, }, { 15, 13, }, 1171 { 15, 12, }, { 15, 11, }, { 15, 10, }, { 15, 9, }, 1172 { 15, 8, }, { 14, 18, }, { 14, 17, }, { 14, 14, }, 1173 { 14, 13, }, { 14, 12, }, { 14, 11, }, { 14, 10, }, 1174 { 14, 9, }, { 14, 8, }, { 13, 19, }, { 13, 18, }, 1175 { 13, 17, }, { 13, 13, }, { 13, 12, }, { 13, 11, }, 1176 { 13, 10, }, { 13, 9, }, { 13, 8, }, { 12, 19, }, 1177 { 12, 18, }, { 12, 17, }, { 12, 11, }, { 12, 9, }, 1178 { 12, 8, }, { 11, 23, }, { 11, 22, }, { 11, 21, }, 1179 { 11, 20, }, { 11, 19, }, { 11, 18, }, { 11, 17, }, 1180 { 11, 11, }, { 11, 10, }, { 11, 9, }, { 11, 8, }, 1181 { 10, 25, }, { 10, 23, }, { 10, 20, }, { 10, 19, }, 1182 { 10, 17, }, { 10, 10, }, { 10, 9, }, { 10, 8, }, 1183 { 9, 27, }, { 9, 23, }, { 9, 21, }, { 9, 19, }, 1184 { 9, 18, }, { 9, 17, }, { 9, 9, }, { 9, 8, }, 1185 { 8, 31, }, { 8, 29, }, { 8, 23, }, { 8, 19, }, 1186 { 8, 17, }, { 8, 8, }, { 7, 35, }, { 7, 31, }, 1187 { 7, 29, }, { 7, 25, }, { 7, 23, }, { 7, 21, }, 1188 { 7, 19, }, { 7, 17, }, { 7, 15, }, { 7, 14, }, 1189 { 7, 13, }, { 7, 12, }, { 7, 11, }, { 7, 10, }, 1190 { 7, 9, }, { 7, 8, }, { 6, 41, }, { 6, 37, }, 1191 { 6, 31, }, { 6, 29, }, { 6, 23, }, { 6, 19, }, 1192 { 6, 17, }, { 6, 13, }, { 6, 11, }, { 6, 10, }, 1193 { 6, 9, }, { 6, 8, }, { 5, 67, }, { 5, 47, }, 1194 { 5, 43, }, { 5, 41, }, { 5, 37, }, { 5, 31, }, 1195 { 5, 29, }, { 5, 25, }, { 5, 23, }, { 5, 19, }, 1196 { 5, 17, }, { 5, 15, }, { 5, 13, }, { 5, 11, }, 1197 { 5, 10, }, { 5, 9, }, { 5, 8, }, { 4, 61, }, 1198 { 4, 59, }, { 4, 53, }, { 4, 47, }, { 4, 43, }, 1199 { 4, 41, }, { 4, 37, }, { 4, 31, }, { 4, 29, }, 1200 { 4, 23, }, { 4, 19, }, { 4, 17, }, { 4, 13, }, 1201 { 4, 9, }, { 4, 8, }, 1202 }; 1203 /* Scale the quotient for comparison to get the fractional part. */ 1204 const unsigned int quot_scale = 65536; 1205 unsigned int sclk = port->uartclk * 2; 1206 unsigned int sdiv = DIV_ROUND_CLOSEST(sclk, baud); 1207 unsigned int best_squot; 1208 unsigned int squot; 1209 unsigned int quot; 1210 u16 cpr; 1211 u8 tcr; 1212 int i; 1213 1214 best_squot = quot_scale; 1215 for (i = 0; i < ARRAY_SIZE(p); i++) { 1216 unsigned int spre; 1217 unsigned int srem; 1218 u8 cp; 1219 u8 tc; 1220 1221 tc = p[i][0]; 1222 cp = p[i][1]; 1223 spre = tc * cp; 1224 1225 srem = sdiv % spre; 1226 if (srem > spre / 2) 1227 srem = spre - srem; 1228 squot = DIV_ROUND_CLOSEST(srem * quot_scale, spre); 1229 1230 if (srem == 0) { 1231 tcr = tc; 1232 cpr = cp; 1233 quot = sdiv / spre; 1234 break; 1235 } else if (squot < best_squot) { 1236 best_squot = squot; 1237 tcr = tc; 1238 cpr = cp; 1239 quot = DIV_ROUND_CLOSEST(sdiv, spre); 1240 } 1241 } 1242 while (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1 && 1243 quot % 2 == 0) { 1244 quot >>= 1; 1245 tcr <<= 1; 1246 } 1247 while (quot > UART_DIV_MAX) { 1248 if (tcr <= (OXSEMI_TORNADO_TCR_MASK + 1) >> 1) { 1249 quot >>= 1; 1250 tcr <<= 1; 1251 } else if (cpr <= OXSEMI_TORNADO_CPR_MASK >> 1) { 1252 quot >>= 1; 1253 cpr <<= 1; 1254 } else { 1255 quot = quot * cpr / OXSEMI_TORNADO_CPR_MASK; 1256 cpr = OXSEMI_TORNADO_CPR_MASK; 1257 } 1258 } 1259 1260 *frac = (cpr << 8) | (tcr & OXSEMI_TORNADO_TCR_MASK); 1261 return quot; 1262 } 1263 1264 /* 1265 * Set the oversampling rate in the transmitter clock cycle register (TCR), 1266 * the clock prescaler in the clock prescaler register (CPR and CPR2), and 1267 * the clock divisor in the divisor latch (DLL and DLM). Note that for 1268 * backwards compatibility any write to CPR clears CPR2 and therefore CPR 1269 * has to be written first, followed by CPR2, which occupies the location 1270 * of CKS used with earlier UART designs. 1271 */ 1272 static void pci_oxsemi_tornado_set_divisor(struct uart_port *port, 1273 unsigned int baud, 1274 unsigned int quot, 1275 unsigned int quot_frac) 1276 { 1277 struct uart_8250_port *up = up_to_u8250p(port); 1278 u8 cpr2 = quot_frac >> 16; 1279 u8 cpr = quot_frac >> 8; 1280 u8 tcr = quot_frac; 1281 1282 serial_icr_write(up, UART_TCR, tcr); 1283 serial_icr_write(up, UART_CPR, cpr); 1284 serial_icr_write(up, UART_CKS, cpr2); 1285 serial8250_do_set_divisor(port, baud, quot); 1286 } 1287 1288 /* 1289 * For Tornado devices we force MCR[7] set for the Divide-by-M N/8 baud rate 1290 * generator prescaler (CPR and CPR2). Otherwise no prescaler would be used. 1291 */ 1292 static void pci_oxsemi_tornado_set_mctrl(struct uart_port *port, 1293 unsigned int mctrl) 1294 { 1295 struct uart_8250_port *up = up_to_u8250p(port); 1296 1297 up->mcr |= UART_MCR_CLKSEL; 1298 serial8250_do_set_mctrl(port, mctrl); 1299 } 1300 1301 /* 1302 * We require EFR features for clock programming, so set UPF_FULL_PROBE 1303 * for full probing regardless of CONFIG_SERIAL_8250_16550A_VARIANTS setting. 1304 */ 1305 static int pci_oxsemi_tornado_setup(struct serial_private *priv, 1306 const struct pciserial_board *board, 1307 struct uart_8250_port *up, int idx) 1308 { 1309 struct pci_dev *dev = priv->dev; 1310 1311 if (pci_oxsemi_tornado_p(dev)) { 1312 up->port.flags |= UPF_FULL_PROBE; 1313 up->port.get_divisor = pci_oxsemi_tornado_get_divisor; 1314 up->port.set_divisor = pci_oxsemi_tornado_set_divisor; 1315 up->port.set_mctrl = pci_oxsemi_tornado_set_mctrl; 1316 } 1317 1318 return pci_default_setup(priv, board, up, idx); 1319 } 1320 1321 #define QPCR_TEST_FOR1 0x3F 1322 #define QPCR_TEST_GET1 0x00 1323 #define QPCR_TEST_FOR2 0x40 1324 #define QPCR_TEST_GET2 0x40 1325 #define QPCR_TEST_FOR3 0x80 1326 #define QPCR_TEST_GET3 0x40 1327 #define QPCR_TEST_FOR4 0xC0 1328 #define QPCR_TEST_GET4 0x80 1329 1330 #define QOPR_CLOCK_X1 0x0000 1331 #define QOPR_CLOCK_X2 0x0001 1332 #define QOPR_CLOCK_X4 0x0002 1333 #define QOPR_CLOCK_X8 0x0003 1334 #define QOPR_CLOCK_RATE_MASK 0x0003 1335 1336 /* Quatech devices have their own extra interface features */ 1337 static struct pci_device_id quatech_cards[] = { 1338 { PCI_DEVICE_DATA(QUATECH, QSC100, 1) }, 1339 { PCI_DEVICE_DATA(QUATECH, DSC100, 1) }, 1340 { PCI_DEVICE_DATA(QUATECH, DSC100E, 0) }, 1341 { PCI_DEVICE_DATA(QUATECH, DSC200, 1) }, 1342 { PCI_DEVICE_DATA(QUATECH, DSC200E, 0) }, 1343 { PCI_DEVICE_DATA(QUATECH, ESC100D, 1) }, 1344 { PCI_DEVICE_DATA(QUATECH, ESC100M, 1) }, 1345 { PCI_DEVICE_DATA(QUATECH, QSCP100, 1) }, 1346 { PCI_DEVICE_DATA(QUATECH, DSCP100, 1) }, 1347 { PCI_DEVICE_DATA(QUATECH, QSCP200, 1) }, 1348 { PCI_DEVICE_DATA(QUATECH, DSCP200, 1) }, 1349 { PCI_DEVICE_DATA(QUATECH, ESCLP100, 0) }, 1350 { PCI_DEVICE_DATA(QUATECH, QSCLP100, 0) }, 1351 { PCI_DEVICE_DATA(QUATECH, DSCLP100, 0) }, 1352 { PCI_DEVICE_DATA(QUATECH, SSCLP100, 0) }, 1353 { PCI_DEVICE_DATA(QUATECH, QSCLP200, 0) }, 1354 { PCI_DEVICE_DATA(QUATECH, DSCLP200, 0) }, 1355 { PCI_DEVICE_DATA(QUATECH, SSCLP200, 0) }, 1356 { PCI_DEVICE_DATA(QUATECH, SPPXP_100, 0) }, 1357 { 0, } 1358 }; 1359 1360 static int pci_quatech_rqopr(struct uart_8250_port *port) 1361 { 1362 unsigned long base = port->port.iobase; 1363 u8 LCR, val; 1364 1365 LCR = inb(base + UART_LCR); 1366 outb(0xBF, base + UART_LCR); 1367 val = inb(base + UART_SCR); 1368 outb(LCR, base + UART_LCR); 1369 return val; 1370 } 1371 1372 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr) 1373 { 1374 unsigned long base = port->port.iobase; 1375 u8 LCR; 1376 1377 LCR = inb(base + UART_LCR); 1378 outb(0xBF, base + UART_LCR); 1379 inb(base + UART_SCR); 1380 outb(qopr, base + UART_SCR); 1381 outb(LCR, base + UART_LCR); 1382 } 1383 1384 static int pci_quatech_rqmcr(struct uart_8250_port *port) 1385 { 1386 unsigned long base = port->port.iobase; 1387 u8 LCR, val, qmcr; 1388 1389 LCR = inb(base + UART_LCR); 1390 outb(0xBF, base + UART_LCR); 1391 val = inb(base + UART_SCR); 1392 outb(val | 0x10, base + UART_SCR); 1393 qmcr = inb(base + UART_MCR); 1394 outb(val, base + UART_SCR); 1395 outb(LCR, base + UART_LCR); 1396 1397 return qmcr; 1398 } 1399 1400 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr) 1401 { 1402 unsigned long base = port->port.iobase; 1403 u8 LCR, val; 1404 1405 LCR = inb(base + UART_LCR); 1406 outb(0xBF, base + UART_LCR); 1407 val = inb(base + UART_SCR); 1408 outb(val | 0x10, base + UART_SCR); 1409 outb(qmcr, base + UART_MCR); 1410 outb(val, base + UART_SCR); 1411 outb(LCR, base + UART_LCR); 1412 } 1413 1414 static int pci_quatech_has_qmcr(struct uart_8250_port *port) 1415 { 1416 unsigned long base = port->port.iobase; 1417 u8 LCR, val; 1418 1419 LCR = inb(base + UART_LCR); 1420 outb(0xBF, base + UART_LCR); 1421 val = inb(base + UART_SCR); 1422 if (val & 0x20) { 1423 outb(0x80, UART_LCR); 1424 if (!(inb(UART_SCR) & 0x20)) { 1425 outb(LCR, base + UART_LCR); 1426 return 1; 1427 } 1428 } 1429 return 0; 1430 } 1431 1432 static int pci_quatech_test(struct uart_8250_port *port) 1433 { 1434 u8 reg, qopr; 1435 1436 qopr = pci_quatech_rqopr(port); 1437 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1); 1438 reg = pci_quatech_rqopr(port) & 0xC0; 1439 if (reg != QPCR_TEST_GET1) 1440 return -EINVAL; 1441 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2); 1442 reg = pci_quatech_rqopr(port) & 0xC0; 1443 if (reg != QPCR_TEST_GET2) 1444 return -EINVAL; 1445 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3); 1446 reg = pci_quatech_rqopr(port) & 0xC0; 1447 if (reg != QPCR_TEST_GET3) 1448 return -EINVAL; 1449 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4); 1450 reg = pci_quatech_rqopr(port) & 0xC0; 1451 if (reg != QPCR_TEST_GET4) 1452 return -EINVAL; 1453 1454 pci_quatech_wqopr(port, qopr); 1455 return 0; 1456 } 1457 1458 static int pci_quatech_clock(struct uart_8250_port *port) 1459 { 1460 u8 qopr, reg, set; 1461 unsigned long clock; 1462 1463 if (pci_quatech_test(port) < 0) 1464 return 1843200; 1465 1466 qopr = pci_quatech_rqopr(port); 1467 1468 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8); 1469 reg = pci_quatech_rqopr(port); 1470 if (reg & QOPR_CLOCK_X8) { 1471 clock = 1843200; 1472 goto out; 1473 } 1474 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8); 1475 reg = pci_quatech_rqopr(port); 1476 if (!(reg & QOPR_CLOCK_X8)) { 1477 clock = 1843200; 1478 goto out; 1479 } 1480 reg &= QOPR_CLOCK_X8; 1481 if (reg == QOPR_CLOCK_X2) { 1482 clock = 3685400; 1483 set = QOPR_CLOCK_X2; 1484 } else if (reg == QOPR_CLOCK_X4) { 1485 clock = 7372800; 1486 set = QOPR_CLOCK_X4; 1487 } else if (reg == QOPR_CLOCK_X8) { 1488 clock = 14745600; 1489 set = QOPR_CLOCK_X8; 1490 } else { 1491 clock = 1843200; 1492 set = QOPR_CLOCK_X1; 1493 } 1494 qopr &= ~QOPR_CLOCK_RATE_MASK; 1495 qopr |= set; 1496 1497 out: 1498 pci_quatech_wqopr(port, qopr); 1499 return clock; 1500 } 1501 1502 static int pci_quatech_rs422(struct uart_8250_port *port) 1503 { 1504 u8 qmcr; 1505 int rs422 = 0; 1506 1507 if (!pci_quatech_has_qmcr(port)) 1508 return 0; 1509 qmcr = pci_quatech_rqmcr(port); 1510 pci_quatech_wqmcr(port, 0xFF); 1511 if (pci_quatech_rqmcr(port)) 1512 rs422 = 1; 1513 pci_quatech_wqmcr(port, qmcr); 1514 return rs422; 1515 } 1516 1517 static int pci_quatech_init(struct pci_dev *dev) 1518 { 1519 const struct pci_device_id *match; 1520 bool amcc = false; 1521 1522 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1523 return serial_8250_warn_need_ioport(dev); 1524 1525 match = pci_match_id(quatech_cards, dev); 1526 if (match) 1527 amcc = match->driver_data; 1528 else 1529 pci_err(dev, "unknown port type '0x%04X'.\n", dev->device); 1530 1531 if (amcc) { 1532 unsigned long base = pci_resource_start(dev, 0); 1533 if (base) { 1534 u32 tmp; 1535 1536 outl(inl(base + 0x38) | 0x00002000, base + 0x38); 1537 tmp = inl(base + 0x3c); 1538 outl(tmp | 0x01000000, base + 0x3c); 1539 outl(tmp & ~0x01000000, base + 0x3c); 1540 } 1541 } 1542 return 0; 1543 } 1544 1545 static int pci_quatech_setup(struct serial_private *priv, 1546 const struct pciserial_board *board, 1547 struct uart_8250_port *port, int idx) 1548 { 1549 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1550 return serial_8250_warn_need_ioport(priv->dev); 1551 1552 /* Needed by pci_quatech calls below */ 1553 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags)); 1554 /* Set up the clocking */ 1555 port->port.uartclk = pci_quatech_clock(port); 1556 /* For now just warn about RS422 */ 1557 if (pci_quatech_rs422(port)) 1558 pci_warn(priv->dev, "software control of RS422 features not currently supported.\n"); 1559 return pci_default_setup(priv, board, port, idx); 1560 } 1561 1562 static int pci_default_setup(struct serial_private *priv, 1563 const struct pciserial_board *board, 1564 struct uart_8250_port *port, int idx) 1565 { 1566 unsigned int bar, offset = board->first_offset, maxnr; 1567 1568 bar = FL_GET_BASE(board->flags); 1569 if (board->flags & FL_BASE_BARS) 1570 bar += idx; 1571 else 1572 offset += idx * board->uart_offset; 1573 1574 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >> 1575 (board->reg_shift + 3); 1576 1577 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr) 1578 return 1; 1579 1580 return setup_port(priv, port, bar, offset, board->reg_shift); 1581 } 1582 1583 static int 1584 ce4100_serial_setup(struct serial_private *priv, 1585 const struct pciserial_board *board, 1586 struct uart_8250_port *port, int idx) 1587 { 1588 int ret; 1589 1590 ret = setup_port(priv, port, idx, 0, board->reg_shift); 1591 port->port.iotype = UPIO_MEM32; 1592 port->port.type = PORT_XSCALE; 1593 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1594 port->port.regshift = 2; 1595 1596 return ret; 1597 } 1598 1599 static int 1600 pci_omegapci_setup(struct serial_private *priv, 1601 const struct pciserial_board *board, 1602 struct uart_8250_port *port, int idx) 1603 { 1604 return setup_port(priv, port, 2, idx * 8, 0); 1605 } 1606 1607 static int 1608 pci_brcm_trumanage_setup(struct serial_private *priv, 1609 const struct pciserial_board *board, 1610 struct uart_8250_port *port, int idx) 1611 { 1612 int ret = pci_default_setup(priv, board, port, idx); 1613 1614 port->port.type = PORT_BRCM_TRUMANAGE; 1615 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE); 1616 return ret; 1617 } 1618 1619 /* RTS will control by MCR if this bit is 0 */ 1620 #define FINTEK_RTS_CONTROL_BY_HW BIT(4) 1621 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */ 1622 #define FINTEK_RTS_INVERT BIT(5) 1623 1624 /* We should do proper H/W transceiver setting before change to RS485 mode */ 1625 static int pci_fintek_rs485_config(struct uart_port *port, struct ktermios *termios, 1626 struct serial_rs485 *rs485) 1627 { 1628 struct pci_dev *pci_dev = to_pci_dev(port->dev); 1629 u8 setting; 1630 u8 *index = (u8 *) port->private_data; 1631 1632 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting); 1633 1634 if (rs485->flags & SER_RS485_ENABLED) { 1635 /* Enable RTS H/W control mode */ 1636 setting |= FINTEK_RTS_CONTROL_BY_HW; 1637 1638 if (rs485->flags & SER_RS485_RTS_ON_SEND) { 1639 /* RTS driving high on TX */ 1640 setting &= ~FINTEK_RTS_INVERT; 1641 } else { 1642 /* RTS driving low on TX */ 1643 setting |= FINTEK_RTS_INVERT; 1644 } 1645 } else { 1646 /* Disable RTS H/W control mode */ 1647 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT); 1648 } 1649 1650 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting); 1651 1652 return 0; 1653 } 1654 1655 static const struct serial_rs485 pci_fintek_rs485_supported = { 1656 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND, 1657 /* F81504/508/512 does not support RTS delay before or after send */ 1658 }; 1659 1660 static int pci_fintek_setup(struct serial_private *priv, 1661 const struct pciserial_board *board, 1662 struct uart_8250_port *port, int idx) 1663 { 1664 struct pci_dev *pdev = priv->dev; 1665 u8 *data; 1666 u8 config_base; 1667 u16 iobase; 1668 1669 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1670 return serial_8250_warn_need_ioport(pdev); 1671 1672 config_base = 0x40 + 0x08 * idx; 1673 1674 /* Get the io address from configuration space */ 1675 pci_read_config_word(pdev, config_base + 4, &iobase); 1676 1677 pci_dbg(pdev, "idx=%d iobase=0x%x", idx, iobase); 1678 1679 port->port.iotype = UPIO_PORT; 1680 port->port.iobase = iobase; 1681 port->port.rs485_config = pci_fintek_rs485_config; 1682 port->port.rs485_supported = pci_fintek_rs485_supported; 1683 1684 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL); 1685 if (!data) 1686 return -ENOMEM; 1687 1688 /* preserve index in PCI configuration space */ 1689 *data = idx; 1690 port->port.private_data = data; 1691 1692 return 0; 1693 } 1694 1695 static int pci_fintek_init(struct pci_dev *dev) 1696 { 1697 unsigned long iobase; 1698 u32 max_port, i; 1699 resource_size_t bar_data[3]; 1700 u8 config_base; 1701 struct serial_private *priv = pci_get_drvdata(dev); 1702 1703 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1704 return serial_8250_warn_need_ioport(dev); 1705 1706 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) || 1707 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) || 1708 !(pci_resource_flags(dev, 3) & IORESOURCE_IO)) 1709 return -ENODEV; 1710 1711 switch (dev->device) { 1712 case 0x1104: /* 4 ports */ 1713 case 0x1108: /* 8 ports */ 1714 max_port = dev->device & 0xff; 1715 break; 1716 case 0x1112: /* 12 ports */ 1717 max_port = 12; 1718 break; 1719 default: 1720 return -EINVAL; 1721 } 1722 1723 /* Get the io address dispatch from the BIOS */ 1724 bar_data[0] = pci_resource_start(dev, 5); 1725 bar_data[1] = pci_resource_start(dev, 4); 1726 bar_data[2] = pci_resource_start(dev, 3); 1727 1728 for (i = 0; i < max_port; ++i) { 1729 /* UART0 configuration offset start from 0x40 */ 1730 config_base = 0x40 + 0x08 * i; 1731 1732 /* Calculate Real IO Port */ 1733 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8; 1734 1735 /* Enable UART I/O port */ 1736 pci_write_config_byte(dev, config_base + 0x00, 0x01); 1737 1738 /* Select 128-byte FIFO and 8x FIFO threshold */ 1739 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1740 1741 /* LSB UART */ 1742 pci_write_config_byte(dev, config_base + 0x04, 1743 (u8)(iobase & 0xff)); 1744 1745 /* MSB UART */ 1746 pci_write_config_byte(dev, config_base + 0x05, 1747 (u8)((iobase & 0xff00) >> 8)); 1748 1749 pci_write_config_byte(dev, config_base + 0x06, dev->irq); 1750 1751 if (!priv) { 1752 /* First init without port data 1753 * force init to RS232 Mode 1754 */ 1755 pci_write_config_byte(dev, config_base + 0x07, 0x01); 1756 } 1757 } 1758 1759 return max_port; 1760 } 1761 1762 static void f815xxa_mem_serial_out(struct uart_port *p, unsigned int offset, u32 value) 1763 { 1764 struct f815xxa_data *data = p->private_data; 1765 unsigned long flags; 1766 1767 spin_lock_irqsave(&data->lock, flags); 1768 writeb(value, p->membase + offset); 1769 readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */ 1770 spin_unlock_irqrestore(&data->lock, flags); 1771 } 1772 1773 static int pci_fintek_f815xxa_setup(struct serial_private *priv, 1774 const struct pciserial_board *board, 1775 struct uart_8250_port *port, int idx) 1776 { 1777 struct pci_dev *pdev = priv->dev; 1778 struct f815xxa_data *data; 1779 1780 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 1781 if (!data) 1782 return -ENOMEM; 1783 1784 data->idx = idx; 1785 spin_lock_init(&data->lock); 1786 1787 port->port.private_data = data; 1788 port->port.iotype = UPIO_MEM; 1789 port->port.flags |= UPF_IOREMAP; 1790 port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx; 1791 port->port.serial_out = f815xxa_mem_serial_out; 1792 1793 return 0; 1794 } 1795 1796 static int pci_fintek_f815xxa_init(struct pci_dev *dev) 1797 { 1798 u32 max_port, i; 1799 int config_base; 1800 1801 if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM)) 1802 return -ENODEV; 1803 1804 switch (dev->device) { 1805 case 0x1204: /* 4 ports */ 1806 case 0x1208: /* 8 ports */ 1807 max_port = dev->device & 0xff; 1808 break; 1809 case 0x1212: /* 12 ports */ 1810 max_port = 12; 1811 break; 1812 default: 1813 return -EINVAL; 1814 } 1815 1816 /* Set to mmio decode */ 1817 pci_write_config_byte(dev, 0x209, 0x40); 1818 1819 for (i = 0; i < max_port; ++i) { 1820 /* UART0 configuration offset start from 0x2A0 */ 1821 config_base = 0x2A0 + 0x08 * i; 1822 1823 /* Select 128-byte FIFO and 8x FIFO threshold */ 1824 pci_write_config_byte(dev, config_base + 0x01, 0x33); 1825 1826 /* Enable UART I/O port */ 1827 pci_write_config_byte(dev, config_base + 0, 0x01); 1828 } 1829 1830 return max_port; 1831 } 1832 1833 static int skip_tx_en_setup(struct serial_private *priv, 1834 const struct pciserial_board *board, 1835 struct uart_8250_port *port, int idx) 1836 { 1837 port->port.quirks |= UPQ_NO_TXEN_TEST; 1838 pci_dbg(priv->dev, 1839 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n", 1840 priv->dev->vendor, priv->dev->device, 1841 priv->dev->subsystem_vendor, priv->dev->subsystem_device); 1842 1843 return pci_default_setup(priv, board, port, idx); 1844 } 1845 1846 static void kt_handle_break(struct uart_port *p) 1847 { 1848 struct uart_8250_port *up = up_to_u8250p(p); 1849 /* 1850 * On receipt of a BI, serial device in Intel ME (Intel 1851 * management engine) needs to have its fifos cleared for sane 1852 * SOL (Serial Over Lan) output. 1853 */ 1854 serial8250_clear_and_reinit_fifos(up); 1855 } 1856 1857 static u32 kt_serial_in(struct uart_port *p, unsigned int offset) 1858 { 1859 struct uart_8250_port *up = up_to_u8250p(p); 1860 u32 val; 1861 1862 /* 1863 * When the Intel ME (management engine) gets reset its serial 1864 * port registers could return 0 momentarily. Functions like 1865 * serial8250_console_write, read and save the IER, perform 1866 * some operation and then restore it. In order to avoid 1867 * setting IER register inadvertently to 0, if the value read 1868 * is 0, double check with ier value in uart_8250_port and use 1869 * that instead. up->ier should be the same value as what is 1870 * currently configured. 1871 */ 1872 val = inb(p->iobase + offset); 1873 if (offset == UART_IER) { 1874 if (val == 0) 1875 val = up->ier; 1876 } 1877 return val; 1878 } 1879 1880 static int kt_serial_setup(struct serial_private *priv, 1881 const struct pciserial_board *board, 1882 struct uart_8250_port *port, int idx) 1883 { 1884 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1885 return serial_8250_warn_need_ioport(priv->dev); 1886 1887 port->port.flags |= UPF_BUG_THRE; 1888 port->port.serial_in = kt_serial_in; 1889 port->port.handle_break = kt_handle_break; 1890 return skip_tx_en_setup(priv, board, port, idx); 1891 } 1892 1893 static int pci_eg20t_init(struct pci_dev *dev) 1894 { 1895 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE) 1896 return -ENODEV; 1897 #else 1898 return 0; 1899 #endif 1900 } 1901 1902 static int 1903 pci_wch_ch353_setup(struct serial_private *priv, 1904 const struct pciserial_board *board, 1905 struct uart_8250_port *port, int idx) 1906 { 1907 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1908 return serial_8250_warn_need_ioport(priv->dev); 1909 1910 port->port.flags |= UPF_FIXED_TYPE; 1911 port->port.type = PORT_16550A; 1912 return pci_default_setup(priv, board, port, idx); 1913 } 1914 1915 static int 1916 pci_wch_ch355_setup(struct serial_private *priv, 1917 const struct pciserial_board *board, 1918 struct uart_8250_port *port, int idx) 1919 { 1920 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1921 return serial_8250_warn_need_ioport(priv->dev); 1922 1923 port->port.flags |= UPF_FIXED_TYPE; 1924 port->port.type = PORT_16550A; 1925 return pci_default_setup(priv, board, port, idx); 1926 } 1927 1928 static int 1929 pci_wch_ch38x_setup(struct serial_private *priv, 1930 const struct pciserial_board *board, 1931 struct uart_8250_port *port, int idx) 1932 { 1933 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1934 return serial_8250_warn_need_ioport(priv->dev); 1935 1936 port->port.flags |= UPF_FIXED_TYPE; 1937 port->port.type = PORT_16850; 1938 return pci_default_setup(priv, board, port, idx); 1939 } 1940 1941 1942 #define CH384_XINT_ENABLE_REG 0xEB 1943 #define CH384_XINT_ENABLE_BIT 0x02 1944 1945 static int pci_wch_ch38x_init(struct pci_dev *dev) 1946 { 1947 int max_port; 1948 unsigned long iobase; 1949 1950 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 1951 return serial_8250_warn_need_ioport(dev); 1952 1953 switch (dev->device) { 1954 case 0x3853: /* 8 ports */ 1955 max_port = 8; 1956 break; 1957 default: 1958 return -EINVAL; 1959 } 1960 1961 iobase = pci_resource_start(dev, 0); 1962 outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG); 1963 1964 return max_port; 1965 } 1966 1967 static void pci_wch_ch38x_exit(struct pci_dev *dev) 1968 { 1969 unsigned long iobase; 1970 1971 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) { 1972 serial_8250_warn_need_ioport(dev); 1973 return; 1974 } 1975 1976 iobase = pci_resource_start(dev, 0); 1977 outb(0x0, iobase + CH384_XINT_ENABLE_REG); 1978 } 1979 1980 1981 static int 1982 pci_sunix_setup(struct serial_private *priv, 1983 const struct pciserial_board *board, 1984 struct uart_8250_port *port, int idx) 1985 { 1986 int bar; 1987 int offset; 1988 1989 port->port.flags |= UPF_FIXED_TYPE; 1990 port->port.type = PORT_SUNIX; 1991 1992 if (idx < 4) { 1993 bar = 0; 1994 offset = idx * board->uart_offset; 1995 } else { 1996 bar = 1; 1997 idx -= 4; 1998 idx = div_s64_rem(idx, 4, &offset); 1999 offset = idx * 64 + offset * board->uart_offset; 2000 } 2001 2002 return setup_port(priv, port, bar, offset, 0); 2003 } 2004 2005 #define MOXA_PUART_GPIO_EN 0x09 2006 #define MOXA_PUART_GPIO_OUT 0x0A 2007 2008 #define MOXA_GPIO_PIN2 BIT(2) 2009 2010 #define MOXA_RS232 0x00 2011 #define MOXA_RS422 0x01 2012 #define MOXA_RS485_4W 0x0B 2013 #define MOXA_RS485_2W 0x0F 2014 #define MOXA_UIR_OFFSET 0x04 2015 #define MOXA_EVEN_RS_MASK GENMASK(3, 0) 2016 #define MOXA_ODD_RS_MASK GENMASK(7, 4) 2017 2018 enum { 2019 MOXA_SUPP_RS232 = BIT(0), 2020 MOXA_SUPP_RS422 = BIT(1), 2021 MOXA_SUPP_RS485 = BIT(2), 2022 }; 2023 2024 static unsigned short moxa_get_nports(unsigned short device) 2025 { 2026 switch (device) { 2027 case PCI_DEVICE_ID_MOXA_CP116E_A_A: 2028 case PCI_DEVICE_ID_MOXA_CP116E_A_B: 2029 return 8; 2030 } 2031 2032 return FIELD_GET(0x00F0, device); 2033 } 2034 2035 static bool pci_moxa_is_mini_pcie(unsigned short device) 2036 { 2037 if (device == PCI_DEVICE_ID_MOXA_CP102N || 2038 device == PCI_DEVICE_ID_MOXA_CP104N || 2039 device == PCI_DEVICE_ID_MOXA_CP112N || 2040 device == PCI_DEVICE_ID_MOXA_CP114N || 2041 device == PCI_DEVICE_ID_MOXA_CP132N || 2042 device == PCI_DEVICE_ID_MOXA_CP134N) 2043 return true; 2044 2045 return false; 2046 } 2047 2048 static unsigned int pci_moxa_supported_rs(struct pci_dev *dev) 2049 { 2050 switch (dev->device & 0x0F00) { 2051 case 0x0000: 2052 case 0x0600: 2053 return MOXA_SUPP_RS232; 2054 case 0x0100: 2055 return MOXA_SUPP_RS232 | MOXA_SUPP_RS422 | MOXA_SUPP_RS485; 2056 case 0x0300: 2057 return MOXA_SUPP_RS422 | MOXA_SUPP_RS485; 2058 } 2059 return 0; 2060 } 2061 2062 static int pci_moxa_set_interface(const struct pci_dev *dev, 2063 unsigned int port_idx, 2064 u8 mode) 2065 { 2066 resource_size_t iobar_addr = pci_resource_start(dev, 2); 2067 resource_size_t UIR_addr = iobar_addr + MOXA_UIR_OFFSET + port_idx / 2; 2068 u8 val; 2069 2070 val = inb(UIR_addr); 2071 2072 if (port_idx % 2) { 2073 val &= ~MOXA_ODD_RS_MASK; 2074 val |= FIELD_PREP(MOXA_ODD_RS_MASK, mode); 2075 } else { 2076 val &= ~MOXA_EVEN_RS_MASK; 2077 val |= FIELD_PREP(MOXA_EVEN_RS_MASK, mode); 2078 } 2079 outb(val, UIR_addr); 2080 2081 return 0; 2082 } 2083 2084 static int pci_moxa_init(struct pci_dev *dev) 2085 { 2086 unsigned short device = dev->device; 2087 resource_size_t iobar_addr = pci_resource_start(dev, 2); 2088 unsigned int i, num_ports = moxa_get_nports(device); 2089 u8 val, init_mode = MOXA_RS232; 2090 2091 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 2092 return serial_8250_warn_need_ioport(dev); 2093 2094 if (!(pci_moxa_supported_rs(dev) & MOXA_SUPP_RS232)) { 2095 init_mode = MOXA_RS422; 2096 } 2097 for (i = 0; i < num_ports; ++i) 2098 pci_moxa_set_interface(dev, i, init_mode); 2099 2100 /* 2101 * Enable hardware buffer to prevent break signal output when system boots up. 2102 * This hardware buffer is only supported on Mini PCIe series. 2103 */ 2104 if (pci_moxa_is_mini_pcie(device)) { 2105 /* Set GPIO direction */ 2106 val = inb(iobar_addr + MOXA_PUART_GPIO_EN); 2107 val |= MOXA_GPIO_PIN2; 2108 outb(val, iobar_addr + MOXA_PUART_GPIO_EN); 2109 /* Enable low GPIO */ 2110 val = inb(iobar_addr + MOXA_PUART_GPIO_OUT); 2111 val &= ~MOXA_GPIO_PIN2; 2112 outb(val, iobar_addr + MOXA_PUART_GPIO_OUT); 2113 } 2114 2115 return num_ports; 2116 } 2117 2118 static int 2119 pci_moxa_setup(struct serial_private *priv, 2120 const struct pciserial_board *board, 2121 struct uart_8250_port *port, int idx) 2122 { 2123 unsigned int bar = FL_GET_BASE(board->flags); 2124 int offset; 2125 2126 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 2127 return serial_8250_warn_need_ioport(priv->dev); 2128 2129 if (board->num_ports == 4 && idx == 3) 2130 offset = 7 * board->uart_offset; 2131 else 2132 offset = idx * board->uart_offset; 2133 2134 return setup_port(priv, port, bar, offset, 0); 2135 } 2136 2137 #define SB_OPTR_IMR0 0x0c /* Interrupt mask register, p0 to p7 */ 2138 static int pci_systembase_init(struct pci_dev *dev) 2139 { 2140 resource_size_t iobase; 2141 2142 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) 2143 return serial_8250_warn_need_ioport(dev); 2144 2145 iobase = pci_resource_start(dev, 1); 2146 2147 /* This will support up to 8 ports */ 2148 outb(0xff, iobase + SB_OPTR_IMR0); 2149 2150 return 0; 2151 } 2152 2153 static void pci_systembase_exit(struct pci_dev *dev) 2154 { 2155 resource_size_t iobase; 2156 2157 if (!IS_ENABLED(CONFIG_HAS_IOPORT)) { 2158 serial_8250_warn_need_ioport(dev); 2159 return; 2160 } 2161 2162 iobase = pci_resource_start(dev, 0); 2163 outb(0x00, iobase + SB_OPTR_IMR0); 2164 } 2165 2166 /* 2167 * Master list of serial port init/setup/exit quirks. 2168 * This does not describe the general nature of the port. 2169 * (ie, baud base, number and location of ports, etc) 2170 * 2171 * This list is ordered alphabetically by vendor then device. 2172 * Specific entries must come before more generic entries. 2173 */ 2174 static struct pci_serial_quirk pci_serial_quirks[] = { 2175 /* 2176 * ADDI-DATA GmbH communication cards <info@addi-data.com> 2177 */ 2178 { 2179 .vendor = PCI_VENDOR_ID_AMCC, 2180 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800, 2181 .subvendor = PCI_ANY_ID, 2182 .subdevice = PCI_ANY_ID, 2183 .setup = addidata_apci7800_setup, 2184 }, 2185 /* 2186 * AFAVLAB cards - these may be called via parport_serial 2187 * It is not clear whether this applies to all products. 2188 */ 2189 { 2190 .vendor = PCI_VENDOR_ID_AFAVLAB, 2191 .device = PCI_ANY_ID, 2192 .subvendor = PCI_ANY_ID, 2193 .subdevice = PCI_ANY_ID, 2194 .setup = afavlab_setup, 2195 }, 2196 /* 2197 * HP Diva 2198 */ 2199 { 2200 .vendor = PCI_VENDOR_ID_HP, 2201 .device = PCI_DEVICE_ID_HP_DIVA, 2202 .subvendor = PCI_ANY_ID, 2203 .subdevice = PCI_ANY_ID, 2204 .init = pci_hp_diva_init, 2205 .setup = pci_hp_diva_setup, 2206 }, 2207 /* 2208 * HPE PCI serial device 2209 */ 2210 { 2211 .vendor = PCI_VENDOR_ID_HP_3PAR, 2212 .device = PCI_DEVICE_ID_HPE_PCI_SERIAL, 2213 .subvendor = PCI_ANY_ID, 2214 .subdevice = PCI_ANY_ID, 2215 .setup = pci_hp_diva_setup, 2216 }, 2217 /* 2218 * Intel 2219 */ 2220 { 2221 .vendor = PCI_VENDOR_ID_INTEL, 2222 .device = PCI_DEVICE_ID_INTEL_80960_RP, 2223 .subvendor = 0xe4bf, 2224 .subdevice = PCI_ANY_ID, 2225 .init = pci_inteli960ni_init, 2226 .setup = pci_default_setup, 2227 }, 2228 { 2229 .vendor = PCI_VENDOR_ID_INTEL, 2230 .device = PCI_DEVICE_ID_INTEL_8257X_SOL, 2231 .subvendor = PCI_ANY_ID, 2232 .subdevice = PCI_ANY_ID, 2233 .setup = skip_tx_en_setup, 2234 }, 2235 { 2236 .vendor = PCI_VENDOR_ID_INTEL, 2237 .device = PCI_DEVICE_ID_INTEL_82573L_SOL, 2238 .subvendor = PCI_ANY_ID, 2239 .subdevice = PCI_ANY_ID, 2240 .setup = skip_tx_en_setup, 2241 }, 2242 { 2243 .vendor = PCI_VENDOR_ID_INTEL, 2244 .device = PCI_DEVICE_ID_INTEL_82573E_SOL, 2245 .subvendor = PCI_ANY_ID, 2246 .subdevice = PCI_ANY_ID, 2247 .setup = skip_tx_en_setup, 2248 }, 2249 { 2250 .vendor = PCI_VENDOR_ID_INTEL, 2251 .device = PCI_DEVICE_ID_INTEL_CE4100_UART, 2252 .subvendor = PCI_ANY_ID, 2253 .subdevice = PCI_ANY_ID, 2254 .setup = ce4100_serial_setup, 2255 }, 2256 { 2257 .vendor = PCI_VENDOR_ID_INTEL, 2258 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT, 2259 .subvendor = PCI_ANY_ID, 2260 .subdevice = PCI_ANY_ID, 2261 .setup = kt_serial_setup, 2262 }, 2263 /* 2264 * ITE 2265 */ 2266 { 2267 .vendor = PCI_VENDOR_ID_ITE, 2268 .device = PCI_DEVICE_ID_ITE_8872, 2269 .subvendor = PCI_ANY_ID, 2270 .subdevice = PCI_ANY_ID, 2271 .init = pci_ite887x_init, 2272 .setup = pci_default_setup, 2273 .exit = pci_ite887x_exit, 2274 }, 2275 /* 2276 * National Instruments 2277 */ 2278 { 2279 .vendor = PCI_VENDOR_ID_NI, 2280 .device = PCI_DEVICE_ID_NI_PCI23216, 2281 .subvendor = PCI_ANY_ID, 2282 .subdevice = PCI_ANY_ID, 2283 .init = pci_ni8420_init, 2284 .setup = pci_default_setup, 2285 .exit = pci_ni8420_exit, 2286 }, 2287 { 2288 .vendor = PCI_VENDOR_ID_NI, 2289 .device = PCI_DEVICE_ID_NI_PCI2328, 2290 .subvendor = PCI_ANY_ID, 2291 .subdevice = PCI_ANY_ID, 2292 .init = pci_ni8420_init, 2293 .setup = pci_default_setup, 2294 .exit = pci_ni8420_exit, 2295 }, 2296 { 2297 .vendor = PCI_VENDOR_ID_NI, 2298 .device = PCI_DEVICE_ID_NI_PCI2324, 2299 .subvendor = PCI_ANY_ID, 2300 .subdevice = PCI_ANY_ID, 2301 .init = pci_ni8420_init, 2302 .setup = pci_default_setup, 2303 .exit = pci_ni8420_exit, 2304 }, 2305 { 2306 .vendor = PCI_VENDOR_ID_NI, 2307 .device = PCI_DEVICE_ID_NI_PCI2322, 2308 .subvendor = PCI_ANY_ID, 2309 .subdevice = PCI_ANY_ID, 2310 .init = pci_ni8420_init, 2311 .setup = pci_default_setup, 2312 .exit = pci_ni8420_exit, 2313 }, 2314 { 2315 .vendor = PCI_VENDOR_ID_NI, 2316 .device = PCI_DEVICE_ID_NI_PCI2324I, 2317 .subvendor = PCI_ANY_ID, 2318 .subdevice = PCI_ANY_ID, 2319 .init = pci_ni8420_init, 2320 .setup = pci_default_setup, 2321 .exit = pci_ni8420_exit, 2322 }, 2323 { 2324 .vendor = PCI_VENDOR_ID_NI, 2325 .device = PCI_DEVICE_ID_NI_PCI2322I, 2326 .subvendor = PCI_ANY_ID, 2327 .subdevice = PCI_ANY_ID, 2328 .init = pci_ni8420_init, 2329 .setup = pci_default_setup, 2330 .exit = pci_ni8420_exit, 2331 }, 2332 { 2333 .vendor = PCI_VENDOR_ID_NI, 2334 .device = PCI_DEVICE_ID_NI_PXI8420_23216, 2335 .subvendor = PCI_ANY_ID, 2336 .subdevice = PCI_ANY_ID, 2337 .init = pci_ni8420_init, 2338 .setup = pci_default_setup, 2339 .exit = pci_ni8420_exit, 2340 }, 2341 { 2342 .vendor = PCI_VENDOR_ID_NI, 2343 .device = PCI_DEVICE_ID_NI_PXI8420_2328, 2344 .subvendor = PCI_ANY_ID, 2345 .subdevice = PCI_ANY_ID, 2346 .init = pci_ni8420_init, 2347 .setup = pci_default_setup, 2348 .exit = pci_ni8420_exit, 2349 }, 2350 { 2351 .vendor = PCI_VENDOR_ID_NI, 2352 .device = PCI_DEVICE_ID_NI_PXI8420_2324, 2353 .subvendor = PCI_ANY_ID, 2354 .subdevice = PCI_ANY_ID, 2355 .init = pci_ni8420_init, 2356 .setup = pci_default_setup, 2357 .exit = pci_ni8420_exit, 2358 }, 2359 { 2360 .vendor = PCI_VENDOR_ID_NI, 2361 .device = PCI_DEVICE_ID_NI_PXI8420_2322, 2362 .subvendor = PCI_ANY_ID, 2363 .subdevice = PCI_ANY_ID, 2364 .init = pci_ni8420_init, 2365 .setup = pci_default_setup, 2366 .exit = pci_ni8420_exit, 2367 }, 2368 { 2369 .vendor = PCI_VENDOR_ID_NI, 2370 .device = PCI_DEVICE_ID_NI_PXI8422_2324, 2371 .subvendor = PCI_ANY_ID, 2372 .subdevice = PCI_ANY_ID, 2373 .init = pci_ni8420_init, 2374 .setup = pci_default_setup, 2375 .exit = pci_ni8420_exit, 2376 }, 2377 { 2378 .vendor = PCI_VENDOR_ID_NI, 2379 .device = PCI_DEVICE_ID_NI_PXI8422_2322, 2380 .subvendor = PCI_ANY_ID, 2381 .subdevice = PCI_ANY_ID, 2382 .init = pci_ni8420_init, 2383 .setup = pci_default_setup, 2384 .exit = pci_ni8420_exit, 2385 }, 2386 { 2387 .vendor = PCI_VENDOR_ID_NI, 2388 .device = PCI_ANY_ID, 2389 .subvendor = PCI_ANY_ID, 2390 .subdevice = PCI_ANY_ID, 2391 .init = pci_ni8430_init, 2392 .setup = pci_ni8430_setup, 2393 .exit = pci_ni8430_exit, 2394 }, 2395 /* Quatech */ 2396 { 2397 .vendor = PCI_VENDOR_ID_QUATECH, 2398 .device = PCI_ANY_ID, 2399 .subvendor = PCI_ANY_ID, 2400 .subdevice = PCI_ANY_ID, 2401 .init = pci_quatech_init, 2402 .setup = pci_quatech_setup, 2403 }, 2404 /* 2405 * Panacom 2406 */ 2407 { 2408 .vendor = PCI_VENDOR_ID_PANACOM, 2409 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM, 2410 .subvendor = PCI_ANY_ID, 2411 .subdevice = PCI_ANY_ID, 2412 .init = pci_plx9050_init, 2413 .setup = pci_default_setup, 2414 .exit = pci_plx9050_exit, 2415 }, 2416 { 2417 .vendor = PCI_VENDOR_ID_PANACOM, 2418 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM, 2419 .subvendor = PCI_ANY_ID, 2420 .subdevice = PCI_ANY_ID, 2421 .init = pci_plx9050_init, 2422 .setup = pci_default_setup, 2423 .exit = pci_plx9050_exit, 2424 }, 2425 /* 2426 * PLX 2427 */ 2428 { 2429 .vendor = PCI_VENDOR_ID_PLX, 2430 .device = PCI_DEVICE_ID_PLX_9050, 2431 .subvendor = PCI_SUBVENDOR_ID_EXSYS, 2432 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055, 2433 .init = pci_plx9050_init, 2434 .setup = pci_default_setup, 2435 .exit = pci_plx9050_exit, 2436 }, 2437 { 2438 .vendor = PCI_VENDOR_ID_PLX, 2439 .device = PCI_DEVICE_ID_PLX_9050, 2440 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN, 2441 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2, 2442 .init = pci_plx9050_init, 2443 .setup = pci_default_setup, 2444 .exit = pci_plx9050_exit, 2445 }, 2446 { 2447 .vendor = PCI_VENDOR_ID_PLX, 2448 .device = PCI_DEVICE_ID_PLX_ROMULUS, 2449 .subvendor = PCI_VENDOR_ID_PLX, 2450 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS, 2451 .init = pci_plx9050_init, 2452 .setup = pci_default_setup, 2453 .exit = pci_plx9050_exit, 2454 }, 2455 /* 2456 * SBS Technologies, Inc., PMC-OCTALPRO 232 2457 */ 2458 { 2459 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2460 .device = PCI_DEVICE_ID_OCTPRO, 2461 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2462 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232, 2463 .init = sbs_init, 2464 .setup = sbs_setup, 2465 .exit = sbs_exit, 2466 }, 2467 /* 2468 * SBS Technologies, Inc., PMC-OCTALPRO 422 2469 */ 2470 { 2471 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2472 .device = PCI_DEVICE_ID_OCTPRO, 2473 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2474 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422, 2475 .init = sbs_init, 2476 .setup = sbs_setup, 2477 .exit = sbs_exit, 2478 }, 2479 /* 2480 * SBS Technologies, Inc., P-Octal 232 2481 */ 2482 { 2483 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2484 .device = PCI_DEVICE_ID_OCTPRO, 2485 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2486 .subdevice = PCI_SUBDEVICE_ID_POCTAL232, 2487 .init = sbs_init, 2488 .setup = sbs_setup, 2489 .exit = sbs_exit, 2490 }, 2491 /* 2492 * SBS Technologies, Inc., P-Octal 422 2493 */ 2494 { 2495 .vendor = PCI_VENDOR_ID_SBSMODULARIO, 2496 .device = PCI_DEVICE_ID_OCTPRO, 2497 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO, 2498 .subdevice = PCI_SUBDEVICE_ID_POCTAL422, 2499 .init = sbs_init, 2500 .setup = sbs_setup, 2501 .exit = sbs_exit, 2502 }, 2503 /* 2504 * SIIG cards - these may be called via parport_serial 2505 */ 2506 { 2507 .vendor = PCI_VENDOR_ID_SIIG, 2508 .device = PCI_ANY_ID, 2509 .subvendor = PCI_ANY_ID, 2510 .subdevice = PCI_ANY_ID, 2511 .init = pci_siig_init, 2512 .setup = pci_siig_setup, 2513 }, 2514 /* Systembase */ 2515 { 2516 .vendor = PCI_VENDOR_ID_SYSTEMBASE, 2517 .device = 0x0008, 2518 .subvendor = PCI_ANY_ID, 2519 .subdevice = PCI_ANY_ID, 2520 .init = pci_systembase_init, 2521 .setup = pci_default_setup, 2522 .exit = pci_systembase_exit, 2523 }, 2524 /* 2525 * Titan cards 2526 */ 2527 { 2528 .vendor = PCI_VENDOR_ID_TITAN, 2529 .device = PCI_DEVICE_ID_TITAN_400L, 2530 .subvendor = PCI_ANY_ID, 2531 .subdevice = PCI_ANY_ID, 2532 .setup = titan_400l_800l_setup, 2533 }, 2534 { 2535 .vendor = PCI_VENDOR_ID_TITAN, 2536 .device = PCI_DEVICE_ID_TITAN_800L, 2537 .subvendor = PCI_ANY_ID, 2538 .subdevice = PCI_ANY_ID, 2539 .setup = titan_400l_800l_setup, 2540 }, 2541 /* 2542 * Timedia cards 2543 */ 2544 { 2545 .vendor = PCI_VENDOR_ID_TIMEDIA, 2546 .device = PCI_DEVICE_ID_TIMEDIA_1889, 2547 .subvendor = PCI_VENDOR_ID_TIMEDIA, 2548 .subdevice = PCI_ANY_ID, 2549 .probe = pci_timedia_probe, 2550 .init = pci_timedia_init, 2551 .setup = pci_timedia_setup, 2552 }, 2553 { 2554 .vendor = PCI_VENDOR_ID_TIMEDIA, 2555 .device = PCI_ANY_ID, 2556 .subvendor = PCI_ANY_ID, 2557 .subdevice = PCI_ANY_ID, 2558 .setup = pci_timedia_setup, 2559 }, 2560 /* 2561 * Sunix PCI serial boards 2562 */ 2563 { 2564 .vendor = PCI_VENDOR_ID_SUNIX, 2565 .device = PCI_DEVICE_ID_SUNIX_1999, 2566 .subvendor = PCI_VENDOR_ID_SUNIX, 2567 .subdevice = PCI_ANY_ID, 2568 .setup = pci_sunix_setup, 2569 }, 2570 /* 2571 * Xircom cards 2572 */ 2573 { 2574 .vendor = PCI_VENDOR_ID_XIRCOM, 2575 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM, 2576 .subvendor = PCI_ANY_ID, 2577 .subdevice = PCI_ANY_ID, 2578 .init = pci_xircom_init, 2579 .setup = pci_default_setup, 2580 }, 2581 /* 2582 * Netmos cards - these may be called via parport_serial 2583 */ 2584 { 2585 .vendor = PCI_VENDOR_ID_NETMOS, 2586 .device = PCI_ANY_ID, 2587 .subvendor = PCI_ANY_ID, 2588 .subdevice = PCI_ANY_ID, 2589 .init = pci_netmos_init, 2590 .setup = pci_netmos_9900_setup, 2591 }, 2592 { 2593 .vendor = PCIE_VENDOR_ID_ASIX, 2594 .device = PCI_ANY_ID, 2595 .subvendor = PCI_ANY_ID, 2596 .subdevice = PCI_ANY_ID, 2597 .init = pci_netmos_init, 2598 .setup = pci_netmos_9900_setup, 2599 }, 2600 /* 2601 * EndRun Technologies 2602 */ 2603 { 2604 .vendor = PCI_VENDOR_ID_ENDRUN, 2605 .device = PCI_ANY_ID, 2606 .subvendor = PCI_ANY_ID, 2607 .subdevice = PCI_ANY_ID, 2608 .init = pci_oxsemi_tornado_init, 2609 .setup = pci_default_setup, 2610 }, 2611 /* 2612 * For Oxford Semiconductor Tornado based devices 2613 */ 2614 { 2615 .vendor = PCI_VENDOR_ID_OXSEMI, 2616 .device = PCI_ANY_ID, 2617 .subvendor = PCI_ANY_ID, 2618 .subdevice = PCI_ANY_ID, 2619 .init = pci_oxsemi_tornado_init, 2620 .setup = pci_oxsemi_tornado_setup, 2621 }, 2622 { 2623 .vendor = PCI_VENDOR_ID_MAINPINE, 2624 .device = PCI_ANY_ID, 2625 .subvendor = PCI_ANY_ID, 2626 .subdevice = PCI_ANY_ID, 2627 .init = pci_oxsemi_tornado_init, 2628 .setup = pci_oxsemi_tornado_setup, 2629 }, 2630 { 2631 .vendor = PCI_VENDOR_ID_DIGI, 2632 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM, 2633 .subvendor = PCI_SUBVENDOR_ID_IBM, 2634 .subdevice = PCI_ANY_ID, 2635 .init = pci_oxsemi_tornado_init, 2636 .setup = pci_oxsemi_tornado_setup, 2637 }, 2638 /* 2639 * Brainboxes devices - all Oxsemi based 2640 */ 2641 { 2642 .vendor = PCI_VENDOR_ID_INTASHIELD, 2643 .device = 0x4027, 2644 .subvendor = PCI_ANY_ID, 2645 .subdevice = PCI_ANY_ID, 2646 .init = pci_oxsemi_tornado_init, 2647 .setup = pci_oxsemi_tornado_setup, 2648 }, 2649 { 2650 .vendor = PCI_VENDOR_ID_INTASHIELD, 2651 .device = 0x4028, 2652 .subvendor = PCI_ANY_ID, 2653 .subdevice = PCI_ANY_ID, 2654 .init = pci_oxsemi_tornado_init, 2655 .setup = pci_oxsemi_tornado_setup, 2656 }, 2657 { 2658 .vendor = PCI_VENDOR_ID_INTASHIELD, 2659 .device = 0x4029, 2660 .subvendor = PCI_ANY_ID, 2661 .subdevice = PCI_ANY_ID, 2662 .init = pci_oxsemi_tornado_init, 2663 .setup = pci_oxsemi_tornado_setup, 2664 }, 2665 { 2666 .vendor = PCI_VENDOR_ID_INTASHIELD, 2667 .device = 0x4019, 2668 .subvendor = PCI_ANY_ID, 2669 .subdevice = PCI_ANY_ID, 2670 .init = pci_oxsemi_tornado_init, 2671 .setup = pci_oxsemi_tornado_setup, 2672 }, 2673 { 2674 .vendor = PCI_VENDOR_ID_INTASHIELD, 2675 .device = 0x4016, 2676 .subvendor = PCI_ANY_ID, 2677 .subdevice = PCI_ANY_ID, 2678 .init = pci_oxsemi_tornado_init, 2679 .setup = pci_oxsemi_tornado_setup, 2680 }, 2681 { 2682 .vendor = PCI_VENDOR_ID_INTASHIELD, 2683 .device = 0x4015, 2684 .subvendor = PCI_ANY_ID, 2685 .subdevice = PCI_ANY_ID, 2686 .init = pci_oxsemi_tornado_init, 2687 .setup = pci_oxsemi_tornado_setup, 2688 }, 2689 { 2690 .vendor = PCI_VENDOR_ID_INTASHIELD, 2691 .device = 0x400A, 2692 .subvendor = PCI_ANY_ID, 2693 .subdevice = PCI_ANY_ID, 2694 .init = pci_oxsemi_tornado_init, 2695 .setup = pci_oxsemi_tornado_setup, 2696 }, 2697 { 2698 .vendor = PCI_VENDOR_ID_INTASHIELD, 2699 .device = 0x400E, 2700 .subvendor = PCI_ANY_ID, 2701 .subdevice = PCI_ANY_ID, 2702 .init = pci_oxsemi_tornado_init, 2703 .setup = pci_oxsemi_tornado_setup, 2704 }, 2705 { 2706 .vendor = PCI_VENDOR_ID_INTASHIELD, 2707 .device = 0x400C, 2708 .subvendor = PCI_ANY_ID, 2709 .subdevice = PCI_ANY_ID, 2710 .init = pci_oxsemi_tornado_init, 2711 .setup = pci_oxsemi_tornado_setup, 2712 }, 2713 { 2714 .vendor = PCI_VENDOR_ID_INTASHIELD, 2715 .device = 0x400B, 2716 .subvendor = PCI_ANY_ID, 2717 .subdevice = PCI_ANY_ID, 2718 .init = pci_oxsemi_tornado_init, 2719 .setup = pci_oxsemi_tornado_setup, 2720 }, 2721 { 2722 .vendor = PCI_VENDOR_ID_INTASHIELD, 2723 .device = 0x400F, 2724 .subvendor = PCI_ANY_ID, 2725 .subdevice = PCI_ANY_ID, 2726 .init = pci_oxsemi_tornado_init, 2727 .setup = pci_oxsemi_tornado_setup, 2728 }, 2729 { 2730 .vendor = PCI_VENDOR_ID_INTASHIELD, 2731 .device = 0x4010, 2732 .subvendor = PCI_ANY_ID, 2733 .subdevice = PCI_ANY_ID, 2734 .init = pci_oxsemi_tornado_init, 2735 .setup = pci_oxsemi_tornado_setup, 2736 }, 2737 { 2738 .vendor = PCI_VENDOR_ID_INTASHIELD, 2739 .device = 0x4011, 2740 .subvendor = PCI_ANY_ID, 2741 .subdevice = PCI_ANY_ID, 2742 .init = pci_oxsemi_tornado_init, 2743 .setup = pci_oxsemi_tornado_setup, 2744 }, 2745 { 2746 .vendor = PCI_VENDOR_ID_INTASHIELD, 2747 .device = 0x401D, 2748 .subvendor = PCI_ANY_ID, 2749 .subdevice = PCI_ANY_ID, 2750 .init = pci_oxsemi_tornado_init, 2751 .setup = pci_oxsemi_tornado_setup, 2752 }, 2753 { 2754 .vendor = PCI_VENDOR_ID_INTASHIELD, 2755 .device = 0x401E, 2756 .subvendor = PCI_ANY_ID, 2757 .subdevice = PCI_ANY_ID, 2758 .init = pci_oxsemi_tornado_init, 2759 .setup = pci_oxsemi_tornado_setup, 2760 }, 2761 { 2762 .vendor = PCI_VENDOR_ID_INTASHIELD, 2763 .device = 0x4013, 2764 .subvendor = PCI_ANY_ID, 2765 .subdevice = PCI_ANY_ID, 2766 .init = pci_oxsemi_tornado_init, 2767 .setup = pci_oxsemi_tornado_setup, 2768 }, 2769 { 2770 .vendor = PCI_VENDOR_ID_INTASHIELD, 2771 .device = 0x4017, 2772 .subvendor = PCI_ANY_ID, 2773 .subdevice = PCI_ANY_ID, 2774 .init = pci_oxsemi_tornado_init, 2775 .setup = pci_oxsemi_tornado_setup, 2776 }, 2777 { 2778 .vendor = PCI_VENDOR_ID_INTASHIELD, 2779 .device = 0x4018, 2780 .subvendor = PCI_ANY_ID, 2781 .subdevice = PCI_ANY_ID, 2782 .init = pci_oxsemi_tornado_init, 2783 .setup = pci_oxsemi_tornado_setup, 2784 }, 2785 { 2786 .vendor = PCI_VENDOR_ID_INTASHIELD, 2787 .device = 0x4026, 2788 .subvendor = PCI_ANY_ID, 2789 .subdevice = PCI_ANY_ID, 2790 .init = pci_oxsemi_tornado_init, 2791 .setup = pci_oxsemi_tornado_setup, 2792 }, 2793 { 2794 .vendor = PCI_VENDOR_ID_INTASHIELD, 2795 .device = 0x4021, 2796 .subvendor = PCI_ANY_ID, 2797 .subdevice = PCI_ANY_ID, 2798 .init = pci_oxsemi_tornado_init, 2799 .setup = pci_oxsemi_tornado_setup, 2800 }, 2801 { 2802 .vendor = PCI_VENDOR_ID_INTEL, 2803 .device = 0x8811, 2804 .subvendor = PCI_ANY_ID, 2805 .subdevice = PCI_ANY_ID, 2806 .init = pci_eg20t_init, 2807 .setup = pci_default_setup, 2808 }, 2809 { 2810 .vendor = PCI_VENDOR_ID_INTEL, 2811 .device = 0x8812, 2812 .subvendor = PCI_ANY_ID, 2813 .subdevice = PCI_ANY_ID, 2814 .init = pci_eg20t_init, 2815 .setup = pci_default_setup, 2816 }, 2817 { 2818 .vendor = PCI_VENDOR_ID_INTEL, 2819 .device = 0x8813, 2820 .subvendor = PCI_ANY_ID, 2821 .subdevice = PCI_ANY_ID, 2822 .init = pci_eg20t_init, 2823 .setup = pci_default_setup, 2824 }, 2825 { 2826 .vendor = PCI_VENDOR_ID_INTEL, 2827 .device = 0x8814, 2828 .subvendor = PCI_ANY_ID, 2829 .subdevice = PCI_ANY_ID, 2830 .init = pci_eg20t_init, 2831 .setup = pci_default_setup, 2832 }, 2833 { 2834 .vendor = 0x10DB, 2835 .device = 0x8027, 2836 .subvendor = PCI_ANY_ID, 2837 .subdevice = PCI_ANY_ID, 2838 .init = pci_eg20t_init, 2839 .setup = pci_default_setup, 2840 }, 2841 { 2842 .vendor = 0x10DB, 2843 .device = 0x8028, 2844 .subvendor = PCI_ANY_ID, 2845 .subdevice = PCI_ANY_ID, 2846 .init = pci_eg20t_init, 2847 .setup = pci_default_setup, 2848 }, 2849 { 2850 .vendor = 0x10DB, 2851 .device = 0x8029, 2852 .subvendor = PCI_ANY_ID, 2853 .subdevice = PCI_ANY_ID, 2854 .init = pci_eg20t_init, 2855 .setup = pci_default_setup, 2856 }, 2857 { 2858 .vendor = 0x10DB, 2859 .device = 0x800C, 2860 .subvendor = PCI_ANY_ID, 2861 .subdevice = PCI_ANY_ID, 2862 .init = pci_eg20t_init, 2863 .setup = pci_default_setup, 2864 }, 2865 { 2866 .vendor = 0x10DB, 2867 .device = 0x800D, 2868 .subvendor = PCI_ANY_ID, 2869 .subdevice = PCI_ANY_ID, 2870 .init = pci_eg20t_init, 2871 .setup = pci_default_setup, 2872 }, 2873 /* 2874 * Cronyx Omega PCI (PLX-chip based) 2875 */ 2876 { 2877 .vendor = PCI_VENDOR_ID_PLX, 2878 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA, 2879 .subvendor = PCI_ANY_ID, 2880 .subdevice = PCI_ANY_ID, 2881 .setup = pci_omegapci_setup, 2882 }, 2883 /* WCH CH353 1S1P card (16550 clone) */ 2884 { 2885 .vendor = PCI_VENDOR_ID_WCHCN, 2886 .device = PCI_DEVICE_ID_WCHCN_CH353_1S1P, 2887 .subvendor = PCI_ANY_ID, 2888 .subdevice = PCI_ANY_ID, 2889 .setup = pci_wch_ch353_setup, 2890 }, 2891 /* WCH CH353 2S1P card (16550 clone) */ 2892 { 2893 .vendor = PCI_VENDOR_ID_WCHCN, 2894 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1P, 2895 .subvendor = PCI_ANY_ID, 2896 .subdevice = PCI_ANY_ID, 2897 .setup = pci_wch_ch353_setup, 2898 }, 2899 /* WCH CH353 4S card (16550 clone) */ 2900 { 2901 .vendor = PCI_VENDOR_ID_WCHCN, 2902 .device = PCI_DEVICE_ID_WCHCN_CH353_4S, 2903 .subvendor = PCI_ANY_ID, 2904 .subdevice = PCI_ANY_ID, 2905 .setup = pci_wch_ch353_setup, 2906 }, 2907 /* WCH CH353 2S1PF card (16550 clone) */ 2908 { 2909 .vendor = PCI_VENDOR_ID_WCHCN, 2910 .device = PCI_DEVICE_ID_WCHCN_CH353_2S1PF, 2911 .subvendor = PCI_ANY_ID, 2912 .subdevice = PCI_ANY_ID, 2913 .setup = pci_wch_ch353_setup, 2914 }, 2915 /* WCH CH352 2S card (16550 clone) */ 2916 { 2917 .vendor = PCI_VENDOR_ID_WCHCN, 2918 .device = PCI_DEVICE_ID_WCHCN_CH352_2S, 2919 .subvendor = PCI_ANY_ID, 2920 .subdevice = PCI_ANY_ID, 2921 .setup = pci_wch_ch353_setup, 2922 }, 2923 /* WCH CH355 4S card (16550 clone) */ 2924 { 2925 .vendor = PCI_VENDOR_ID_WCHCN, 2926 .device = PCI_DEVICE_ID_WCHCN_CH355_4S, 2927 .subvendor = PCI_ANY_ID, 2928 .subdevice = PCI_ANY_ID, 2929 .setup = pci_wch_ch355_setup, 2930 }, 2931 /* WCH CH382 2S card (16850 clone) */ 2932 { 2933 .vendor = PCI_VENDOR_ID_WCHIC, 2934 .device = PCI_DEVICE_ID_WCHIC_CH382_2S, 2935 .subvendor = PCI_ANY_ID, 2936 .subdevice = PCI_ANY_ID, 2937 .setup = pci_wch_ch38x_setup, 2938 }, 2939 /* WCH CH382 2S1P card (16850 clone) */ 2940 { 2941 .vendor = PCI_VENDOR_ID_WCHIC, 2942 .device = PCI_DEVICE_ID_WCHIC_CH382_2S1P, 2943 .subvendor = PCI_ANY_ID, 2944 .subdevice = PCI_ANY_ID, 2945 .setup = pci_wch_ch38x_setup, 2946 }, 2947 /* WCH CH384 4S card (16850 clone) */ 2948 { 2949 .vendor = PCI_VENDOR_ID_WCHIC, 2950 .device = PCI_DEVICE_ID_WCHIC_CH384_4S, 2951 .subvendor = PCI_ANY_ID, 2952 .subdevice = PCI_ANY_ID, 2953 .setup = pci_wch_ch38x_setup, 2954 }, 2955 /* WCH CH384 8S card (16850 clone) */ 2956 { 2957 .vendor = PCI_VENDOR_ID_WCHIC, 2958 .device = PCI_DEVICE_ID_WCHIC_CH384_8S, 2959 .subvendor = PCI_ANY_ID, 2960 .subdevice = PCI_ANY_ID, 2961 .init = pci_wch_ch38x_init, 2962 .exit = pci_wch_ch38x_exit, 2963 .setup = pci_wch_ch38x_setup, 2964 }, 2965 /* 2966 * Broadcom TruManage (NetXtreme) 2967 */ 2968 { 2969 .vendor = PCI_VENDOR_ID_BROADCOM, 2970 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE, 2971 .subvendor = PCI_ANY_ID, 2972 .subdevice = PCI_ANY_ID, 2973 .setup = pci_brcm_trumanage_setup, 2974 }, 2975 { 2976 .vendor = 0x1c29, 2977 .device = 0x1104, 2978 .subvendor = PCI_ANY_ID, 2979 .subdevice = PCI_ANY_ID, 2980 .setup = pci_fintek_setup, 2981 .init = pci_fintek_init, 2982 }, 2983 { 2984 .vendor = 0x1c29, 2985 .device = 0x1108, 2986 .subvendor = PCI_ANY_ID, 2987 .subdevice = PCI_ANY_ID, 2988 .setup = pci_fintek_setup, 2989 .init = pci_fintek_init, 2990 }, 2991 { 2992 .vendor = 0x1c29, 2993 .device = 0x1112, 2994 .subvendor = PCI_ANY_ID, 2995 .subdevice = PCI_ANY_ID, 2996 .setup = pci_fintek_setup, 2997 .init = pci_fintek_init, 2998 }, 2999 /* 3000 * MOXA 3001 */ 3002 { 3003 .vendor = PCI_VENDOR_ID_MOXA, 3004 .device = PCI_ANY_ID, 3005 .subvendor = PCI_ANY_ID, 3006 .subdevice = PCI_ANY_ID, 3007 .init = pci_moxa_init, 3008 .setup = pci_moxa_setup, 3009 }, 3010 { 3011 .vendor = 0x1c29, 3012 .device = 0x1204, 3013 .subvendor = PCI_ANY_ID, 3014 .subdevice = PCI_ANY_ID, 3015 .setup = pci_fintek_f815xxa_setup, 3016 .init = pci_fintek_f815xxa_init, 3017 }, 3018 { 3019 .vendor = 0x1c29, 3020 .device = 0x1208, 3021 .subvendor = PCI_ANY_ID, 3022 .subdevice = PCI_ANY_ID, 3023 .setup = pci_fintek_f815xxa_setup, 3024 .init = pci_fintek_f815xxa_init, 3025 }, 3026 { 3027 .vendor = 0x1c29, 3028 .device = 0x1212, 3029 .subvendor = PCI_ANY_ID, 3030 .subdevice = PCI_ANY_ID, 3031 .setup = pci_fintek_f815xxa_setup, 3032 .init = pci_fintek_f815xxa_init, 3033 }, 3034 3035 /* 3036 * Default "match everything" terminator entry 3037 */ 3038 { 3039 .vendor = PCI_ANY_ID, 3040 .device = PCI_ANY_ID, 3041 .subvendor = PCI_ANY_ID, 3042 .subdevice = PCI_ANY_ID, 3043 .setup = pci_default_setup, 3044 } 3045 }; 3046 3047 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id) 3048 { 3049 return quirk_id == PCI_ANY_ID || quirk_id == dev_id; 3050 } 3051 3052 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev) 3053 { 3054 struct pci_serial_quirk *quirk; 3055 3056 for (quirk = pci_serial_quirks; ; quirk++) 3057 if (quirk_id_matches(quirk->vendor, dev->vendor) && 3058 quirk_id_matches(quirk->device, dev->device) && 3059 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) && 3060 quirk_id_matches(quirk->subdevice, dev->subsystem_device)) 3061 break; 3062 return quirk; 3063 } 3064 3065 /* 3066 * This is the configuration table for all of the PCI serial boards 3067 * which we support. It is directly indexed by the pci_board_num_t enum 3068 * value, which is encoded in the pci_device_id PCI probe table's 3069 * driver_data member. 3070 * 3071 * The makeup of these names are: 3072 * pbn_bn{_bt}_n_baud{_offsetinhex} 3073 * 3074 * bn = PCI BAR number 3075 * bt = Index using PCI BARs 3076 * n = number of serial ports 3077 * baud = baud rate 3078 * offsetinhex = offset for each sequential port (in hex) 3079 * 3080 * This table is sorted by (in order): bn, bt, baud, offsetindex, n. 3081 * 3082 * Please note: in theory if n = 1, _bt infix should make no difference. 3083 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200 3084 */ 3085 enum pci_board_num_t { 3086 pbn_default = 0, 3087 3088 pbn_b0_1_115200, 3089 pbn_b0_2_115200, 3090 pbn_b0_4_115200, 3091 pbn_b0_5_115200, 3092 pbn_b0_8_115200, 3093 3094 pbn_b0_1_921600, 3095 pbn_b0_2_921600, 3096 pbn_b0_4_921600, 3097 pbn_b0_8_921600, 3098 3099 pbn_b0_2_1130000, 3100 3101 pbn_b0_4_1152000, 3102 3103 pbn_b0_4_1250000, 3104 3105 pbn_b0_2_1843200, 3106 pbn_b0_4_1843200, 3107 3108 pbn_b0_1_15625000, 3109 3110 pbn_b0_bt_1_115200, 3111 pbn_b0_bt_2_115200, 3112 pbn_b0_bt_4_115200, 3113 pbn_b0_bt_8_115200, 3114 3115 pbn_b0_bt_1_460800, 3116 pbn_b0_bt_2_460800, 3117 pbn_b0_bt_4_460800, 3118 3119 pbn_b0_bt_1_921600, 3120 pbn_b0_bt_2_921600, 3121 pbn_b0_bt_4_921600, 3122 pbn_b0_bt_8_921600, 3123 3124 pbn_b1_1_115200, 3125 pbn_b1_2_115200, 3126 pbn_b1_4_115200, 3127 pbn_b1_8_115200, 3128 pbn_b1_16_115200, 3129 3130 pbn_b1_1_921600, 3131 pbn_b1_2_921600, 3132 pbn_b1_4_921600, 3133 pbn_b1_8_921600, 3134 3135 pbn_b1_2_1250000, 3136 3137 pbn_b1_bt_1_115200, 3138 pbn_b1_bt_2_115200, 3139 pbn_b1_bt_4_115200, 3140 3141 pbn_b1_bt_2_921600, 3142 3143 pbn_b1_1_1382400, 3144 pbn_b1_2_1382400, 3145 pbn_b1_4_1382400, 3146 pbn_b1_8_1382400, 3147 3148 pbn_b2_1_115200, 3149 pbn_b2_2_115200, 3150 pbn_b2_4_115200, 3151 pbn_b2_8_115200, 3152 3153 pbn_b2_1_460800, 3154 pbn_b2_4_460800, 3155 pbn_b2_8_460800, 3156 pbn_b2_16_460800, 3157 3158 pbn_b2_1_921600, 3159 pbn_b2_4_921600, 3160 pbn_b2_8_921600, 3161 3162 pbn_b2_8_1152000, 3163 3164 pbn_b2_bt_1_115200, 3165 pbn_b2_bt_2_115200, 3166 pbn_b2_bt_4_115200, 3167 3168 pbn_b2_bt_2_921600, 3169 pbn_b2_bt_4_921600, 3170 3171 pbn_b3_2_115200, 3172 pbn_b3_4_115200, 3173 pbn_b3_8_115200, 3174 3175 pbn_b4_bt_2_921600, 3176 pbn_b4_bt_4_921600, 3177 pbn_b4_bt_8_921600, 3178 3179 /* 3180 * Board-specific versions. 3181 */ 3182 pbn_panacom, 3183 pbn_panacom2, 3184 pbn_panacom4, 3185 pbn_plx_romulus, 3186 pbn_oxsemi, 3187 pbn_oxsemi_1_15625000, 3188 pbn_oxsemi_2_15625000, 3189 pbn_oxsemi_4_15625000, 3190 pbn_oxsemi_8_15625000, 3191 pbn_intel_i960, 3192 pbn_sgi_ioc3, 3193 pbn_computone_4, 3194 pbn_computone_6, 3195 pbn_computone_8, 3196 pbn_sbsxrsio, 3197 pbn_pasemi_1682M, 3198 pbn_ni8430_2, 3199 pbn_ni8430_4, 3200 pbn_ni8430_8, 3201 pbn_ni8430_16, 3202 pbn_ADDIDATA_PCIe_1_3906250, 3203 pbn_ADDIDATA_PCIe_2_3906250, 3204 pbn_ADDIDATA_PCIe_4_3906250, 3205 pbn_ADDIDATA_PCIe_8_3906250, 3206 pbn_ce4100_1_115200, 3207 pbn_omegapci, 3208 pbn_NETMOS9900_2s_115200, 3209 pbn_brcm_trumanage, 3210 pbn_fintek_4, 3211 pbn_fintek_8, 3212 pbn_fintek_12, 3213 pbn_fintek_F81504A, 3214 pbn_fintek_F81508A, 3215 pbn_fintek_F81512A, 3216 pbn_wch382_2, 3217 pbn_wch384_4, 3218 pbn_wch384_8, 3219 pbn_sunix_pci_1s, 3220 pbn_sunix_pci_2s, 3221 pbn_sunix_pci_4s, 3222 pbn_sunix_pci_8s, 3223 pbn_sunix_pci_16s, 3224 pbn_titan_1_4000000, 3225 pbn_titan_2_4000000, 3226 pbn_titan_4_4000000, 3227 pbn_titan_8_4000000, 3228 pbn_moxa_2, 3229 pbn_moxa_4, 3230 pbn_moxa_8, 3231 }; 3232 3233 /* 3234 * uart_offset - the space between channels 3235 * reg_shift - describes how the UART registers are mapped 3236 * to PCI memory by the card. 3237 * For example IER register on SBS, Inc. PMC-OctPro is located at 3238 * offset 0x10 from the UART base, while UART_IER is defined as 1 3239 * in include/linux/serial_reg.h, 3240 * see first lines of serial_in() and serial_out() in 8250.c 3241 */ 3242 3243 static struct pciserial_board pci_boards[] = { 3244 [pbn_default] = { 3245 .flags = FL_BASE0, 3246 .num_ports = 1, 3247 .base_baud = 115200, 3248 .uart_offset = 8, 3249 }, 3250 [pbn_b0_1_115200] = { 3251 .flags = FL_BASE0, 3252 .num_ports = 1, 3253 .base_baud = 115200, 3254 .uart_offset = 8, 3255 }, 3256 [pbn_b0_2_115200] = { 3257 .flags = FL_BASE0, 3258 .num_ports = 2, 3259 .base_baud = 115200, 3260 .uart_offset = 8, 3261 }, 3262 [pbn_b0_4_115200] = { 3263 .flags = FL_BASE0, 3264 .num_ports = 4, 3265 .base_baud = 115200, 3266 .uart_offset = 8, 3267 }, 3268 [pbn_b0_5_115200] = { 3269 .flags = FL_BASE0, 3270 .num_ports = 5, 3271 .base_baud = 115200, 3272 .uart_offset = 8, 3273 }, 3274 [pbn_b0_8_115200] = { 3275 .flags = FL_BASE0, 3276 .num_ports = 8, 3277 .base_baud = 115200, 3278 .uart_offset = 8, 3279 }, 3280 [pbn_b0_1_921600] = { 3281 .flags = FL_BASE0, 3282 .num_ports = 1, 3283 .base_baud = 921600, 3284 .uart_offset = 8, 3285 }, 3286 [pbn_b0_2_921600] = { 3287 .flags = FL_BASE0, 3288 .num_ports = 2, 3289 .base_baud = 921600, 3290 .uart_offset = 8, 3291 }, 3292 [pbn_b0_4_921600] = { 3293 .flags = FL_BASE0, 3294 .num_ports = 4, 3295 .base_baud = 921600, 3296 .uart_offset = 8, 3297 }, 3298 [pbn_b0_8_921600] = { 3299 .flags = FL_BASE0, 3300 .num_ports = 8, 3301 .base_baud = 921600, 3302 .uart_offset = 8, 3303 }, 3304 3305 [pbn_b0_2_1130000] = { 3306 .flags = FL_BASE0, 3307 .num_ports = 2, 3308 .base_baud = 1130000, 3309 .uart_offset = 8, 3310 }, 3311 3312 [pbn_b0_4_1152000] = { 3313 .flags = FL_BASE0, 3314 .num_ports = 4, 3315 .base_baud = 1152000, 3316 .uart_offset = 8, 3317 }, 3318 3319 [pbn_b0_4_1250000] = { 3320 .flags = FL_BASE0, 3321 .num_ports = 4, 3322 .base_baud = 1250000, 3323 .uart_offset = 8, 3324 }, 3325 3326 [pbn_b0_2_1843200] = { 3327 .flags = FL_BASE0, 3328 .num_ports = 2, 3329 .base_baud = 1843200, 3330 .uart_offset = 8, 3331 }, 3332 [pbn_b0_4_1843200] = { 3333 .flags = FL_BASE0, 3334 .num_ports = 4, 3335 .base_baud = 1843200, 3336 .uart_offset = 8, 3337 }, 3338 3339 [pbn_b0_1_15625000] = { 3340 .flags = FL_BASE0, 3341 .num_ports = 1, 3342 .base_baud = 15625000, 3343 .uart_offset = 8, 3344 }, 3345 3346 [pbn_b0_bt_1_115200] = { 3347 .flags = FL_BASE0|FL_BASE_BARS, 3348 .num_ports = 1, 3349 .base_baud = 115200, 3350 .uart_offset = 8, 3351 }, 3352 [pbn_b0_bt_2_115200] = { 3353 .flags = FL_BASE0|FL_BASE_BARS, 3354 .num_ports = 2, 3355 .base_baud = 115200, 3356 .uart_offset = 8, 3357 }, 3358 [pbn_b0_bt_4_115200] = { 3359 .flags = FL_BASE0|FL_BASE_BARS, 3360 .num_ports = 4, 3361 .base_baud = 115200, 3362 .uart_offset = 8, 3363 }, 3364 [pbn_b0_bt_8_115200] = { 3365 .flags = FL_BASE0|FL_BASE_BARS, 3366 .num_ports = 8, 3367 .base_baud = 115200, 3368 .uart_offset = 8, 3369 }, 3370 3371 [pbn_b0_bt_1_460800] = { 3372 .flags = FL_BASE0|FL_BASE_BARS, 3373 .num_ports = 1, 3374 .base_baud = 460800, 3375 .uart_offset = 8, 3376 }, 3377 [pbn_b0_bt_2_460800] = { 3378 .flags = FL_BASE0|FL_BASE_BARS, 3379 .num_ports = 2, 3380 .base_baud = 460800, 3381 .uart_offset = 8, 3382 }, 3383 [pbn_b0_bt_4_460800] = { 3384 .flags = FL_BASE0|FL_BASE_BARS, 3385 .num_ports = 4, 3386 .base_baud = 460800, 3387 .uart_offset = 8, 3388 }, 3389 3390 [pbn_b0_bt_1_921600] = { 3391 .flags = FL_BASE0|FL_BASE_BARS, 3392 .num_ports = 1, 3393 .base_baud = 921600, 3394 .uart_offset = 8, 3395 }, 3396 [pbn_b0_bt_2_921600] = { 3397 .flags = FL_BASE0|FL_BASE_BARS, 3398 .num_ports = 2, 3399 .base_baud = 921600, 3400 .uart_offset = 8, 3401 }, 3402 [pbn_b0_bt_4_921600] = { 3403 .flags = FL_BASE0|FL_BASE_BARS, 3404 .num_ports = 4, 3405 .base_baud = 921600, 3406 .uart_offset = 8, 3407 }, 3408 [pbn_b0_bt_8_921600] = { 3409 .flags = FL_BASE0|FL_BASE_BARS, 3410 .num_ports = 8, 3411 .base_baud = 921600, 3412 .uart_offset = 8, 3413 }, 3414 3415 [pbn_b1_1_115200] = { 3416 .flags = FL_BASE1, 3417 .num_ports = 1, 3418 .base_baud = 115200, 3419 .uart_offset = 8, 3420 }, 3421 [pbn_b1_2_115200] = { 3422 .flags = FL_BASE1, 3423 .num_ports = 2, 3424 .base_baud = 115200, 3425 .uart_offset = 8, 3426 }, 3427 [pbn_b1_4_115200] = { 3428 .flags = FL_BASE1, 3429 .num_ports = 4, 3430 .base_baud = 115200, 3431 .uart_offset = 8, 3432 }, 3433 [pbn_b1_8_115200] = { 3434 .flags = FL_BASE1, 3435 .num_ports = 8, 3436 .base_baud = 115200, 3437 .uart_offset = 8, 3438 }, 3439 [pbn_b1_16_115200] = { 3440 .flags = FL_BASE1, 3441 .num_ports = 16, 3442 .base_baud = 115200, 3443 .uart_offset = 8, 3444 }, 3445 3446 [pbn_b1_1_921600] = { 3447 .flags = FL_BASE1, 3448 .num_ports = 1, 3449 .base_baud = 921600, 3450 .uart_offset = 8, 3451 }, 3452 [pbn_b1_2_921600] = { 3453 .flags = FL_BASE1, 3454 .num_ports = 2, 3455 .base_baud = 921600, 3456 .uart_offset = 8, 3457 }, 3458 [pbn_b1_4_921600] = { 3459 .flags = FL_BASE1, 3460 .num_ports = 4, 3461 .base_baud = 921600, 3462 .uart_offset = 8, 3463 }, 3464 [pbn_b1_8_921600] = { 3465 .flags = FL_BASE1, 3466 .num_ports = 8, 3467 .base_baud = 921600, 3468 .uart_offset = 8, 3469 }, 3470 [pbn_b1_2_1250000] = { 3471 .flags = FL_BASE1, 3472 .num_ports = 2, 3473 .base_baud = 1250000, 3474 .uart_offset = 8, 3475 }, 3476 3477 [pbn_b1_bt_1_115200] = { 3478 .flags = FL_BASE1|FL_BASE_BARS, 3479 .num_ports = 1, 3480 .base_baud = 115200, 3481 .uart_offset = 8, 3482 }, 3483 [pbn_b1_bt_2_115200] = { 3484 .flags = FL_BASE1|FL_BASE_BARS, 3485 .num_ports = 2, 3486 .base_baud = 115200, 3487 .uart_offset = 8, 3488 }, 3489 [pbn_b1_bt_4_115200] = { 3490 .flags = FL_BASE1|FL_BASE_BARS, 3491 .num_ports = 4, 3492 .base_baud = 115200, 3493 .uart_offset = 8, 3494 }, 3495 3496 [pbn_b1_bt_2_921600] = { 3497 .flags = FL_BASE1|FL_BASE_BARS, 3498 .num_ports = 2, 3499 .base_baud = 921600, 3500 .uart_offset = 8, 3501 }, 3502 3503 [pbn_b1_1_1382400] = { 3504 .flags = FL_BASE1, 3505 .num_ports = 1, 3506 .base_baud = 1382400, 3507 .uart_offset = 8, 3508 }, 3509 [pbn_b1_2_1382400] = { 3510 .flags = FL_BASE1, 3511 .num_ports = 2, 3512 .base_baud = 1382400, 3513 .uart_offset = 8, 3514 }, 3515 [pbn_b1_4_1382400] = { 3516 .flags = FL_BASE1, 3517 .num_ports = 4, 3518 .base_baud = 1382400, 3519 .uart_offset = 8, 3520 }, 3521 [pbn_b1_8_1382400] = { 3522 .flags = FL_BASE1, 3523 .num_ports = 8, 3524 .base_baud = 1382400, 3525 .uart_offset = 8, 3526 }, 3527 3528 [pbn_b2_1_115200] = { 3529 .flags = FL_BASE2, 3530 .num_ports = 1, 3531 .base_baud = 115200, 3532 .uart_offset = 8, 3533 }, 3534 [pbn_b2_2_115200] = { 3535 .flags = FL_BASE2, 3536 .num_ports = 2, 3537 .base_baud = 115200, 3538 .uart_offset = 8, 3539 }, 3540 [pbn_b2_4_115200] = { 3541 .flags = FL_BASE2, 3542 .num_ports = 4, 3543 .base_baud = 115200, 3544 .uart_offset = 8, 3545 }, 3546 [pbn_b2_8_115200] = { 3547 .flags = FL_BASE2, 3548 .num_ports = 8, 3549 .base_baud = 115200, 3550 .uart_offset = 8, 3551 }, 3552 3553 [pbn_b2_1_460800] = { 3554 .flags = FL_BASE2, 3555 .num_ports = 1, 3556 .base_baud = 460800, 3557 .uart_offset = 8, 3558 }, 3559 [pbn_b2_4_460800] = { 3560 .flags = FL_BASE2, 3561 .num_ports = 4, 3562 .base_baud = 460800, 3563 .uart_offset = 8, 3564 }, 3565 [pbn_b2_8_460800] = { 3566 .flags = FL_BASE2, 3567 .num_ports = 8, 3568 .base_baud = 460800, 3569 .uart_offset = 8, 3570 }, 3571 [pbn_b2_16_460800] = { 3572 .flags = FL_BASE2, 3573 .num_ports = 16, 3574 .base_baud = 460800, 3575 .uart_offset = 8, 3576 }, 3577 3578 [pbn_b2_1_921600] = { 3579 .flags = FL_BASE2, 3580 .num_ports = 1, 3581 .base_baud = 921600, 3582 .uart_offset = 8, 3583 }, 3584 [pbn_b2_4_921600] = { 3585 .flags = FL_BASE2, 3586 .num_ports = 4, 3587 .base_baud = 921600, 3588 .uart_offset = 8, 3589 }, 3590 [pbn_b2_8_921600] = { 3591 .flags = FL_BASE2, 3592 .num_ports = 8, 3593 .base_baud = 921600, 3594 .uart_offset = 8, 3595 }, 3596 3597 [pbn_b2_8_1152000] = { 3598 .flags = FL_BASE2, 3599 .num_ports = 8, 3600 .base_baud = 1152000, 3601 .uart_offset = 8, 3602 }, 3603 3604 [pbn_b2_bt_1_115200] = { 3605 .flags = FL_BASE2|FL_BASE_BARS, 3606 .num_ports = 1, 3607 .base_baud = 115200, 3608 .uart_offset = 8, 3609 }, 3610 [pbn_b2_bt_2_115200] = { 3611 .flags = FL_BASE2|FL_BASE_BARS, 3612 .num_ports = 2, 3613 .base_baud = 115200, 3614 .uart_offset = 8, 3615 }, 3616 [pbn_b2_bt_4_115200] = { 3617 .flags = FL_BASE2|FL_BASE_BARS, 3618 .num_ports = 4, 3619 .base_baud = 115200, 3620 .uart_offset = 8, 3621 }, 3622 3623 [pbn_b2_bt_2_921600] = { 3624 .flags = FL_BASE2|FL_BASE_BARS, 3625 .num_ports = 2, 3626 .base_baud = 921600, 3627 .uart_offset = 8, 3628 }, 3629 [pbn_b2_bt_4_921600] = { 3630 .flags = FL_BASE2|FL_BASE_BARS, 3631 .num_ports = 4, 3632 .base_baud = 921600, 3633 .uart_offset = 8, 3634 }, 3635 3636 [pbn_b3_2_115200] = { 3637 .flags = FL_BASE3, 3638 .num_ports = 2, 3639 .base_baud = 115200, 3640 .uart_offset = 8, 3641 }, 3642 [pbn_b3_4_115200] = { 3643 .flags = FL_BASE3, 3644 .num_ports = 4, 3645 .base_baud = 115200, 3646 .uart_offset = 8, 3647 }, 3648 [pbn_b3_8_115200] = { 3649 .flags = FL_BASE3, 3650 .num_ports = 8, 3651 .base_baud = 115200, 3652 .uart_offset = 8, 3653 }, 3654 3655 [pbn_b4_bt_2_921600] = { 3656 .flags = FL_BASE4, 3657 .num_ports = 2, 3658 .base_baud = 921600, 3659 .uart_offset = 8, 3660 }, 3661 [pbn_b4_bt_4_921600] = { 3662 .flags = FL_BASE4, 3663 .num_ports = 4, 3664 .base_baud = 921600, 3665 .uart_offset = 8, 3666 }, 3667 [pbn_b4_bt_8_921600] = { 3668 .flags = FL_BASE4, 3669 .num_ports = 8, 3670 .base_baud = 921600, 3671 .uart_offset = 8, 3672 }, 3673 3674 /* 3675 * Entries following this are board-specific. 3676 */ 3677 3678 /* 3679 * Panacom - IOMEM 3680 */ 3681 [pbn_panacom] = { 3682 .flags = FL_BASE2, 3683 .num_ports = 2, 3684 .base_baud = 921600, 3685 .uart_offset = 0x400, 3686 .reg_shift = 7, 3687 }, 3688 [pbn_panacom2] = { 3689 .flags = FL_BASE2|FL_BASE_BARS, 3690 .num_ports = 2, 3691 .base_baud = 921600, 3692 .uart_offset = 0x400, 3693 .reg_shift = 7, 3694 }, 3695 [pbn_panacom4] = { 3696 .flags = FL_BASE2|FL_BASE_BARS, 3697 .num_ports = 4, 3698 .base_baud = 921600, 3699 .uart_offset = 0x400, 3700 .reg_shift = 7, 3701 }, 3702 3703 /* I think this entry is broken - the first_offset looks wrong --rmk */ 3704 [pbn_plx_romulus] = { 3705 .flags = FL_BASE2, 3706 .num_ports = 4, 3707 .base_baud = 921600, 3708 .uart_offset = 8 << 2, 3709 .reg_shift = 2, 3710 .first_offset = 0x03, 3711 }, 3712 3713 /* 3714 * This board uses the size of PCI Base region 0 to 3715 * signal now many ports are available 3716 */ 3717 [pbn_oxsemi] = { 3718 .flags = FL_BASE0|FL_REGION_SZ_CAP, 3719 .num_ports = 32, 3720 .base_baud = 115200, 3721 .uart_offset = 8, 3722 }, 3723 [pbn_oxsemi_1_15625000] = { 3724 .flags = FL_BASE0, 3725 .num_ports = 1, 3726 .base_baud = 15625000, 3727 .uart_offset = 0x200, 3728 .first_offset = 0x1000, 3729 }, 3730 [pbn_oxsemi_2_15625000] = { 3731 .flags = FL_BASE0, 3732 .num_ports = 2, 3733 .base_baud = 15625000, 3734 .uart_offset = 0x200, 3735 .first_offset = 0x1000, 3736 }, 3737 [pbn_oxsemi_4_15625000] = { 3738 .flags = FL_BASE0, 3739 .num_ports = 4, 3740 .base_baud = 15625000, 3741 .uart_offset = 0x200, 3742 .first_offset = 0x1000, 3743 }, 3744 [pbn_oxsemi_8_15625000] = { 3745 .flags = FL_BASE0, 3746 .num_ports = 8, 3747 .base_baud = 15625000, 3748 .uart_offset = 0x200, 3749 .first_offset = 0x1000, 3750 }, 3751 3752 3753 /* 3754 * EKF addition for i960 Boards form EKF with serial port. 3755 * Max 256 ports. 3756 */ 3757 [pbn_intel_i960] = { 3758 .flags = FL_BASE0, 3759 .num_ports = 32, 3760 .base_baud = 921600, 3761 .uart_offset = 8 << 2, 3762 .reg_shift = 2, 3763 .first_offset = 0x10000, 3764 }, 3765 [pbn_sgi_ioc3] = { 3766 .flags = FL_BASE0|FL_NOIRQ, 3767 .num_ports = 1, 3768 .base_baud = 458333, 3769 .uart_offset = 8, 3770 .reg_shift = 0, 3771 .first_offset = 0x20178, 3772 }, 3773 3774 /* 3775 * Computone - uses IOMEM. 3776 */ 3777 [pbn_computone_4] = { 3778 .flags = FL_BASE0, 3779 .num_ports = 4, 3780 .base_baud = 921600, 3781 .uart_offset = 0x40, 3782 .reg_shift = 2, 3783 .first_offset = 0x200, 3784 }, 3785 [pbn_computone_6] = { 3786 .flags = FL_BASE0, 3787 .num_ports = 6, 3788 .base_baud = 921600, 3789 .uart_offset = 0x40, 3790 .reg_shift = 2, 3791 .first_offset = 0x200, 3792 }, 3793 [pbn_computone_8] = { 3794 .flags = FL_BASE0, 3795 .num_ports = 8, 3796 .base_baud = 921600, 3797 .uart_offset = 0x40, 3798 .reg_shift = 2, 3799 .first_offset = 0x200, 3800 }, 3801 [pbn_sbsxrsio] = { 3802 .flags = FL_BASE0, 3803 .num_ports = 8, 3804 .base_baud = 460800, 3805 .uart_offset = 256, 3806 .reg_shift = 4, 3807 }, 3808 /* 3809 * PA Semi PWRficient PA6T-1682M on-chip UART 3810 */ 3811 [pbn_pasemi_1682M] = { 3812 .flags = FL_BASE0, 3813 .num_ports = 1, 3814 .base_baud = 8333333, 3815 }, 3816 /* 3817 * National Instruments 843x 3818 */ 3819 [pbn_ni8430_16] = { 3820 .flags = FL_BASE0, 3821 .num_ports = 16, 3822 .base_baud = 3686400, 3823 .uart_offset = 0x10, 3824 .first_offset = 0x800, 3825 }, 3826 [pbn_ni8430_8] = { 3827 .flags = FL_BASE0, 3828 .num_ports = 8, 3829 .base_baud = 3686400, 3830 .uart_offset = 0x10, 3831 .first_offset = 0x800, 3832 }, 3833 [pbn_ni8430_4] = { 3834 .flags = FL_BASE0, 3835 .num_ports = 4, 3836 .base_baud = 3686400, 3837 .uart_offset = 0x10, 3838 .first_offset = 0x800, 3839 }, 3840 [pbn_ni8430_2] = { 3841 .flags = FL_BASE0, 3842 .num_ports = 2, 3843 .base_baud = 3686400, 3844 .uart_offset = 0x10, 3845 .first_offset = 0x800, 3846 }, 3847 /* 3848 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com> 3849 */ 3850 [pbn_ADDIDATA_PCIe_1_3906250] = { 3851 .flags = FL_BASE0, 3852 .num_ports = 1, 3853 .base_baud = 3906250, 3854 .uart_offset = 0x200, 3855 .first_offset = 0x1000, 3856 }, 3857 [pbn_ADDIDATA_PCIe_2_3906250] = { 3858 .flags = FL_BASE0, 3859 .num_ports = 2, 3860 .base_baud = 3906250, 3861 .uart_offset = 0x200, 3862 .first_offset = 0x1000, 3863 }, 3864 [pbn_ADDIDATA_PCIe_4_3906250] = { 3865 .flags = FL_BASE0, 3866 .num_ports = 4, 3867 .base_baud = 3906250, 3868 .uart_offset = 0x200, 3869 .first_offset = 0x1000, 3870 }, 3871 [pbn_ADDIDATA_PCIe_8_3906250] = { 3872 .flags = FL_BASE0, 3873 .num_ports = 8, 3874 .base_baud = 3906250, 3875 .uart_offset = 0x200, 3876 .first_offset = 0x1000, 3877 }, 3878 [pbn_ce4100_1_115200] = { 3879 .flags = FL_BASE_BARS, 3880 .num_ports = 2, 3881 .base_baud = 921600, 3882 .reg_shift = 2, 3883 }, 3884 [pbn_omegapci] = { 3885 .flags = FL_BASE0, 3886 .num_ports = 8, 3887 .base_baud = 115200, 3888 .uart_offset = 0x200, 3889 }, 3890 [pbn_NETMOS9900_2s_115200] = { 3891 .flags = FL_BASE0, 3892 .num_ports = 2, 3893 .base_baud = 115200, 3894 }, 3895 [pbn_brcm_trumanage] = { 3896 .flags = FL_BASE0, 3897 .num_ports = 1, 3898 .reg_shift = 2, 3899 .base_baud = 115200, 3900 }, 3901 [pbn_fintek_4] = { 3902 .num_ports = 4, 3903 .uart_offset = 8, 3904 .base_baud = 115200, 3905 .first_offset = 0x40, 3906 }, 3907 [pbn_fintek_8] = { 3908 .num_ports = 8, 3909 .uart_offset = 8, 3910 .base_baud = 115200, 3911 .first_offset = 0x40, 3912 }, 3913 [pbn_fintek_12] = { 3914 .num_ports = 12, 3915 .uart_offset = 8, 3916 .base_baud = 115200, 3917 .first_offset = 0x40, 3918 }, 3919 [pbn_fintek_F81504A] = { 3920 .num_ports = 4, 3921 .uart_offset = 8, 3922 .base_baud = 115200, 3923 }, 3924 [pbn_fintek_F81508A] = { 3925 .num_ports = 8, 3926 .uart_offset = 8, 3927 .base_baud = 115200, 3928 }, 3929 [pbn_fintek_F81512A] = { 3930 .num_ports = 12, 3931 .uart_offset = 8, 3932 .base_baud = 115200, 3933 }, 3934 [pbn_wch382_2] = { 3935 .flags = FL_BASE0, 3936 .num_ports = 2, 3937 .base_baud = 115200, 3938 .uart_offset = 8, 3939 .first_offset = 0xC0, 3940 }, 3941 [pbn_wch384_4] = { 3942 .flags = FL_BASE0, 3943 .num_ports = 4, 3944 .base_baud = 115200, 3945 .uart_offset = 8, 3946 .first_offset = 0xC0, 3947 }, 3948 [pbn_wch384_8] = { 3949 .flags = FL_BASE0, 3950 .num_ports = 8, 3951 .base_baud = 115200, 3952 .uart_offset = 8, 3953 .first_offset = 0x00, 3954 }, 3955 [pbn_sunix_pci_1s] = { 3956 .num_ports = 1, 3957 .base_baud = 921600, 3958 .uart_offset = 0x8, 3959 }, 3960 [pbn_sunix_pci_2s] = { 3961 .num_ports = 2, 3962 .base_baud = 921600, 3963 .uart_offset = 0x8, 3964 }, 3965 [pbn_sunix_pci_4s] = { 3966 .num_ports = 4, 3967 .base_baud = 921600, 3968 .uart_offset = 0x8, 3969 }, 3970 [pbn_sunix_pci_8s] = { 3971 .num_ports = 8, 3972 .base_baud = 921600, 3973 .uart_offset = 0x8, 3974 }, 3975 [pbn_sunix_pci_16s] = { 3976 .num_ports = 16, 3977 .base_baud = 921600, 3978 .uart_offset = 0x8, 3979 }, 3980 [pbn_titan_1_4000000] = { 3981 .flags = FL_BASE0, 3982 .num_ports = 1, 3983 .base_baud = 4000000, 3984 .uart_offset = 0x200, 3985 .first_offset = 0x1000, 3986 }, 3987 [pbn_titan_2_4000000] = { 3988 .flags = FL_BASE0, 3989 .num_ports = 2, 3990 .base_baud = 4000000, 3991 .uart_offset = 0x200, 3992 .first_offset = 0x1000, 3993 }, 3994 [pbn_titan_4_4000000] = { 3995 .flags = FL_BASE0, 3996 .num_ports = 4, 3997 .base_baud = 4000000, 3998 .uart_offset = 0x200, 3999 .first_offset = 0x1000, 4000 }, 4001 [pbn_titan_8_4000000] = { 4002 .flags = FL_BASE0, 4003 .num_ports = 8, 4004 .base_baud = 4000000, 4005 .uart_offset = 0x200, 4006 .first_offset = 0x1000, 4007 }, 4008 [pbn_moxa_2] = { 4009 .flags = FL_BASE1, 4010 .num_ports = 2, 4011 .base_baud = 921600, 4012 .uart_offset = 0x200, 4013 }, 4014 [pbn_moxa_4] = { 4015 .flags = FL_BASE1, 4016 .num_ports = 4, 4017 .base_baud = 921600, 4018 .uart_offset = 0x200, 4019 }, 4020 [pbn_moxa_8] = { 4021 .flags = FL_BASE1, 4022 .num_ports = 8, 4023 .base_baud = 921600, 4024 .uart_offset = 0x200, 4025 }, 4026 }; 4027 4028 #define REPORT_CONFIG(option) \ 4029 (IS_ENABLED(CONFIG_##option) ? 0 : (kernel_ulong_t)&#option) 4030 #define REPORT_8250_CONFIG(option) \ 4031 (IS_ENABLED(CONFIG_SERIAL_8250_##option) ? \ 4032 0 : (kernel_ulong_t)&"SERIAL_8250_"#option) 4033 4034 static const struct pci_device_id blacklist[] = { 4035 /* softmodems */ 4036 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */ 4037 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */ 4038 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */ 4039 4040 /* multi-io cards handled by parport_serial */ 4041 /* WCH CH353 2S1P */ 4042 { PCI_VDEVICE(WCHCN, 0x7053), .driver_data = REPORT_CONFIG(PARPORT_SERIAL), }, 4043 /* WCH CH353 1S1P */ 4044 { PCI_VDEVICE(WCHCN, 0x5053), .driver_data = REPORT_CONFIG(PARPORT_SERIAL), }, 4045 /* WCH CH382 2S1P */ 4046 { PCI_VDEVICE(WCHIC, 0x3250), .driver_data = REPORT_CONFIG(PARPORT_SERIAL), }, 4047 4048 /* Intel platforms with MID UART */ 4049 { PCI_VDEVICE(INTEL, 0x081b), .driver_data = REPORT_8250_CONFIG(MID), }, 4050 { PCI_VDEVICE(INTEL, 0x081c), .driver_data = REPORT_8250_CONFIG(MID), }, 4051 { PCI_VDEVICE(INTEL, 0x081d), .driver_data = REPORT_8250_CONFIG(MID), }, 4052 { PCI_VDEVICE(INTEL, 0x1191), .driver_data = REPORT_8250_CONFIG(MID), }, 4053 { PCI_VDEVICE(INTEL, 0x18d8), .driver_data = REPORT_8250_CONFIG(MID), }, 4054 { PCI_VDEVICE(INTEL, 0x19d8), .driver_data = REPORT_8250_CONFIG(MID), }, 4055 4056 /* Intel platforms with DesignWare UART */ 4057 { PCI_VDEVICE(INTEL, 0x0936), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4058 { PCI_VDEVICE(INTEL, 0x0f0a), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4059 { PCI_VDEVICE(INTEL, 0x0f0c), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4060 { PCI_VDEVICE(INTEL, 0x228a), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4061 { PCI_VDEVICE(INTEL, 0x228c), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4062 { PCI_VDEVICE(INTEL, 0x4b96), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4063 { PCI_VDEVICE(INTEL, 0x4b97), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4064 { PCI_VDEVICE(INTEL, 0x4b98), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4065 { PCI_VDEVICE(INTEL, 0x4b99), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4066 { PCI_VDEVICE(INTEL, 0x4b9a), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4067 { PCI_VDEVICE(INTEL, 0x4b9b), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4068 { PCI_VDEVICE(INTEL, 0x9ce3), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4069 { PCI_VDEVICE(INTEL, 0x9ce4), .driver_data = REPORT_8250_CONFIG(LPSS), }, 4070 4071 /* Exar devices */ 4072 { PCI_VDEVICE(EXAR, PCI_ANY_ID), .driver_data = REPORT_8250_CONFIG(EXAR), }, 4073 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), .driver_data = REPORT_8250_CONFIG(EXAR), }, 4074 4075 /* Pericom devices */ 4076 { PCI_VDEVICE(PERICOM, PCI_ANY_ID), .driver_data = REPORT_8250_CONFIG(PERICOM), }, 4077 { PCI_VDEVICE(ACCESSIO, PCI_ANY_ID), .driver_data = REPORT_8250_CONFIG(PERICOM), }, 4078 4079 /* End of the black list */ 4080 { } 4081 }; 4082 4083 static int serial_pci_is_class_communication(struct pci_dev *dev) 4084 { 4085 /* 4086 * If it is not a communications device or the programming 4087 * interface is greater than 6, give up. 4088 */ 4089 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) && 4090 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) && 4091 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) || 4092 (dev->class & 0xff) > 6) 4093 return -ENODEV; 4094 4095 return 0; 4096 } 4097 4098 /* 4099 * Given a complete unknown PCI device, try to use some heuristics to 4100 * guess what the configuration might be, based on the pitiful PCI 4101 * serial specs. Returns 0 on success, -ENODEV on failure. 4102 */ 4103 static int 4104 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board) 4105 { 4106 int num_iomem, num_port, first_port = -1, i; 4107 int rc; 4108 4109 rc = serial_pci_is_class_communication(dev); 4110 if (rc) 4111 return rc; 4112 4113 /* 4114 * Should we try to make guesses for multiport serial devices later? 4115 */ 4116 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL) 4117 return -ENODEV; 4118 4119 num_iomem = num_port = 0; 4120 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 4121 if (pci_resource_flags(dev, i) & IORESOURCE_IO) { 4122 num_port++; 4123 if (first_port == -1) 4124 first_port = i; 4125 } 4126 if (pci_resource_flags(dev, i) & IORESOURCE_MEM) 4127 num_iomem++; 4128 } 4129 4130 /* 4131 * If there is 1 or 0 iomem regions, and exactly one port, 4132 * use it. We guess the number of ports based on the IO 4133 * region size. 4134 */ 4135 if (num_iomem <= 1 && num_port == 1) { 4136 board->flags = first_port; 4137 board->num_ports = pci_resource_len(dev, first_port) / 8; 4138 return 0; 4139 } 4140 4141 /* 4142 * Now guess if we've got a board which indexes by BARs. 4143 * Each IO BAR should be 8 bytes, and they should follow 4144 * consecutively. 4145 */ 4146 first_port = -1; 4147 num_port = 0; 4148 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 4149 if (pci_resource_flags(dev, i) & IORESOURCE_IO && 4150 pci_resource_len(dev, i) == 8 && 4151 (first_port == -1 || (first_port + num_port) == i)) { 4152 num_port++; 4153 if (first_port == -1) 4154 first_port = i; 4155 } 4156 } 4157 4158 if (num_port > 1) { 4159 board->flags = first_port | FL_BASE_BARS; 4160 board->num_ports = num_port; 4161 return 0; 4162 } 4163 4164 return -ENODEV; 4165 } 4166 4167 static inline int 4168 serial_pci_matches(const struct pciserial_board *board, 4169 const struct pciserial_board *guessed) 4170 { 4171 return 4172 board->num_ports == guessed->num_ports && 4173 board->base_baud == guessed->base_baud && 4174 board->uart_offset == guessed->uart_offset && 4175 board->reg_shift == guessed->reg_shift && 4176 board->first_offset == guessed->first_offset; 4177 } 4178 4179 struct serial_private * 4180 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board) 4181 { 4182 struct uart_8250_port uart; 4183 struct serial_private *priv; 4184 struct pci_serial_quirk *quirk; 4185 int rc, nr_ports, i; 4186 4187 nr_ports = board->num_ports; 4188 4189 /* 4190 * Find an init and setup quirks. 4191 */ 4192 quirk = find_quirk(dev); 4193 4194 /* 4195 * Run the new-style initialization function. 4196 * The initialization function returns: 4197 * <0 - error 4198 * 0 - use board->num_ports 4199 * >0 - number of ports 4200 */ 4201 if (quirk->init) { 4202 rc = quirk->init(dev); 4203 if (rc < 0) { 4204 priv = ERR_PTR(rc); 4205 goto err_out; 4206 } 4207 if (rc) 4208 nr_ports = rc; 4209 } 4210 4211 priv = kzalloc_flex(*priv, line, nr_ports); 4212 if (!priv) { 4213 priv = ERR_PTR(-ENOMEM); 4214 goto err_deinit; 4215 } 4216 4217 priv->dev = dev; 4218 priv->quirk = quirk; 4219 4220 memset(&uart, 0, sizeof(uart)); 4221 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ; 4222 uart.port.uartclk = board->base_baud * 16; 4223 4224 if (board->flags & FL_NOIRQ) { 4225 uart.port.irq = 0; 4226 } else { 4227 if (pci_match_id(pci_use_msi, dev)) { 4228 pci_dbg(dev, "Using MSI(-X) interrupts\n"); 4229 pci_set_master(dev); 4230 uart.port.flags &= ~UPF_SHARE_IRQ; 4231 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES); 4232 } else { 4233 pci_dbg(dev, "Using legacy interrupts\n"); 4234 rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_INTX); 4235 } 4236 if (rc < 0) { 4237 kfree(priv); 4238 priv = ERR_PTR(rc); 4239 goto err_deinit; 4240 } 4241 4242 uart.port.irq = pci_irq_vector(dev, 0); 4243 } 4244 4245 uart.port.dev = &dev->dev; 4246 4247 for (i = 0; i < nr_ports; i++) { 4248 if (quirk->setup(priv, board, &uart, i)) 4249 break; 4250 4251 pci_dbg(dev, "Setup PCI port: port %lx, irq %d, type %d\n", 4252 uart.port.iobase, uart.port.irq, uart.port.iotype); 4253 4254 priv->line[i] = serial8250_register_8250_port(&uart); 4255 if (priv->line[i] < 0) { 4256 pci_err(dev, 4257 "Couldn't register serial port %lx, irq %d, type %d, error %d\n", 4258 uart.port.iobase, uart.port.irq, 4259 uart.port.iotype, priv->line[i]); 4260 break; 4261 } 4262 } 4263 priv->nr = i; 4264 priv->board = board; 4265 return priv; 4266 4267 err_deinit: 4268 if (quirk->exit) 4269 quirk->exit(dev); 4270 err_out: 4271 return priv; 4272 } 4273 EXPORT_SYMBOL_GPL(pciserial_init_ports); 4274 4275 static void pciserial_detach_ports(struct serial_private *priv) 4276 { 4277 struct pci_serial_quirk *quirk; 4278 int i; 4279 4280 for (i = 0; i < priv->nr; i++) 4281 serial8250_unregister_port(priv->line[i]); 4282 4283 /* 4284 * Find the exit quirks. 4285 */ 4286 quirk = find_quirk(priv->dev); 4287 if (quirk->exit) 4288 quirk->exit(priv->dev); 4289 } 4290 4291 void pciserial_remove_ports(struct serial_private *priv) 4292 { 4293 pciserial_detach_ports(priv); 4294 kfree(priv); 4295 } 4296 EXPORT_SYMBOL_GPL(pciserial_remove_ports); 4297 4298 void pciserial_suspend_ports(struct serial_private *priv) 4299 { 4300 int i; 4301 4302 for (i = 0; i < priv->nr; i++) 4303 if (priv->line[i] >= 0) 4304 serial8250_suspend_port(priv->line[i]); 4305 4306 /* 4307 * Ensure that every init quirk is properly torn down 4308 */ 4309 if (priv->quirk->exit) 4310 priv->quirk->exit(priv->dev); 4311 } 4312 EXPORT_SYMBOL_GPL(pciserial_suspend_ports); 4313 4314 void pciserial_resume_ports(struct serial_private *priv) 4315 { 4316 int i; 4317 4318 /* 4319 * Ensure that the board is correctly configured. 4320 */ 4321 if (priv->quirk->init) 4322 priv->quirk->init(priv->dev); 4323 4324 for (i = 0; i < priv->nr; i++) 4325 if (priv->line[i] >= 0) 4326 serial8250_resume_port(priv->line[i]); 4327 } 4328 EXPORT_SYMBOL_GPL(pciserial_resume_ports); 4329 4330 /* 4331 * Probe one serial board. Unfortunately, there is no rhyme nor reason 4332 * to the arrangement of serial ports on a PCI card. 4333 */ 4334 static int 4335 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent) 4336 { 4337 struct pci_serial_quirk *quirk; 4338 struct serial_private *priv; 4339 const struct pciserial_board *board; 4340 const struct pci_device_id *exclude; 4341 struct pciserial_board tmp; 4342 int rc; 4343 4344 quirk = find_quirk(dev); 4345 if (quirk->probe) { 4346 rc = quirk->probe(dev); 4347 if (rc) 4348 return rc; 4349 } 4350 4351 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) { 4352 pci_err(dev, "invalid driver_data: %ld\n", ent->driver_data); 4353 return -EINVAL; 4354 } 4355 4356 board = &pci_boards[ent->driver_data]; 4357 4358 exclude = pci_match_id(blacklist, dev); 4359 if (exclude) { 4360 if (exclude->driver_data) 4361 pci_warn(dev, "ignoring port, enable %s to handle\n", 4362 (const char *)exclude->driver_data); 4363 return -ENODEV; 4364 } 4365 4366 rc = pcim_enable_device(dev); 4367 pci_save_state(dev); 4368 if (rc) 4369 return rc; 4370 4371 if (ent->driver_data == pbn_default) { 4372 /* 4373 * Use a copy of the pci_board entry for this; 4374 * avoid changing entries in the table. 4375 */ 4376 memcpy(&tmp, board, sizeof(struct pciserial_board)); 4377 board = &tmp; 4378 4379 /* 4380 * We matched one of our class entries. Try to 4381 * determine the parameters of this board. 4382 */ 4383 rc = serial_pci_guess_board(dev, &tmp); 4384 if (rc) 4385 return rc; 4386 } else { 4387 /* 4388 * We matched an explicit entry. If we are able to 4389 * detect this boards settings with our heuristic, 4390 * then we no longer need this entry. 4391 */ 4392 memcpy(&tmp, &pci_boards[pbn_default], 4393 sizeof(struct pciserial_board)); 4394 rc = serial_pci_guess_board(dev, &tmp); 4395 if (rc == 0 && serial_pci_matches(board, &tmp)) 4396 moan_device("Redundant entry in serial pci_table.", 4397 dev); 4398 } 4399 4400 priv = pciserial_init_ports(dev, board); 4401 if (IS_ERR(priv)) 4402 return PTR_ERR(priv); 4403 4404 pci_set_drvdata(dev, priv); 4405 return 0; 4406 } 4407 4408 static void pciserial_remove_one(struct pci_dev *dev) 4409 { 4410 struct serial_private *priv = pci_get_drvdata(dev); 4411 4412 pciserial_remove_ports(priv); 4413 } 4414 4415 #ifdef CONFIG_PM_SLEEP 4416 static int pciserial_suspend_one(struct device *dev) 4417 { 4418 struct serial_private *priv = dev_get_drvdata(dev); 4419 4420 if (priv) 4421 pciserial_suspend_ports(priv); 4422 4423 return 0; 4424 } 4425 4426 static int pciserial_resume_one(struct device *dev) 4427 { 4428 struct pci_dev *pdev = to_pci_dev(dev); 4429 struct serial_private *priv = pci_get_drvdata(pdev); 4430 int err; 4431 4432 if (priv) { 4433 /* 4434 * The device may have been disabled. Re-enable it. 4435 */ 4436 err = pci_enable_device(pdev); 4437 /* FIXME: We cannot simply error out here */ 4438 if (err) 4439 pci_err(pdev, "Unable to re-enable ports, trying to continue.\n"); 4440 pciserial_resume_ports(priv); 4441 } 4442 return 0; 4443 } 4444 #endif 4445 4446 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one, 4447 pciserial_resume_one); 4448 4449 static const struct pci_device_id serial_pci_tbl[] = { 4450 { 4451 PCI_VDEVICE_SUB(ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI1600, 4452 PCI_DEVICE_ID_ADVANTECH_PCI1600_1611, PCI_ANY_ID), 4453 .driver_data = pbn_b0_4_921600, 4454 }, { 4455 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */ 4456 PCI_VDEVICE_SUB(ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620, 4457 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001), 4458 .driver_data = pbn_b2_8_921600, 4459 }, { 4460 /* Advantech also use 0x3618 and 0xf618 */ 4461 PCI_VDEVICE_SUB(ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618, 4462 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID), 4463 .driver_data = pbn_b0_4_921600, 4464 }, { 4465 PCI_VDEVICE_SUB(ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618, 4466 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID), 4467 .driver_data = pbn_b0_4_921600, 4468 }, { 4469 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V960, 4470 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232), 4471 .driver_data = pbn_b1_8_1382400, 4472 }, { 4473 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V960, 4474 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232), 4475 .driver_data = pbn_b1_4_1382400, 4476 }, { 4477 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V960, 4478 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232), 4479 .driver_data = pbn_b1_2_1382400, 4480 }, { 4481 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351, 4482 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232), 4483 .driver_data = pbn_b1_8_1382400, 4484 }, { 4485 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351, 4486 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232), 4487 .driver_data = pbn_b1_4_1382400, 4488 }, { 4489 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351, 4490 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232), 4491 .driver_data = pbn_b1_2_1382400, 4492 }, { 4493 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351, 4494 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485), 4495 .driver_data = pbn_b1_8_921600, 4496 }, { 4497 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351, 4498 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4), 4499 .driver_data = pbn_b1_8_921600, 4500 }, { 4501 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351, 4502 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485), 4503 .driver_data = pbn_b1_4_921600, 4504 }, { 4505 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351, 4506 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2), 4507 .driver_data = pbn_b1_4_921600, 4508 }, { 4509 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351, 4510 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485), 4511 .driver_data = pbn_b1_2_921600, 4512 }, { 4513 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351, 4514 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6), 4515 .driver_data = pbn_b1_8_921600, 4516 }, { 4517 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351, 4518 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1), 4519 .driver_data = pbn_b1_8_921600, 4520 }, { 4521 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351, 4522 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1), 4523 .driver_data = pbn_b1_4_921600, 4524 }, { 4525 PCI_VDEVICE_SUB(V3, PCI_DEVICE_ID_V3_V351, 4526 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ), 4527 .driver_data = pbn_b1_2_1250000, 4528 }, { 4529 PCI_VDEVICE_SUB(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4530 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2), 4531 .driver_data = pbn_b0_2_1843200, 4532 }, { 4533 PCI_VDEVICE_SUB(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4534 PCI_SUBVENDOR_ID_CONNECT_TECH, PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4), 4535 .driver_data = pbn_b0_4_1843200, 4536 }, { 4537 PCI_VDEVICE_SUB(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4538 PCI_VENDOR_ID_AFAVLAB, PCI_SUBDEVICE_ID_AFAVLAB_P061), 4539 .driver_data = pbn_b0_4_1152000, 4540 }, { 4541 PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530), 4542 .driver_data = pbn_b2_bt_1_115200, 4543 }, { 4544 PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2), 4545 .driver_data = pbn_b2_bt_2_115200, 4546 }, { 4547 PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422), 4548 .driver_data = pbn_b2_bt_4_115200, 4549 }, { 4550 PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232), 4551 .driver_data = pbn_b2_bt_2_115200, 4552 }, { 4553 PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4), 4554 .driver_data = pbn_b2_bt_4_115200, 4555 }, { 4556 PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8), 4557 .driver_data = pbn_b2_8_115200, 4558 }, { 4559 PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803), 4560 .driver_data = pbn_b2_8_460800, 4561 }, { 4562 PCI_VDEVICE(SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8), 4563 .driver_data = pbn_b2_8_115200, 4564 }, { 4565 PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2), 4566 .driver_data = pbn_b2_bt_2_115200, 4567 }, { 4568 PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_SPCOM200), 4569 .driver_data = pbn_b2_bt_2_921600, 4570 }, { 4571 /* VScom SPCOM800, from sl@s.pl */ 4572 PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_SPCOM800), 4573 .driver_data = pbn_b2_8_921600, 4574 }, { 4575 PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_1077), 4576 .driver_data = pbn_b2_4_921600, 4577 }, { 4578 /* Unknown card - subdevice 0x1584 */ 4579 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050, 4580 PCI_VENDOR_ID_PLX, PCI_SUBDEVICE_ID_UNKNOWN_0x1584), 4581 .driver_data = pbn_b2_4_115200, 4582 }, { 4583 /* Unknown card - subdevice 0x1588 */ 4584 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050, 4585 PCI_VENDOR_ID_PLX, PCI_SUBDEVICE_ID_UNKNOWN_0x1588), 4586 .driver_data = pbn_b2_8_115200, 4587 }, { 4588 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050, 4589 PCI_SUBVENDOR_ID_KEYSPAN, PCI_SUBDEVICE_ID_KEYSPAN_SX2), 4590 .driver_data = pbn_panacom, 4591 }, { 4592 PCI_VDEVICE(PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM), 4593 .driver_data = pbn_panacom4, 4594 }, { 4595 PCI_VDEVICE(PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM), 4596 .driver_data = pbn_panacom2, 4597 }, { 4598 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9030, 4599 PCI_VENDOR_ID_ESDGMBH, PCI_DEVICE_ID_ESDGMBH_CPCIASIO4), 4600 .driver_data = pbn_b2_4_115200, 4601 }, { 4602 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050, 4603 PCI_SUBVENDOR_ID_CHASE_PCIFAST, PCI_SUBDEVICE_ID_CHASE_PCIFAST4), 4604 .driver_data = pbn_b2_4_460800, 4605 }, { 4606 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050, 4607 PCI_SUBVENDOR_ID_CHASE_PCIFAST, PCI_SUBDEVICE_ID_CHASE_PCIFAST8), 4608 .driver_data = pbn_b2_8_460800, 4609 }, { 4610 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050, 4611 PCI_SUBVENDOR_ID_CHASE_PCIFAST, PCI_SUBDEVICE_ID_CHASE_PCIFAST16), 4612 .driver_data = pbn_b2_16_460800, 4613 }, { 4614 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050, 4615 PCI_SUBVENDOR_ID_CHASE_PCIFAST, PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC), 4616 .driver_data = pbn_b2_16_460800, 4617 }, { 4618 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050, 4619 PCI_SUBVENDOR_ID_CHASE_PCIRAS, PCI_SUBDEVICE_ID_CHASE_PCIRAS4), 4620 .driver_data = pbn_b2_4_460800, 4621 }, { 4622 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050, 4623 PCI_SUBVENDOR_ID_CHASE_PCIRAS, PCI_SUBDEVICE_ID_CHASE_PCIRAS8), 4624 .driver_data = pbn_b2_8_460800, 4625 }, { 4626 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9050, 4627 PCI_SUBVENDOR_ID_EXSYS, PCI_SUBDEVICE_ID_EXSYS_4055), 4628 .driver_data = pbn_b2_4_115200, 4629 }, { 4630 /* 4631 * Megawolf Romulus PCI Serial Card, from Mike Hudson 4632 * (Exoray@isys.ca) 4633 */ 4634 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_ROMULUS, 4635 0x10b5, 0x106a), 4636 .driver_data = pbn_plx_romulus, 4637 }, 4638 4639 /* 4640 * Quatech cards. These actually have configurable clocks but for 4641 * now we just use the default. 4642 * 4643 * 100 series are RS232, 200 series RS422, 4644 */ 4645 { 4646 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_QSC100), 4647 .driver_data = pbn_b1_4_115200, 4648 }, { 4649 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSC100), 4650 .driver_data = pbn_b1_2_115200, 4651 }, { 4652 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E), 4653 .driver_data = pbn_b2_2_115200, 4654 }, { 4655 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSC200), 4656 .driver_data = pbn_b1_2_115200, 4657 }, { 4658 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E), 4659 .driver_data = pbn_b2_2_115200, 4660 }, { 4661 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_QSC200), 4662 .driver_data = pbn_b1_4_115200, 4663 }, { 4664 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D), 4665 .driver_data = pbn_b1_8_115200, 4666 }, { 4667 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M), 4668 .driver_data = pbn_b1_8_115200, 4669 }, { 4670 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100), 4671 .driver_data = pbn_b1_4_115200, 4672 }, { 4673 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100), 4674 .driver_data = pbn_b1_2_115200, 4675 }, { 4676 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200), 4677 .driver_data = pbn_b1_4_115200, 4678 }, { 4679 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200), 4680 .driver_data = pbn_b1_2_115200, 4681 }, { 4682 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100), 4683 .driver_data = pbn_b2_4_115200, 4684 }, { 4685 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100), 4686 .driver_data = pbn_b2_2_115200, 4687 }, { 4688 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100), 4689 .driver_data = pbn_b2_1_115200, 4690 }, { 4691 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200), 4692 .driver_data = pbn_b2_4_115200, 4693 }, { 4694 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200), 4695 .driver_data = pbn_b2_2_115200, 4696 }, { 4697 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200), 4698 .driver_data = pbn_b2_1_115200, 4699 }, { 4700 PCI_VDEVICE(QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100), 4701 .driver_data = pbn_b0_8_115200, 4702 }, { 4703 PCI_VDEVICE_SUB(SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954, 4704 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4), 4705 .driver_data = pbn_b0_4_921600, 4706 }, { 4707 PCI_VDEVICE_SUB(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954, 4708 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL), 4709 .driver_data = pbn_b0_4_1152000, 4710 }, { 4711 PCI_VDEVICE(OXSEMI, 0x9505), 4712 .driver_data = pbn_b0_bt_2_921600, 4713 }, { 4714 /* 4715 * The below card is a little controversial since it is the 4716 * subject of a PCI vendor/device ID clash. (See 4717 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html). 4718 * For now just used the hex ID 0x950a. 4719 */ 4720 PCI_VDEVICE_SUB(OXSEMI, 0x950a, 4721 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00), 4722 .driver_data = pbn_b0_2_115200, 4723 }, { 4724 PCI_VDEVICE_SUB(OXSEMI, 0x950a, 4725 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30), 4726 .driver_data = pbn_b0_2_115200, 4727 }, { 4728 PCI_VDEVICE(OXSEMI, 0x950a), 4729 .driver_data = pbn_b0_2_1130000, 4730 }, { 4731 PCI_VDEVICE_SUB(OXSEMI, PCI_DEVICE_ID_OXSEMI_C950, 4732 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950), 4733 .driver_data = pbn_b0_1_921600, 4734 }, { 4735 PCI_VDEVICE(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954), 4736 .driver_data = pbn_b0_4_115200, 4737 }, { 4738 PCI_VDEVICE(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952), 4739 .driver_data = pbn_b0_bt_2_921600, 4740 }, { 4741 PCI_VDEVICE(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958), 4742 .driver_data = pbn_b2_8_1152000, 4743 }, 4744 4745 /* 4746 * Oxford Semiconductor Inc. Tornado PCI express device range. 4747 */ 4748 { 4749 PCI_VDEVICE(OXSEMI, 0xc101), /* OXPCIe952 1 Legacy UART */ 4750 .driver_data = pbn_b0_1_15625000, 4751 }, { 4752 PCI_VDEVICE(OXSEMI, 0xc105), /* OXPCIe952 1 Legacy UART */ 4753 .driver_data = pbn_b0_1_15625000, 4754 }, { 4755 PCI_VDEVICE(OXSEMI, 0xc11b), /* OXPCIe952 1 Native UART */ 4756 .driver_data = pbn_oxsemi_1_15625000, 4757 }, { 4758 PCI_VDEVICE(OXSEMI, 0xc11f), /* OXPCIe952 1 Native UART */ 4759 .driver_data = pbn_oxsemi_1_15625000, 4760 }, { 4761 PCI_VDEVICE(OXSEMI, 0xc120), /* OXPCIe952 1 Legacy UART */ 4762 .driver_data = pbn_b0_1_15625000, 4763 }, { 4764 PCI_VDEVICE(OXSEMI, 0xc124), /* OXPCIe952 1 Legacy UART */ 4765 .driver_data = pbn_b0_1_15625000, 4766 }, { 4767 PCI_VDEVICE(OXSEMI, 0xc138), /* OXPCIe952 1 Native UART */ 4768 .driver_data = pbn_oxsemi_1_15625000, 4769 }, { 4770 PCI_VDEVICE(OXSEMI, 0xc13d), /* OXPCIe952 1 Native UART */ 4771 .driver_data = pbn_oxsemi_1_15625000, 4772 }, { 4773 PCI_VDEVICE(OXSEMI, 0xc140), /* OXPCIe952 1 Legacy UART */ 4774 .driver_data = pbn_b0_1_15625000, 4775 }, { 4776 PCI_VDEVICE(OXSEMI, 0xc141), /* OXPCIe952 1 Legacy UART */ 4777 .driver_data = pbn_b0_1_15625000, 4778 }, { 4779 PCI_VDEVICE(OXSEMI, 0xc144), /* OXPCIe952 1 Legacy UART */ 4780 .driver_data = pbn_b0_1_15625000, 4781 }, { 4782 PCI_VDEVICE(OXSEMI, 0xc145), /* OXPCIe952 1 Legacy UART */ 4783 .driver_data = pbn_b0_1_15625000, 4784 }, { 4785 PCI_VDEVICE(OXSEMI, 0xc158), /* OXPCIe952 2 Native UART */ 4786 .driver_data = pbn_oxsemi_2_15625000, 4787 }, { 4788 PCI_VDEVICE(OXSEMI, 0xc15d), /* OXPCIe952 2 Native UART */ 4789 .driver_data = pbn_oxsemi_2_15625000, 4790 }, { 4791 PCI_VDEVICE(OXSEMI, 0xc208), /* OXPCIe954 4 Native UART */ 4792 .driver_data = pbn_oxsemi_4_15625000, 4793 }, { 4794 PCI_VDEVICE(OXSEMI, 0xc20d), /* OXPCIe954 4 Native UART */ 4795 .driver_data = pbn_oxsemi_4_15625000, 4796 }, { 4797 PCI_VDEVICE(OXSEMI, 0xc308), /* OXPCIe958 8 Native UART */ 4798 .driver_data = pbn_oxsemi_8_15625000, 4799 }, { 4800 PCI_VDEVICE(OXSEMI, 0xc30d), /* OXPCIe958 8 Native UART */ 4801 .driver_data = pbn_oxsemi_8_15625000, 4802 }, { 4803 PCI_VDEVICE(OXSEMI, 0xc40b), /* OXPCIe200 1 Native UART */ 4804 .driver_data = pbn_oxsemi_1_15625000, 4805 }, { 4806 PCI_VDEVICE(OXSEMI, 0xc40f), /* OXPCIe200 1 Native UART */ 4807 .driver_data = pbn_oxsemi_1_15625000, 4808 }, { 4809 PCI_VDEVICE(OXSEMI, 0xc41b), /* OXPCIe200 1 Native UART */ 4810 .driver_data = pbn_oxsemi_1_15625000, 4811 }, { 4812 PCI_VDEVICE(OXSEMI, 0xc41f), /* OXPCIe200 1 Native UART */ 4813 .driver_data = pbn_oxsemi_1_15625000, 4814 }, { 4815 PCI_VDEVICE(OXSEMI, 0xc42b), /* OXPCIe200 1 Native UART */ 4816 .driver_data = pbn_oxsemi_1_15625000, 4817 }, { 4818 PCI_VDEVICE(OXSEMI, 0xc42f), /* OXPCIe200 1 Native UART */ 4819 .driver_data = pbn_oxsemi_1_15625000, 4820 }, { 4821 PCI_VDEVICE(OXSEMI, 0xc43b), /* OXPCIe200 1 Native UART */ 4822 .driver_data = pbn_oxsemi_1_15625000, 4823 }, { 4824 PCI_VDEVICE(OXSEMI, 0xc43f), /* OXPCIe200 1 Native UART */ 4825 .driver_data = pbn_oxsemi_1_15625000, 4826 }, { 4827 PCI_VDEVICE(OXSEMI, 0xc44b), /* OXPCIe200 1 Native UART */ 4828 .driver_data = pbn_oxsemi_1_15625000, 4829 }, { 4830 PCI_VDEVICE(OXSEMI, 0xc44f), /* OXPCIe200 1 Native UART */ 4831 .driver_data = pbn_oxsemi_1_15625000, 4832 }, { 4833 PCI_VDEVICE(OXSEMI, 0xc45b), /* OXPCIe200 1 Native UART */ 4834 .driver_data = pbn_oxsemi_1_15625000, 4835 }, { 4836 PCI_VDEVICE(OXSEMI, 0xc45f), /* OXPCIe200 1 Native UART */ 4837 .driver_data = pbn_oxsemi_1_15625000, 4838 }, { 4839 PCI_VDEVICE(OXSEMI, 0xc46b), /* OXPCIe200 1 Native UART */ 4840 .driver_data = pbn_oxsemi_1_15625000, 4841 }, { 4842 PCI_VDEVICE(OXSEMI, 0xc46f), /* OXPCIe200 1 Native UART */ 4843 .driver_data = pbn_oxsemi_1_15625000, 4844 }, { 4845 PCI_VDEVICE(OXSEMI, 0xc47b), /* OXPCIe200 1 Native UART */ 4846 .driver_data = pbn_oxsemi_1_15625000, 4847 }, { 4848 PCI_VDEVICE(OXSEMI, 0xc47f), /* OXPCIe200 1 Native UART */ 4849 .driver_data = pbn_oxsemi_1_15625000, 4850 }, { 4851 PCI_VDEVICE(OXSEMI, 0xc48b), /* OXPCIe200 1 Native UART */ 4852 .driver_data = pbn_oxsemi_1_15625000, 4853 }, { 4854 PCI_VDEVICE(OXSEMI, 0xc48f), /* OXPCIe200 1 Native UART */ 4855 .driver_data = pbn_oxsemi_1_15625000, 4856 }, { 4857 PCI_VDEVICE(OXSEMI, 0xc49b), /* OXPCIe200 1 Native UART */ 4858 .driver_data = pbn_oxsemi_1_15625000, 4859 }, { 4860 PCI_VDEVICE(OXSEMI, 0xc49f), /* OXPCIe200 1 Native UART */ 4861 .driver_data = pbn_oxsemi_1_15625000, 4862 }, { 4863 PCI_VDEVICE(OXSEMI, 0xc4ab), /* OXPCIe200 1 Native UART */ 4864 .driver_data = pbn_oxsemi_1_15625000, 4865 }, { 4866 PCI_VDEVICE(OXSEMI, 0xc4af), /* OXPCIe200 1 Native UART */ 4867 .driver_data = pbn_oxsemi_1_15625000, 4868 }, { 4869 PCI_VDEVICE(OXSEMI, 0xc4bb), /* OXPCIe200 1 Native UART */ 4870 .driver_data = pbn_oxsemi_1_15625000, 4871 }, { 4872 PCI_VDEVICE(OXSEMI, 0xc4bf), /* OXPCIe200 1 Native UART */ 4873 .driver_data = pbn_oxsemi_1_15625000, 4874 }, { 4875 PCI_VDEVICE(OXSEMI, 0xc4cb), /* OXPCIe200 1 Native UART */ 4876 .driver_data = pbn_oxsemi_1_15625000, 4877 }, { 4878 PCI_VDEVICE(OXSEMI, 0xc4cf), /* OXPCIe200 1 Native UART */ 4879 .driver_data = pbn_oxsemi_1_15625000, 4880 }, 4881 /* 4882 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado 4883 */ 4884 { 4885 /* IQ Express 1 Port V.34 Super-G3 Fax */ 4886 PCI_VDEVICE_SUB(MAINPINE, 0x4000, 4887 PCI_VENDOR_ID_MAINPINE, 0x4001), 4888 .driver_data = pbn_oxsemi_1_15625000, 4889 }, { 4890 /* IQ Express 2 Port V.34 Super-G3 Fax */ 4891 PCI_VDEVICE_SUB(MAINPINE, 0x4000, 4892 PCI_VENDOR_ID_MAINPINE, 0x4002), 4893 .driver_data = pbn_oxsemi_2_15625000, 4894 }, { 4895 /* IQ Express 4 Port V.34 Super-G3 Fax */ 4896 PCI_VDEVICE_SUB(MAINPINE, 0x4000, 4897 PCI_VENDOR_ID_MAINPINE, 0x4004), 4898 .driver_data = pbn_oxsemi_4_15625000, 4899 }, { 4900 /* IQ Express 8 Port V.34 Super-G3 Fax */ 4901 PCI_VDEVICE_SUB(MAINPINE, 0x4000, 4902 PCI_VENDOR_ID_MAINPINE, 0x4008), 4903 .driver_data = pbn_oxsemi_8_15625000, 4904 }, 4905 4906 /* 4907 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado 4908 */ 4909 { 4910 PCI_VDEVICE_SUB(DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM, 4911 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID), 4912 .driver_data = pbn_oxsemi_2_15625000, 4913 }, 4914 4915 /* 4916 * EndRun Technologies. PCI express device range. 4917 * EndRun PTP/1588 has 2 Native UARTs utilizing OxSemi 952. 4918 */ 4919 { 4920 PCI_VDEVICE(ENDRUN, PCI_DEVICE_ID_ENDRUN_1588), 4921 .driver_data = pbn_oxsemi_2_15625000, 4922 }, 4923 4924 /* 4925 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards, 4926 * from skokodyn@yahoo.com 4927 */ 4928 { 4929 PCI_VDEVICE_SUB(SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4930 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232), 4931 .driver_data = pbn_sbsxrsio, 4932 }, { 4933 PCI_VDEVICE_SUB(SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4934 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422), 4935 .driver_data = pbn_sbsxrsio, 4936 }, { 4937 PCI_VDEVICE_SUB(SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4938 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232), 4939 .driver_data = pbn_sbsxrsio, 4940 }, { 4941 PCI_VDEVICE_SUB(SBSMODULARIO, PCI_DEVICE_ID_OCTPRO, 4942 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422), 4943 .driver_data = pbn_sbsxrsio, 4944 }, 4945 4946 /* 4947 * Digitan DS560-558, from jimd@esoft.com 4948 */ 4949 { 4950 PCI_VDEVICE(ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM), 4951 .driver_data = pbn_b1_1_115200, 4952 }, 4953 4954 /* 4955 * Titan Electronic cards 4956 * The 400L and 800L have a custom setup quirk. 4957 */ 4958 { 4959 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_100), 4960 .driver_data = pbn_b0_1_921600, 4961 }, { 4962 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200), 4963 .driver_data = pbn_b0_2_921600, 4964 }, { 4965 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_400), 4966 .driver_data = pbn_b0_4_921600, 4967 }, { 4968 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800B), 4969 .driver_data = pbn_b0_4_921600, 4970 }, { 4971 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_100L), 4972 .driver_data = pbn_b1_1_921600, 4973 }, { 4974 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200L), 4975 .driver_data = pbn_b1_bt_2_921600, 4976 }, { 4977 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_400L), 4978 .driver_data = pbn_b0_bt_4_921600, 4979 }, { 4980 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800L), 4981 .driver_data = pbn_b0_bt_8_921600, 4982 }, { 4983 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200I), 4984 .driver_data = pbn_b4_bt_2_921600, 4985 }, { 4986 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_400I), 4987 .driver_data = pbn_b4_bt_4_921600, 4988 }, { 4989 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800I), 4990 .driver_data = pbn_b4_bt_8_921600, 4991 }, { 4992 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_400EH), 4993 .driver_data = pbn_b0_4_921600, 4994 }, { 4995 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800EH), 4996 .driver_data = pbn_b0_4_921600, 4997 }, { 4998 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800EHB), 4999 .driver_data = pbn_b0_4_921600, 5000 }, { 5001 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_100E), 5002 .driver_data = pbn_titan_1_4000000, 5003 }, { 5004 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200E), 5005 .driver_data = pbn_titan_2_4000000, 5006 }, { 5007 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_400E), 5008 .driver_data = pbn_titan_4_4000000, 5009 }, { 5010 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800E), 5011 .driver_data = pbn_titan_8_4000000, 5012 }, { 5013 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200EI), 5014 .driver_data = pbn_titan_2_4000000, 5015 }, { 5016 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200EISI), 5017 .driver_data = pbn_titan_2_4000000, 5018 }, { 5019 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_200V3), 5020 .driver_data = pbn_b0_bt_2_921600, 5021 }, { 5022 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_400V3), 5023 .driver_data = pbn_b0_4_921600, 5024 }, { 5025 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_410V3), 5026 .driver_data = pbn_b0_4_921600, 5027 }, { 5028 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800V3), 5029 .driver_data = pbn_b0_4_921600, 5030 }, { 5031 PCI_VDEVICE(TITAN, PCI_DEVICE_ID_TITAN_800V3B), 5032 .driver_data = pbn_b0_4_921600, 5033 }, { 5034 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550), 5035 .driver_data = pbn_b2_1_460800, 5036 }, { 5037 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650), 5038 .driver_data = pbn_b2_1_460800, 5039 }, { 5040 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850), 5041 .driver_data = pbn_b2_1_460800, 5042 }, { 5043 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550), 5044 .driver_data = pbn_b2_bt_2_921600, 5045 }, { 5046 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650), 5047 .driver_data = pbn_b2_bt_2_921600, 5048 }, { 5049 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850), 5050 .driver_data = pbn_b2_bt_2_921600, 5051 }, { 5052 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550), 5053 .driver_data = pbn_b2_bt_4_921600, 5054 }, { 5055 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650), 5056 .driver_data = pbn_b2_bt_4_921600, 5057 }, { 5058 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850), 5059 .driver_data = pbn_b2_bt_4_921600, 5060 }, { 5061 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550), 5062 .driver_data = pbn_b0_1_921600, 5063 }, { 5064 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650), 5065 .driver_data = pbn_b0_1_921600, 5066 }, { 5067 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850), 5068 .driver_data = pbn_b0_1_921600, 5069 }, { 5070 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550), 5071 .driver_data = pbn_b0_bt_2_921600, 5072 }, { 5073 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650), 5074 .driver_data = pbn_b0_bt_2_921600, 5075 }, { 5076 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850), 5077 .driver_data = pbn_b0_bt_2_921600, 5078 }, { 5079 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550), 5080 .driver_data = pbn_b0_bt_4_921600, 5081 }, { 5082 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650), 5083 .driver_data = pbn_b0_bt_4_921600, 5084 }, { 5085 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850), 5086 .driver_data = pbn_b0_bt_4_921600, 5087 }, { 5088 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550), 5089 .driver_data = pbn_b0_bt_8_921600, 5090 }, { 5091 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650), 5092 .driver_data = pbn_b0_bt_8_921600, 5093 }, { 5094 PCI_VDEVICE(SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850), 5095 .driver_data = pbn_b0_bt_8_921600, 5096 }, 5097 5098 /* 5099 * Computone devices submitted by Doug McNash dmcnash@computone.com 5100 */ 5101 { 5102 PCI_VDEVICE_SUB(COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 5103 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4), 5104 .driver_data = pbn_computone_4, 5105 }, { 5106 PCI_VDEVICE_SUB(COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 5107 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8), 5108 .driver_data = pbn_computone_8, 5109 }, { 5110 PCI_VDEVICE_SUB(COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG, 5111 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6), 5112 .driver_data = pbn_computone_6, 5113 }, 5114 5115 { 5116 PCI_VDEVICE(OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N), 5117 .driver_data = pbn_oxsemi, 5118 }, { 5119 PCI_VDEVICE_SUB(TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889, 5120 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID), 5121 .driver_data = pbn_b0_bt_1_921600, 5122 }, 5123 5124 /* 5125 * Sunix PCI serial boards 5126 */ 5127 { 5128 PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5129 PCI_VENDOR_ID_SUNIX, 0x0001), 5130 .driver_data = pbn_sunix_pci_1s, 5131 }, { 5132 PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5133 PCI_VENDOR_ID_SUNIX, 0x0002), 5134 .driver_data = pbn_sunix_pci_2s, 5135 }, { 5136 PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5137 PCI_VENDOR_ID_SUNIX, 0x0004), 5138 .driver_data = pbn_sunix_pci_4s, 5139 }, { 5140 PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5141 PCI_VENDOR_ID_SUNIX, 0x0084), 5142 .driver_data = pbn_sunix_pci_4s, 5143 }, { 5144 PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5145 PCI_VENDOR_ID_SUNIX, 0x0008), 5146 .driver_data = pbn_sunix_pci_8s, 5147 }, { 5148 PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5149 PCI_VENDOR_ID_SUNIX, 0x0088), 5150 .driver_data = pbn_sunix_pci_8s, 5151 }, { 5152 PCI_VDEVICE_SUB(SUNIX, PCI_DEVICE_ID_SUNIX_1999, 5153 PCI_VENDOR_ID_SUNIX, 0x0010), 5154 .driver_data = pbn_sunix_pci_16s, 5155 }, 5156 5157 /* 5158 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org> 5159 */ 5160 { 5161 PCI_VDEVICE(AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028), 5162 .driver_data = pbn_b0_bt_8_115200, 5163 }, { 5164 PCI_VDEVICE(AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030), 5165 .driver_data = pbn_b0_bt_8_115200, 5166 }, { 5167 PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_DSERIAL), 5168 .driver_data = pbn_b0_bt_2_115200, 5169 }, { 5170 PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A), 5171 .driver_data = pbn_b0_bt_2_115200, 5172 }, { 5173 PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B), 5174 .driver_data = pbn_b0_bt_2_115200, 5175 }, { 5176 PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_OCTO_A), 5177 .driver_data = pbn_b0_bt_4_460800, 5178 }, { 5179 PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_OCTO_B), 5180 .driver_data = pbn_b0_bt_4_460800, 5181 }, { 5182 PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS), 5183 .driver_data = pbn_b0_bt_2_460800, 5184 }, { 5185 PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_QUAD_A), 5186 .driver_data = pbn_b0_bt_2_460800, 5187 }, { 5188 PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_QUAD_B), 5189 .driver_data = pbn_b0_bt_2_460800, 5190 }, { 5191 PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_SSERIAL), 5192 .driver_data = pbn_b0_bt_1_115200, 5193 }, { 5194 PCI_VDEVICE(LAVA, PCI_DEVICE_ID_LAVA_PORT_650), 5195 .driver_data = pbn_b0_bt_1_460800, 5196 }, 5197 5198 /* 5199 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408). 5200 * Cards are identified by their subsystem vendor IDs, which 5201 * (in hex) match the model number. 5202 * 5203 * Note that JC140x are RS422/485 cards which require ox950 5204 * ACR = 0x10, and as such are not currently fully supported. 5205 */ 5206 { 5207 PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5208 0x1204, 0x0004), 5209 .driver_data = pbn_b0_4_921600, 5210 }, { 5211 PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5212 0x1208, 0x0004), 5213 .driver_data = pbn_b0_4_921600, 5214 }, 5215 /* { 5216 PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5217 0x1402, 0x0002), 5218 .driver_data = pbn_b0_2_921600, 5219 }, */ 5220 /* { 5221 PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0, 5222 0x1404, 0x0004), 5223 .driver_data = pbn_b0_4_921600, 5224 }, */ 5225 { 5226 PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1, 5227 0x1208, 0x0004), 5228 .driver_data = pbn_b0_4_921600, 5229 }, { 5230 PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 5231 0x1204, 0x0004), 5232 .driver_data = pbn_b0_4_921600, 5233 }, { 5234 PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2, 5235 0x1208, 0x0004), 5236 .driver_data = pbn_b0_4_921600, 5237 }, { 5238 PCI_VDEVICE_SUB(KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3, 5239 0x1208, 0x0004), 5240 .driver_data = pbn_b0_4_921600, 5241 }, 5242 /* 5243 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com 5244 */ 5245 { 5246 PCI_VDEVICE(DELL, PCI_DEVICE_ID_DELL_RAC4), 5247 .driver_data = pbn_b1_1_1382400, 5248 }, 5249 5250 /* 5251 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com 5252 */ 5253 { 5254 PCI_VDEVICE(DELL, PCI_DEVICE_ID_DELL_RACIII), 5255 .driver_data = pbn_b1_1_1382400, 5256 }, 5257 5258 /* 5259 * RAStel 2 port modem, gerg@moreton.com.au 5260 */ 5261 { 5262 PCI_VDEVICE(MORETON, PCI_DEVICE_ID_RASTEL_2PORT), 5263 .driver_data = pbn_b2_bt_2_115200, 5264 }, 5265 5266 /* 5267 * EKF addition for i960 Boards form EKF with serial port 5268 */ 5269 { 5270 PCI_VDEVICE_SUB(INTEL, PCI_DEVICE_ID_INTEL_80960_RP, 5271 0xE4BF, PCI_ANY_ID), 5272 .driver_data = pbn_intel_i960, 5273 }, 5274 5275 /* 5276 * Xircom Cardbus/Ethernet combos 5277 */ 5278 { 5279 PCI_VDEVICE(XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM), 5280 .driver_data = pbn_b0_1_115200, 5281 }, 5282 /* 5283 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry) 5284 */ 5285 { 5286 PCI_VDEVICE(XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G), 5287 .driver_data = pbn_b0_1_115200, 5288 }, 5289 5290 /* 5291 * Untested PCI modems, sent in from various folks... 5292 */ 5293 5294 { 5295 /* Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de> */ 5296 PCI_VDEVICE_SUB(ROCKWELL, 0x1004, 0x1048, 0x1500), 5297 .driver_data = pbn_b1_1_115200, 5298 }, { 5299 PCI_VDEVICE_SUB(SGI, PCI_DEVICE_ID_SGI_IOC3, 0xFF00, 0), 5300 .driver_data = pbn_sgi_ioc3, 5301 }, 5302 5303 /* 5304 * HP Diva card 5305 */ 5306 { 5307 PCI_VDEVICE_SUB(HP, PCI_DEVICE_ID_HP_DIVA, 5308 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3), 5309 .driver_data = pbn_b1_1_115200, 5310 }, { 5311 PCI_VDEVICE(HP, PCI_DEVICE_ID_HP_DIVA), 5312 .driver_data = pbn_b0_5_115200, 5313 }, { 5314 PCI_VDEVICE(HP, PCI_DEVICE_ID_HP_DIVA_AUX), 5315 .driver_data = pbn_b2_1_115200, 5316 }, { 5317 /* HPE PCI serial device */ 5318 PCI_VDEVICE(HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL), 5319 .driver_data = pbn_b1_1_115200, 5320 }, { 5321 PCI_VDEVICE(DCI, PCI_DEVICE_ID_DCI_PCCOM2), 5322 .driver_data = pbn_b3_2_115200, 5323 }, { 5324 PCI_VDEVICE(DCI, PCI_DEVICE_ID_DCI_PCCOM4), 5325 .driver_data = pbn_b3_4_115200, 5326 }, { 5327 PCI_VDEVICE(DCI, PCI_DEVICE_ID_DCI_PCCOM8), 5328 .driver_data = pbn_b3_8_115200, 5329 }, { 5330 /* Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke) */ 5331 PCI_VDEVICE(TOPIC, PCI_DEVICE_ID_TOPIC_TP560), 5332 .driver_data = pbn_b0_1_115200, 5333 }, { 5334 /* ITE */ 5335 PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8872), 5336 .driver_data = pbn_b1_bt_1_115200, 5337 }, { 5338 /* IntaShield IS-100 */ 5339 PCI_VDEVICE(INTASHIELD, 0x0D60), 5340 .driver_data = pbn_b2_1_115200, 5341 }, { 5342 /* IntaShield IS-200; 135a.0d80 */ 5343 PCI_VDEVICE(INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200), 5344 .driver_data = pbn_b2_2_115200, 5345 }, { 5346 /* IntaShield IS-400; 135a.0dc0 */ 5347 PCI_VDEVICE(INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400), 5348 .driver_data = pbn_b2_4_115200, 5349 }, { 5350 /* IntaShield IX-100 */ 5351 PCI_VDEVICE(INTASHIELD, 0x4027), 5352 .driver_data = pbn_oxsemi_1_15625000, 5353 }, { 5354 /* IntaShield IX-200 */ 5355 PCI_VDEVICE(INTASHIELD, 0x4028), 5356 .driver_data = pbn_oxsemi_2_15625000, 5357 }, { 5358 /* IntaShield IX-400 */ 5359 PCI_VDEVICE(INTASHIELD, 0x4029), 5360 .driver_data = pbn_oxsemi_4_15625000, 5361 }, 5362 /* Brainboxes Devices */ 5363 /* 5364 * Brainboxes UC-101 5365 */ 5366 { 5367 PCI_VDEVICE(INTASHIELD, 0x0BA1), 5368 .driver_data = pbn_b2_2_115200, 5369 }, { 5370 PCI_VDEVICE(INTASHIELD, 0x0BA2), 5371 .driver_data = pbn_b2_2_115200, 5372 }, { 5373 PCI_VDEVICE(INTASHIELD, 0x0BA3), 5374 .driver_data = pbn_b2_2_115200, 5375 }, 5376 /* 5377 * Brainboxes UC-235/246 5378 */ 5379 { 5380 PCI_VDEVICE(INTASHIELD, 0x0AA1), 5381 .driver_data = pbn_b2_1_115200, 5382 }, { 5383 PCI_VDEVICE(INTASHIELD, 0x0AA2), 5384 .driver_data = pbn_b2_1_115200, 5385 }, 5386 /* 5387 * Brainboxes UC-253/UC-734 5388 */ 5389 { 5390 PCI_VDEVICE(INTASHIELD, 0x0CA1), 5391 .driver_data = pbn_b2_2_115200, 5392 }, 5393 /* 5394 * Brainboxes UC-260/271/701/756 5395 */ 5396 { 5397 PCI_DEVICE(PCI_VENDOR_ID_INTASHIELD, 0x0D21), 5398 .class = PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5399 .class_mask = 0xffff00, 5400 .driver_data = pbn_b2_4_115200, 5401 }, { 5402 PCI_DEVICE(PCI_VENDOR_ID_INTASHIELD, 0x0E34), 5403 .class = PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 5404 .class_mask = 0xffff00, 5405 .driver_data = pbn_b2_4_115200, 5406 }, 5407 /* 5408 * Brainboxes UC-268 5409 */ 5410 { 5411 PCI_VDEVICE(INTASHIELD, 0x0841), 5412 .driver_data = pbn_b2_4_115200, 5413 }, 5414 /* 5415 * Brainboxes UC-275/279 5416 */ 5417 { 5418 PCI_VDEVICE(INTASHIELD, 0x0881), 5419 .driver_data = pbn_b2_8_115200, 5420 }, 5421 /* 5422 * Brainboxes UC-302 5423 */ 5424 { 5425 PCI_VDEVICE(INTASHIELD, 0x08E1), 5426 .driver_data = pbn_b2_2_115200, 5427 }, { 5428 PCI_VDEVICE(INTASHIELD, 0x08E2), 5429 .driver_data = pbn_b2_2_115200, 5430 }, { 5431 PCI_VDEVICE(INTASHIELD, 0x08E3), 5432 .driver_data = pbn_b2_2_115200, 5433 }, 5434 /* 5435 * Brainboxes UC-310 5436 */ 5437 { 5438 PCI_VDEVICE(INTASHIELD, 0x08C1), 5439 .driver_data = pbn_b2_2_115200, 5440 }, 5441 /* 5442 * Brainboxes UC-313 5443 */ 5444 { 5445 PCI_VDEVICE(INTASHIELD, 0x08A1), 5446 .driver_data = pbn_b2_2_115200, 5447 }, { 5448 PCI_VDEVICE(INTASHIELD, 0x08A2), 5449 .driver_data = pbn_b2_2_115200, 5450 }, { 5451 PCI_VDEVICE(INTASHIELD, 0x08A3), 5452 .driver_data = pbn_b2_2_115200, 5453 }, 5454 /* 5455 * Brainboxes UC-320/324 5456 */ 5457 { 5458 PCI_VDEVICE(INTASHIELD, 0x0A61), 5459 .driver_data = pbn_b2_1_115200, 5460 }, 5461 /* 5462 * Brainboxes UC-346 5463 */ 5464 { 5465 PCI_VDEVICE(INTASHIELD, 0x0B01), 5466 .driver_data = pbn_b2_4_115200, 5467 }, { 5468 PCI_VDEVICE(INTASHIELD, 0x0B02), 5469 .driver_data = pbn_b2_4_115200, 5470 }, 5471 /* 5472 * Brainboxes UC-357 5473 */ 5474 { 5475 PCI_VDEVICE(INTASHIELD, 0x0A81), 5476 .driver_data = pbn_b2_2_115200, 5477 }, { 5478 PCI_VDEVICE(INTASHIELD, 0x0A82), 5479 .driver_data = pbn_b2_2_115200, 5480 }, { 5481 PCI_VDEVICE(INTASHIELD, 0x0A83), 5482 .driver_data = pbn_b2_2_115200, 5483 }, 5484 /* 5485 * Brainboxes UC-368 5486 */ 5487 { 5488 PCI_VDEVICE(INTASHIELD, 0x0C41), 5489 .driver_data = pbn_b2_4_115200, 5490 }, { 5491 PCI_VDEVICE(INTASHIELD, 0x0C42), 5492 .driver_data = pbn_b2_4_115200, 5493 }, { 5494 PCI_VDEVICE(INTASHIELD, 0x0C43), 5495 .driver_data = pbn_b2_4_115200, 5496 }, 5497 /* 5498 * Brainboxes UC-420 5499 */ 5500 { 5501 PCI_VDEVICE(INTASHIELD, 0x0921), 5502 .driver_data = pbn_b2_4_115200, 5503 }, 5504 /* 5505 * Brainboxes UC-607 5506 */ 5507 { 5508 PCI_VDEVICE(INTASHIELD, 0x09A1), 5509 .driver_data = pbn_b2_2_115200, 5510 }, { 5511 PCI_VDEVICE(INTASHIELD, 0x09A2), 5512 .driver_data = pbn_b2_2_115200, 5513 }, { 5514 PCI_VDEVICE(INTASHIELD, 0x09A3), 5515 .driver_data = pbn_b2_2_115200, 5516 }, 5517 /* 5518 * Brainboxes UC-836 5519 */ 5520 { 5521 PCI_VDEVICE(INTASHIELD, 0x0D41), 5522 .driver_data = pbn_b2_4_115200, 5523 }, 5524 /* 5525 * Brainboxes UP-189 5526 */ 5527 { 5528 PCI_VDEVICE(INTASHIELD, 0x0AC1), 5529 .driver_data = pbn_b2_2_115200, 5530 }, { 5531 PCI_VDEVICE(INTASHIELD, 0x0AC2), 5532 .driver_data = pbn_b2_2_115200, 5533 }, { 5534 PCI_VDEVICE(INTASHIELD, 0x0AC3), 5535 .driver_data = pbn_b2_2_115200, 5536 }, 5537 /* 5538 * Brainboxes UP-200 5539 */ 5540 { 5541 PCI_VDEVICE(INTASHIELD, 0x0B21), 5542 .driver_data = pbn_b2_2_115200, 5543 }, { 5544 PCI_VDEVICE(INTASHIELD, 0x0B22), 5545 .driver_data = pbn_b2_2_115200, 5546 }, { 5547 PCI_VDEVICE(INTASHIELD, 0x0B23), 5548 .driver_data = pbn_b2_2_115200, 5549 }, 5550 /* 5551 * Brainboxes UP-869 5552 */ 5553 { 5554 PCI_VDEVICE(INTASHIELD, 0x0C01), 5555 .driver_data = pbn_b2_2_115200, 5556 }, { 5557 PCI_VDEVICE(INTASHIELD, 0x0C02), 5558 .driver_data = pbn_b2_2_115200, 5559 }, { 5560 PCI_VDEVICE(INTASHIELD, 0x0C03), 5561 .driver_data = pbn_b2_2_115200, 5562 }, 5563 /* 5564 * Brainboxes UP-880 5565 */ 5566 { 5567 PCI_VDEVICE(INTASHIELD, 0x0C21), 5568 .driver_data = pbn_b2_2_115200, 5569 }, { 5570 PCI_VDEVICE(INTASHIELD, 0x0C22), 5571 .driver_data = pbn_b2_2_115200, 5572 }, { 5573 PCI_VDEVICE(INTASHIELD, 0x0C23), 5574 .driver_data = pbn_b2_2_115200, 5575 }, 5576 /* 5577 * Brainboxes PX-101 5578 */ 5579 { 5580 PCI_VDEVICE(INTASHIELD, 0x4005), 5581 .driver_data = pbn_b0_2_115200, 5582 }, { 5583 PCI_VDEVICE(INTASHIELD, 0x4019), 5584 .driver_data = pbn_oxsemi_2_15625000, 5585 }, 5586 /* 5587 * Brainboxes PX-235/246 5588 */ 5589 { 5590 PCI_VDEVICE(INTASHIELD, 0x4004), 5591 .driver_data = pbn_b0_1_115200, 5592 }, { 5593 PCI_VDEVICE(INTASHIELD, 0x4016), 5594 .driver_data = pbn_oxsemi_1_15625000, 5595 }, 5596 /* 5597 * Brainboxes PX-203/PX-257 5598 */ 5599 { 5600 PCI_VDEVICE(INTASHIELD, 0x4006), 5601 .driver_data = pbn_b0_2_115200, 5602 }, { 5603 PCI_VDEVICE(INTASHIELD, 0x4015), 5604 .driver_data = pbn_oxsemi_2_15625000, 5605 }, 5606 /* 5607 * Brainboxes PX-260/PX-701 5608 */ 5609 { 5610 PCI_VDEVICE(INTASHIELD, 0x400A), 5611 .driver_data = pbn_oxsemi_4_15625000, 5612 }, 5613 /* 5614 * Brainboxes PX-275/279 5615 */ 5616 { 5617 PCI_VDEVICE(INTASHIELD, 0x0E41), 5618 .driver_data = pbn_b2_8_115200, 5619 }, 5620 /* 5621 * Brainboxes PX-310 5622 */ 5623 { 5624 PCI_VDEVICE(INTASHIELD, 0x400E), 5625 .driver_data = pbn_oxsemi_2_15625000, 5626 }, 5627 /* 5628 * Brainboxes PX-313 5629 */ 5630 { 5631 PCI_VDEVICE(INTASHIELD, 0x400C), 5632 .driver_data = pbn_oxsemi_2_15625000, 5633 }, 5634 /* 5635 * Brainboxes PX-320/324/PX-376/PX-387 5636 */ 5637 { 5638 PCI_VDEVICE(INTASHIELD, 0x400B), 5639 .driver_data = pbn_oxsemi_1_15625000, 5640 }, 5641 /* 5642 * Brainboxes PX-335/346 5643 */ 5644 { 5645 PCI_VDEVICE(INTASHIELD, 0x400F), 5646 .driver_data = pbn_oxsemi_4_15625000, 5647 }, 5648 /* 5649 * Brainboxes PX-368 5650 */ 5651 { 5652 PCI_VDEVICE(INTASHIELD, 0x4010), 5653 .driver_data = pbn_oxsemi_4_15625000, 5654 }, 5655 /* 5656 * Brainboxes PX-420 5657 */ 5658 { 5659 PCI_VDEVICE(INTASHIELD, 0x4000), 5660 .driver_data = pbn_b0_4_115200, 5661 }, { 5662 PCI_VDEVICE(INTASHIELD, 0x4011), 5663 .driver_data = pbn_oxsemi_4_15625000, 5664 }, 5665 /* 5666 * Brainboxes PX-475 5667 */ 5668 { 5669 PCI_VDEVICE(INTASHIELD, 0x401D), 5670 .driver_data = pbn_oxsemi_1_15625000, 5671 }, 5672 /* 5673 * Brainboxes PX-803/PX-857 5674 */ 5675 { 5676 PCI_VDEVICE(INTASHIELD, 0x4009), 5677 .driver_data = pbn_b0_2_115200, 5678 }, { 5679 PCI_VDEVICE(INTASHIELD, 0x4018), 5680 .driver_data = pbn_oxsemi_2_15625000, 5681 }, { 5682 PCI_VDEVICE(INTASHIELD, 0x401E), 5683 .driver_data = pbn_oxsemi_2_15625000, 5684 }, 5685 /* 5686 * Brainboxes PX-820 5687 */ 5688 { 5689 PCI_VDEVICE(INTASHIELD, 0x4002), 5690 .driver_data = pbn_b0_4_115200, 5691 }, { 5692 PCI_VDEVICE(INTASHIELD, 0x4013), 5693 .driver_data = pbn_oxsemi_4_15625000, 5694 }, 5695 /* 5696 * Brainboxes PX-835/PX-846 5697 */ 5698 { 5699 PCI_VDEVICE(INTASHIELD, 0x4008), 5700 .driver_data = pbn_b0_1_115200, 5701 }, { 5702 PCI_VDEVICE(INTASHIELD, 0x4017), 5703 .driver_data = pbn_oxsemi_1_15625000, 5704 }, 5705 /* 5706 * Brainboxes XC-235 5707 */ 5708 { 5709 PCI_VDEVICE(INTASHIELD, 0x4026), 5710 .driver_data = pbn_oxsemi_1_15625000, 5711 }, 5712 /* 5713 * Brainboxes XC-475 5714 */ 5715 { 5716 PCI_VDEVICE(INTASHIELD, 0x4021), 5717 .driver_data = pbn_oxsemi_1_15625000, 5718 }, 5719 5720 /* 5721 * Perle PCI-RAS cards 5722 */ 5723 { 5724 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9030, 5725 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4), 5726 .driver_data = pbn_b2_4_921600, 5727 }, 5728 { 5729 PCI_VDEVICE_SUB(PLX, PCI_DEVICE_ID_PLX_9030, 5730 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8), 5731 .driver_data = pbn_b2_8_921600, 5732 }, 5733 5734 /* 5735 * Mainpine series cards: Fairly standard layout but fools 5736 * parts of the autodetect in some cases and uses otherwise 5737 * unmatched communications subclasses in the PCI Express case 5738 */ 5739 5740 { 5741 /* RockForceDUO */ 5742 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5743 PCI_VENDOR_ID_MAINPINE, 0x0200), 5744 .driver_data = pbn_b0_2_115200, 5745 }, { 5746 /* RockForceQUATRO */ 5747 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5748 PCI_VENDOR_ID_MAINPINE, 0x0300), 5749 .driver_data = pbn_b0_4_115200, 5750 }, { 5751 /* RockForceDUO+ */ 5752 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5753 PCI_VENDOR_ID_MAINPINE, 0x0400), 5754 .driver_data = pbn_b0_2_115200, 5755 }, { 5756 /* RockForceQUATRO+ */ 5757 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5758 PCI_VENDOR_ID_MAINPINE, 0x0500), 5759 .driver_data = pbn_b0_4_115200, 5760 }, { 5761 /* RockForce+ */ 5762 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5763 PCI_VENDOR_ID_MAINPINE, 0x0600), 5764 .driver_data = pbn_b0_2_115200, 5765 }, { 5766 /* RockForce+ */ 5767 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5768 PCI_VENDOR_ID_MAINPINE, 0x0700), 5769 .driver_data = pbn_b0_4_115200, 5770 }, { 5771 /* RockForceOCTO+ */ 5772 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5773 PCI_VENDOR_ID_MAINPINE, 0x0800), 5774 .driver_data = pbn_b0_8_115200, 5775 }, { 5776 /* RockForceDUO+ */ 5777 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5778 PCI_VENDOR_ID_MAINPINE, 0x0C00), 5779 .driver_data = pbn_b0_2_115200, 5780 }, { 5781 /* RockForceQUARTRO+ */ 5782 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5783 PCI_VENDOR_ID_MAINPINE, 0x0D00), 5784 .driver_data = pbn_b0_4_115200, 5785 }, { 5786 /* RockForceOCTO+ */ 5787 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5788 PCI_VENDOR_ID_MAINPINE, 0x1D00), 5789 .driver_data = pbn_b0_8_115200, 5790 }, { 5791 /* RockForceD1 */ 5792 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5793 PCI_VENDOR_ID_MAINPINE, 0x2000), 5794 .driver_data = pbn_b0_1_115200, 5795 }, { 5796 /* RockForceF1 */ 5797 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5798 PCI_VENDOR_ID_MAINPINE, 0x2100), 5799 .driver_data = pbn_b0_1_115200, 5800 }, { /* RockForceD2 */ 5801 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5802 PCI_VENDOR_ID_MAINPINE, 0x2200), 5803 .driver_data = pbn_b0_2_115200, 5804 }, { /* RockForceF2 */ 5805 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5806 PCI_VENDOR_ID_MAINPINE, 0x2300), 5807 .driver_data = pbn_b0_2_115200, 5808 }, { 5809 /* RockForceD4 */ 5810 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5811 PCI_VENDOR_ID_MAINPINE, 0x2400), 5812 .driver_data = pbn_b0_4_115200, 5813 }, { 5814 /* RockForceF4 */ 5815 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5816 PCI_VENDOR_ID_MAINPINE, 0x2500), 5817 .driver_data = pbn_b0_4_115200, 5818 }, { 5819 /* RockForceD8 */ 5820 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5821 PCI_VENDOR_ID_MAINPINE, 0x2600), 5822 .driver_data = pbn_b0_8_115200, 5823 }, { 5824 /* RockForceF8 */ 5825 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5826 PCI_VENDOR_ID_MAINPINE, 0x2700), 5827 .driver_data = pbn_b0_8_115200, 5828 }, { 5829 /* IQ Express D1 */ 5830 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5831 PCI_VENDOR_ID_MAINPINE, 0x3000), 5832 .driver_data = pbn_b0_1_115200, 5833 }, { 5834 /* IQ Express F1 */ 5835 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5836 PCI_VENDOR_ID_MAINPINE, 0x3100), 5837 .driver_data = pbn_b0_1_115200, 5838 }, { 5839 /* IQ Express D2 */ 5840 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5841 PCI_VENDOR_ID_MAINPINE, 0x3200), 5842 .driver_data = pbn_b0_2_115200, 5843 }, { 5844 /* IQ Express F2 */ 5845 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5846 PCI_VENDOR_ID_MAINPINE, 0x3300), 5847 .driver_data = pbn_b0_2_115200, 5848 }, { 5849 /* IQ Express D4 */ 5850 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5851 PCI_VENDOR_ID_MAINPINE, 0x3400), 5852 .driver_data = pbn_b0_4_115200, 5853 }, { 5854 /* IQ Express F4 */ 5855 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5856 PCI_VENDOR_ID_MAINPINE, 0x3500), 5857 .driver_data = pbn_b0_4_115200, 5858 }, { 5859 /* IQ Express D8 */ 5860 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5861 PCI_VENDOR_ID_MAINPINE, 0x3C00), 5862 .driver_data = pbn_b0_8_115200, 5863 }, { 5864 /* IQ Express F8 */ 5865 PCI_VDEVICE_SUB(MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE, 5866 PCI_VENDOR_ID_MAINPINE, 0x3D00), 5867 .driver_data = pbn_b0_8_115200, 5868 }, 5869 5870 { 5871 /* PA Semi PA6T-1682M on-chip UART */ 5872 PCI_VDEVICE(PASEMI, 0xa004), 5873 .driver_data = pbn_pasemi_1682M, 5874 }, 5875 5876 /* 5877 * National Instruments 5878 */ 5879 { 5880 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI23216), 5881 .driver_data = pbn_b1_16_115200, 5882 }, { 5883 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI2328), 5884 .driver_data = pbn_b1_8_115200, 5885 }, { 5886 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI2324), 5887 .driver_data = pbn_b1_bt_4_115200, 5888 }, { 5889 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI2322), 5890 .driver_data = pbn_b1_bt_2_115200, 5891 }, { 5892 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI2324I), 5893 .driver_data = pbn_b1_bt_4_115200, 5894 }, { 5895 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI2322I), 5896 .driver_data = pbn_b1_bt_2_115200, 5897 }, { 5898 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8420_23216), 5899 .driver_data = pbn_b1_16_115200, 5900 }, { 5901 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8420_2328), 5902 .driver_data = pbn_b1_8_115200, 5903 }, { 5904 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8420_2324), 5905 .driver_data = pbn_b1_bt_4_115200, 5906 }, { 5907 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8420_2322), 5908 .driver_data = pbn_b1_bt_2_115200, 5909 }, { 5910 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8422_2324), 5911 .driver_data = pbn_b1_bt_4_115200, 5912 }, { 5913 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8422_2322), 5914 .driver_data = pbn_b1_bt_2_115200, 5915 }, { 5916 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8430_2322), 5917 .driver_data = pbn_ni8430_2, 5918 }, { 5919 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI8430_2322), 5920 .driver_data = pbn_ni8430_2, 5921 }, { 5922 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8430_2324), 5923 .driver_data = pbn_ni8430_4, 5924 }, { 5925 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI8430_2324), 5926 .driver_data = pbn_ni8430_4, 5927 }, { 5928 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8430_2328), 5929 .driver_data = pbn_ni8430_8, 5930 }, { 5931 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI8430_2328), 5932 .driver_data = pbn_ni8430_8, 5933 }, { 5934 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8430_23216), 5935 .driver_data = pbn_ni8430_16, 5936 }, { 5937 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI8430_23216), 5938 .driver_data = pbn_ni8430_16, 5939 }, { 5940 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8432_2322), 5941 .driver_data = pbn_ni8430_2, 5942 }, { 5943 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI8432_2322), 5944 .driver_data = pbn_ni8430_2, 5945 }, { 5946 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PXI8432_2324), 5947 .driver_data = pbn_ni8430_4, 5948 }, { 5949 PCI_VDEVICE(NI, PCI_DEVICE_ID_NI_PCI8432_2324), 5950 .driver_data = pbn_ni8430_4, 5951 }, 5952 5953 /* 5954 * MOXA 5955 */ 5956 { 5957 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102E), 5958 .driver_data = pbn_moxa_2, 5959 }, { 5960 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102EL), 5961 .driver_data = pbn_moxa_2, 5962 }, { 5963 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102N), 5964 .driver_data = pbn_moxa_2, 5965 }, { 5966 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL_A), 5967 .driver_data = pbn_moxa_4, 5968 }, { 5969 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104N), 5970 .driver_data = pbn_moxa_4, 5971 }, { 5972 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP112N), 5973 .driver_data = pbn_moxa_2, 5974 }, { 5975 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114EL), 5976 .driver_data = pbn_moxa_4, 5977 }, { 5978 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114N), 5979 .driver_data = pbn_moxa_4, 5980 }, { 5981 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_A), 5982 .driver_data = pbn_moxa_8, 5983 }, { 5984 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP116E_A_B), 5985 .driver_data = pbn_moxa_8, 5986 }, { 5987 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL_A), 5988 .driver_data = pbn_moxa_8, 5989 }, { 5990 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118E_A_I), 5991 .driver_data = pbn_moxa_8, 5992 }, { 5993 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132EL), 5994 .driver_data = pbn_moxa_2, 5995 }, { 5996 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132N), 5997 .driver_data = pbn_moxa_2, 5998 }, { 5999 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134EL_A), 6000 .driver_data = pbn_moxa_4, 6001 }, { 6002 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134N), 6003 .driver_data = pbn_moxa_4, 6004 }, { 6005 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP138E_A), 6006 .driver_data = pbn_moxa_8, 6007 }, { 6008 PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL_A), 6009 .driver_data = pbn_moxa_8, 6010 }, 6011 6012 /* 6013 * ADDI-DATA GmbH communication cards <info@addi-data.com> 6014 */ 6015 { 6016 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7500), 6017 .driver_data = pbn_b0_4_115200, 6018 }, { 6019 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7420), 6020 .driver_data = pbn_b0_2_115200, 6021 }, { 6022 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7300), 6023 .driver_data = pbn_b0_1_115200, 6024 }, { 6025 PCI_VDEVICE(AMCC, PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800), 6026 .driver_data = pbn_b1_8_115200, 6027 }, { 6028 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7500_2), 6029 .driver_data = pbn_b0_4_115200, 6030 }, { 6031 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7420_2), 6032 .driver_data = pbn_b0_2_115200, 6033 }, { 6034 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7300_2), 6035 .driver_data = pbn_b0_1_115200, 6036 }, { 6037 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7500_3), 6038 .driver_data = pbn_b0_4_115200, 6039 }, { 6040 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7420_3), 6041 .driver_data = pbn_b0_2_115200, 6042 }, { 6043 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7300_3), 6044 .driver_data = pbn_b0_1_115200, 6045 }, { 6046 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCI7800_3), 6047 .driver_data = pbn_b0_8_115200, 6048 }, { 6049 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCIe7500), 6050 .driver_data = pbn_ADDIDATA_PCIe_4_3906250, 6051 }, { 6052 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCIe7420), 6053 .driver_data = pbn_ADDIDATA_PCIe_2_3906250, 6054 }, { 6055 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCIe7300), 6056 .driver_data = pbn_ADDIDATA_PCIe_1_3906250, 6057 }, { 6058 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_APCIe7800), 6059 .driver_data = pbn_ADDIDATA_PCIe_8_3906250, 6060 }, { 6061 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_CPCI7500), 6062 .driver_data = pbn_b0_4_115200, 6063 }, { 6064 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_CPCI7500_NG), 6065 .driver_data = pbn_b0_4_115200, 6066 }, { 6067 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_CPCI7420_NG), 6068 .driver_data = pbn_b0_2_115200, 6069 }, { 6070 PCI_VDEVICE(ADDIDATA, PCI_DEVICE_ID_ADDIDATA_CPCI7300_NG), 6071 .driver_data = pbn_b0_1_115200, 6072 }, { 6073 PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9835, 6074 PCI_VENDOR_ID_IBM, 0x0299), 6075 .driver_data = pbn_b0_bt_2_115200, 6076 }, 6077 6078 /* 6079 * other NetMos 9835 devices are most likely handled by the 6080 * parport_serial driver, check drivers/parport/parport_serial.c 6081 * before adding them here. 6082 */ 6083 6084 { 6085 PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9901, 6086 0xA000, 0x1000), 6087 .driver_data = pbn_b0_1_115200, 6088 }, { 6089 /* the 9901 is a rebranded 9912 */ 6090 PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9912, 6091 0xA000, 0x1000), 6092 .driver_data = pbn_b0_1_115200, 6093 }, { 6094 PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9922, 6095 0xA000, 0x1000), 6096 .driver_data = pbn_b0_1_115200, 6097 }, { 6098 PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9904, 6099 0xA000, 0x1000), 6100 .driver_data = pbn_b0_1_115200, 6101 }, { 6102 PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9900, 6103 0xA000, 0x1000), 6104 .driver_data = pbn_b0_1_115200, 6105 }, { 6106 PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9900, 6107 0xA000, 0x3002), 6108 .driver_data = pbn_NETMOS9900_2s_115200, 6109 }, { 6110 PCI_DEVICE_SUB(PCIE_VENDOR_ID_ASIX, PCIE_DEVICE_ID_AX99100, 6111 0xA000, 0x1000), 6112 .driver_data = pbn_b0_1_115200, 6113 }, 6114 6115 /* 6116 * Best Connectivity and Rosewill PCI Multi I/O cards 6117 */ 6118 6119 { 6120 PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9865, 6121 0xA000, 0x1000), 6122 .driver_data = pbn_b0_1_115200, 6123 }, { 6124 PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9865, 6125 0xA000, 0x3002), 6126 .driver_data = pbn_b0_bt_2_115200, 6127 }, { 6128 PCI_VDEVICE_SUB(NETMOS, PCI_DEVICE_ID_NETMOS_9865, 6129 0xA000, 0x3004), 6130 .driver_data = pbn_b0_bt_4_115200, 6131 }, 6132 6133 /* 6134 * ASIX AX99100 PCIe to Multi I/O Controller 6135 */ 6136 { 6137 PCI_VDEVICE_SUB(ASIX, PCI_DEVICE_ID_ASIX_AX99100, 6138 0xA000, 0x1000), 6139 .driver_data = pbn_b0_1_115200, 6140 }, 6141 6142 /* Intel CE4100 */ 6143 { 6144 PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART), 6145 .driver_data = pbn_ce4100_1_115200, 6146 }, 6147 6148 /* 6149 * Cronyx Omega PCI 6150 */ 6151 { 6152 PCI_VDEVICE(PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA), 6153 .driver_data = pbn_omegapci, 6154 }, 6155 6156 /* 6157 * Broadcom TruManage 6158 */ 6159 { 6160 PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE), 6161 .driver_data = pbn_brcm_trumanage, 6162 }, 6163 6164 /* 6165 * AgeStar as-prs2-009 6166 */ 6167 { 6168 PCI_VDEVICE(AGESTAR, PCI_DEVICE_ID_AGESTAR_9375), 6169 .driver_data = pbn_b0_bt_2_115200, 6170 }, 6171 6172 /* 6173 * WCH CH353 series devices: The 2S1P is handled by parport_serial 6174 * so not listed here. 6175 */ 6176 { 6177 PCI_VDEVICE(WCHCN, PCI_DEVICE_ID_WCHCN_CH353_4S), 6178 .driver_data = pbn_b0_bt_4_115200, 6179 }, { 6180 PCI_VDEVICE(WCHCN, PCI_DEVICE_ID_WCHCN_CH353_2S1PF), 6181 .driver_data = pbn_b0_bt_2_115200, 6182 }, { 6183 PCI_VDEVICE(WCHCN, PCI_DEVICE_ID_WCHCN_CH355_4S), 6184 .driver_data = pbn_b0_bt_4_115200, 6185 }, { 6186 PCI_VDEVICE(WCHIC, PCI_DEVICE_ID_WCHIC_CH382_2S), 6187 .driver_data = pbn_wch382_2, 6188 }, { 6189 PCI_VDEVICE(WCHIC, PCI_DEVICE_ID_WCHIC_CH384_4S), 6190 .driver_data = pbn_wch384_4, 6191 }, { 6192 PCI_VDEVICE(WCHIC, PCI_DEVICE_ID_WCHIC_CH384_8S), 6193 .driver_data = pbn_wch384_8, 6194 }, 6195 6196 /* 6197 * Realtek RealManage 6198 */ 6199 { 6200 PCI_VDEVICE(REALTEK, 0x816a), 6201 .driver_data = pbn_b0_1_115200, 6202 }, { 6203 PCI_VDEVICE(REALTEK, 0x816b), 6204 .driver_data = pbn_b0_1_115200, 6205 }, 6206 6207 /* Systembase Multi I/O cards */ 6208 { 6209 PCI_VDEVICE(SYSTEMBASE, 0x0008), 6210 .driver_data = pbn_b0_8_921600, 6211 }, 6212 6213 /* Fintek PCI serial cards */ 6214 { 6215 PCI_DEVICE(0x1c29, 0x1104), 6216 .driver_data = pbn_fintek_4, 6217 }, { 6218 PCI_DEVICE(0x1c29, 0x1108), 6219 .driver_data = pbn_fintek_8, 6220 }, { 6221 PCI_DEVICE(0x1c29, 0x1112), 6222 .driver_data = pbn_fintek_12, 6223 }, { 6224 PCI_DEVICE(0x1c29, 0x1204), 6225 .driver_data = pbn_fintek_F81504A, 6226 }, { 6227 PCI_DEVICE(0x1c29, 0x1208), 6228 .driver_data = pbn_fintek_F81508A, 6229 }, { 6230 PCI_DEVICE(0x1c29, 0x1212), 6231 .driver_data = pbn_fintek_F81512A, 6232 }, 6233 6234 /* MKS Tenta SCOM-080x serial cards */ 6235 { 6236 PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000, 6237 }, { 6238 PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000, 6239 }, 6240 6241 /* Amazon PCI serial device */ 6242 { 6243 PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200, 6244 }, 6245 6246 /* 6247 * These entries match devices with class COMMUNICATION_SERIAL, 6248 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL 6249 */ 6250 { 6251 PCI_DEVICE_CLASS(PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00), 6252 .driver_data = pbn_default, 6253 }, { 6254 PCI_DEVICE_CLASS(PCI_CLASS_COMMUNICATION_MODEM << 8, 0xffff00), 6255 .driver_data = pbn_default, 6256 }, { 6257 PCI_DEVICE_CLASS(PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00), 6258 .driver_data = pbn_default, 6259 }, 6260 { } 6261 }; 6262 6263 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev, 6264 pci_channel_state_t state) 6265 { 6266 struct serial_private *priv = pci_get_drvdata(dev); 6267 6268 if (state == pci_channel_io_perm_failure) 6269 return PCI_ERS_RESULT_DISCONNECT; 6270 6271 if (priv) 6272 pciserial_detach_ports(priv); 6273 6274 pci_disable_device(dev); 6275 6276 return PCI_ERS_RESULT_NEED_RESET; 6277 } 6278 6279 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev) 6280 { 6281 int rc; 6282 6283 rc = pci_enable_device(dev); 6284 6285 if (rc) 6286 return PCI_ERS_RESULT_DISCONNECT; 6287 6288 pci_restore_state(dev); 6289 6290 return PCI_ERS_RESULT_RECOVERED; 6291 } 6292 6293 static void serial8250_io_resume(struct pci_dev *dev) 6294 { 6295 struct serial_private *priv = pci_get_drvdata(dev); 6296 struct serial_private *new; 6297 6298 if (!priv) 6299 return; 6300 6301 new = pciserial_init_ports(dev, priv->board); 6302 if (!IS_ERR(new)) { 6303 pci_set_drvdata(dev, new); 6304 kfree(priv); 6305 } 6306 } 6307 6308 static const struct pci_error_handlers serial8250_err_handler = { 6309 .error_detected = serial8250_io_error_detected, 6310 .slot_reset = serial8250_io_slot_reset, 6311 .resume = serial8250_io_resume, 6312 }; 6313 6314 static struct pci_driver serial_pci_driver = { 6315 .name = "serial", 6316 .probe = pciserial_init_one, 6317 .remove = pciserial_remove_one, 6318 .driver = { 6319 .pm = &pciserial_pm_ops, 6320 }, 6321 .id_table = serial_pci_tbl, 6322 .err_handler = &serial8250_err_handler, 6323 }; 6324 6325 module_pci_driver(serial_pci_driver); 6326 6327 MODULE_LICENSE("GPL"); 6328 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module"); 6329 MODULE_DEVICE_TABLE(pci, serial_pci_tbl); 6330 MODULE_IMPORT_NS("SERIAL_8250_PCI"); 6331