1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * IIO driver for Bosch BNO055 IMU 4 * 5 * Copyright (C) 2021-2022 Istituto Italiano di Tecnologia 6 * Electronic Design Laboratory 7 * Written by Andrea Merello <andrea.merello@iit.it> 8 * 9 * Portions of this driver are taken from the BNO055 driver patch 10 * from Vlad Dogaru which is Copyright (c) 2016, Intel Corporation. 11 * 12 * This driver is also based on BMI160 driver, which is: 13 * Copyright (c) 2016, Intel Corporation. 14 * Copyright (c) 2019, Martin Kelly. 15 */ 16 17 #include <linux/bitfield.h> 18 #include <linux/bitmap.h> 19 #include <linux/clk.h> 20 #include <linux/debugfs.h> 21 #include <linux/device.h> 22 #include <linux/firmware.h> 23 #include <linux/gpio/consumer.h> 24 #include <linux/module.h> 25 #include <linux/mutex.h> 26 #include <linux/regmap.h> 27 #include <linux/util_macros.h> 28 29 #include <linux/iio/buffer.h> 30 #include <linux/iio/iio.h> 31 #include <linux/iio/sysfs.h> 32 #include <linux/iio/trigger_consumer.h> 33 #include <linux/iio/triggered_buffer.h> 34 35 #include "bno055.h" 36 37 #define BNO055_FW_UID_FMT "bno055-caldata-%*phN.dat" 38 #define BNO055_FW_GENERIC_NAME "bno055-caldata.dat" 39 40 /* common registers */ 41 #define BNO055_PAGESEL_REG 0x7 42 43 /* page 0 registers */ 44 #define BNO055_CHIP_ID_REG 0x0 45 #define BNO055_CHIP_ID_MAGIC 0xA0 46 #define BNO055_SW_REV_LSB_REG 0x4 47 #define BNO055_SW_REV_MSB_REG 0x5 48 #define BNO055_ACC_DATA_X_LSB_REG 0x8 49 #define BNO055_ACC_DATA_Y_LSB_REG 0xA 50 #define BNO055_ACC_DATA_Z_LSB_REG 0xC 51 #define BNO055_MAG_DATA_X_LSB_REG 0xE 52 #define BNO055_MAG_DATA_Y_LSB_REG 0x10 53 #define BNO055_MAG_DATA_Z_LSB_REG 0x12 54 #define BNO055_GYR_DATA_X_LSB_REG 0x14 55 #define BNO055_GYR_DATA_Y_LSB_REG 0x16 56 #define BNO055_GYR_DATA_Z_LSB_REG 0x18 57 #define BNO055_EUL_DATA_X_LSB_REG 0x1A 58 #define BNO055_EUL_DATA_Y_LSB_REG 0x1C 59 #define BNO055_EUL_DATA_Z_LSB_REG 0x1E 60 #define BNO055_QUAT_DATA_W_LSB_REG 0x20 61 #define BNO055_LIA_DATA_X_LSB_REG 0x28 62 #define BNO055_LIA_DATA_Y_LSB_REG 0x2A 63 #define BNO055_LIA_DATA_Z_LSB_REG 0x2C 64 #define BNO055_GRAVITY_DATA_X_LSB_REG 0x2E 65 #define BNO055_GRAVITY_DATA_Y_LSB_REG 0x30 66 #define BNO055_GRAVITY_DATA_Z_LSB_REG 0x32 67 #define BNO055_SCAN_CH_COUNT ((BNO055_GRAVITY_DATA_Z_LSB_REG - BNO055_ACC_DATA_X_LSB_REG) / 2 + 1) 68 #define BNO055_TEMP_REG 0x34 69 #define BNO055_CALIB_STAT_REG 0x35 70 #define BNO055_CALIB_STAT_MAGN_SHIFT 0 71 #define BNO055_CALIB_STAT_ACCEL_SHIFT 2 72 #define BNO055_CALIB_STAT_GYRO_SHIFT 4 73 #define BNO055_CALIB_STAT_SYS_SHIFT 6 74 #define BNO055_SYS_ERR_REG 0x3A 75 #define BNO055_POWER_MODE_REG 0x3E 76 #define BNO055_POWER_MODE_NORMAL 0 77 #define BNO055_SYS_TRIGGER_REG 0x3F 78 #define BNO055_SYS_TRIGGER_RST_SYS BIT(5) 79 #define BNO055_SYS_TRIGGER_CLK_SEL BIT(7) 80 #define BNO055_OPR_MODE_REG 0x3D 81 #define BNO055_OPR_MODE_CONFIG 0x0 82 #define BNO055_OPR_MODE_AMG 0x7 83 #define BNO055_OPR_MODE_FUSION_FMC_OFF 0xB 84 #define BNO055_OPR_MODE_FUSION 0xC 85 #define BNO055_UNIT_SEL_REG 0x3B 86 /* Android orientation mode means: pitch value decreases turning clockwise */ 87 #define BNO055_UNIT_SEL_ANDROID BIT(7) 88 #define BNO055_UNIT_SEL_GYR_RPS BIT(1) 89 #define BNO055_CALDATA_START 0x55 90 #define BNO055_CALDATA_END 0x6A 91 #define BNO055_CALDATA_LEN 22 92 93 /* 94 * The difference in address between the register that contains the 95 * value and the register that contains the offset. This applies for 96 * accel, gyro and magn channels. 97 */ 98 #define BNO055_REG_OFFSET_ADDR 0x4D 99 100 /* page 1 registers */ 101 #define BNO055_PG1(x) ((x) | 0x80) 102 #define BNO055_ACC_CONFIG_REG BNO055_PG1(0x8) 103 #define BNO055_ACC_CONFIG_LPF_MASK GENMASK(4, 2) 104 #define BNO055_ACC_CONFIG_RANGE_MASK GENMASK(1, 0) 105 #define BNO055_MAG_CONFIG_REG BNO055_PG1(0x9) 106 #define BNO055_MAG_CONFIG_HIGHACCURACY 0x18 107 #define BNO055_MAG_CONFIG_ODR_MASK GENMASK(2, 0) 108 #define BNO055_GYR_CONFIG_REG BNO055_PG1(0xA) 109 #define BNO055_GYR_CONFIG_RANGE_MASK GENMASK(2, 0) 110 #define BNO055_GYR_CONFIG_LPF_MASK GENMASK(5, 3) 111 #define BNO055_GYR_AM_SET_REG BNO055_PG1(0x1F) 112 #define BNO055_UID_LOWER_REG BNO055_PG1(0x50) 113 #define BNO055_UID_HIGHER_REG BNO055_PG1(0x5F) 114 #define BNO055_UID_LEN 16 115 116 struct bno055_sysfs_attr { 117 const int *vals; 118 int len; 119 const int *fusion_vals; 120 const int *hw_xlate; 121 int hw_xlate_len; 122 int type; 123 }; 124 125 static const int bno055_acc_lpf_vals[] = { 126 7, 810000, 15, 630000, 31, 250000, 62, 500000, 127 125, 0, 250, 0, 500, 0, 1000, 0, 128 }; 129 130 static const struct bno055_sysfs_attr bno055_acc_lpf = { 131 .vals = bno055_acc_lpf_vals, 132 .len = ARRAY_SIZE(bno055_acc_lpf_vals), 133 .fusion_vals = (const int[]){62, 500000}, 134 .type = IIO_VAL_INT_PLUS_MICRO, 135 }; 136 137 static const int bno055_acc_range_vals[] = { 138 /* G: 2, 4, 8, 16 */ 139 1962, 3924, 7848, 15696 140 }; 141 142 static const struct bno055_sysfs_attr bno055_acc_range = { 143 .vals = bno055_acc_range_vals, 144 .len = ARRAY_SIZE(bno055_acc_range_vals), 145 .fusion_vals = (const int[]){3924}, /* 4G */ 146 .type = IIO_VAL_INT, 147 }; 148 149 /* 150 * Theoretically the IMU should return data in a given (i.e. fixed) unit 151 * regardless of the range setting. This happens for the accelerometer, but not 152 * for the gyroscope; the gyroscope range setting affects the scale. 153 * This is probably due to this[0] bug. 154 * For this reason we map the internal range setting onto the standard IIO scale 155 * attribute for gyro. 156 * Since the bug[0] may be fixed in future, we check for the IMU FW version and 157 * eventually warn the user. 158 * Currently we just don't care about "range" attributes for gyro. 159 * 160 * [0] https://community.bosch-sensortec.com/t5/MEMS-sensors-forum/BNO055-Wrong-sensitivity-resolution-in-datasheet/td-p/10266 161 */ 162 163 /* 164 * dps = hwval * (dps_range/2^15) 165 * rps = hwval * (rps_range/2^15) 166 * = hwval * (dps_range/(2^15 * k)) 167 * where k is rad-to-deg factor 168 */ 169 static const int bno055_gyr_scale_vals[] = { 170 125, 1877467, 250, 1877467, 500, 1877467, 171 1000, 1877467, 2000, 1877467, 172 }; 173 174 static const int bno055_gyr_scale_hw_xlate[] = {0, 1, 2, 3, 4}; 175 static const struct bno055_sysfs_attr bno055_gyr_scale = { 176 .vals = bno055_gyr_scale_vals, 177 .len = ARRAY_SIZE(bno055_gyr_scale_vals), 178 .fusion_vals = (const int[]){1, 900}, 179 .hw_xlate = bno055_gyr_scale_hw_xlate, 180 .hw_xlate_len = ARRAY_SIZE(bno055_gyr_scale_hw_xlate), 181 .type = IIO_VAL_FRACTIONAL, 182 }; 183 184 static const int bno055_gyr_lpf_vals[] = {12, 23, 32, 47, 64, 116, 230, 523}; 185 static const int bno055_gyr_lpf_hw_xlate[] = {5, 4, 7, 3, 6, 2, 1, 0}; 186 static const struct bno055_sysfs_attr bno055_gyr_lpf = { 187 .vals = bno055_gyr_lpf_vals, 188 .len = ARRAY_SIZE(bno055_gyr_lpf_vals), 189 .fusion_vals = (const int[]){32}, 190 .hw_xlate = bno055_gyr_lpf_hw_xlate, 191 .hw_xlate_len = ARRAY_SIZE(bno055_gyr_lpf_hw_xlate), 192 .type = IIO_VAL_INT, 193 }; 194 195 static const int bno055_mag_odr_vals[] = {2, 6, 8, 10, 15, 20, 25, 30}; 196 static const struct bno055_sysfs_attr bno055_mag_odr = { 197 .vals = bno055_mag_odr_vals, 198 .len = ARRAY_SIZE(bno055_mag_odr_vals), 199 .fusion_vals = (const int[]){20}, 200 .type = IIO_VAL_INT, 201 }; 202 203 struct bno055_priv { 204 struct regmap *regmap; 205 struct device *dev; 206 struct clk *clk; 207 int operation_mode; 208 int xfer_burst_break_thr; 209 struct mutex lock; 210 u8 uid[BNO055_UID_LEN]; 211 struct gpio_desc *reset_gpio; 212 bool sw_reset; 213 union { 214 IIO_DECLARE_BUFFER_WITH_TS(__le16, chans, BNO055_SCAN_CH_COUNT); 215 /* 216 * This struct is not used, but it is here to ensure proper size 217 * and alignment of the scan buffer above (because of the extra 218 * requirements of the quaternion field). Technically it is not 219 * needed in this case, because other fields just happen to make 220 * things correctly aligned already. But it is better to be 221 * explicit about the requirements anyway. The actual contents 222 * of the scan buffer will vary depending on which channels are 223 * enabled. 224 */ 225 struct { 226 __le16 acc[3]; 227 __le16 magn[3]; 228 __le16 gyr[3]; 229 __le16 yaw; 230 __le16 pitch; 231 __le16 roll; 232 IIO_DECLARE_QUATERNION(__le16, quaternion); 233 __le16 lia[3]; 234 __le16 gravity[3]; 235 aligned_s64 timestamp; 236 }; 237 } buf; 238 struct dentry *debugfs; 239 }; 240 241 static bool bno055_regmap_volatile(struct device *dev, unsigned int reg) 242 { 243 /* data and status registers */ 244 if (reg >= BNO055_ACC_DATA_X_LSB_REG && reg <= BNO055_SYS_ERR_REG) 245 return true; 246 247 /* when in fusion mode, config is updated by chip */ 248 if (reg == BNO055_MAG_CONFIG_REG || 249 reg == BNO055_ACC_CONFIG_REG || 250 reg == BNO055_GYR_CONFIG_REG) 251 return true; 252 253 /* calibration data may be updated by the IMU */ 254 if (reg >= BNO055_CALDATA_START && reg <= BNO055_CALDATA_END) 255 return true; 256 257 return false; 258 } 259 260 static bool bno055_regmap_readable(struct device *dev, unsigned int reg) 261 { 262 /* unnamed PG0 reserved areas */ 263 if ((reg < BNO055_PG1(0) && reg > BNO055_CALDATA_END) || 264 reg == 0x3C) 265 return false; 266 267 /* unnamed PG1 reserved areas */ 268 if (reg > BNO055_PG1(BNO055_UID_HIGHER_REG) || 269 (reg < BNO055_PG1(BNO055_UID_LOWER_REG) && reg > BNO055_PG1(BNO055_GYR_AM_SET_REG)) || 270 reg == BNO055_PG1(0xE) || 271 (reg < BNO055_PG1(BNO055_PAGESEL_REG) && reg >= BNO055_PG1(0x0))) 272 return false; 273 return true; 274 } 275 276 static bool bno055_regmap_writeable(struct device *dev, unsigned int reg) 277 { 278 /* 279 * Unreadable registers are indeed reserved; there are no WO regs 280 * (except for a single bit in SYS_TRIGGER register) 281 */ 282 if (!bno055_regmap_readable(dev, reg)) 283 return false; 284 285 /* data and status registers */ 286 if (reg >= BNO055_ACC_DATA_X_LSB_REG && reg <= BNO055_SYS_ERR_REG) 287 return false; 288 289 /* ID areas */ 290 if (reg < BNO055_PAGESEL_REG || 291 (reg <= BNO055_UID_HIGHER_REG && reg >= BNO055_UID_LOWER_REG)) 292 return false; 293 294 return true; 295 } 296 297 static const struct regmap_range_cfg bno055_regmap_ranges[] = { 298 { 299 .range_min = 0, 300 .range_max = 0x7f * 2, 301 .selector_reg = BNO055_PAGESEL_REG, 302 .selector_mask = GENMASK(7, 0), 303 .selector_shift = 0, 304 .window_start = 0, 305 .window_len = 0x80, 306 }, 307 }; 308 309 const struct regmap_config bno055_regmap_config = { 310 .name = "bno055", 311 .reg_bits = 8, 312 .val_bits = 8, 313 .ranges = bno055_regmap_ranges, 314 .num_ranges = 1, 315 .volatile_reg = bno055_regmap_volatile, 316 .max_register = 0x80 * 2, 317 .writeable_reg = bno055_regmap_writeable, 318 .readable_reg = bno055_regmap_readable, 319 .cache_type = REGCACHE_MAPLE, 320 }; 321 EXPORT_SYMBOL_NS_GPL(bno055_regmap_config, "IIO_BNO055"); 322 323 /* must be called in configuration mode */ 324 static int bno055_calibration_load(struct bno055_priv *priv, const u8 *data, int len) 325 { 326 if (len != BNO055_CALDATA_LEN) { 327 dev_dbg(priv->dev, "Invalid calibration file size %d (expected %d)", 328 len, BNO055_CALDATA_LEN); 329 return -EINVAL; 330 } 331 332 dev_dbg(priv->dev, "loading cal data: %*ph", BNO055_CALDATA_LEN, data); 333 return regmap_bulk_write(priv->regmap, BNO055_CALDATA_START, 334 data, BNO055_CALDATA_LEN); 335 } 336 337 static int bno055_operation_mode_do_set(struct bno055_priv *priv, 338 int operation_mode) 339 { 340 int ret; 341 342 ret = regmap_write(priv->regmap, BNO055_OPR_MODE_REG, 343 operation_mode); 344 if (ret) 345 return ret; 346 347 /* Following datasheet specifications: sensor takes 7mS up to 19 mS to switch mode */ 348 msleep(20); 349 350 return 0; 351 } 352 353 static int bno055_system_reset(struct bno055_priv *priv) 354 { 355 int ret; 356 357 if (priv->reset_gpio) { 358 gpiod_set_value_cansleep(priv->reset_gpio, 0); 359 usleep_range(5000, 10000); 360 gpiod_set_value_cansleep(priv->reset_gpio, 1); 361 } else if (priv->sw_reset) { 362 ret = regmap_write(priv->regmap, BNO055_SYS_TRIGGER_REG, 363 BNO055_SYS_TRIGGER_RST_SYS); 364 if (ret) 365 return ret; 366 } else { 367 return 0; 368 } 369 370 regcache_drop_region(priv->regmap, 0x0, 0xff); 371 usleep_range(650000, 700000); 372 373 return 0; 374 } 375 376 static int bno055_init(struct bno055_priv *priv, const u8 *caldata, int len) 377 { 378 int ret; 379 380 ret = bno055_operation_mode_do_set(priv, BNO055_OPR_MODE_CONFIG); 381 if (ret) 382 return ret; 383 384 ret = regmap_write(priv->regmap, BNO055_POWER_MODE_REG, 385 BNO055_POWER_MODE_NORMAL); 386 if (ret) 387 return ret; 388 389 ret = regmap_write(priv->regmap, BNO055_SYS_TRIGGER_REG, 390 priv->clk ? BNO055_SYS_TRIGGER_CLK_SEL : 0); 391 if (ret) 392 return ret; 393 394 /* use standard SI units */ 395 ret = regmap_write(priv->regmap, BNO055_UNIT_SEL_REG, 396 BNO055_UNIT_SEL_ANDROID | BNO055_UNIT_SEL_GYR_RPS); 397 if (ret) 398 return ret; 399 400 if (caldata) { 401 ret = bno055_calibration_load(priv, caldata, len); 402 if (ret) 403 dev_warn(priv->dev, "failed to load calibration data with error %d\n", 404 ret); 405 } 406 407 return 0; 408 } 409 410 static ssize_t bno055_operation_mode_set(struct bno055_priv *priv, 411 int operation_mode) 412 { 413 u8 caldata[BNO055_CALDATA_LEN]; 414 int ret; 415 416 mutex_lock(&priv->lock); 417 418 ret = bno055_operation_mode_do_set(priv, BNO055_OPR_MODE_CONFIG); 419 if (ret) 420 goto exit_unlock; 421 422 if (operation_mode == BNO055_OPR_MODE_FUSION || 423 operation_mode == BNO055_OPR_MODE_FUSION_FMC_OFF) { 424 /* for entering fusion mode, reset the chip to clear the algo state */ 425 ret = regmap_bulk_read(priv->regmap, BNO055_CALDATA_START, caldata, 426 BNO055_CALDATA_LEN); 427 if (ret) 428 goto exit_unlock; 429 430 ret = bno055_system_reset(priv); 431 if (ret) 432 goto exit_unlock; 433 434 ret = bno055_init(priv, caldata, BNO055_CALDATA_LEN); 435 if (ret) 436 goto exit_unlock; 437 } 438 439 ret = bno055_operation_mode_do_set(priv, operation_mode); 440 if (ret) 441 goto exit_unlock; 442 443 priv->operation_mode = operation_mode; 444 445 exit_unlock: 446 mutex_unlock(&priv->lock); 447 return ret; 448 } 449 450 static void bno055_uninit(void *arg) 451 { 452 struct bno055_priv *priv = arg; 453 454 /* stop the IMU */ 455 bno055_operation_mode_do_set(priv, BNO055_OPR_MODE_CONFIG); 456 } 457 458 #define BNO055_CHANNEL(_type, _axis, _index, _address, _sep, _sh, _avail) { \ 459 .address = _address, \ 460 .type = _type, \ 461 .modified = 1, \ 462 .channel2 = IIO_MOD_##_axis, \ 463 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | (_sep), \ 464 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | (_sh), \ 465 .info_mask_shared_by_type_available = _avail, \ 466 .scan_index = _index, \ 467 .scan_type = { \ 468 .sign = 's', \ 469 .realbits = 16, \ 470 .storagebits = 16, \ 471 .endianness = IIO_LE, \ 472 .repeat = IIO_MOD_##_axis == IIO_MOD_QUATERNION ? 4 : 0, \ 473 }, \ 474 } 475 476 /* scan indexes follow DATA register order */ 477 enum bno055_scan_axis { 478 BNO055_SCAN_ACCEL_X, 479 BNO055_SCAN_ACCEL_Y, 480 BNO055_SCAN_ACCEL_Z, 481 BNO055_SCAN_MAGN_X, 482 BNO055_SCAN_MAGN_Y, 483 BNO055_SCAN_MAGN_Z, 484 BNO055_SCAN_GYRO_X, 485 BNO055_SCAN_GYRO_Y, 486 BNO055_SCAN_GYRO_Z, 487 BNO055_SCAN_YAW, 488 BNO055_SCAN_ROLL, 489 BNO055_SCAN_PITCH, 490 BNO055_SCAN_QUATERNION, 491 BNO055_SCAN_LIA_X, 492 BNO055_SCAN_LIA_Y, 493 BNO055_SCAN_LIA_Z, 494 BNO055_SCAN_GRAVITY_X, 495 BNO055_SCAN_GRAVITY_Y, 496 BNO055_SCAN_GRAVITY_Z, 497 BNO055_SCAN_TIMESTAMP, 498 _BNO055_SCAN_MAX 499 }; 500 501 static const struct iio_chan_spec bno055_channels[] = { 502 /* accelerometer */ 503 BNO055_CHANNEL(IIO_ACCEL, X, BNO055_SCAN_ACCEL_X, 504 BNO055_ACC_DATA_X_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET), 505 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), 506 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY)), 507 BNO055_CHANNEL(IIO_ACCEL, Y, BNO055_SCAN_ACCEL_Y, 508 BNO055_ACC_DATA_Y_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET), 509 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), 510 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY)), 511 BNO055_CHANNEL(IIO_ACCEL, Z, BNO055_SCAN_ACCEL_Z, 512 BNO055_ACC_DATA_Z_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET), 513 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), 514 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY)), 515 /* gyroscope */ 516 BNO055_CHANNEL(IIO_ANGL_VEL, X, BNO055_SCAN_GYRO_X, 517 BNO055_GYR_DATA_X_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET), 518 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), 519 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | 520 BIT(IIO_CHAN_INFO_SCALE)), 521 BNO055_CHANNEL(IIO_ANGL_VEL, Y, BNO055_SCAN_GYRO_Y, 522 BNO055_GYR_DATA_Y_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET), 523 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), 524 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | 525 BIT(IIO_CHAN_INFO_SCALE)), 526 BNO055_CHANNEL(IIO_ANGL_VEL, Z, BNO055_SCAN_GYRO_Z, 527 BNO055_GYR_DATA_Z_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET), 528 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), 529 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | 530 BIT(IIO_CHAN_INFO_SCALE)), 531 /* magnetometer */ 532 BNO055_CHANNEL(IIO_MAGN, X, BNO055_SCAN_MAGN_X, 533 BNO055_MAG_DATA_X_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET), 534 BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT(IIO_CHAN_INFO_SAMP_FREQ)), 535 BNO055_CHANNEL(IIO_MAGN, Y, BNO055_SCAN_MAGN_Y, 536 BNO055_MAG_DATA_Y_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET), 537 BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT(IIO_CHAN_INFO_SAMP_FREQ)), 538 BNO055_CHANNEL(IIO_MAGN, Z, BNO055_SCAN_MAGN_Z, 539 BNO055_MAG_DATA_Z_LSB_REG, BIT(IIO_CHAN_INFO_OFFSET), 540 BIT(IIO_CHAN_INFO_SAMP_FREQ), BIT(IIO_CHAN_INFO_SAMP_FREQ)), 541 /* euler angle */ 542 BNO055_CHANNEL(IIO_ROT, YAW, BNO055_SCAN_YAW, 543 BNO055_EUL_DATA_X_LSB_REG, 0, 0, 0), 544 BNO055_CHANNEL(IIO_ROT, ROLL, BNO055_SCAN_ROLL, 545 BNO055_EUL_DATA_Y_LSB_REG, 0, 0, 0), 546 BNO055_CHANNEL(IIO_ROT, PITCH, BNO055_SCAN_PITCH, 547 BNO055_EUL_DATA_Z_LSB_REG, 0, 0, 0), 548 /* quaternion */ 549 BNO055_CHANNEL(IIO_ROT, QUATERNION, BNO055_SCAN_QUATERNION, 550 BNO055_QUAT_DATA_W_LSB_REG, 0, 0, 0), 551 552 /* linear acceleration */ 553 BNO055_CHANNEL(IIO_ACCEL, LINEAR_X, BNO055_SCAN_LIA_X, 554 BNO055_LIA_DATA_X_LSB_REG, 0, 0, 0), 555 BNO055_CHANNEL(IIO_ACCEL, LINEAR_Y, BNO055_SCAN_LIA_Y, 556 BNO055_LIA_DATA_Y_LSB_REG, 0, 0, 0), 557 BNO055_CHANNEL(IIO_ACCEL, LINEAR_Z, BNO055_SCAN_LIA_Z, 558 BNO055_LIA_DATA_Z_LSB_REG, 0, 0, 0), 559 560 /* gravity vector */ 561 BNO055_CHANNEL(IIO_GRAVITY, X, BNO055_SCAN_GRAVITY_X, 562 BNO055_GRAVITY_DATA_X_LSB_REG, 0, 0, 0), 563 BNO055_CHANNEL(IIO_GRAVITY, Y, BNO055_SCAN_GRAVITY_Y, 564 BNO055_GRAVITY_DATA_Y_LSB_REG, 0, 0, 0), 565 BNO055_CHANNEL(IIO_GRAVITY, Z, BNO055_SCAN_GRAVITY_Z, 566 BNO055_GRAVITY_DATA_Z_LSB_REG, 0, 0, 0), 567 568 { 569 .type = IIO_TEMP, 570 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), 571 .scan_index = -1, 572 }, 573 IIO_CHAN_SOFT_TIMESTAMP(BNO055_SCAN_TIMESTAMP), 574 }; 575 576 static int bno055_get_regmask(struct bno055_priv *priv, int *val, int *val2, 577 int reg, int mask, 578 const struct bno055_sysfs_attr *attr) 579 { 580 const int shift = __ffs(mask); 581 int hwval, idx; 582 int ret; 583 int i; 584 585 ret = regmap_read(priv->regmap, reg, &hwval); 586 if (ret) 587 return ret; 588 589 idx = (hwval & mask) >> shift; 590 if (attr->hw_xlate) 591 for (i = 0; i < attr->hw_xlate_len; i++) 592 if (attr->hw_xlate[i] == idx) { 593 idx = i; 594 break; 595 } 596 if (attr->type == IIO_VAL_INT) { 597 *val = attr->vals[idx]; 598 } else { /* IIO_VAL_INT_PLUS_MICRO or IIO_VAL_FRACTIONAL */ 599 *val = attr->vals[idx * 2]; 600 *val2 = attr->vals[idx * 2 + 1]; 601 } 602 603 return attr->type; 604 } 605 606 static int bno055_set_regmask(struct bno055_priv *priv, int val, int val2, 607 int reg, int mask, 608 const struct bno055_sysfs_attr *attr) 609 { 610 const int shift = __ffs(mask); 611 int best_delta; 612 int req_val; 613 int tbl_val; 614 bool first; 615 int delta; 616 int hwval; 617 int ret; 618 int len; 619 int i; 620 621 /* 622 * The closest value the HW supports is only one in fusion mode, 623 * and it is autoselected, so don't do anything, just return OK, 624 * as the closest possible value has been (virtually) selected 625 */ 626 if (priv->operation_mode != BNO055_OPR_MODE_AMG) 627 return 0; 628 629 len = attr->len; 630 631 /* 632 * We always get a request in INT_PLUS_MICRO, but we 633 * take care of the micro part only when we really have 634 * non-integer tables. This prevents 32-bit overflow with 635 * larger integers contained in integer tables. 636 */ 637 req_val = val; 638 if (attr->type != IIO_VAL_INT) { 639 len /= 2; 640 req_val = min(val, 2147) * 1000000 + val2; 641 } 642 643 first = true; 644 for (i = 0; i < len; i++) { 645 switch (attr->type) { 646 case IIO_VAL_INT: 647 tbl_val = attr->vals[i]; 648 break; 649 case IIO_VAL_INT_PLUS_MICRO: 650 WARN_ON(attr->vals[i * 2] > 2147); 651 tbl_val = attr->vals[i * 2] * 1000000 + 652 attr->vals[i * 2 + 1]; 653 break; 654 case IIO_VAL_FRACTIONAL: 655 WARN_ON(attr->vals[i * 2] > 4294); 656 tbl_val = attr->vals[i * 2] * 1000000 / 657 attr->vals[i * 2 + 1]; 658 break; 659 default: 660 return -EINVAL; 661 } 662 delta = abs(tbl_val - req_val); 663 if (first || delta < best_delta) { 664 best_delta = delta; 665 hwval = i; 666 first = false; 667 } 668 } 669 670 if (attr->hw_xlate) 671 hwval = attr->hw_xlate[hwval]; 672 673 ret = bno055_operation_mode_do_set(priv, BNO055_OPR_MODE_CONFIG); 674 if (ret) 675 return ret; 676 677 ret = regmap_update_bits(priv->regmap, reg, mask, hwval << shift); 678 if (ret) 679 return ret; 680 681 return bno055_operation_mode_do_set(priv, BNO055_OPR_MODE_AMG); 682 } 683 684 static int bno055_read_simple_chan(struct iio_dev *indio_dev, 685 struct iio_chan_spec const *chan, 686 int *val, int *val2, long mask) 687 { 688 struct bno055_priv *priv = iio_priv(indio_dev); 689 __le16 raw_val; 690 int ret; 691 692 switch (mask) { 693 case IIO_CHAN_INFO_RAW: 694 ret = regmap_bulk_read(priv->regmap, chan->address, 695 &raw_val, sizeof(raw_val)); 696 if (ret < 0) 697 return ret; 698 *val = sign_extend32(le16_to_cpu(raw_val), 15); 699 return IIO_VAL_INT; 700 case IIO_CHAN_INFO_OFFSET: 701 if (priv->operation_mode != BNO055_OPR_MODE_AMG) { 702 *val = 0; 703 } else { 704 ret = regmap_bulk_read(priv->regmap, 705 chan->address + 706 BNO055_REG_OFFSET_ADDR, 707 &raw_val, sizeof(raw_val)); 708 if (ret < 0) 709 return ret; 710 /* 711 * IMU reports sensor offsets; IIO wants correction 712 * offsets, thus we need the 'minus' here. 713 */ 714 *val = -sign_extend32(le16_to_cpu(raw_val), 15); 715 } 716 return IIO_VAL_INT; 717 case IIO_CHAN_INFO_SCALE: 718 *val = 1; 719 switch (chan->type) { 720 case IIO_GRAVITY: 721 /* Table 3-35: 1 m/s^2 = 100 LSB */ 722 case IIO_ACCEL: 723 /* Table 3-17: 1 m/s^2 = 100 LSB */ 724 *val2 = 100; 725 break; 726 case IIO_MAGN: 727 /* 728 * Table 3-19: 1 uT = 16 LSB. But we need 729 * Gauss: 1G = 0.1 uT. 730 */ 731 *val2 = 160; 732 break; 733 case IIO_ANGL_VEL: 734 /* 735 * Table 3-22: 1 Rps = 900 LSB 736 * .. but this is not exactly true. See comment at the 737 * beginning of this file. 738 */ 739 if (priv->operation_mode != BNO055_OPR_MODE_AMG) { 740 *val = bno055_gyr_scale.fusion_vals[0]; 741 *val2 = bno055_gyr_scale.fusion_vals[1]; 742 return IIO_VAL_FRACTIONAL; 743 } 744 745 return bno055_get_regmask(priv, val, val2, 746 BNO055_GYR_CONFIG_REG, 747 BNO055_GYR_CONFIG_RANGE_MASK, 748 &bno055_gyr_scale); 749 break; 750 case IIO_ROT: 751 /* Table 3-28: 1 degree = 16 LSB */ 752 *val2 = 16; 753 break; 754 default: 755 return -EINVAL; 756 } 757 return IIO_VAL_FRACTIONAL; 758 759 case IIO_CHAN_INFO_SAMP_FREQ: 760 if (chan->type != IIO_MAGN) 761 return -EINVAL; 762 763 return bno055_get_regmask(priv, val, val2, 764 BNO055_MAG_CONFIG_REG, 765 BNO055_MAG_CONFIG_ODR_MASK, 766 &bno055_mag_odr); 767 768 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 769 switch (chan->type) { 770 case IIO_ANGL_VEL: 771 return bno055_get_regmask(priv, val, val2, 772 BNO055_GYR_CONFIG_REG, 773 BNO055_GYR_CONFIG_LPF_MASK, 774 &bno055_gyr_lpf); 775 case IIO_ACCEL: 776 return bno055_get_regmask(priv, val, val2, 777 BNO055_ACC_CONFIG_REG, 778 BNO055_ACC_CONFIG_LPF_MASK, 779 &bno055_acc_lpf); 780 default: 781 return -EINVAL; 782 } 783 784 default: 785 return -EINVAL; 786 } 787 } 788 789 static int bno055_sysfs_attr_avail(struct bno055_priv *priv, 790 const struct bno055_sysfs_attr *attr, 791 const int **vals, int *length) 792 { 793 if (priv->operation_mode != BNO055_OPR_MODE_AMG) { 794 /* locked when fusion enabled */ 795 *vals = attr->fusion_vals; 796 if (attr->type == IIO_VAL_INT) 797 *length = 1; 798 else 799 *length = 2; /* IIO_VAL_INT_PLUS_MICRO or IIO_VAL_FRACTIONAL*/ 800 } else { 801 *vals = attr->vals; 802 *length = attr->len; 803 } 804 805 return attr->type; 806 } 807 808 static int bno055_read_avail(struct iio_dev *indio_dev, 809 struct iio_chan_spec const *chan, 810 const int **vals, int *type, int *length, 811 long mask) 812 { 813 struct bno055_priv *priv = iio_priv(indio_dev); 814 815 switch (mask) { 816 case IIO_CHAN_INFO_SCALE: 817 switch (chan->type) { 818 case IIO_ANGL_VEL: 819 *type = bno055_sysfs_attr_avail(priv, &bno055_gyr_scale, 820 vals, length); 821 return IIO_AVAIL_LIST; 822 default: 823 return -EINVAL; 824 } 825 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 826 switch (chan->type) { 827 case IIO_ANGL_VEL: 828 *type = bno055_sysfs_attr_avail(priv, &bno055_gyr_lpf, 829 vals, length); 830 return IIO_AVAIL_LIST; 831 case IIO_ACCEL: 832 *type = bno055_sysfs_attr_avail(priv, &bno055_acc_lpf, 833 vals, length); 834 return IIO_AVAIL_LIST; 835 default: 836 return -EINVAL; 837 } 838 839 break; 840 case IIO_CHAN_INFO_SAMP_FREQ: 841 switch (chan->type) { 842 case IIO_MAGN: 843 *type = bno055_sysfs_attr_avail(priv, &bno055_mag_odr, 844 vals, length); 845 return IIO_AVAIL_LIST; 846 default: 847 return -EINVAL; 848 } 849 default: 850 return -EINVAL; 851 } 852 } 853 854 static int bno055_read_temp_chan(struct iio_dev *indio_dev, int *val) 855 { 856 struct bno055_priv *priv = iio_priv(indio_dev); 857 unsigned int raw_val; 858 int ret; 859 860 ret = regmap_read(priv->regmap, BNO055_TEMP_REG, &raw_val); 861 if (ret < 0) 862 return ret; 863 864 /* 865 * Tables 3-36 and 3-37: one byte of priv, signed, 1 LSB = 1C. 866 * ABI wants milliC. 867 */ 868 *val = raw_val * 1000; 869 870 return IIO_VAL_INT; 871 } 872 873 static int bno055_read_quaternion(struct iio_dev *indio_dev, 874 struct iio_chan_spec const *chan, 875 int size, int *vals, int *val_len, 876 long mask) 877 { 878 struct bno055_priv *priv = iio_priv(indio_dev); 879 __le16 raw_vals[4]; 880 int i, ret; 881 882 switch (mask) { 883 case IIO_CHAN_INFO_RAW: 884 if (size < 4) 885 return -EINVAL; 886 ret = regmap_bulk_read(priv->regmap, 887 BNO055_QUAT_DATA_W_LSB_REG, 888 raw_vals, sizeof(raw_vals)); 889 if (ret < 0) 890 return ret; 891 for (i = 0; i < 4; i++) 892 vals[i] = sign_extend32(le16_to_cpu(raw_vals[i]), 15); 893 *val_len = 4; 894 return IIO_VAL_INT_MULTIPLE; 895 case IIO_CHAN_INFO_SCALE: 896 /* Table 3-31: 1 quaternion = 2^14 LSB */ 897 if (size < 2) 898 return -EINVAL; 899 vals[0] = 1; 900 vals[1] = 14; 901 return IIO_VAL_FRACTIONAL_LOG2; 902 default: 903 return -EINVAL; 904 } 905 } 906 907 static bool bno055_is_chan_readable(struct iio_dev *indio_dev, 908 struct iio_chan_spec const *chan) 909 { 910 struct bno055_priv *priv = iio_priv(indio_dev); 911 912 if (priv->operation_mode != BNO055_OPR_MODE_AMG) 913 return true; 914 915 switch (chan->type) { 916 case IIO_GRAVITY: 917 case IIO_ROT: 918 return false; 919 case IIO_ACCEL: 920 if (chan->channel2 == IIO_MOD_LINEAR_X || 921 chan->channel2 == IIO_MOD_LINEAR_Y || 922 chan->channel2 == IIO_MOD_LINEAR_Z) 923 return false; 924 return true; 925 default: 926 return true; 927 } 928 } 929 930 static int _bno055_read_raw_multi(struct iio_dev *indio_dev, 931 struct iio_chan_spec const *chan, 932 int size, int *vals, int *val_len, 933 long mask) 934 { 935 if (!bno055_is_chan_readable(indio_dev, chan)) 936 return -EBUSY; 937 938 switch (chan->type) { 939 case IIO_MAGN: 940 case IIO_ACCEL: 941 case IIO_ANGL_VEL: 942 case IIO_GRAVITY: 943 if (size < 2) 944 return -EINVAL; 945 *val_len = 2; 946 return bno055_read_simple_chan(indio_dev, chan, 947 &vals[0], &vals[1], 948 mask); 949 case IIO_TEMP: 950 *val_len = 1; 951 return bno055_read_temp_chan(indio_dev, &vals[0]); 952 case IIO_ROT: 953 /* 954 * Rotation is exposed as either a quaternion or three 955 * Euler angles. 956 */ 957 if (chan->channel2 == IIO_MOD_QUATERNION) 958 return bno055_read_quaternion(indio_dev, chan, 959 size, vals, 960 val_len, mask); 961 if (size < 2) 962 return -EINVAL; 963 *val_len = 2; 964 return bno055_read_simple_chan(indio_dev, chan, 965 &vals[0], &vals[1], 966 mask); 967 default: 968 return -EINVAL; 969 } 970 } 971 972 static int bno055_read_raw_multi(struct iio_dev *indio_dev, 973 struct iio_chan_spec const *chan, 974 int size, int *vals, int *val_len, 975 long mask) 976 { 977 struct bno055_priv *priv = iio_priv(indio_dev); 978 int ret; 979 980 mutex_lock(&priv->lock); 981 ret = _bno055_read_raw_multi(indio_dev, chan, size, 982 vals, val_len, mask); 983 mutex_unlock(&priv->lock); 984 return ret; 985 } 986 987 static int _bno055_write_raw(struct iio_dev *iio_dev, 988 struct iio_chan_spec const *chan, 989 int val, int val2, long mask) 990 { 991 struct bno055_priv *priv = iio_priv(iio_dev); 992 993 switch (chan->type) { 994 case IIO_MAGN: 995 switch (mask) { 996 case IIO_CHAN_INFO_SAMP_FREQ: 997 return bno055_set_regmask(priv, val, val2, 998 BNO055_MAG_CONFIG_REG, 999 BNO055_MAG_CONFIG_ODR_MASK, 1000 &bno055_mag_odr); 1001 default: 1002 return -EINVAL; 1003 } 1004 case IIO_ACCEL: 1005 switch (mask) { 1006 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 1007 return bno055_set_regmask(priv, val, val2, 1008 BNO055_ACC_CONFIG_REG, 1009 BNO055_ACC_CONFIG_LPF_MASK, 1010 &bno055_acc_lpf); 1011 1012 default: 1013 return -EINVAL; 1014 } 1015 case IIO_ANGL_VEL: 1016 switch (mask) { 1017 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 1018 return bno055_set_regmask(priv, val, val2, 1019 BNO055_GYR_CONFIG_REG, 1020 BNO055_GYR_CONFIG_LPF_MASK, 1021 &bno055_gyr_lpf); 1022 case IIO_CHAN_INFO_SCALE: 1023 return bno055_set_regmask(priv, val, val2, 1024 BNO055_GYR_CONFIG_REG, 1025 BNO055_GYR_CONFIG_RANGE_MASK, 1026 &bno055_gyr_scale); 1027 default: 1028 return -EINVAL; 1029 } 1030 default: 1031 return -EINVAL; 1032 } 1033 } 1034 1035 static int bno055_write_raw(struct iio_dev *iio_dev, 1036 struct iio_chan_spec const *chan, 1037 int val, int val2, long mask) 1038 { 1039 struct bno055_priv *priv = iio_priv(iio_dev); 1040 int ret; 1041 1042 mutex_lock(&priv->lock); 1043 ret = _bno055_write_raw(iio_dev, chan, val, val2, mask); 1044 mutex_unlock(&priv->lock); 1045 1046 return ret; 1047 } 1048 1049 static ssize_t in_accel_range_raw_available_show(struct device *dev, 1050 struct device_attribute *attr, 1051 char *buf) 1052 { 1053 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev)); 1054 int len = 0; 1055 int i; 1056 1057 if (priv->operation_mode != BNO055_OPR_MODE_AMG) 1058 return sysfs_emit(buf, "%d\n", bno055_acc_range.fusion_vals[0]); 1059 1060 for (i = 0; i < bno055_acc_range.len; i++) 1061 len += sysfs_emit_at(buf, len, "%d ", bno055_acc_range.vals[i]); 1062 buf[len - 1] = '\n'; 1063 1064 return len; 1065 } 1066 1067 static ssize_t fusion_enable_show(struct device *dev, 1068 struct device_attribute *attr, 1069 char *buf) 1070 { 1071 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev)); 1072 1073 return sysfs_emit(buf, "%d\n", 1074 priv->operation_mode != BNO055_OPR_MODE_AMG); 1075 } 1076 1077 static ssize_t fusion_enable_store(struct device *dev, 1078 struct device_attribute *attr, 1079 const char *buf, size_t len) 1080 { 1081 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 1082 struct bno055_priv *priv = iio_priv(indio_dev); 1083 bool en; 1084 int ret; 1085 1086 if (indio_dev->active_scan_mask && 1087 !bitmap_empty(indio_dev->active_scan_mask, _BNO055_SCAN_MAX)) 1088 return -EBUSY; 1089 1090 ret = kstrtobool(buf, &en); 1091 if (ret) 1092 return -EINVAL; 1093 1094 if (!en) 1095 return bno055_operation_mode_set(priv, BNO055_OPR_MODE_AMG) ?: len; 1096 1097 /* 1098 * Coming from AMG means the FMC was off, just switch to fusion but 1099 * don't change anything that doesn't belong to us (i.e let FMC stay off). 1100 * Coming from any other fusion mode means we don't need to do anything. 1101 */ 1102 if (priv->operation_mode == BNO055_OPR_MODE_AMG) 1103 return bno055_operation_mode_set(priv, BNO055_OPR_MODE_FUSION_FMC_OFF) ?: len; 1104 1105 return len; 1106 } 1107 1108 static ssize_t in_magn_calibration_fast_enable_show(struct device *dev, 1109 struct device_attribute *attr, 1110 char *buf) 1111 { 1112 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev)); 1113 1114 return sysfs_emit(buf, "%d\n", 1115 priv->operation_mode == BNO055_OPR_MODE_FUSION); 1116 } 1117 1118 static ssize_t in_magn_calibration_fast_enable_store(struct device *dev, 1119 struct device_attribute *attr, 1120 const char *buf, size_t len) 1121 { 1122 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 1123 struct bno055_priv *priv = iio_priv(indio_dev); 1124 int ret; 1125 1126 if (indio_dev->active_scan_mask && 1127 !bitmap_empty(indio_dev->active_scan_mask, _BNO055_SCAN_MAX)) 1128 return -EBUSY; 1129 1130 if (sysfs_streq(buf, "0")) { 1131 if (priv->operation_mode == BNO055_OPR_MODE_FUSION) { 1132 ret = bno055_operation_mode_set(priv, BNO055_OPR_MODE_FUSION_FMC_OFF); 1133 if (ret) 1134 return ret; 1135 } 1136 } else { 1137 if (priv->operation_mode == BNO055_OPR_MODE_AMG) 1138 return -EINVAL; 1139 1140 if (priv->operation_mode != BNO055_OPR_MODE_FUSION) { 1141 ret = bno055_operation_mode_set(priv, BNO055_OPR_MODE_FUSION); 1142 if (ret) 1143 return ret; 1144 } 1145 } 1146 1147 return len; 1148 } 1149 1150 static ssize_t in_accel_range_raw_show(struct device *dev, 1151 struct device_attribute *attr, 1152 char *buf) 1153 { 1154 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev)); 1155 int val; 1156 int ret; 1157 1158 ret = bno055_get_regmask(priv, &val, NULL, 1159 BNO055_ACC_CONFIG_REG, 1160 BNO055_ACC_CONFIG_RANGE_MASK, 1161 &bno055_acc_range); 1162 if (ret < 0) 1163 return ret; 1164 1165 return sysfs_emit(buf, "%d\n", val); 1166 } 1167 1168 static ssize_t in_accel_range_raw_store(struct device *dev, 1169 struct device_attribute *attr, 1170 const char *buf, size_t len) 1171 { 1172 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev)); 1173 unsigned long val; 1174 int ret; 1175 1176 ret = kstrtoul(buf, 10, &val); 1177 if (ret) 1178 return ret; 1179 1180 mutex_lock(&priv->lock); 1181 ret = bno055_set_regmask(priv, val, 0, 1182 BNO055_ACC_CONFIG_REG, 1183 BNO055_ACC_CONFIG_RANGE_MASK, 1184 &bno055_acc_range); 1185 mutex_unlock(&priv->lock); 1186 1187 return ret ?: len; 1188 } 1189 1190 static ssize_t bno055_get_calib_status(struct device *dev, char *buf, int which) 1191 { 1192 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev)); 1193 int calib; 1194 int ret; 1195 int val; 1196 1197 if (priv->operation_mode == BNO055_OPR_MODE_AMG || 1198 (priv->operation_mode == BNO055_OPR_MODE_FUSION_FMC_OFF && 1199 which == BNO055_CALIB_STAT_MAGN_SHIFT)) { 1200 calib = 0; 1201 } else { 1202 mutex_lock(&priv->lock); 1203 ret = regmap_read(priv->regmap, BNO055_CALIB_STAT_REG, &val); 1204 mutex_unlock(&priv->lock); 1205 1206 if (ret) 1207 return -EIO; 1208 1209 calib = ((val >> which) & GENMASK(1, 0)) + 1; 1210 } 1211 1212 return sysfs_emit(buf, "%d\n", calib); 1213 } 1214 1215 static ssize_t serialnumber_show(struct device *dev, 1216 struct device_attribute *attr, 1217 char *buf) 1218 { 1219 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(dev)); 1220 1221 return sysfs_emit(buf, "%*ph\n", BNO055_UID_LEN, priv->uid); 1222 } 1223 1224 static ssize_t calibration_data_read(struct file *filp, struct kobject *kobj, 1225 const struct bin_attribute *bin_attr, char *buf, 1226 loff_t pos, size_t count) 1227 { 1228 struct bno055_priv *priv = iio_priv(dev_to_iio_dev(kobj_to_dev(kobj))); 1229 u8 data[BNO055_CALDATA_LEN]; 1230 int ret; 1231 1232 /* 1233 * Calibration data is volatile; reading it in chunks will possibly 1234 * results in inconsistent data. We require the user to read the whole 1235 * blob in a single chunk 1236 */ 1237 if (count < BNO055_CALDATA_LEN || pos) 1238 return -EINVAL; 1239 1240 mutex_lock(&priv->lock); 1241 ret = bno055_operation_mode_do_set(priv, BNO055_OPR_MODE_CONFIG); 1242 if (ret) 1243 goto exit_unlock; 1244 1245 ret = regmap_bulk_read(priv->regmap, BNO055_CALDATA_START, data, 1246 BNO055_CALDATA_LEN); 1247 if (ret) 1248 goto exit_unlock; 1249 1250 ret = bno055_operation_mode_do_set(priv, priv->operation_mode); 1251 if (ret) 1252 goto exit_unlock; 1253 1254 memcpy(buf, data, BNO055_CALDATA_LEN); 1255 1256 ret = BNO055_CALDATA_LEN; 1257 exit_unlock: 1258 mutex_unlock(&priv->lock); 1259 return ret; 1260 } 1261 1262 static ssize_t sys_calibration_auto_status_show(struct device *dev, 1263 struct device_attribute *a, 1264 char *buf) 1265 { 1266 return bno055_get_calib_status(dev, buf, BNO055_CALIB_STAT_SYS_SHIFT); 1267 } 1268 1269 static ssize_t in_accel_calibration_auto_status_show(struct device *dev, 1270 struct device_attribute *a, 1271 char *buf) 1272 { 1273 return bno055_get_calib_status(dev, buf, BNO055_CALIB_STAT_ACCEL_SHIFT); 1274 } 1275 1276 static ssize_t in_gyro_calibration_auto_status_show(struct device *dev, 1277 struct device_attribute *a, 1278 char *buf) 1279 { 1280 return bno055_get_calib_status(dev, buf, BNO055_CALIB_STAT_GYRO_SHIFT); 1281 } 1282 1283 static ssize_t in_magn_calibration_auto_status_show(struct device *dev, 1284 struct device_attribute *a, 1285 char *buf) 1286 { 1287 return bno055_get_calib_status(dev, buf, BNO055_CALIB_STAT_MAGN_SHIFT); 1288 } 1289 1290 static int bno055_debugfs_reg_access(struct iio_dev *iio_dev, unsigned int reg, 1291 unsigned int writeval, unsigned int *readval) 1292 { 1293 struct bno055_priv *priv = iio_priv(iio_dev); 1294 1295 if (readval) 1296 return regmap_read(priv->regmap, reg, readval); 1297 else 1298 return regmap_write(priv->regmap, reg, writeval); 1299 } 1300 1301 static ssize_t bno055_show_fw_version(struct file *file, char __user *userbuf, 1302 size_t count, loff_t *ppos) 1303 { 1304 struct bno055_priv *priv = file->private_data; 1305 int rev, ver; 1306 char *buf; 1307 int ret; 1308 1309 ret = regmap_read(priv->regmap, BNO055_SW_REV_LSB_REG, &rev); 1310 if (ret) 1311 return ret; 1312 1313 ret = regmap_read(priv->regmap, BNO055_SW_REV_MSB_REG, &ver); 1314 if (ret) 1315 return ret; 1316 1317 buf = kasprintf(GFP_KERNEL, "ver: 0x%x, rev: 0x%x\n", ver, rev); 1318 if (!buf) 1319 return -ENOMEM; 1320 1321 ret = simple_read_from_buffer(userbuf, count, ppos, buf, strlen(buf)); 1322 kfree(buf); 1323 1324 return ret; 1325 } 1326 1327 static const struct file_operations bno055_fw_version_ops = { 1328 .open = simple_open, 1329 .read = bno055_show_fw_version, 1330 .llseek = default_llseek, 1331 .owner = THIS_MODULE, 1332 }; 1333 1334 static void bno055_debugfs_remove(void *_priv) 1335 { 1336 struct bno055_priv *priv = _priv; 1337 1338 debugfs_remove(priv->debugfs); 1339 priv->debugfs = NULL; 1340 } 1341 1342 static void bno055_debugfs_init(struct iio_dev *iio_dev) 1343 { 1344 struct bno055_priv *priv = iio_priv(iio_dev); 1345 1346 priv->debugfs = debugfs_create_file("firmware_version", 0400, 1347 iio_get_debugfs_dentry(iio_dev), 1348 priv, &bno055_fw_version_ops); 1349 if (!IS_ERR(priv->debugfs)) 1350 devm_add_action_or_reset(priv->dev, bno055_debugfs_remove, 1351 priv); 1352 if (IS_ERR_OR_NULL(priv->debugfs)) 1353 dev_warn(priv->dev, "failed to setup debugfs"); 1354 } 1355 1356 static IIO_DEVICE_ATTR_RW(fusion_enable, 0); 1357 static IIO_DEVICE_ATTR_RW(in_magn_calibration_fast_enable, 0); 1358 static IIO_DEVICE_ATTR_RW(in_accel_range_raw, 0); 1359 1360 static IIO_DEVICE_ATTR_RO(in_accel_range_raw_available, 0); 1361 static IIO_DEVICE_ATTR_RO(sys_calibration_auto_status, 0); 1362 static IIO_DEVICE_ATTR_RO(in_accel_calibration_auto_status, 0); 1363 static IIO_DEVICE_ATTR_RO(in_gyro_calibration_auto_status, 0); 1364 static IIO_DEVICE_ATTR_RO(in_magn_calibration_auto_status, 0); 1365 static IIO_DEVICE_ATTR_RO(serialnumber, 0); 1366 1367 static struct attribute *bno055_attrs[] = { 1368 &iio_dev_attr_in_accel_range_raw_available.dev_attr.attr, 1369 &iio_dev_attr_in_accel_range_raw.dev_attr.attr, 1370 &iio_dev_attr_fusion_enable.dev_attr.attr, 1371 &iio_dev_attr_in_magn_calibration_fast_enable.dev_attr.attr, 1372 &iio_dev_attr_sys_calibration_auto_status.dev_attr.attr, 1373 &iio_dev_attr_in_accel_calibration_auto_status.dev_attr.attr, 1374 &iio_dev_attr_in_gyro_calibration_auto_status.dev_attr.attr, 1375 &iio_dev_attr_in_magn_calibration_auto_status.dev_attr.attr, 1376 &iio_dev_attr_serialnumber.dev_attr.attr, 1377 NULL 1378 }; 1379 1380 static const BIN_ATTR_RO(calibration_data, BNO055_CALDATA_LEN); 1381 1382 static const struct bin_attribute *const bno055_bin_attrs[] = { 1383 &bin_attr_calibration_data, 1384 NULL 1385 }; 1386 1387 static const struct attribute_group bno055_attrs_group = { 1388 .attrs = bno055_attrs, 1389 .bin_attrs = bno055_bin_attrs, 1390 }; 1391 1392 static const struct iio_info bno055_info = { 1393 .read_raw_multi = bno055_read_raw_multi, 1394 .read_avail = bno055_read_avail, 1395 .write_raw = bno055_write_raw, 1396 .attrs = &bno055_attrs_group, 1397 .debugfs_reg_access = bno055_debugfs_reg_access, 1398 }; 1399 1400 /* 1401 * Reads len samples from the HW, stores them in buf starting from buf_idx, 1402 * and applies mask to cull (skip) unneeded samples. 1403 * Updates buf_idx incrementing with the number of stored samples. 1404 * Samples from HW are transferred into buf, then in-place copy on buf is 1405 * performed in order to cull samples that need to be skipped. 1406 * This avoids copies of the first samples until we hit the 1st sample to skip, 1407 * and also avoids having an extra bounce buffer. 1408 * buf must be able to contain len elements in spite of how many samples we are 1409 * going to cull. 1410 */ 1411 static int bno055_scan_xfer(struct bno055_priv *priv, 1412 int start_ch, int len, unsigned long mask, 1413 __le16 *buf, int *buf_idx) 1414 { 1415 const int base = BNO055_ACC_DATA_X_LSB_REG; 1416 bool quat_in_read = false; 1417 int buf_base = *buf_idx; 1418 __le16 *dst, *src; 1419 int offs_fixup = 0; 1420 int xfer_len = len; 1421 int ret; 1422 int i, n; 1423 1424 if (!mask) 1425 return 0; 1426 1427 /* 1428 * All channels are made up 1 16-bit sample, except for quaternion that 1429 * is made up 4 16-bit values. 1430 * For us the quaternion CH is just like 4 regular CHs. 1431 * If our read starts past the quaternion make sure to adjust the 1432 * starting offset; if the quaternion is contained in our scan then make 1433 * sure to adjust the read len. 1434 */ 1435 if (start_ch > BNO055_SCAN_QUATERNION) { 1436 start_ch += 3; 1437 } else if ((start_ch <= BNO055_SCAN_QUATERNION) && 1438 ((start_ch + len) > BNO055_SCAN_QUATERNION)) { 1439 quat_in_read = true; 1440 xfer_len += 3; 1441 } 1442 1443 ret = regmap_bulk_read(priv->regmap, 1444 base + start_ch * sizeof(__le16), 1445 buf + buf_base, 1446 xfer_len * sizeof(__le16)); 1447 if (ret) 1448 return ret; 1449 1450 for_each_set_bit(i, &mask, len) { 1451 if (quat_in_read && ((start_ch + i) > BNO055_SCAN_QUATERNION)) 1452 offs_fixup = 3; 1453 1454 dst = buf + *buf_idx; 1455 src = buf + buf_base + offs_fixup + i; 1456 1457 n = (start_ch + i == BNO055_SCAN_QUATERNION) ? 4 : 1; 1458 1459 if (dst != src) 1460 memcpy(dst, src, n * sizeof(__le16)); 1461 1462 *buf_idx += n; 1463 } 1464 return 0; 1465 } 1466 1467 static irqreturn_t bno055_trigger_handler(int irq, void *p) 1468 { 1469 struct iio_poll_func *pf = p; 1470 struct iio_dev *iio_dev = pf->indio_dev; 1471 struct bno055_priv *priv = iio_priv(iio_dev); 1472 int xfer_start, start, end, prev_end; 1473 unsigned long mask; 1474 int quat_extra_len; 1475 bool first = true; 1476 int buf_idx = 0; 1477 bool thr_hit; 1478 int ret; 1479 1480 mutex_lock(&priv->lock); 1481 1482 /* 1483 * Walk the bitmap and eventually perform several transfers. 1484 * Bitmap ones-fields that are separated by gaps <= xfer_burst_break_thr 1485 * will be included in same transfer. 1486 * Every time the bitmap contains a gap wider than xfer_burst_break_thr 1487 * then we split the transfer, skipping the gap. 1488 */ 1489 for_each_set_bitrange(start, end, iio_dev->active_scan_mask, 1490 iio_get_masklength(iio_dev)) { 1491 /* 1492 * First transfer will start from the beginning of the first 1493 * ones-field in the bitmap 1494 */ 1495 if (first) { 1496 xfer_start = start; 1497 } else { 1498 /* 1499 * We found the next ones-field; check whether to 1500 * include it in * the current transfer or not (i.e. 1501 * let's perform the current * transfer and prepare for 1502 * another one). 1503 */ 1504 1505 /* 1506 * In case the zeros-gap contains the quaternion bit, 1507 * then its length is actually 4 words instead of 1 1508 * (i.e. +3 wrt other channels). 1509 */ 1510 quat_extra_len = ((start > BNO055_SCAN_QUATERNION) && 1511 (prev_end <= BNO055_SCAN_QUATERNION)) ? 3 : 0; 1512 1513 /* If the gap is wider than xfer_burst_break_thr then.. */ 1514 thr_hit = (start - prev_end + quat_extra_len) > 1515 priv->xfer_burst_break_thr; 1516 1517 /* 1518 * .. transfer all the data up to the gap. Then set the 1519 * next transfer start index at right after the gap 1520 * (i.e. at the start of this ones-field). 1521 */ 1522 if (thr_hit) { 1523 mask = *iio_dev->active_scan_mask >> xfer_start; 1524 ret = bno055_scan_xfer(priv, xfer_start, 1525 prev_end - xfer_start, 1526 mask, priv->buf.chans, &buf_idx); 1527 if (ret) 1528 goto done; 1529 xfer_start = start; 1530 } 1531 } 1532 first = false; 1533 prev_end = end; 1534 } 1535 1536 /* 1537 * We finished walking the bitmap; no more gaps to check for. Just 1538 * perform the current transfer. 1539 */ 1540 mask = *iio_dev->active_scan_mask >> xfer_start; 1541 ret = bno055_scan_xfer(priv, xfer_start, 1542 prev_end - xfer_start, 1543 mask, priv->buf.chans, &buf_idx); 1544 1545 if (!ret) 1546 iio_push_to_buffers_with_timestamp(iio_dev, 1547 &priv->buf, pf->timestamp); 1548 done: 1549 mutex_unlock(&priv->lock); 1550 iio_trigger_notify_done(iio_dev->trig); 1551 return IRQ_HANDLED; 1552 } 1553 1554 static int bno055_buffer_preenable(struct iio_dev *indio_dev) 1555 { 1556 struct bno055_priv *priv = iio_priv(indio_dev); 1557 const unsigned long fusion_mask = 1558 BIT(BNO055_SCAN_YAW) | 1559 BIT(BNO055_SCAN_ROLL) | 1560 BIT(BNO055_SCAN_PITCH) | 1561 BIT(BNO055_SCAN_QUATERNION) | 1562 BIT(BNO055_SCAN_LIA_X) | 1563 BIT(BNO055_SCAN_LIA_Y) | 1564 BIT(BNO055_SCAN_LIA_Z) | 1565 BIT(BNO055_SCAN_GRAVITY_X) | 1566 BIT(BNO055_SCAN_GRAVITY_Y) | 1567 BIT(BNO055_SCAN_GRAVITY_Z); 1568 1569 if (priv->operation_mode == BNO055_OPR_MODE_AMG && 1570 bitmap_intersects(indio_dev->active_scan_mask, &fusion_mask, 1571 _BNO055_SCAN_MAX)) 1572 return -EBUSY; 1573 return 0; 1574 } 1575 1576 static const struct iio_buffer_setup_ops bno055_buffer_setup_ops = { 1577 .preenable = bno055_buffer_preenable, 1578 }; 1579 1580 int bno055_probe(struct device *dev, struct regmap *regmap, 1581 int xfer_burst_break_thr, bool sw_reset) 1582 { 1583 const struct firmware *caldata = NULL; 1584 struct bno055_priv *priv; 1585 struct iio_dev *iio_dev; 1586 char *fw_name_buf; 1587 unsigned int val; 1588 int rev, ver; 1589 int ret; 1590 1591 iio_dev = devm_iio_device_alloc(dev, sizeof(*priv)); 1592 if (!iio_dev) 1593 return -ENOMEM; 1594 1595 iio_dev->name = "bno055"; 1596 priv = iio_priv(iio_dev); 1597 mutex_init(&priv->lock); 1598 priv->regmap = regmap; 1599 priv->dev = dev; 1600 priv->xfer_burst_break_thr = xfer_burst_break_thr; 1601 priv->sw_reset = sw_reset; 1602 1603 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1604 if (IS_ERR(priv->reset_gpio)) 1605 return dev_err_probe(dev, PTR_ERR(priv->reset_gpio), "Failed to get reset GPIO\n"); 1606 1607 priv->clk = devm_clk_get_optional_enabled(dev, "clk"); 1608 if (IS_ERR(priv->clk)) 1609 return dev_err_probe(dev, PTR_ERR(priv->clk), "Failed to get CLK\n"); 1610 1611 if (priv->reset_gpio) { 1612 usleep_range(5000, 10000); 1613 gpiod_set_value_cansleep(priv->reset_gpio, 1); 1614 usleep_range(650000, 750000); 1615 } else if (!sw_reset) { 1616 dev_warn(dev, "No usable reset method; IMU may be unreliable\n"); 1617 } 1618 1619 ret = regmap_read(priv->regmap, BNO055_CHIP_ID_REG, &val); 1620 if (ret) 1621 return ret; 1622 1623 if (val != BNO055_CHIP_ID_MAGIC) 1624 dev_warn(dev, "Unrecognized chip ID 0x%x\n", val); 1625 1626 /* 1627 * In case we haven't a HW reset pin, we can still reset the chip via 1628 * register write. This is probably nonsense in case we can't even 1629 * communicate with the chip or the chip isn't the one we expect (i.e. 1630 * we don't write to unknown chips), so we perform SW reset only after 1631 * chip magic ID check 1632 */ 1633 if (!priv->reset_gpio) { 1634 ret = bno055_system_reset(priv); 1635 if (ret) 1636 return ret; 1637 } 1638 1639 ret = regmap_read(priv->regmap, BNO055_SW_REV_LSB_REG, &rev); 1640 if (ret) 1641 return ret; 1642 1643 ret = regmap_read(priv->regmap, BNO055_SW_REV_MSB_REG, &ver); 1644 if (ret) 1645 return ret; 1646 1647 /* 1648 * The stock FW version contains a bug (see comment at the beginning of 1649 * this file) that causes the anglvel scale to be changed depending on 1650 * the chip range setting. We workaround this, but we don't know what 1651 * other FW versions might do. 1652 */ 1653 if (ver != 0x3 || rev != 0x11) 1654 dev_warn(dev, "Untested firmware version. Anglvel scale may not work as expected\n"); 1655 1656 ret = regmap_bulk_read(priv->regmap, BNO055_UID_LOWER_REG, 1657 priv->uid, BNO055_UID_LEN); 1658 if (ret) 1659 return ret; 1660 1661 /* Sensor calibration data */ 1662 fw_name_buf = kasprintf(GFP_KERNEL, BNO055_FW_UID_FMT, 1663 BNO055_UID_LEN, priv->uid); 1664 if (!fw_name_buf) 1665 return -ENOMEM; 1666 1667 ret = request_firmware(&caldata, fw_name_buf, dev); 1668 kfree(fw_name_buf); 1669 if (ret) 1670 ret = request_firmware(&caldata, BNO055_FW_GENERIC_NAME, dev); 1671 if (ret) { 1672 dev_notice(dev, "Calibration file load failed. See instruction in kernel Documentation/iio/bno055.rst\n"); 1673 ret = bno055_init(priv, NULL, 0); 1674 } else { 1675 ret = bno055_init(priv, caldata->data, caldata->size); 1676 release_firmware(caldata); 1677 } 1678 if (ret) 1679 return ret; 1680 1681 priv->operation_mode = BNO055_OPR_MODE_FUSION; 1682 ret = bno055_operation_mode_do_set(priv, priv->operation_mode); 1683 if (ret) 1684 return ret; 1685 1686 ret = devm_add_action_or_reset(dev, bno055_uninit, priv); 1687 if (ret) 1688 return ret; 1689 1690 iio_dev->channels = bno055_channels; 1691 iio_dev->num_channels = ARRAY_SIZE(bno055_channels); 1692 iio_dev->info = &bno055_info; 1693 iio_dev->modes = INDIO_DIRECT_MODE; 1694 1695 ret = devm_iio_triggered_buffer_setup(dev, iio_dev, 1696 iio_pollfunc_store_time, 1697 bno055_trigger_handler, 1698 &bno055_buffer_setup_ops); 1699 if (ret) 1700 return ret; 1701 1702 ret = devm_iio_device_register(dev, iio_dev); 1703 if (ret) 1704 return ret; 1705 1706 bno055_debugfs_init(iio_dev); 1707 1708 return 0; 1709 } 1710 EXPORT_SYMBOL_NS_GPL(bno055_probe, "IIO_BNO055"); 1711 1712 MODULE_AUTHOR("Andrea Merello <andrea.merello@iit.it>"); 1713 MODULE_DESCRIPTION("Bosch BNO055 driver"); 1714 MODULE_LICENSE("GPL"); 1715