1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Watchdog driver for Intel Keem Bay non-secure watchdog.
4 *
5 * Copyright (C) 2020 Intel Corporation
6 */
7
8 #include <linux/arm-smccc.h>
9 #include <linux/bits.h>
10 #include <linux/clk.h>
11 #include <linux/interrupt.h>
12 #include <linux/io.h>
13 #include <linux/limits.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/reboot.h>
17 #include <linux/watchdog.h>
18
19 /* Non-secure watchdog register offsets */
20 #define TIM_WATCHDOG 0x0
21 #define TIM_WATCHDOG_INT_THRES 0x4
22 #define TIM_WDOG_EN 0x8
23 #define TIM_SAFE 0xc
24
25 #define WDT_TH_INT_MASK BIT(8)
26 #define WDT_TO_INT_MASK BIT(9)
27 #define WDT_INT_CLEAR_SMC 0x8200ff18
28
29 #define WDT_UNLOCK 0xf1d0dead
30 #define WDT_DISABLE 0x0
31 #define WDT_ENABLE 0x1
32
33 #define WDT_LOAD_MAX U32_MAX
34 #define WDT_LOAD_MIN 1
35
36 #define WDT_TIMEOUT 5
37 #define WDT_PRETIMEOUT 4
38
39 static unsigned int timeout = WDT_TIMEOUT;
40 module_param(timeout, int, 0);
41 MODULE_PARM_DESC(timeout, "Watchdog timeout period in seconds (default = "
42 __MODULE_STRING(WDT_TIMEOUT) ")");
43
44 static bool nowayout = WATCHDOG_NOWAYOUT;
45 module_param(nowayout, bool, 0);
46 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default = "
47 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
48
49 struct keembay_wdt {
50 struct watchdog_device wdd;
51 struct clk *clk;
52 unsigned int rate;
53 int to_irq;
54 int th_irq;
55 void __iomem *base;
56 };
57
keembay_wdt_readl(struct keembay_wdt * wdt,u32 offset)58 static inline u32 keembay_wdt_readl(struct keembay_wdt *wdt, u32 offset)
59 {
60 return readl(wdt->base + offset);
61 }
62
keembay_wdt_writel(struct keembay_wdt * wdt,u32 offset,u32 val)63 static inline void keembay_wdt_writel(struct keembay_wdt *wdt, u32 offset, u32 val)
64 {
65 writel(WDT_UNLOCK, wdt->base + TIM_SAFE);
66 writel(val, wdt->base + offset);
67 }
68
keembay_wdt_set_timeout_reg(struct watchdog_device * wdog)69 static void keembay_wdt_set_timeout_reg(struct watchdog_device *wdog)
70 {
71 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
72
73 keembay_wdt_writel(wdt, TIM_WATCHDOG, wdog->timeout * wdt->rate);
74 }
75
keembay_wdt_set_pretimeout_reg(struct watchdog_device * wdog)76 static void keembay_wdt_set_pretimeout_reg(struct watchdog_device *wdog)
77 {
78 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
79 u32 th_val = 0;
80
81 if (wdog->pretimeout)
82 th_val = wdog->timeout - wdog->pretimeout;
83
84 keembay_wdt_writel(wdt, TIM_WATCHDOG_INT_THRES, th_val * wdt->rate);
85 }
86
keembay_wdt_start(struct watchdog_device * wdog)87 static int keembay_wdt_start(struct watchdog_device *wdog)
88 {
89 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
90
91 keembay_wdt_writel(wdt, TIM_WDOG_EN, WDT_ENABLE);
92
93 return 0;
94 }
95
keembay_wdt_stop(struct watchdog_device * wdog)96 static int keembay_wdt_stop(struct watchdog_device *wdog)
97 {
98 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
99
100 keembay_wdt_writel(wdt, TIM_WDOG_EN, WDT_DISABLE);
101
102 return 0;
103 }
104
keembay_wdt_ping(struct watchdog_device * wdog)105 static int keembay_wdt_ping(struct watchdog_device *wdog)
106 {
107 keembay_wdt_set_timeout_reg(wdog);
108
109 return 0;
110 }
111
keembay_wdt_set_timeout(struct watchdog_device * wdog,u32 t)112 static int keembay_wdt_set_timeout(struct watchdog_device *wdog, u32 t)
113 {
114 wdog->timeout = t;
115 keembay_wdt_set_timeout_reg(wdog);
116 keembay_wdt_set_pretimeout_reg(wdog);
117
118 return 0;
119 }
120
keembay_wdt_set_pretimeout(struct watchdog_device * wdog,u32 t)121 static int keembay_wdt_set_pretimeout(struct watchdog_device *wdog, u32 t)
122 {
123 if (t > wdog->timeout)
124 return -EINVAL;
125
126 wdog->pretimeout = t;
127 keembay_wdt_set_pretimeout_reg(wdog);
128
129 return 0;
130 }
131
keembay_wdt_get_timeleft(struct watchdog_device * wdog)132 static unsigned int keembay_wdt_get_timeleft(struct watchdog_device *wdog)
133 {
134 struct keembay_wdt *wdt = watchdog_get_drvdata(wdog);
135
136 return keembay_wdt_readl(wdt, TIM_WATCHDOG) / wdt->rate;
137 }
138
139 /*
140 * SMC call is used to clear the interrupt bits, because the TIM_GEN_CONFIG
141 * register is in the secure bank.
142 */
keembay_wdt_to_isr(int irq,void * dev_id)143 static irqreturn_t keembay_wdt_to_isr(int irq, void *dev_id)
144 {
145 struct keembay_wdt *wdt = dev_id;
146 struct arm_smccc_res res;
147
148 arm_smccc_smc(WDT_INT_CLEAR_SMC, WDT_TO_INT_MASK, 0, 0, 0, 0, 0, 0, &res);
149 dev_crit(wdt->wdd.parent, "Intel Keem Bay non-secure wdt timeout.\n");
150 emergency_restart();
151
152 return IRQ_HANDLED;
153 }
154
keembay_wdt_th_isr(int irq,void * dev_id)155 static irqreturn_t keembay_wdt_th_isr(int irq, void *dev_id)
156 {
157 struct keembay_wdt *wdt = dev_id;
158 struct arm_smccc_res res;
159
160 keembay_wdt_set_pretimeout(&wdt->wdd, 0x0);
161
162 arm_smccc_smc(WDT_INT_CLEAR_SMC, WDT_TH_INT_MASK, 0, 0, 0, 0, 0, 0, &res);
163 dev_crit(wdt->wdd.parent, "Intel Keem Bay non-secure wdt pre-timeout.\n");
164 watchdog_notify_pretimeout(&wdt->wdd);
165
166 return IRQ_HANDLED;
167 }
168
169 static const struct watchdog_info keembay_wdt_info = {
170 .identity = "Intel Keem Bay Watchdog Timer",
171 .options = WDIOF_SETTIMEOUT |
172 WDIOF_PRETIMEOUT |
173 WDIOF_MAGICCLOSE |
174 WDIOF_KEEPALIVEPING,
175 };
176
177 static const struct watchdog_ops keembay_wdt_ops = {
178 .owner = THIS_MODULE,
179 .start = keembay_wdt_start,
180 .stop = keembay_wdt_stop,
181 .ping = keembay_wdt_ping,
182 .set_timeout = keembay_wdt_set_timeout,
183 .set_pretimeout = keembay_wdt_set_pretimeout,
184 .get_timeleft = keembay_wdt_get_timeleft,
185 };
186
keembay_wdt_probe(struct platform_device * pdev)187 static int keembay_wdt_probe(struct platform_device *pdev)
188 {
189 struct device *dev = &pdev->dev;
190 struct keembay_wdt *wdt;
191 int ret;
192
193 wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
194 if (!wdt)
195 return -ENOMEM;
196
197 wdt->base = devm_platform_ioremap_resource(pdev, 0);
198 if (IS_ERR(wdt->base))
199 return PTR_ERR(wdt->base);
200
201 /* we do not need to enable the clock as it is enabled by default */
202 wdt->clk = devm_clk_get(dev, NULL);
203 if (IS_ERR(wdt->clk))
204 return dev_err_probe(dev, PTR_ERR(wdt->clk), "Failed to get clock\n");
205
206 wdt->rate = clk_get_rate(wdt->clk);
207 if (!wdt->rate)
208 return dev_err_probe(dev, -EINVAL, "Failed to get clock rate\n");
209
210 wdt->th_irq = platform_get_irq_byname(pdev, "threshold");
211 if (wdt->th_irq < 0)
212 return dev_err_probe(dev, wdt->th_irq, "Failed to get IRQ for threshold\n");
213
214 ret = devm_request_irq(dev, wdt->th_irq, keembay_wdt_th_isr, 0,
215 "keembay-wdt", wdt);
216 if (ret)
217 return ret;
218
219 wdt->to_irq = platform_get_irq_byname(pdev, "timeout");
220 if (wdt->to_irq < 0)
221 return dev_err_probe(dev, wdt->to_irq, "Failed to get IRQ for timeout\n");
222
223 ret = devm_request_irq(dev, wdt->to_irq, keembay_wdt_to_isr, 0,
224 "keembay-wdt", wdt);
225 if (ret)
226 return ret;
227
228 wdt->wdd.parent = dev;
229 wdt->wdd.info = &keembay_wdt_info;
230 wdt->wdd.ops = &keembay_wdt_ops;
231 wdt->wdd.min_timeout = WDT_LOAD_MIN;
232 wdt->wdd.max_timeout = WDT_LOAD_MAX / wdt->rate;
233 wdt->wdd.timeout = WDT_TIMEOUT;
234 wdt->wdd.pretimeout = WDT_PRETIMEOUT;
235
236 watchdog_set_drvdata(&wdt->wdd, wdt);
237 watchdog_set_nowayout(&wdt->wdd, nowayout);
238 watchdog_init_timeout(&wdt->wdd, timeout, dev);
239 keembay_wdt_set_timeout(&wdt->wdd, wdt->wdd.timeout);
240 keembay_wdt_set_pretimeout(&wdt->wdd, wdt->wdd.pretimeout);
241
242 ret = devm_watchdog_register_device(dev, &wdt->wdd);
243 if (ret)
244 return dev_err_probe(dev, ret, "Failed to register watchdog device.\n");
245
246 platform_set_drvdata(pdev, wdt);
247 dev_info(dev, "Initial timeout %d sec%s.\n",
248 wdt->wdd.timeout, nowayout ? ", nowayout" : "");
249
250 return 0;
251 }
252
keembay_wdt_suspend(struct device * dev)253 static int __maybe_unused keembay_wdt_suspend(struct device *dev)
254 {
255 struct keembay_wdt *wdt = dev_get_drvdata(dev);
256
257 if (watchdog_active(&wdt->wdd))
258 return keembay_wdt_stop(&wdt->wdd);
259
260 return 0;
261 }
262
keembay_wdt_resume(struct device * dev)263 static int __maybe_unused keembay_wdt_resume(struct device *dev)
264 {
265 struct keembay_wdt *wdt = dev_get_drvdata(dev);
266
267 if (watchdog_active(&wdt->wdd))
268 return keembay_wdt_start(&wdt->wdd);
269
270 return 0;
271 }
272
273 static SIMPLE_DEV_PM_OPS(keembay_wdt_pm_ops, keembay_wdt_suspend,
274 keembay_wdt_resume);
275
276 static const struct of_device_id keembay_wdt_match[] = {
277 { .compatible = "intel,keembay-wdt" },
278 { }
279 };
280 MODULE_DEVICE_TABLE(of, keembay_wdt_match);
281
282 static struct platform_driver keembay_wdt_driver = {
283 .probe = keembay_wdt_probe,
284 .driver = {
285 .name = "keembay_wdt",
286 .of_match_table = keembay_wdt_match,
287 .pm = &keembay_wdt_pm_ops,
288 },
289 };
290
291 module_platform_driver(keembay_wdt_driver);
292
293 MODULE_DESCRIPTION("Intel Keem Bay SoC watchdog driver");
294 MODULE_AUTHOR("Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com");
295 MODULE_LICENSE("GPL v2");
296