1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Intel Tiger Lake PCH pinctrl/GPIO driver 4 * 5 * Copyright (C) 2019 - 2020, Intel Corporation 6 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 7 * Mika Westerberg <mika.westerberg@linux.intel.com> 8 */ 9 10 #include <linux/mod_devicetable.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm.h> 14 15 #include <linux/pinctrl/pinctrl.h> 16 17 #include "pinctrl-intel.h" 18 19 #define TGL_LP_PAD_OWN 0x020 20 #define TGL_LP_PADCFGLOCK 0x080 21 #define TGL_LP_HOSTSW_OWN 0x0b0 22 #define TGL_LP_GPI_IS 0x100 23 #define TGL_LP_GPI_IE 0x120 24 25 #define TGL_H_PAD_OWN 0x020 26 #define TGL_H_PADCFGLOCK 0x090 27 #define TGL_H_HOSTSW_OWN 0x0c0 28 #define TGL_H_GPI_IS 0x100 29 #define TGL_H_GPI_IE 0x120 30 31 #define TGL_LP_COMMUNITY(b, s, e, g) \ 32 INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_LP) 33 34 #define TGL_H_COMMUNITY(b, s, e, g) \ 35 INTEL_COMMUNITY_GPPS(b, s, e, g, TGL_H) 36 37 /* Tiger Lake-LP */ 38 static const struct pinctrl_pin_desc tgllp_pins[] = { 39 /* GPP_B */ 40 PINCTRL_PIN(0, "CORE_VID_0"), 41 PINCTRL_PIN(1, "CORE_VID_1"), 42 PINCTRL_PIN(2, "VRALERTB"), 43 PINCTRL_PIN(3, "CPU_GP_2"), 44 PINCTRL_PIN(4, "CPU_GP_3"), 45 PINCTRL_PIN(5, "ISH_I2C0_SDA"), 46 PINCTRL_PIN(6, "ISH_I2C0_SCL"), 47 PINCTRL_PIN(7, "ISH_I2C1_SDA"), 48 PINCTRL_PIN(8, "ISH_I2C1_SCL"), 49 PINCTRL_PIN(9, "I2C5_SDA"), 50 PINCTRL_PIN(10, "I2C5_SCL"), 51 PINCTRL_PIN(11, "PMCALERTB"), 52 PINCTRL_PIN(12, "SLP_S0B"), 53 PINCTRL_PIN(13, "PLTRSTB"), 54 PINCTRL_PIN(14, "SPKR"), 55 PINCTRL_PIN(15, "GSPI0_CS0B"), 56 PINCTRL_PIN(16, "GSPI0_CLK"), 57 PINCTRL_PIN(17, "GSPI0_MISO"), 58 PINCTRL_PIN(18, "GSPI0_MOSI"), 59 PINCTRL_PIN(19, "GSPI1_CS0B"), 60 PINCTRL_PIN(20, "GSPI1_CLK"), 61 PINCTRL_PIN(21, "GSPI1_MISO"), 62 PINCTRL_PIN(22, "GSPI1_MOSI"), 63 PINCTRL_PIN(23, "SML1ALERTB"), 64 PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"), 65 PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"), 66 /* GPP_T */ 67 PINCTRL_PIN(26, "I2C6_SDA"), 68 PINCTRL_PIN(27, "I2C6_SCL"), 69 PINCTRL_PIN(28, "I2C7_SDA"), 70 PINCTRL_PIN(29, "I2C7_SCL"), 71 PINCTRL_PIN(30, "UART4_RXD"), 72 PINCTRL_PIN(31, "UART4_TXD"), 73 PINCTRL_PIN(32, "UART4_RTSB"), 74 PINCTRL_PIN(33, "UART4_CTSB"), 75 PINCTRL_PIN(34, "UART5_RXD"), 76 PINCTRL_PIN(35, "UART5_TXD"), 77 PINCTRL_PIN(36, "UART5_RTSB"), 78 PINCTRL_PIN(37, "UART5_CTSB"), 79 PINCTRL_PIN(38, "UART6_RXD"), 80 PINCTRL_PIN(39, "UART6_TXD"), 81 PINCTRL_PIN(40, "UART6_RTSB"), 82 PINCTRL_PIN(41, "UART6_CTSB"), 83 /* GPP_A */ 84 PINCTRL_PIN(42, "ESPI_IO_0"), 85 PINCTRL_PIN(43, "ESPI_IO_1"), 86 PINCTRL_PIN(44, "ESPI_IO_2"), 87 PINCTRL_PIN(45, "ESPI_IO_3"), 88 PINCTRL_PIN(46, "ESPI_CSB"), 89 PINCTRL_PIN(47, "ESPI_CLK"), 90 PINCTRL_PIN(48, "ESPI_RESETB"), 91 PINCTRL_PIN(49, "I2S2_SCLK"), 92 PINCTRL_PIN(50, "I2S2_SFRM"), 93 PINCTRL_PIN(51, "I2S2_TXD"), 94 PINCTRL_PIN(52, "I2S2_RXD"), 95 PINCTRL_PIN(53, "PMC_I2C_SDA"), 96 PINCTRL_PIN(54, "SATAXPCIE_1"), 97 PINCTRL_PIN(55, "PMC_I2C_SCL"), 98 PINCTRL_PIN(56, "USB2_OCB_1"), 99 PINCTRL_PIN(57, "USB2_OCB_2"), 100 PINCTRL_PIN(58, "USB2_OCB_3"), 101 PINCTRL_PIN(59, "DDSP_HPD_C"), 102 PINCTRL_PIN(60, "DDSP_HPD_B"), 103 PINCTRL_PIN(61, "DDSP_HPD_1"), 104 PINCTRL_PIN(62, "DDSP_HPD_2"), 105 PINCTRL_PIN(63, "GPPC_A_21"), 106 PINCTRL_PIN(64, "GPPC_A_22"), 107 PINCTRL_PIN(65, "I2S1_SCLK"), 108 PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"), 109 /* GPP_S */ 110 PINCTRL_PIN(67, "SNDW0_CLK"), 111 PINCTRL_PIN(68, "SNDW0_DATA"), 112 PINCTRL_PIN(69, "SNDW1_CLK"), 113 PINCTRL_PIN(70, "SNDW1_DATA"), 114 PINCTRL_PIN(71, "SNDW2_CLK"), 115 PINCTRL_PIN(72, "SNDW2_DATA"), 116 PINCTRL_PIN(73, "SNDW3_CLK"), 117 PINCTRL_PIN(74, "SNDW3_DATA"), 118 /* GPP_H */ 119 PINCTRL_PIN(75, "GPPC_H_0"), 120 PINCTRL_PIN(76, "GPPC_H_1"), 121 PINCTRL_PIN(77, "GPPC_H_2"), 122 PINCTRL_PIN(78, "SX_EXIT_HOLDOFFB"), 123 PINCTRL_PIN(79, "I2C2_SDA"), 124 PINCTRL_PIN(80, "I2C2_SCL"), 125 PINCTRL_PIN(81, "I2C3_SDA"), 126 PINCTRL_PIN(82, "I2C3_SCL"), 127 PINCTRL_PIN(83, "I2C4_SDA"), 128 PINCTRL_PIN(84, "I2C4_SCL"), 129 PINCTRL_PIN(85, "SRCCLKREQB_4"), 130 PINCTRL_PIN(86, "SRCCLKREQB_5"), 131 PINCTRL_PIN(87, "M2_SKT2_CFG_0"), 132 PINCTRL_PIN(88, "M2_SKT2_CFG_1"), 133 PINCTRL_PIN(89, "M2_SKT2_CFG_2"), 134 PINCTRL_PIN(90, "M2_SKT2_CFG_3"), 135 PINCTRL_PIN(91, "DDPB_CTRLCLK"), 136 PINCTRL_PIN(92, "DDPB_CTRLDATA"), 137 PINCTRL_PIN(93, "CPU_C10_GATEB"), 138 PINCTRL_PIN(94, "TIME_SYNC_0"), 139 PINCTRL_PIN(95, "IMGCLKOUT_1"), 140 PINCTRL_PIN(96, "IMGCLKOUT_2"), 141 PINCTRL_PIN(97, "IMGCLKOUT_3"), 142 PINCTRL_PIN(98, "IMGCLKOUT_4"), 143 /* GPP_D */ 144 PINCTRL_PIN(99, "ISH_GP_0"), 145 PINCTRL_PIN(100, "ISH_GP_1"), 146 PINCTRL_PIN(101, "ISH_GP_2"), 147 PINCTRL_PIN(102, "ISH_GP_3"), 148 PINCTRL_PIN(103, "IMGCLKOUT_0"), 149 PINCTRL_PIN(104, "SRCCLKREQB_0"), 150 PINCTRL_PIN(105, "SRCCLKREQB_1"), 151 PINCTRL_PIN(106, "SRCCLKREQB_2"), 152 PINCTRL_PIN(107, "SRCCLKREQB_3"), 153 PINCTRL_PIN(108, "ISH_SPI_CSB"), 154 PINCTRL_PIN(109, "ISH_SPI_CLK"), 155 PINCTRL_PIN(110, "ISH_SPI_MISO"), 156 PINCTRL_PIN(111, "ISH_SPI_MOSI"), 157 PINCTRL_PIN(112, "ISH_UART0_RXD"), 158 PINCTRL_PIN(113, "ISH_UART0_TXD"), 159 PINCTRL_PIN(114, "ISH_UART0_RTSB"), 160 PINCTRL_PIN(115, "ISH_UART0_CTSB"), 161 PINCTRL_PIN(116, "ISH_GP_4"), 162 PINCTRL_PIN(117, "ISH_GP_5"), 163 PINCTRL_PIN(118, "I2S_MCLK1_OUT"), 164 PINCTRL_PIN(119, "GSPI2_CLK_LOOPBK"), 165 /* GPP_U */ 166 PINCTRL_PIN(120, "UART3_RXD"), 167 PINCTRL_PIN(121, "UART3_TXD"), 168 PINCTRL_PIN(122, "UART3_RTSB"), 169 PINCTRL_PIN(123, "UART3_CTSB"), 170 PINCTRL_PIN(124, "GSPI3_CS0B"), 171 PINCTRL_PIN(125, "GSPI3_CLK"), 172 PINCTRL_PIN(126, "GSPI3_MISO"), 173 PINCTRL_PIN(127, "GSPI3_MOSI"), 174 PINCTRL_PIN(128, "GSPI4_CS0B"), 175 PINCTRL_PIN(129, "GSPI4_CLK"), 176 PINCTRL_PIN(130, "GSPI4_MISO"), 177 PINCTRL_PIN(131, "GSPI4_MOSI"), 178 PINCTRL_PIN(132, "GSPI5_CS0B"), 179 PINCTRL_PIN(133, "GSPI5_CLK"), 180 PINCTRL_PIN(134, "GSPI5_MISO"), 181 PINCTRL_PIN(135, "GSPI5_MOSI"), 182 PINCTRL_PIN(136, "GSPI6_CS0B"), 183 PINCTRL_PIN(137, "GSPI6_CLK"), 184 PINCTRL_PIN(138, "GSPI6_MISO"), 185 PINCTRL_PIN(139, "GSPI6_MOSI"), 186 PINCTRL_PIN(140, "GSPI3_CLK_LOOPBK"), 187 PINCTRL_PIN(141, "GSPI4_CLK_LOOPBK"), 188 PINCTRL_PIN(142, "GSPI5_CLK_LOOPBK"), 189 PINCTRL_PIN(143, "GSPI6_CLK_LOOPBK"), 190 /* vGPIO */ 191 PINCTRL_PIN(144, "CNV_BTEN"), 192 PINCTRL_PIN(145, "CNV_BT_HOST_WAKEB"), 193 PINCTRL_PIN(146, "CNV_BT_IF_SELECT"), 194 PINCTRL_PIN(147, "vCNV_BT_UART_TXD"), 195 PINCTRL_PIN(148, "vCNV_BT_UART_RXD"), 196 PINCTRL_PIN(149, "vCNV_BT_UART_CTS_B"), 197 PINCTRL_PIN(150, "vCNV_BT_UART_RTS_B"), 198 PINCTRL_PIN(151, "vCNV_MFUART1_TXD"), 199 PINCTRL_PIN(152, "vCNV_MFUART1_RXD"), 200 PINCTRL_PIN(153, "vCNV_MFUART1_CTS_B"), 201 PINCTRL_PIN(154, "vCNV_MFUART1_RTS_B"), 202 PINCTRL_PIN(155, "vUART0_TXD"), 203 PINCTRL_PIN(156, "vUART0_RXD"), 204 PINCTRL_PIN(157, "vUART0_CTS_B"), 205 PINCTRL_PIN(158, "vUART0_RTS_B"), 206 PINCTRL_PIN(159, "vISH_UART0_TXD"), 207 PINCTRL_PIN(160, "vISH_UART0_RXD"), 208 PINCTRL_PIN(161, "vISH_UART0_CTS_B"), 209 PINCTRL_PIN(162, "vISH_UART0_RTS_B"), 210 PINCTRL_PIN(163, "vCNV_BT_I2S_BCLK"), 211 PINCTRL_PIN(164, "vCNV_BT_I2S_WS_SYNC"), 212 PINCTRL_PIN(165, "vCNV_BT_I2S_SDO"), 213 PINCTRL_PIN(166, "vCNV_BT_I2S_SDI"), 214 PINCTRL_PIN(167, "vI2S2_SCLK"), 215 PINCTRL_PIN(168, "vI2S2_SFRM"), 216 PINCTRL_PIN(169, "vI2S2_TXD"), 217 PINCTRL_PIN(170, "vI2S2_RXD"), 218 /* GPP_C */ 219 PINCTRL_PIN(171, "SMBCLK"), 220 PINCTRL_PIN(172, "SMBDATA"), 221 PINCTRL_PIN(173, "SMBALERTB"), 222 PINCTRL_PIN(174, "SML0CLK"), 223 PINCTRL_PIN(175, "SML0DATA"), 224 PINCTRL_PIN(176, "SML0ALERTB"), 225 PINCTRL_PIN(177, "SML1CLK"), 226 PINCTRL_PIN(178, "SML1DATA"), 227 PINCTRL_PIN(179, "UART0_RXD"), 228 PINCTRL_PIN(180, "UART0_TXD"), 229 PINCTRL_PIN(181, "UART0_RTSB"), 230 PINCTRL_PIN(182, "UART0_CTSB"), 231 PINCTRL_PIN(183, "UART1_RXD"), 232 PINCTRL_PIN(184, "UART1_TXD"), 233 PINCTRL_PIN(185, "UART1_RTSB"), 234 PINCTRL_PIN(186, "UART1_CTSB"), 235 PINCTRL_PIN(187, "I2C0_SDA"), 236 PINCTRL_PIN(188, "I2C0_SCL"), 237 PINCTRL_PIN(189, "I2C1_SDA"), 238 PINCTRL_PIN(190, "I2C1_SCL"), 239 PINCTRL_PIN(191, "UART2_RXD"), 240 PINCTRL_PIN(192, "UART2_TXD"), 241 PINCTRL_PIN(193, "UART2_RTSB"), 242 PINCTRL_PIN(194, "UART2_CTSB"), 243 /* GPP_F */ 244 PINCTRL_PIN(195, "CNV_BRI_DT"), 245 PINCTRL_PIN(196, "CNV_BRI_RSP"), 246 PINCTRL_PIN(197, "CNV_RGI_DT"), 247 PINCTRL_PIN(198, "CNV_RGI_RSP"), 248 PINCTRL_PIN(199, "CNV_RF_RESET_B"), 249 PINCTRL_PIN(200, "GPPC_F_5"), 250 PINCTRL_PIN(201, "CNV_PA_BLANKING"), 251 PINCTRL_PIN(202, "GPPC_F_7"), 252 PINCTRL_PIN(203, "I2S_MCLK2_INOUT"), 253 PINCTRL_PIN(204, "BOOTMPC"), 254 PINCTRL_PIN(205, "GPPC_F_10"), 255 PINCTRL_PIN(206, "GPPC_F_11"), 256 PINCTRL_PIN(207, "GSXDOUT"), 257 PINCTRL_PIN(208, "GSXSLOAD"), 258 PINCTRL_PIN(209, "GSXDIN"), 259 PINCTRL_PIN(210, "GSXSRESETB"), 260 PINCTRL_PIN(211, "GSXCLK"), 261 PINCTRL_PIN(212, "GMII_MDC"), 262 PINCTRL_PIN(213, "GMII_MDIO"), 263 PINCTRL_PIN(214, "SRCCLKREQB_6"), 264 PINCTRL_PIN(215, "EXT_PWR_GATEB"), 265 PINCTRL_PIN(216, "EXT_PWR_GATE2B"), 266 PINCTRL_PIN(217, "VNN_CTRL"), 267 PINCTRL_PIN(218, "V1P05_CTRL"), 268 PINCTRL_PIN(219, "GPPF_CLK_LOOPBACK"), 269 /* HVCMOS */ 270 PINCTRL_PIN(220, "L_BKLTEN"), 271 PINCTRL_PIN(221, "L_BKLTCTL"), 272 PINCTRL_PIN(222, "L_VDDEN"), 273 PINCTRL_PIN(223, "SYS_PWROK"), 274 PINCTRL_PIN(224, "SYS_RESETB"), 275 PINCTRL_PIN(225, "MLK_RSTB"), 276 /* GPP_E */ 277 PINCTRL_PIN(226, "SATAXPCIE_0"), 278 PINCTRL_PIN(227, "SPI1_IO_2"), 279 PINCTRL_PIN(228, "SPI1_IO_3"), 280 PINCTRL_PIN(229, "CPU_GP_0"), 281 PINCTRL_PIN(230, "SATA_DEVSLP_0"), 282 PINCTRL_PIN(231, "SATA_DEVSLP_1"), 283 PINCTRL_PIN(232, "GPPC_E_6"), 284 PINCTRL_PIN(233, "CPU_GP_1"), 285 PINCTRL_PIN(234, "SPI1_CS1B"), 286 PINCTRL_PIN(235, "USB2_OCB_0"), 287 PINCTRL_PIN(236, "SPI1_CSB"), 288 PINCTRL_PIN(237, "SPI1_CLK"), 289 PINCTRL_PIN(238, "SPI1_MISO_IO_1"), 290 PINCTRL_PIN(239, "SPI1_MOSI_IO_0"), 291 PINCTRL_PIN(240, "DDSP_HPD_A"), 292 PINCTRL_PIN(241, "ISH_GP_6"), 293 PINCTRL_PIN(242, "ISH_GP_7"), 294 PINCTRL_PIN(243, "GPPC_E_17"), 295 PINCTRL_PIN(244, "DDP1_CTRLCLK"), 296 PINCTRL_PIN(245, "DDP1_CTRLDATA"), 297 PINCTRL_PIN(246, "DDP2_CTRLCLK"), 298 PINCTRL_PIN(247, "DDP2_CTRLDATA"), 299 PINCTRL_PIN(248, "DDPA_CTRLCLK"), 300 PINCTRL_PIN(249, "DDPA_CTRLDATA"), 301 PINCTRL_PIN(250, "SPI1_CLK_LOOPBK"), 302 /* JTAG */ 303 PINCTRL_PIN(251, "JTAG_TDO"), 304 PINCTRL_PIN(252, "JTAGX"), 305 PINCTRL_PIN(253, "PRDYB"), 306 PINCTRL_PIN(254, "PREQB"), 307 PINCTRL_PIN(255, "CPU_TRSTB"), 308 PINCTRL_PIN(256, "JTAG_TDI"), 309 PINCTRL_PIN(257, "JTAG_TMS"), 310 PINCTRL_PIN(258, "JTAG_TCK"), 311 PINCTRL_PIN(259, "DBG_PMODE"), 312 /* GPP_R */ 313 PINCTRL_PIN(260, "HDA_BCLK"), 314 PINCTRL_PIN(261, "HDA_SYNC"), 315 PINCTRL_PIN(262, "HDA_SDO"), 316 PINCTRL_PIN(263, "HDA_SDI_0"), 317 PINCTRL_PIN(264, "HDA_RSTB"), 318 PINCTRL_PIN(265, "HDA_SDI_1"), 319 PINCTRL_PIN(266, "GPP_R_6"), 320 PINCTRL_PIN(267, "GPP_R_7"), 321 /* SPI */ 322 PINCTRL_PIN(268, "SPI0_IO_2"), 323 PINCTRL_PIN(269, "SPI0_IO_3"), 324 PINCTRL_PIN(270, "SPI0_MOSI_IO_0"), 325 PINCTRL_PIN(271, "SPI0_MISO_IO_1"), 326 PINCTRL_PIN(272, "SPI0_TPM_CSB"), 327 PINCTRL_PIN(273, "SPI0_FLASH_0_CSB"), 328 PINCTRL_PIN(274, "SPI0_FLASH_1_CSB"), 329 PINCTRL_PIN(275, "SPI0_CLK"), 330 PINCTRL_PIN(276, "SPI0_CLK_LOOPBK"), 331 }; 332 333 static const struct intel_padgroup tgllp_community0_gpps[] = { 334 INTEL_GPP(0, 0, 25, 0), /* GPP_B */ 335 INTEL_GPP(1, 26, 41, 32), /* GPP_T */ 336 INTEL_GPP(2, 42, 66, 64), /* GPP_A */ 337 }; 338 339 static const struct intel_padgroup tgllp_community1_gpps[] = { 340 INTEL_GPP(0, 67, 74, 96), /* GPP_S */ 341 INTEL_GPP(1, 75, 98, 128), /* GPP_H */ 342 INTEL_GPP(2, 99, 119, 160), /* GPP_D */ 343 INTEL_GPP(3, 120, 143, 192), /* GPP_U */ 344 INTEL_GPP(4, 144, 170, 224), /* vGPIO */ 345 }; 346 347 static const struct intel_padgroup tgllp_community4_gpps[] = { 348 INTEL_GPP(0, 171, 194, 256), /* GPP_C */ 349 INTEL_GPP(1, 195, 219, 288), /* GPP_F */ 350 INTEL_GPP(2, 220, 225, INTEL_GPIO_BASE_NOMAP), /* HVCMOS */ 351 INTEL_GPP(3, 226, 250, 320), /* GPP_E */ 352 INTEL_GPP(4, 251, 259, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 353 }; 354 355 static const struct intel_padgroup tgllp_community5_gpps[] = { 356 INTEL_GPP(0, 260, 267, 352), /* GPP_R */ 357 INTEL_GPP(1, 268, 276, INTEL_GPIO_BASE_NOMAP), /* SPI */ 358 }; 359 360 static const struct intel_community tgllp_communities[] = { 361 TGL_LP_COMMUNITY(0, 0, 66, tgllp_community0_gpps), 362 TGL_LP_COMMUNITY(1, 67, 170, tgllp_community1_gpps), 363 TGL_LP_COMMUNITY(2, 171, 259, tgllp_community4_gpps), 364 TGL_LP_COMMUNITY(3, 260, 276, tgllp_community5_gpps), 365 }; 366 367 static const struct intel_pinctrl_soc_data tgllp_soc_data = { 368 .pins = tgllp_pins, 369 .npins = ARRAY_SIZE(tgllp_pins), 370 .communities = tgllp_communities, 371 .ncommunities = ARRAY_SIZE(tgllp_communities), 372 }; 373 374 /* Tiger Lake-H */ 375 static const struct pinctrl_pin_desc tglh_pins[] = { 376 /* GPP_A */ 377 PINCTRL_PIN(0, "SPI0_IO_2"), 378 PINCTRL_PIN(1, "SPI0_IO_3"), 379 PINCTRL_PIN(2, "SPI0_MOSI_IO_0"), 380 PINCTRL_PIN(3, "SPI0_MISO_IO_1"), 381 PINCTRL_PIN(4, "SPI0_TPM_CSB"), 382 PINCTRL_PIN(5, "SPI0_FLASH_0_CSB"), 383 PINCTRL_PIN(6, "SPI0_FLASH_1_CSB"), 384 PINCTRL_PIN(7, "SPI0_CLK"), 385 PINCTRL_PIN(8, "ESPI_IO_0"), 386 PINCTRL_PIN(9, "ESPI_IO_1"), 387 PINCTRL_PIN(10, "ESPI_IO_2"), 388 PINCTRL_PIN(11, "ESPI_IO_3"), 389 PINCTRL_PIN(12, "ESPI_CS0B"), 390 PINCTRL_PIN(13, "ESPI_CLK"), 391 PINCTRL_PIN(14, "ESPI_RESETB"), 392 PINCTRL_PIN(15, "ESPI_CS1B"), 393 PINCTRL_PIN(16, "ESPI_CS2B"), 394 PINCTRL_PIN(17, "ESPI_CS3B"), 395 PINCTRL_PIN(18, "ESPI_ALERT0B"), 396 PINCTRL_PIN(19, "ESPI_ALERT1B"), 397 PINCTRL_PIN(20, "ESPI_ALERT2B"), 398 PINCTRL_PIN(21, "ESPI_ALERT3B"), 399 PINCTRL_PIN(22, "GPPC_A_14"), 400 PINCTRL_PIN(23, "SPI0_CLK_LOOPBK"), 401 PINCTRL_PIN(24, "ESPI_CLK_LOOPBK"), 402 /* GPP_R */ 403 PINCTRL_PIN(25, "HDA_BCLK"), 404 PINCTRL_PIN(26, "HDA_SYNC"), 405 PINCTRL_PIN(27, "HDA_SDO"), 406 PINCTRL_PIN(28, "HDA_SDI_0"), 407 PINCTRL_PIN(29, "HDA_RSTB"), 408 PINCTRL_PIN(30, "HDA_SDI_1"), 409 PINCTRL_PIN(31, "GPP_R_6"), 410 PINCTRL_PIN(32, "GPP_R_7"), 411 PINCTRL_PIN(33, "GPP_R_8"), 412 PINCTRL_PIN(34, "PCIE_LNK_DOWN"), 413 PINCTRL_PIN(35, "ISH_UART0_RTSB"), 414 PINCTRL_PIN(36, "SX_EXIT_HOLDOFFB"), 415 PINCTRL_PIN(37, "CLKOUT_48"), 416 PINCTRL_PIN(38, "ISH_GP_7"), 417 PINCTRL_PIN(39, "ISH_GP_0"), 418 PINCTRL_PIN(40, "ISH_GP_1"), 419 PINCTRL_PIN(41, "ISH_GP_2"), 420 PINCTRL_PIN(42, "ISH_GP_3"), 421 PINCTRL_PIN(43, "ISH_GP_4"), 422 PINCTRL_PIN(44, "ISH_GP_5"), 423 /* GPP_B */ 424 PINCTRL_PIN(45, "GSPI0_CS1B"), 425 PINCTRL_PIN(46, "GSPI1_CS1B"), 426 PINCTRL_PIN(47, "VRALERTB"), 427 PINCTRL_PIN(48, "CPU_GP_2"), 428 PINCTRL_PIN(49, "CPU_GP_3"), 429 PINCTRL_PIN(50, "SRCCLKREQB_0"), 430 PINCTRL_PIN(51, "SRCCLKREQB_1"), 431 PINCTRL_PIN(52, "SRCCLKREQB_2"), 432 PINCTRL_PIN(53, "SRCCLKREQB_3"), 433 PINCTRL_PIN(54, "SRCCLKREQB_4"), 434 PINCTRL_PIN(55, "SRCCLKREQB_5"), 435 PINCTRL_PIN(56, "I2S_MCLK"), 436 PINCTRL_PIN(57, "SLP_S0B"), 437 PINCTRL_PIN(58, "PLTRSTB"), 438 PINCTRL_PIN(59, "SPKR"), 439 PINCTRL_PIN(60, "GSPI0_CS0B"), 440 PINCTRL_PIN(61, "GSPI0_CLK"), 441 PINCTRL_PIN(62, "GSPI0_MISO"), 442 PINCTRL_PIN(63, "GSPI0_MOSI"), 443 PINCTRL_PIN(64, "GSPI1_CS0B"), 444 PINCTRL_PIN(65, "GSPI1_CLK"), 445 PINCTRL_PIN(66, "GSPI1_MISO"), 446 PINCTRL_PIN(67, "GSPI1_MOSI"), 447 PINCTRL_PIN(68, "SML1ALERTB"), 448 PINCTRL_PIN(69, "GSPI0_CLK_LOOPBK"), 449 PINCTRL_PIN(70, "GSPI1_CLK_LOOPBK"), 450 /* vGPIO_0 */ 451 PINCTRL_PIN(71, "ESPI_USB_OCB_0"), 452 PINCTRL_PIN(72, "ESPI_USB_OCB_1"), 453 PINCTRL_PIN(73, "ESPI_USB_OCB_2"), 454 PINCTRL_PIN(74, "ESPI_USB_OCB_3"), 455 PINCTRL_PIN(75, "USB_CPU_OCB_0"), 456 PINCTRL_PIN(76, "USB_CPU_OCB_1"), 457 PINCTRL_PIN(77, "USB_CPU_OCB_2"), 458 PINCTRL_PIN(78, "USB_CPU_OCB_3"), 459 /* GPP_D */ 460 PINCTRL_PIN(79, "SPI1_CSB"), 461 PINCTRL_PIN(80, "SPI1_CLK"), 462 PINCTRL_PIN(81, "SPI1_MISO_IO_1"), 463 PINCTRL_PIN(82, "SPI1_MOSI_IO_0"), 464 PINCTRL_PIN(83, "SML1CLK"), 465 PINCTRL_PIN(84, "I2S2_SFRM"), 466 PINCTRL_PIN(85, "I2S2_TXD"), 467 PINCTRL_PIN(86, "I2S2_RXD"), 468 PINCTRL_PIN(87, "I2S2_SCLK"), 469 PINCTRL_PIN(88, "SML0CLK"), 470 PINCTRL_PIN(89, "SML0DATA"), 471 PINCTRL_PIN(90, "GPP_D_11"), 472 PINCTRL_PIN(91, "ISH_UART0_CTSB"), 473 PINCTRL_PIN(92, "SPI1_IO_2"), 474 PINCTRL_PIN(93, "SPI1_IO_3"), 475 PINCTRL_PIN(94, "SML1DATA"), 476 PINCTRL_PIN(95, "GSPI3_CS0B"), 477 PINCTRL_PIN(96, "GSPI3_CLK"), 478 PINCTRL_PIN(97, "GSPI3_MISO"), 479 PINCTRL_PIN(98, "GSPI3_MOSI"), 480 PINCTRL_PIN(99, "UART3_RXD"), 481 PINCTRL_PIN(100, "UART3_TXD"), 482 PINCTRL_PIN(101, "UART3_RTSB"), 483 PINCTRL_PIN(102, "UART3_CTSB"), 484 PINCTRL_PIN(103, "SPI1_CLK_LOOPBK"), 485 PINCTRL_PIN(104, "GSPI3_CLK_LOOPBK"), 486 /* GPP_C */ 487 PINCTRL_PIN(105, "SMBCLK"), 488 PINCTRL_PIN(106, "SMBDATA"), 489 PINCTRL_PIN(107, "SMBALERTB"), 490 PINCTRL_PIN(108, "ISH_UART0_RXD"), 491 PINCTRL_PIN(109, "ISH_UART0_TXD"), 492 PINCTRL_PIN(110, "SML0ALERTB"), 493 PINCTRL_PIN(111, "ISH_I2C2_SDA"), 494 PINCTRL_PIN(112, "ISH_I2C2_SCL"), 495 PINCTRL_PIN(113, "UART0_RXD"), 496 PINCTRL_PIN(114, "UART0_TXD"), 497 PINCTRL_PIN(115, "UART0_RTSB"), 498 PINCTRL_PIN(116, "UART0_CTSB"), 499 PINCTRL_PIN(117, "UART1_RXD"), 500 PINCTRL_PIN(118, "UART1_TXD"), 501 PINCTRL_PIN(119, "UART1_RTSB"), 502 PINCTRL_PIN(120, "UART1_CTSB"), 503 PINCTRL_PIN(121, "I2C0_SDA"), 504 PINCTRL_PIN(122, "I2C0_SCL"), 505 PINCTRL_PIN(123, "I2C1_SDA"), 506 PINCTRL_PIN(124, "I2C1_SCL"), 507 PINCTRL_PIN(125, "UART2_RXD"), 508 PINCTRL_PIN(126, "UART2_TXD"), 509 PINCTRL_PIN(127, "UART2_RTSB"), 510 PINCTRL_PIN(128, "UART2_CTSB"), 511 /* GPP_S */ 512 PINCTRL_PIN(129, "SNDW1_CLK"), 513 PINCTRL_PIN(130, "SNDW1_DATA"), 514 PINCTRL_PIN(131, "SNDW2_CLK"), 515 PINCTRL_PIN(132, "SNDW2_DATA"), 516 PINCTRL_PIN(133, "SNDW3_CLK"), 517 PINCTRL_PIN(134, "SNDW3_DATA"), 518 PINCTRL_PIN(135, "SNDW4_CLK"), 519 PINCTRL_PIN(136, "SNDW4_DATA"), 520 /* GPP_G */ 521 PINCTRL_PIN(137, "DDPA_CTRLCLK"), 522 PINCTRL_PIN(138, "DDPA_CTRLDATA"), 523 PINCTRL_PIN(139, "DNX_FORCE_RELOAD"), 524 PINCTRL_PIN(140, "GMII_MDC_0"), 525 PINCTRL_PIN(141, "GMII_MDIO_0"), 526 PINCTRL_PIN(142, "SLP_DRAMB"), 527 PINCTRL_PIN(143, "GPPC_G_6"), 528 PINCTRL_PIN(144, "GPPC_G_7"), 529 PINCTRL_PIN(145, "ISH_SPI_CSB"), 530 PINCTRL_PIN(146, "ISH_SPI_CLK"), 531 PINCTRL_PIN(147, "ISH_SPI_MISO"), 532 PINCTRL_PIN(148, "ISH_SPI_MOSI"), 533 PINCTRL_PIN(149, "DDP1_CTRLCLK"), 534 PINCTRL_PIN(150, "DDP1_CTRLDATA"), 535 PINCTRL_PIN(151, "DDP2_CTRLCLK"), 536 PINCTRL_PIN(152, "DDP2_CTRLDATA"), 537 PINCTRL_PIN(153, "GSPI2_CLK_LOOPBK"), 538 /* vGPIO */ 539 PINCTRL_PIN(154, "CNV_BTEN"), 540 PINCTRL_PIN(155, "CNV_BT_HOST_WAKEB"), 541 PINCTRL_PIN(156, "CNV_BT_IF_SELECT"), 542 PINCTRL_PIN(157, "vCNV_BT_UART_TXD"), 543 PINCTRL_PIN(158, "vCNV_BT_UART_RXD"), 544 PINCTRL_PIN(159, "vCNV_BT_UART_CTS_B"), 545 PINCTRL_PIN(160, "vCNV_BT_UART_RTS_B"), 546 PINCTRL_PIN(161, "vCNV_MFUART1_TXD"), 547 PINCTRL_PIN(162, "vCNV_MFUART1_RXD"), 548 PINCTRL_PIN(163, "vCNV_MFUART1_CTS_B"), 549 PINCTRL_PIN(164, "vCNV_MFUART1_RTS_B"), 550 PINCTRL_PIN(165, "vUART0_TXD"), 551 PINCTRL_PIN(166, "vUART0_RXD"), 552 PINCTRL_PIN(167, "vUART0_CTS_B"), 553 PINCTRL_PIN(168, "vUART0_RTS_B"), 554 PINCTRL_PIN(169, "vISH_UART0_TXD"), 555 PINCTRL_PIN(170, "vISH_UART0_RXD"), 556 PINCTRL_PIN(171, "vISH_UART0_CTS_B"), 557 PINCTRL_PIN(172, "vISH_UART0_RTS_B"), 558 PINCTRL_PIN(173, "vCNV_BT_I2S_BCLK"), 559 PINCTRL_PIN(174, "vCNV_BT_I2S_WS_SYNC"), 560 PINCTRL_PIN(175, "vCNV_BT_I2S_SDO"), 561 PINCTRL_PIN(176, "vCNV_BT_I2S_SDI"), 562 PINCTRL_PIN(177, "vI2S2_SCLK"), 563 PINCTRL_PIN(178, "vI2S2_SFRM"), 564 PINCTRL_PIN(179, "vI2S2_TXD"), 565 PINCTRL_PIN(180, "vI2S2_RXD"), 566 /* GPP_E */ 567 PINCTRL_PIN(181, "SATAXPCIE_0"), 568 PINCTRL_PIN(182, "SATAXPCIE_1"), 569 PINCTRL_PIN(183, "SATAXPCIE_2"), 570 PINCTRL_PIN(184, "CPU_GP_0"), 571 PINCTRL_PIN(185, "SATA_DEVSLP_0"), 572 PINCTRL_PIN(186, "SATA_DEVSLP_1"), 573 PINCTRL_PIN(187, "SATA_DEVSLP_2"), 574 PINCTRL_PIN(188, "CPU_GP_1"), 575 PINCTRL_PIN(189, "SATA_LEDB"), 576 PINCTRL_PIN(190, "USB2_OCB_0"), 577 PINCTRL_PIN(191, "USB2_OCB_1"), 578 PINCTRL_PIN(192, "USB2_OCB_2"), 579 PINCTRL_PIN(193, "USB2_OCB_3"), 580 /* GPP_F */ 581 PINCTRL_PIN(194, "SATAXPCIE_3"), 582 PINCTRL_PIN(195, "SATAXPCIE_4"), 583 PINCTRL_PIN(196, "SATAXPCIE_5"), 584 PINCTRL_PIN(197, "SATAXPCIE_6"), 585 PINCTRL_PIN(198, "SATAXPCIE_7"), 586 PINCTRL_PIN(199, "SATA_DEVSLP_3"), 587 PINCTRL_PIN(200, "SATA_DEVSLP_4"), 588 PINCTRL_PIN(201, "SATA_DEVSLP_5"), 589 PINCTRL_PIN(202, "SATA_DEVSLP_6"), 590 PINCTRL_PIN(203, "SATA_DEVSLP_7"), 591 PINCTRL_PIN(204, "SATA_SCLOCK"), 592 PINCTRL_PIN(205, "SATA_SLOAD"), 593 PINCTRL_PIN(206, "SATA_SDATAOUT1"), 594 PINCTRL_PIN(207, "SATA_SDATAOUT0"), 595 PINCTRL_PIN(208, "PS_ONB"), 596 PINCTRL_PIN(209, "M2_SKT2_CFG_0"), 597 PINCTRL_PIN(210, "M2_SKT2_CFG_1"), 598 PINCTRL_PIN(211, "M2_SKT2_CFG_2"), 599 PINCTRL_PIN(212, "M2_SKT2_CFG_3"), 600 PINCTRL_PIN(213, "L_VDDEN"), 601 PINCTRL_PIN(214, "L_BKLTEN"), 602 PINCTRL_PIN(215, "L_BKLTCTL"), 603 PINCTRL_PIN(216, "VNN_CTRL"), 604 PINCTRL_PIN(217, "GPP_F_23"), 605 /* GPP_H */ 606 PINCTRL_PIN(218, "SRCCLKREQB_6"), 607 PINCTRL_PIN(219, "SRCCLKREQB_7"), 608 PINCTRL_PIN(220, "SRCCLKREQB_8"), 609 PINCTRL_PIN(221, "SRCCLKREQB_9"), 610 PINCTRL_PIN(222, "SRCCLKREQB_10"), 611 PINCTRL_PIN(223, "SRCCLKREQB_11"), 612 PINCTRL_PIN(224, "SRCCLKREQB_12"), 613 PINCTRL_PIN(225, "SRCCLKREQB_13"), 614 PINCTRL_PIN(226, "SRCCLKREQB_14"), 615 PINCTRL_PIN(227, "SRCCLKREQB_15"), 616 PINCTRL_PIN(228, "SML2CLK"), 617 PINCTRL_PIN(229, "SML2DATA"), 618 PINCTRL_PIN(230, "SML2ALERTB"), 619 PINCTRL_PIN(231, "SML3CLK"), 620 PINCTRL_PIN(232, "SML3DATA"), 621 PINCTRL_PIN(233, "SML3ALERTB"), 622 PINCTRL_PIN(234, "SML4CLK"), 623 PINCTRL_PIN(235, "SML4DATA"), 624 PINCTRL_PIN(236, "SML4ALERTB"), 625 PINCTRL_PIN(237, "ISH_I2C0_SDA"), 626 PINCTRL_PIN(238, "ISH_I2C0_SCL"), 627 PINCTRL_PIN(239, "ISH_I2C1_SDA"), 628 PINCTRL_PIN(240, "ISH_I2C1_SCL"), 629 PINCTRL_PIN(241, "TIME_SYNC_0"), 630 /* GPP_J */ 631 PINCTRL_PIN(242, "CNV_PA_BLANKING"), 632 PINCTRL_PIN(243, "CPU_C10_GATEB"), 633 PINCTRL_PIN(244, "CNV_BRI_DT"), 634 PINCTRL_PIN(245, "CNV_BRI_RSP"), 635 PINCTRL_PIN(246, "CNV_RGI_DT"), 636 PINCTRL_PIN(247, "CNV_RGI_RSP"), 637 PINCTRL_PIN(248, "CNV_MFUART2_RXD"), 638 PINCTRL_PIN(249, "CNV_MFUART2_TXD"), 639 PINCTRL_PIN(250, "GPP_J_8"), 640 PINCTRL_PIN(251, "GPP_J_9"), 641 /* GPP_K */ 642 PINCTRL_PIN(252, "GSXDOUT"), 643 PINCTRL_PIN(253, "GSXSLOAD"), 644 PINCTRL_PIN(254, "GSXDIN"), 645 PINCTRL_PIN(255, "GSXSRESETB"), 646 PINCTRL_PIN(256, "GSXCLK"), 647 PINCTRL_PIN(257, "ADR_COMPLETE"), 648 PINCTRL_PIN(258, "DDSP_HPD_A"), 649 PINCTRL_PIN(259, "DDSP_HPD_B"), 650 PINCTRL_PIN(260, "CORE_VID_0"), 651 PINCTRL_PIN(261, "CORE_VID_1"), 652 PINCTRL_PIN(262, "DDSP_HPD_C"), 653 PINCTRL_PIN(263, "GPP_K_11"), 654 PINCTRL_PIN(264, "SYS_PWROK"), 655 PINCTRL_PIN(265, "SYS_RESETB"), 656 PINCTRL_PIN(266, "MLK_RSTB"), 657 /* GPP_I */ 658 PINCTRL_PIN(267, "PMCALERTB"), 659 PINCTRL_PIN(268, "DDSP_HPD_1"), 660 PINCTRL_PIN(269, "DDSP_HPD_2"), 661 PINCTRL_PIN(270, "DDSP_HPD_3"), 662 PINCTRL_PIN(271, "DDSP_HPD_4"), 663 PINCTRL_PIN(272, "DDPB_CTRLCLK"), 664 PINCTRL_PIN(273, "DDPB_CTRLDATA"), 665 PINCTRL_PIN(274, "DDPC_CTRLCLK"), 666 PINCTRL_PIN(275, "DDPC_CTRLDATA"), 667 PINCTRL_PIN(276, "FUSA_DIAGTEST_EN"), 668 PINCTRL_PIN(277, "FUSA_DIAGTEST_MODE"), 669 PINCTRL_PIN(278, "USB2_OCB_4"), 670 PINCTRL_PIN(279, "USB2_OCB_5"), 671 PINCTRL_PIN(280, "USB2_OCB_6"), 672 PINCTRL_PIN(281, "USB2_OCB_7"), 673 /* JTAG */ 674 PINCTRL_PIN(282, "JTAG_TDO"), 675 PINCTRL_PIN(283, "JTAGX"), 676 PINCTRL_PIN(284, "PRDYB"), 677 PINCTRL_PIN(285, "PREQB"), 678 PINCTRL_PIN(286, "JTAG_TDI"), 679 PINCTRL_PIN(287, "JTAG_TMS"), 680 PINCTRL_PIN(288, "JTAG_TCK"), 681 PINCTRL_PIN(289, "DBG_PMODE"), 682 PINCTRL_PIN(290, "CPU_TRSTB"), 683 }; 684 685 static const struct intel_padgroup tglh_community0_gpps[] = { 686 INTEL_GPP(0, 0, 24, 0), /* GPP_A */ 687 INTEL_GPP(1, 25, 44, 32), /* GPP_R */ 688 INTEL_GPP(2, 45, 70, 64), /* GPP_B */ 689 INTEL_GPP(3, 71, 78, 96), /* vGPIO_0 */ 690 }; 691 692 static const struct intel_padgroup tglh_community1_gpps[] = { 693 INTEL_GPP(0, 79, 104, 128), /* GPP_D */ 694 INTEL_GPP(1, 105, 128, 160), /* GPP_C */ 695 INTEL_GPP(2, 129, 136, 192), /* GPP_S */ 696 INTEL_GPP(3, 137, 153, 224), /* GPP_G */ 697 INTEL_GPP(4, 154, 180, 256), /* vGPIO */ 698 }; 699 700 static const struct intel_padgroup tglh_community3_gpps[] = { 701 INTEL_GPP(0, 181, 193, 288), /* GPP_E */ 702 INTEL_GPP(1, 194, 217, 320), /* GPP_F */ 703 }; 704 705 static const struct intel_padgroup tglh_community4_gpps[] = { 706 INTEL_GPP(0, 218, 241, 352), /* GPP_H */ 707 INTEL_GPP(1, 242, 251, 384), /* GPP_J */ 708 INTEL_GPP(2, 252, 266, 416), /* GPP_K */ 709 }; 710 711 static const struct intel_padgroup tglh_community5_gpps[] = { 712 INTEL_GPP(0, 267, 281, 448), /* GPP_I */ 713 INTEL_GPP(1, 282, 290, INTEL_GPIO_BASE_NOMAP), /* JTAG */ 714 }; 715 716 static const struct intel_community tglh_communities[] = { 717 TGL_H_COMMUNITY(0, 0, 78, tglh_community0_gpps), 718 TGL_H_COMMUNITY(1, 79, 180, tglh_community1_gpps), 719 TGL_H_COMMUNITY(2, 181, 217, tglh_community3_gpps), 720 TGL_H_COMMUNITY(3, 218, 266, tglh_community4_gpps), 721 TGL_H_COMMUNITY(4, 267, 290, tglh_community5_gpps), 722 }; 723 724 static const struct intel_pinctrl_soc_data tglh_soc_data = { 725 .pins = tglh_pins, 726 .npins = ARRAY_SIZE(tglh_pins), 727 .communities = tglh_communities, 728 .ncommunities = ARRAY_SIZE(tglh_communities), 729 }; 730 731 static const struct acpi_device_id tgl_pinctrl_acpi_match[] = { 732 { "INT34C5", (kernel_ulong_t)&tgllp_soc_data }, 733 { "INT34C6", (kernel_ulong_t)&tglh_soc_data }, 734 { "INTC1055", (kernel_ulong_t)&tgllp_soc_data }, 735 { } 736 }; 737 MODULE_DEVICE_TABLE(acpi, tgl_pinctrl_acpi_match); 738 739 static struct platform_driver tgl_pinctrl_driver = { 740 .probe = intel_pinctrl_probe_by_hid, 741 .driver = { 742 .name = "tigerlake-pinctrl", 743 .acpi_match_table = tgl_pinctrl_acpi_match, 744 .pm = pm_sleep_ptr(&intel_pinctrl_pm_ops), 745 }, 746 }; 747 module_platform_driver(tgl_pinctrl_driver); 748 749 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 750 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 751 MODULE_DESCRIPTION("Intel Tiger Lake PCH pinctrl/GPIO driver"); 752 MODULE_LICENSE("GPL v2"); 753 MODULE_IMPORT_NS("PINCTRL_INTEL"); 754