1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * set_id_regs - Test for setting ID register from usersapce.
4 *
5 * Copyright (c) 2023 Google LLC.
6 *
7 *
8 * Test that KVM supports setting ID registers from userspace and handles the
9 * feature set correctly.
10 */
11
12 #include <stdint.h>
13 #include "kvm_util.h"
14 #include "processor.h"
15 #include "test_util.h"
16 #include <linux/bitfield.h>
17
18 enum ftr_type {
19 FTR_EXACT, /* Use a predefined safe value */
20 FTR_LOWER_SAFE, /* Smaller value is safe */
21 FTR_HIGHER_SAFE, /* Bigger value is safe */
22 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */
23 FTR_END, /* Mark the last ftr bits */
24 };
25
26 #define FTR_SIGNED true /* Value should be treated as signed */
27 #define FTR_UNSIGNED false /* Value should be treated as unsigned */
28
29 struct reg_ftr_bits {
30 char *name;
31 bool sign;
32 enum ftr_type type;
33 uint8_t shift;
34 uint64_t mask;
35 /*
36 * For FTR_EXACT, safe_val is used as the exact safe value.
37 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value.
38 */
39 int64_t safe_val;
40 };
41
42 struct test_feature_reg {
43 uint32_t reg;
44 const struct reg_ftr_bits *ftr_bits;
45 };
46
47 #define __REG_FTR_BITS(NAME, SIGNED, TYPE, SHIFT, MASK, SAFE_VAL) \
48 { \
49 .name = #NAME, \
50 .sign = SIGNED, \
51 .type = TYPE, \
52 .shift = SHIFT, \
53 .mask = MASK, \
54 .safe_val = SAFE_VAL, \
55 }
56
57 #define REG_FTR_BITS(type, reg, field, safe_val) \
58 __REG_FTR_BITS(reg##_##field, FTR_UNSIGNED, type, reg##_##field##_SHIFT, \
59 reg##_##field##_MASK, safe_val)
60
61 #define S_REG_FTR_BITS(type, reg, field, safe_val) \
62 __REG_FTR_BITS(reg##_##field, FTR_SIGNED, type, reg##_##field##_SHIFT, \
63 reg##_##field##_MASK, safe_val)
64
65 #define REG_FTR_END \
66 { \
67 .type = FTR_END, \
68 }
69
70 static const struct reg_ftr_bits ftr_id_aa64dfr0_el1[] = {
71 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DoubleLock, 0),
72 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, WRPs, 0),
73 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, PMUVer, 0),
74 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64DFR0_EL1, DebugVer, ID_AA64DFR0_EL1_DebugVer_IMP),
75 REG_FTR_END,
76 };
77
78 static const struct reg_ftr_bits ftr_id_dfr0_el1[] = {
79 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, PerfMon, ID_DFR0_EL1_PerfMon_PMUv3),
80 REG_FTR_BITS(FTR_LOWER_SAFE, ID_DFR0_EL1, CopDbg, ID_DFR0_EL1_CopDbg_Armv8),
81 REG_FTR_END,
82 };
83
84 static const struct reg_ftr_bits ftr_id_aa64isar0_el1[] = {
85 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RNDR, 0),
86 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TLB, 0),
87 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TS, 0),
88 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, FHM, 0),
89 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, DP, 0),
90 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM4, 0),
91 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SM3, 0),
92 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA3, 0),
93 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, RDM, 0),
94 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, TME, 0),
95 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, ATOMIC, 0),
96 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, CRC32, 0),
97 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA2, 0),
98 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, SHA1, 0),
99 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR0_EL1, AES, 0),
100 REG_FTR_END,
101 };
102
103 static const struct reg_ftr_bits ftr_id_aa64isar1_el1[] = {
104 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LS64, 0),
105 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, XS, 0),
106 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, I8MM, 0),
107 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DGH, 0),
108 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, BF16, 0),
109 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SPECRES, 0),
110 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, SB, 0),
111 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FRINTTS, 0),
112 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, LRCPC, 0),
113 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, FCMA, 0),
114 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, JSCVT, 0),
115 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR1_EL1, DPB, 0),
116 REG_FTR_END,
117 };
118
119 static const struct reg_ftr_bits ftr_id_aa64isar2_el1[] = {
120 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, BC, 0),
121 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, RPRES, 0),
122 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR2_EL1, WFxT, 0),
123 REG_FTR_END,
124 };
125
126 static const struct reg_ftr_bits ftr_id_aa64isar3_el1[] = {
127 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, FPRCVT, 0),
128 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, LSFE, 0),
129 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ISAR3_EL1, FAMINMAX, 0),
130 REG_FTR_END,
131 };
132
133 static const struct reg_ftr_bits ftr_id_aa64pfr0_el1[] = {
134 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV3, 0),
135 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, CSV2, 0),
136 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, DIT, 0),
137 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, SEL2, 0),
138 REG_FTR_BITS(FTR_EXACT, ID_AA64PFR0_EL1, GIC, 0),
139 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL3, 1),
140 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL2, 1),
141 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL1, 1),
142 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR0_EL1, EL0, 1),
143 REG_FTR_END,
144 };
145
146 static const struct reg_ftr_bits ftr_id_aa64pfr1_el1[] = {
147 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, DF2, 0),
148 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, CSV2_frac, 0),
149 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, SSBS, ID_AA64PFR1_EL1_SSBS_NI),
150 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64PFR1_EL1, BT, 0),
151 REG_FTR_END,
152 };
153
154 static const struct reg_ftr_bits ftr_id_aa64mmfr0_el1[] = {
155 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, ECV, 0),
156 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, EXS, 0),
157 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN4_2, 1),
158 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN64_2, 1),
159 REG_FTR_BITS(FTR_EXACT, ID_AA64MMFR0_EL1, TGRAN16_2, 1),
160 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN4, 0),
161 S_REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN64, 0),
162 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, TGRAN16, 0),
163 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGENDEL0, 0),
164 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, SNSMEM, 0),
165 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, BIGEND, 0),
166 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR0_EL1, PARANGE, 0),
167 REG_FTR_END,
168 };
169
170 static const struct reg_ftr_bits ftr_id_aa64mmfr1_el1[] = {
171 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TIDCP1, 0),
172 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, AFP, 0),
173 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HCX, 0),
174 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, ETS, 0),
175 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, TWED, 0),
176 REG_FTR_BITS(FTR_HIGHER_SAFE, ID_AA64MMFR1_EL1, SpecSEI, 0),
177 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, PAN, 0),
178 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, LO, 0),
179 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HPDS, 0),
180 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR1_EL1, HAFDBS, 0),
181 REG_FTR_END,
182 };
183
184 static const struct reg_ftr_bits ftr_id_aa64mmfr2_el1[] = {
185 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, E0PD, 0),
186 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, BBM, 0),
187 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, TTL, 0),
188 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, AT, 0),
189 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, ST, 0),
190 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, VARange, 0),
191 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, IESB, 0),
192 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, LSM, 0),
193 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, UAO, 0),
194 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR2_EL1, CnP, 0),
195 REG_FTR_END,
196 };
197
198 static const struct reg_ftr_bits ftr_id_aa64mmfr3_el1[] = {
199 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, S1POE, 0),
200 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, S1PIE, 0),
201 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, SCTLRX, 0),
202 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64MMFR3_EL1, TCRX, 0),
203 REG_FTR_END,
204 };
205
206 static const struct reg_ftr_bits ftr_id_aa64zfr0_el1[] = {
207 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F64MM, 0),
208 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, F32MM, 0),
209 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, I8MM, 0),
210 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SM4, 0),
211 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SHA3, 0),
212 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BF16, 0),
213 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, BitPerm, 0),
214 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, AES, 0),
215 REG_FTR_BITS(FTR_LOWER_SAFE, ID_AA64ZFR0_EL1, SVEver, 0),
216 REG_FTR_END,
217 };
218
219 #define TEST_REG(id, table) \
220 { \
221 .reg = id, \
222 .ftr_bits = &((table)[0]), \
223 }
224
225 static struct test_feature_reg test_regs[] = {
226 TEST_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0_el1),
227 TEST_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0_el1),
228 TEST_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0_el1),
229 TEST_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1_el1),
230 TEST_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2_el1),
231 TEST_REG(SYS_ID_AA64ISAR3_EL1, ftr_id_aa64isar3_el1),
232 TEST_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0_el1),
233 TEST_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1_el1),
234 TEST_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0_el1),
235 TEST_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1_el1),
236 TEST_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2_el1),
237 TEST_REG(SYS_ID_AA64MMFR3_EL1, ftr_id_aa64mmfr3_el1),
238 TEST_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0_el1),
239 };
240
241 #define GUEST_REG_SYNC(id) GUEST_SYNC_ARGS(0, id, read_sysreg_s(id), 0, 0);
242
guest_code(void)243 static void guest_code(void)
244 {
245 GUEST_REG_SYNC(SYS_ID_AA64DFR0_EL1);
246 GUEST_REG_SYNC(SYS_ID_DFR0_EL1);
247 GUEST_REG_SYNC(SYS_ID_AA64ISAR0_EL1);
248 GUEST_REG_SYNC(SYS_ID_AA64ISAR1_EL1);
249 GUEST_REG_SYNC(SYS_ID_AA64ISAR2_EL1);
250 GUEST_REG_SYNC(SYS_ID_AA64ISAR3_EL1);
251 GUEST_REG_SYNC(SYS_ID_AA64PFR0_EL1);
252 GUEST_REG_SYNC(SYS_ID_AA64PFR1_EL1);
253 GUEST_REG_SYNC(SYS_ID_AA64MMFR0_EL1);
254 GUEST_REG_SYNC(SYS_ID_AA64MMFR1_EL1);
255 GUEST_REG_SYNC(SYS_ID_AA64MMFR2_EL1);
256 GUEST_REG_SYNC(SYS_ID_AA64MMFR3_EL1);
257 GUEST_REG_SYNC(SYS_ID_AA64ZFR0_EL1);
258 GUEST_REG_SYNC(SYS_MPIDR_EL1);
259 GUEST_REG_SYNC(SYS_CLIDR_EL1);
260 GUEST_REG_SYNC(SYS_CTR_EL0);
261 GUEST_REG_SYNC(SYS_MIDR_EL1);
262 GUEST_REG_SYNC(SYS_REVIDR_EL1);
263 GUEST_REG_SYNC(SYS_AIDR_EL1);
264
265 GUEST_DONE();
266 }
267
268 /* Return a safe value to a given ftr_bits an ftr value */
get_safe_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)269 uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
270 {
271 uint64_t ftr_max = ftr_bits->mask >> ftr_bits->shift;
272
273 TEST_ASSERT(ftr_max > 1, "This test doesn't support single bit features");
274
275 if (ftr_bits->sign == FTR_UNSIGNED) {
276 switch (ftr_bits->type) {
277 case FTR_EXACT:
278 ftr = ftr_bits->safe_val;
279 break;
280 case FTR_LOWER_SAFE:
281 if (ftr > ftr_bits->safe_val)
282 ftr--;
283 break;
284 case FTR_HIGHER_SAFE:
285 if (ftr < ftr_max)
286 ftr++;
287 break;
288 case FTR_HIGHER_OR_ZERO_SAFE:
289 if (ftr == ftr_max)
290 ftr = 0;
291 else if (ftr != 0)
292 ftr++;
293 break;
294 default:
295 break;
296 }
297 } else if (ftr != ftr_max) {
298 switch (ftr_bits->type) {
299 case FTR_EXACT:
300 ftr = ftr_bits->safe_val;
301 break;
302 case FTR_LOWER_SAFE:
303 if (ftr > ftr_bits->safe_val)
304 ftr--;
305 break;
306 case FTR_HIGHER_SAFE:
307 if (ftr < ftr_max - 1)
308 ftr++;
309 break;
310 case FTR_HIGHER_OR_ZERO_SAFE:
311 if (ftr != 0 && ftr != ftr_max - 1)
312 ftr++;
313 break;
314 default:
315 break;
316 }
317 }
318
319 return ftr;
320 }
321
322 /* Return an invalid value to a given ftr_bits an ftr value */
get_invalid_value(const struct reg_ftr_bits * ftr_bits,uint64_t ftr)323 uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
324 {
325 uint64_t ftr_max = ftr_bits->mask >> ftr_bits->shift;
326
327 TEST_ASSERT(ftr_max > 1, "This test doesn't support single bit features");
328
329 if (ftr_bits->sign == FTR_UNSIGNED) {
330 switch (ftr_bits->type) {
331 case FTR_EXACT:
332 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
333 break;
334 case FTR_LOWER_SAFE:
335 ftr++;
336 break;
337 case FTR_HIGHER_SAFE:
338 ftr--;
339 break;
340 case FTR_HIGHER_OR_ZERO_SAFE:
341 if (ftr == 0)
342 ftr = ftr_max;
343 else
344 ftr--;
345 break;
346 default:
347 break;
348 }
349 } else if (ftr != ftr_max) {
350 switch (ftr_bits->type) {
351 case FTR_EXACT:
352 ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
353 break;
354 case FTR_LOWER_SAFE:
355 ftr++;
356 break;
357 case FTR_HIGHER_SAFE:
358 ftr--;
359 break;
360 case FTR_HIGHER_OR_ZERO_SAFE:
361 if (ftr == 0)
362 ftr = ftr_max - 1;
363 else
364 ftr--;
365 break;
366 default:
367 break;
368 }
369 } else {
370 ftr = 0;
371 }
372
373 return ftr;
374 }
375
test_reg_set_success(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)376 static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
377 const struct reg_ftr_bits *ftr_bits)
378 {
379 uint8_t shift = ftr_bits->shift;
380 uint64_t mask = ftr_bits->mask;
381 uint64_t val, new_val, ftr;
382
383 val = vcpu_get_reg(vcpu, reg);
384 ftr = (val & mask) >> shift;
385
386 ftr = get_safe_value(ftr_bits, ftr);
387
388 ftr <<= shift;
389 val &= ~mask;
390 val |= ftr;
391
392 vcpu_set_reg(vcpu, reg, val);
393 new_val = vcpu_get_reg(vcpu, reg);
394 TEST_ASSERT_EQ(new_val, val);
395
396 return new_val;
397 }
398
test_reg_set_fail(struct kvm_vcpu * vcpu,uint64_t reg,const struct reg_ftr_bits * ftr_bits)399 static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
400 const struct reg_ftr_bits *ftr_bits)
401 {
402 uint8_t shift = ftr_bits->shift;
403 uint64_t mask = ftr_bits->mask;
404 uint64_t val, old_val, ftr;
405 int r;
406
407 val = vcpu_get_reg(vcpu, reg);
408 ftr = (val & mask) >> shift;
409
410 ftr = get_invalid_value(ftr_bits, ftr);
411
412 old_val = val;
413 ftr <<= shift;
414 val &= ~mask;
415 val |= ftr;
416
417 r = __vcpu_set_reg(vcpu, reg, val);
418 TEST_ASSERT(r < 0 && errno == EINVAL,
419 "Unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
420
421 val = vcpu_get_reg(vcpu, reg);
422 TEST_ASSERT_EQ(val, old_val);
423 }
424
425 static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE];
426
427 #define encoding_to_range_idx(encoding) \
428 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding), \
429 sys_reg_CRn(encoding), sys_reg_CRm(encoding), \
430 sys_reg_Op2(encoding))
431
432
test_vm_ftr_id_regs(struct kvm_vcpu * vcpu,bool aarch64_only)433 static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only)
434 {
435 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
436 struct reg_mask_range range = {
437 .addr = (__u64)masks,
438 };
439 int ret;
440
441 /* KVM should return error when reserved field is not zero */
442 range.reserved[0] = 1;
443 ret = __vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
444 TEST_ASSERT(ret, "KVM doesn't check invalid parameters.");
445
446 /* Get writable masks for feature ID registers */
447 memset(range.reserved, 0, sizeof(range.reserved));
448 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
449
450 for (int i = 0; i < ARRAY_SIZE(test_regs); i++) {
451 const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits;
452 uint32_t reg_id = test_regs[i].reg;
453 uint64_t reg = KVM_ARM64_SYS_REG(reg_id);
454 int idx;
455
456 /* Get the index to masks array for the idreg */
457 idx = encoding_to_range_idx(reg_id);
458
459 for (int j = 0; ftr_bits[j].type != FTR_END; j++) {
460 /* Skip aarch32 reg on aarch64 only system, since they are RAZ/WI. */
461 if (aarch64_only && sys_reg_CRm(reg_id) < 4) {
462 ksft_test_result_skip("%s on AARCH64 only system\n",
463 ftr_bits[j].name);
464 continue;
465 }
466
467 /* Make sure the feature field is writable */
468 TEST_ASSERT_EQ(masks[idx] & ftr_bits[j].mask, ftr_bits[j].mask);
469
470 test_reg_set_fail(vcpu, reg, &ftr_bits[j]);
471
472 test_reg_vals[idx] = test_reg_set_success(vcpu, reg,
473 &ftr_bits[j]);
474
475 ksft_test_result_pass("%s\n", ftr_bits[j].name);
476 }
477 }
478 }
479
480 #define MPAM_IDREG_TEST 6
test_user_set_mpam_reg(struct kvm_vcpu * vcpu)481 static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu)
482 {
483 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
484 struct reg_mask_range range = {
485 .addr = (__u64)masks,
486 };
487 uint64_t val;
488 int idx, err;
489
490 /*
491 * If ID_AA64PFR0.MPAM is _not_ officially modifiable and is zero,
492 * check that if it can be set to 1, (i.e. it is supported by the
493 * hardware), that it can't be set to other values.
494 */
495
496 /* Get writable masks for feature ID registers */
497 memset(range.reserved, 0, sizeof(range.reserved));
498 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
499
500 /* Writeable? Nothing to test! */
501 idx = encoding_to_range_idx(SYS_ID_AA64PFR0_EL1);
502 if ((masks[idx] & ID_AA64PFR0_EL1_MPAM_MASK) == ID_AA64PFR0_EL1_MPAM_MASK) {
503 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is officially writable, nothing to test\n");
504 return;
505 }
506
507 /* Get the id register value */
508 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
509
510 /* Try to set MPAM=0. This should always be possible. */
511 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
512 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 0);
513 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
514 if (err)
515 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM=0 was not accepted\n");
516 else
517 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=0 worked\n");
518
519 /* Try to set MPAM=1 */
520 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
521 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 1);
522 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
523 if (err)
524 ksft_test_result_skip("ID_AA64PFR0_EL1.MPAM is not writable, nothing to test\n");
525 else
526 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM=1 was writable\n");
527
528 /* Try to set MPAM=2 */
529 val &= ~ID_AA64PFR0_EL1_MPAM_MASK;
530 val |= FIELD_PREP(ID_AA64PFR0_EL1_MPAM_MASK, 2);
531 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), val);
532 if (err)
533 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM not arbitrarily modifiable\n");
534 else
535 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM value should not be ignored\n");
536
537 /* And again for ID_AA64PFR1_EL1.MPAM_frac */
538 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1);
539 if ((masks[idx] & ID_AA64PFR1_EL1_MPAM_frac_MASK) == ID_AA64PFR1_EL1_MPAM_frac_MASK) {
540 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is officially writable, nothing to test\n");
541 return;
542 }
543
544 /* Get the id register value */
545 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
546
547 /* Try to set MPAM_frac=0. This should always be possible. */
548 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
549 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 0);
550 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
551 if (err)
552 ksft_test_result_fail("ID_AA64PFR0_EL1.MPAM_frac=0 was not accepted\n");
553 else
554 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=0 worked\n");
555
556 /* Try to set MPAM_frac=1 */
557 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
558 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 1);
559 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
560 if (err)
561 ksft_test_result_skip("ID_AA64PFR1_EL1.MPAM_frac is not writable, nothing to test\n");
562 else
563 ksft_test_result_pass("ID_AA64PFR0_EL1.MPAM_frac=1 was writable\n");
564
565 /* Try to set MPAM_frac=2 */
566 val &= ~ID_AA64PFR1_EL1_MPAM_frac_MASK;
567 val |= FIELD_PREP(ID_AA64PFR1_EL1_MPAM_frac_MASK, 2);
568 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
569 if (err)
570 ksft_test_result_pass("ID_AA64PFR1_EL1.MPAM_frac not arbitrarily modifiable\n");
571 else
572 ksft_test_result_fail("ID_AA64PFR1_EL1.MPAM_frac value should not be ignored\n");
573 }
574
575 #define MTE_IDREG_TEST 1
test_user_set_mte_reg(struct kvm_vcpu * vcpu)576 static void test_user_set_mte_reg(struct kvm_vcpu *vcpu)
577 {
578 uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
579 struct reg_mask_range range = {
580 .addr = (__u64)masks,
581 };
582 uint64_t val;
583 uint64_t mte;
584 uint64_t mte_frac;
585 int idx, err;
586
587 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
588 mte = FIELD_GET(ID_AA64PFR1_EL1_MTE, val);
589 if (!mte) {
590 ksft_test_result_skip("MTE capability not supported, nothing to test\n");
591 return;
592 }
593
594 /* Get writable masks for feature ID registers */
595 memset(range.reserved, 0, sizeof(range.reserved));
596 vm_ioctl(vcpu->vm, KVM_ARM_GET_REG_WRITABLE_MASKS, &range);
597
598 idx = encoding_to_range_idx(SYS_ID_AA64PFR1_EL1);
599 if ((masks[idx] & ID_AA64PFR1_EL1_MTE_frac_MASK) == ID_AA64PFR1_EL1_MTE_frac_MASK) {
600 ksft_test_result_skip("ID_AA64PFR1_EL1.MTE_frac is officially writable, nothing to test\n");
601 return;
602 }
603
604 /*
605 * When MTE is supported but MTE_ASYMM is not (ID_AA64PFR1_EL1.MTE == 2)
606 * ID_AA64PFR1_EL1.MTE_frac == 0xF indicates MTE_ASYNC is unsupported
607 * and MTE_frac == 0 indicates it is supported.
608 *
609 * As MTE_frac was previously unconditionally read as 0, check
610 * that the set to 0 succeeds but does not change MTE_frac
611 * from unsupported (0xF) to supported (0).
612 *
613 */
614 mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val);
615 if (mte != ID_AA64PFR1_EL1_MTE_MTE2 ||
616 mte_frac != ID_AA64PFR1_EL1_MTE_frac_NI) {
617 ksft_test_result_skip("MTE_ASYNC or MTE_ASYMM are supported, nothing to test\n");
618 return;
619 }
620
621 /* Try to set MTE_frac=0. */
622 val &= ~ID_AA64PFR1_EL1_MTE_frac_MASK;
623 val |= FIELD_PREP(ID_AA64PFR1_EL1_MTE_frac_MASK, 0);
624 err = __vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1), val);
625 if (err) {
626 ksft_test_result_fail("ID_AA64PFR1_EL1.MTE_frac=0 was not accepted\n");
627 return;
628 }
629
630 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
631 mte_frac = FIELD_GET(ID_AA64PFR1_EL1_MTE_frac, val);
632 if (mte_frac == ID_AA64PFR1_EL1_MTE_frac_NI)
633 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac=0 accepted and still 0xF\n");
634 else
635 ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac no longer 0xF\n");
636 }
637
test_guest_reg_read(struct kvm_vcpu * vcpu)638 static void test_guest_reg_read(struct kvm_vcpu *vcpu)
639 {
640 bool done = false;
641 struct ucall uc;
642
643 while (!done) {
644 vcpu_run(vcpu);
645
646 switch (get_ucall(vcpu, &uc)) {
647 case UCALL_ABORT:
648 REPORT_GUEST_ASSERT(uc);
649 break;
650 case UCALL_SYNC:
651 /* Make sure the written values are seen by guest */
652 TEST_ASSERT_EQ(test_reg_vals[encoding_to_range_idx(uc.args[2])],
653 uc.args[3]);
654 break;
655 case UCALL_DONE:
656 done = true;
657 break;
658 default:
659 TEST_FAIL("Unexpected ucall: %lu", uc.cmd);
660 }
661 }
662 }
663
664 /* Politely lifted from arch/arm64/include/asm/cache.h */
665 /* Ctypen, bits[3(n - 1) + 2 : 3(n - 1)], for n = 1 to 7 */
666 #define CLIDR_CTYPE_SHIFT(level) (3 * (level - 1))
667 #define CLIDR_CTYPE_MASK(level) (7 << CLIDR_CTYPE_SHIFT(level))
668 #define CLIDR_CTYPE(clidr, level) \
669 (((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
670
test_clidr(struct kvm_vcpu * vcpu)671 static void test_clidr(struct kvm_vcpu *vcpu)
672 {
673 uint64_t clidr;
674 int level;
675
676 clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1));
677
678 /* find the first empty level in the cache hierarchy */
679 for (level = 1; level <= 7; level++) {
680 if (!CLIDR_CTYPE(clidr, level))
681 break;
682 }
683
684 /*
685 * If you have a mind-boggling 7 levels of cache, congratulations, you
686 * get to fix this.
687 */
688 TEST_ASSERT(level <= 7, "can't find an empty level in cache hierarchy");
689
690 /* stick in a unified cache level */
691 clidr |= BIT(2) << CLIDR_CTYPE_SHIFT(level);
692
693 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1), clidr);
694 test_reg_vals[encoding_to_range_idx(SYS_CLIDR_EL1)] = clidr;
695 }
696
test_ctr(struct kvm_vcpu * vcpu)697 static void test_ctr(struct kvm_vcpu *vcpu)
698 {
699 u64 ctr;
700
701 ctr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0));
702 ctr &= ~CTR_EL0_DIC_MASK;
703 if (ctr & CTR_EL0_IminLine_MASK)
704 ctr--;
705
706 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CTR_EL0), ctr);
707 test_reg_vals[encoding_to_range_idx(SYS_CTR_EL0)] = ctr;
708 }
709
test_id_reg(struct kvm_vcpu * vcpu,u32 id)710 static void test_id_reg(struct kvm_vcpu *vcpu, u32 id)
711 {
712 u64 val;
713
714 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(id));
715 val++;
716 vcpu_set_reg(vcpu, KVM_ARM64_SYS_REG(id), val);
717 test_reg_vals[encoding_to_range_idx(id)] = val;
718 }
719
test_vcpu_ftr_id_regs(struct kvm_vcpu * vcpu)720 static void test_vcpu_ftr_id_regs(struct kvm_vcpu *vcpu)
721 {
722 test_clidr(vcpu);
723 test_ctr(vcpu);
724
725 test_id_reg(vcpu, SYS_MPIDR_EL1);
726 ksft_test_result_pass("%s\n", __func__);
727 }
728
test_vcpu_non_ftr_id_regs(struct kvm_vcpu * vcpu)729 static void test_vcpu_non_ftr_id_regs(struct kvm_vcpu *vcpu)
730 {
731 test_id_reg(vcpu, SYS_MIDR_EL1);
732 test_id_reg(vcpu, SYS_REVIDR_EL1);
733 test_id_reg(vcpu, SYS_AIDR_EL1);
734
735 ksft_test_result_pass("%s\n", __func__);
736 }
737
test_assert_id_reg_unchanged(struct kvm_vcpu * vcpu,uint32_t encoding)738 static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding)
739 {
740 size_t idx = encoding_to_range_idx(encoding);
741 uint64_t observed;
742
743 observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding));
744 TEST_ASSERT_EQ(test_reg_vals[idx], observed);
745 }
746
test_reset_preserves_id_regs(struct kvm_vcpu * vcpu)747 static void test_reset_preserves_id_regs(struct kvm_vcpu *vcpu)
748 {
749 /*
750 * Calls KVM_ARM_VCPU_INIT behind the scenes, which will do an
751 * architectural reset of the vCPU.
752 */
753 aarch64_vcpu_setup(vcpu, NULL);
754
755 for (int i = 0; i < ARRAY_SIZE(test_regs); i++)
756 test_assert_id_reg_unchanged(vcpu, test_regs[i].reg);
757
758 test_assert_id_reg_unchanged(vcpu, SYS_MPIDR_EL1);
759 test_assert_id_reg_unchanged(vcpu, SYS_CLIDR_EL1);
760 test_assert_id_reg_unchanged(vcpu, SYS_CTR_EL0);
761 test_assert_id_reg_unchanged(vcpu, SYS_MIDR_EL1);
762 test_assert_id_reg_unchanged(vcpu, SYS_REVIDR_EL1);
763 test_assert_id_reg_unchanged(vcpu, SYS_AIDR_EL1);
764
765 ksft_test_result_pass("%s\n", __func__);
766 }
767
main(void)768 int main(void)
769 {
770 struct kvm_vcpu *vcpu;
771 struct kvm_vm *vm;
772 bool aarch64_only;
773 uint64_t val, el0;
774 int test_cnt, i, j;
775
776 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES));
777 TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_WRITABLE_IMP_ID_REGS));
778
779 test_wants_mte();
780
781 vm = vm_create(1);
782 vm_enable_cap(vm, KVM_CAP_ARM_WRITABLE_IMP_ID_REGS, 0);
783 vcpu = vm_vcpu_add(vm, 0, guest_code);
784 kvm_arch_vm_finalize_vcpus(vm);
785
786 /* Check for AARCH64 only system */
787 val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
788 el0 = FIELD_GET(ID_AA64PFR0_EL1_EL0, val);
789 aarch64_only = (el0 == ID_AA64PFR0_EL1_EL0_IMP);
790
791 ksft_print_header();
792
793 test_cnt = 3 + MPAM_IDREG_TEST + MTE_IDREG_TEST;
794 for (i = 0; i < ARRAY_SIZE(test_regs); i++)
795 for (j = 0; test_regs[i].ftr_bits[j].type != FTR_END; j++)
796 test_cnt++;
797
798 ksft_set_plan(test_cnt);
799
800 test_vm_ftr_id_regs(vcpu, aarch64_only);
801 test_vcpu_ftr_id_regs(vcpu);
802 test_vcpu_non_ftr_id_regs(vcpu);
803 test_user_set_mpam_reg(vcpu);
804 test_user_set_mte_reg(vcpu);
805
806 test_guest_reg_read(vcpu);
807
808 test_reset_preserves_id_regs(vcpu);
809
810 kvm_vm_free(vm);
811
812 ksft_finished();
813 }
814