1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2004-2007,2011-2012 Freescale Semiconductor, Inc.
4 * All rights reserved.
5 *
6 * Author: Li Yang <leoli@freescale.com>
7 * Jiang Bo <tanya.jiang@freescale.com>
8 *
9 * Description:
10 * Freescale high-speed USB SOC DR module device controller driver.
11 * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
12 * The driver is previously named as mpc_udc. Based on bare board
13 * code from Dave Liu and Shlomi Gridish.
14 */
15
16 #define pr_fmt(x) "udc: " x
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/ioport.h>
21 #include <linux/types.h>
22 #include <linux/errno.h>
23 #include <linux/err.h>
24 #include <linux/slab.h>
25 #include <linux/string_choices.h>
26 #include <linux/init.h>
27 #include <linux/list.h>
28 #include <linux/interrupt.h>
29 #include <linux/proc_fs.h>
30 #include <linux/mm.h>
31 #include <linux/moduleparam.h>
32 #include <linux/device.h>
33 #include <linux/usb/ch9.h>
34 #include <linux/usb/gadget.h>
35 #include <linux/usb/otg.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/platform_device.h>
38 #include <linux/fsl_devices.h>
39 #include <linux/dmapool.h>
40
41 #include <asm/byteorder.h>
42 #include <asm/io.h>
43 #include <linux/unaligned.h>
44 #include <asm/dma.h>
45
46 #include "fsl_usb2_udc.h"
47
48 #define DRIVER_DESC "Freescale High-Speed USB SOC Device Controller driver"
49 #define DRIVER_AUTHOR "Li Yang/Jiang Bo"
50 #define DRIVER_VERSION "Apr 20, 2007"
51
52 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
53
54 static const char driver_name[] = "fsl-usb2-udc";
55
56 static struct usb_dr_device __iomem *dr_regs;
57
58 static struct usb_sys_interface __iomem *usb_sys_regs;
59
60 /* it is initialized in probe() */
61 static struct fsl_udc *udc_controller = NULL;
62
63 static const struct usb_endpoint_descriptor
64 fsl_ep0_desc = {
65 .bLength = USB_DT_ENDPOINT_SIZE,
66 .bDescriptorType = USB_DT_ENDPOINT,
67 .bEndpointAddress = 0,
68 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
69 .wMaxPacketSize = USB_MAX_CTRL_PAYLOAD,
70 };
71
72 static void fsl_ep_fifo_flush(struct usb_ep *_ep);
73
74 #ifdef CONFIG_PPC32
75 /*
76 * On some SoCs, the USB controller registers can be big or little endian,
77 * depending on the version of the chip. In order to be able to run the
78 * same kernel binary on 2 different versions of an SoC, the BE/LE decision
79 * must be made at run time. _fsl_readl and fsl_writel are pointers to the
80 * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
81 * call through those pointers. Platform code for SoCs that have BE USB
82 * registers should set pdata->big_endian_mmio flag.
83 *
84 * This also applies to controller-to-cpu accessors for the USB descriptors,
85 * since their endianness is also SoC dependant. Platform code for SoCs that
86 * have BE USB descriptors should set pdata->big_endian_desc flag.
87 */
_fsl_readl_be(const unsigned __iomem * p)88 static u32 _fsl_readl_be(const unsigned __iomem *p)
89 {
90 return in_be32(p);
91 }
92
_fsl_readl_le(const unsigned __iomem * p)93 static u32 _fsl_readl_le(const unsigned __iomem *p)
94 {
95 return in_le32(p);
96 }
97
_fsl_writel_be(u32 v,unsigned __iomem * p)98 static void _fsl_writel_be(u32 v, unsigned __iomem *p)
99 {
100 out_be32(p, v);
101 }
102
_fsl_writel_le(u32 v,unsigned __iomem * p)103 static void _fsl_writel_le(u32 v, unsigned __iomem *p)
104 {
105 out_le32(p, v);
106 }
107
108 static u32 (*_fsl_readl)(const unsigned __iomem *p);
109 static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
110
111 #define fsl_readl(p) (*_fsl_readl)((p))
112 #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
113
fsl_set_accessors(struct fsl_usb2_platform_data * pdata)114 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata)
115 {
116 if (pdata->big_endian_mmio) {
117 _fsl_readl = _fsl_readl_be;
118 _fsl_writel = _fsl_writel_be;
119 } else {
120 _fsl_readl = _fsl_readl_le;
121 _fsl_writel = _fsl_writel_le;
122 }
123 }
124
cpu_to_hc32(const u32 x)125 static inline u32 cpu_to_hc32(const u32 x)
126 {
127 return udc_controller->pdata->big_endian_desc
128 ? (__force u32)cpu_to_be32(x)
129 : (__force u32)cpu_to_le32(x);
130 }
131
hc32_to_cpu(const u32 x)132 static inline u32 hc32_to_cpu(const u32 x)
133 {
134 return udc_controller->pdata->big_endian_desc
135 ? be32_to_cpu((__force __be32)x)
136 : le32_to_cpu((__force __le32)x);
137 }
138 #else /* !CONFIG_PPC32 */
fsl_set_accessors(struct fsl_usb2_platform_data * pdata)139 static inline void fsl_set_accessors(struct fsl_usb2_platform_data *pdata) {}
140
141 #define fsl_readl(addr) readl(addr)
142 #define fsl_writel(val32, addr) writel(val32, addr)
143 #define cpu_to_hc32(x) cpu_to_le32(x)
144 #define hc32_to_cpu(x) le32_to_cpu(x)
145 #endif /* CONFIG_PPC32 */
146
147 /********************************************************************
148 * Internal Used Function
149 ********************************************************************/
150 /*-----------------------------------------------------------------
151 * done() - retire a request; caller blocked irqs
152 * @status : request status to be set, only works when
153 * request is still in progress.
154 *--------------------------------------------------------------*/
done(struct fsl_ep * ep,struct fsl_req * req,int status)155 static void done(struct fsl_ep *ep, struct fsl_req *req, int status)
156 __releases(ep->udc->lock)
157 __acquires(ep->udc->lock)
158 {
159 struct fsl_udc *udc = NULL;
160 unsigned char stopped = ep->stopped;
161 struct ep_td_struct *curr_td, *next_td;
162 int j;
163
164 udc = (struct fsl_udc *)ep->udc;
165 /* Removed the req from fsl_ep->queue */
166 list_del_init(&req->queue);
167
168 /* req.status should be set as -EINPROGRESS in ep_queue() */
169 if (req->req.status == -EINPROGRESS)
170 req->req.status = status;
171 else
172 status = req->req.status;
173
174 /* Free dtd for the request */
175 next_td = req->head;
176 for (j = 0; j < req->dtd_count; j++) {
177 curr_td = next_td;
178 if (j != req->dtd_count - 1) {
179 next_td = curr_td->next_td_virt;
180 }
181 dma_pool_free(udc->td_pool, curr_td, curr_td->td_dma);
182 }
183
184 usb_gadget_unmap_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
185
186 if (status && (status != -ESHUTDOWN))
187 dev_vdbg(udc->dev, "complete %s req %p stat %d len %u/%u\n",
188 ep->ep.name, &req->req, status,
189 req->req.actual, req->req.length);
190
191 ep->stopped = 1;
192
193 spin_unlock(&ep->udc->lock);
194
195 usb_gadget_giveback_request(&ep->ep, &req->req);
196
197 spin_lock(&ep->udc->lock);
198 ep->stopped = stopped;
199 }
200
201 /*-----------------------------------------------------------------
202 * nuke(): delete all requests related to this ep
203 * called with spinlock held
204 *--------------------------------------------------------------*/
nuke(struct fsl_ep * ep,int status)205 static void nuke(struct fsl_ep *ep, int status)
206 {
207 ep->stopped = 1;
208
209 /* Flush fifo */
210 fsl_ep_fifo_flush(&ep->ep);
211
212 /* Whether this eq has request linked */
213 while (!list_empty(&ep->queue)) {
214 struct fsl_req *req = NULL;
215
216 req = list_entry(ep->queue.next, struct fsl_req, queue);
217 done(ep, req, status);
218 }
219 }
220
221 /*------------------------------------------------------------------
222 Internal Hardware related function
223 ------------------------------------------------------------------*/
224
dr_controller_setup(struct fsl_udc * udc)225 static int dr_controller_setup(struct fsl_udc *udc)
226 {
227 unsigned int tmp, portctrl, ep_num;
228 unsigned int max_no_of_ep;
229 unsigned int ctrl;
230 unsigned long timeout;
231
232 #define FSL_UDC_RESET_TIMEOUT 1000
233
234 /* Config PHY interface */
235 portctrl = fsl_readl(&dr_regs->portsc1);
236 portctrl &= ~(PORTSCX_PHY_TYPE_SEL | PORTSCX_PORT_WIDTH);
237 switch (udc->phy_mode) {
238 case FSL_USB2_PHY_ULPI:
239 if (udc->pdata->have_sysif_regs) {
240 if (udc->pdata->controller_ver) {
241 /* controller version 1.6 or above */
242 ctrl = __raw_readl(&usb_sys_regs->control);
243 ctrl &= ~USB_CTRL_UTMI_PHY_EN;
244 ctrl |= USB_CTRL_USB_EN;
245 __raw_writel(ctrl, &usb_sys_regs->control);
246 }
247 }
248 portctrl |= PORTSCX_PTS_ULPI;
249 break;
250 case FSL_USB2_PHY_UTMI_WIDE:
251 portctrl |= PORTSCX_PTW_16BIT;
252 fallthrough;
253 case FSL_USB2_PHY_UTMI:
254 case FSL_USB2_PHY_UTMI_DUAL:
255 if (udc->pdata->have_sysif_regs) {
256 if (udc->pdata->controller_ver) {
257 /* controller version 1.6 or above */
258 ctrl = __raw_readl(&usb_sys_regs->control);
259 ctrl |= (USB_CTRL_UTMI_PHY_EN |
260 USB_CTRL_USB_EN);
261 __raw_writel(ctrl, &usb_sys_regs->control);
262 mdelay(FSL_UTMI_PHY_DLY); /* Delay for UTMI
263 PHY CLK to become stable - 10ms*/
264 }
265 }
266 portctrl |= PORTSCX_PTS_UTMI;
267 break;
268 case FSL_USB2_PHY_SERIAL:
269 portctrl |= PORTSCX_PTS_FSLS;
270 break;
271 default:
272 return -EINVAL;
273 }
274 fsl_writel(portctrl, &dr_regs->portsc1);
275
276 /* Stop and reset the usb controller */
277 tmp = fsl_readl(&dr_regs->usbcmd);
278 tmp &= ~USB_CMD_RUN_STOP;
279 fsl_writel(tmp, &dr_regs->usbcmd);
280
281 tmp = fsl_readl(&dr_regs->usbcmd);
282 tmp |= USB_CMD_CTRL_RESET;
283 fsl_writel(tmp, &dr_regs->usbcmd);
284
285 /* Wait for reset to complete */
286 timeout = jiffies + FSL_UDC_RESET_TIMEOUT;
287 while (fsl_readl(&dr_regs->usbcmd) & USB_CMD_CTRL_RESET) {
288 if (time_after(jiffies, timeout)) {
289 dev_err(udc->dev, "udc reset timeout!\n");
290 return -ETIMEDOUT;
291 }
292 cpu_relax();
293 }
294
295 /* Set the controller as device mode */
296 tmp = fsl_readl(&dr_regs->usbmode);
297 tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
298 tmp |= USB_MODE_CTRL_MODE_DEVICE;
299 /* Disable Setup Lockout */
300 tmp |= USB_MODE_SETUP_LOCK_OFF;
301 if (udc->pdata->es)
302 tmp |= USB_MODE_ES;
303 fsl_writel(tmp, &dr_regs->usbmode);
304
305 /* Clear the setup status */
306 fsl_writel(0, &dr_regs->usbsts);
307
308 tmp = udc->ep_qh_dma;
309 tmp &= USB_EP_LIST_ADDRESS_MASK;
310 fsl_writel(tmp, &dr_regs->endpointlistaddr);
311
312 dev_vdbg(udc->dev,
313 "vir[qh_base] is %p phy[qh_base] is 0x%8x reg is 0x%8x\n",
314 udc->ep_qh, (int)tmp,
315 fsl_readl(&dr_regs->endpointlistaddr));
316
317 max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
318 for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
319 tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
320 tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
321 tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
322 | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
323 fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
324 }
325 /* Config control enable i/o output, cpu endian register */
326 if (udc->pdata->have_sysif_regs) {
327 ctrl = __raw_readl(&usb_sys_regs->control);
328 ctrl |= USB_CTRL_IOENB;
329 __raw_writel(ctrl, &usb_sys_regs->control);
330 }
331
332 #if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
333 /* Turn on cache snooping hardware, since some PowerPC platforms
334 * wholly rely on hardware to deal with cache coherent. */
335
336 if (udc->pdata->have_sysif_regs) {
337 /* Setup Snooping for all the 4GB space */
338 tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
339 __raw_writel(tmp, &usb_sys_regs->snoop1);
340 tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
341 __raw_writel(tmp, &usb_sys_regs->snoop2);
342 }
343 #endif
344
345 return 0;
346 }
347
348 /* Enable DR irq and set controller to run state */
dr_controller_run(struct fsl_udc * udc)349 static void dr_controller_run(struct fsl_udc *udc)
350 {
351 u32 temp;
352
353 /* Enable DR irq reg */
354 temp = USB_INTR_INT_EN | USB_INTR_ERR_INT_EN
355 | USB_INTR_PTC_DETECT_EN | USB_INTR_RESET_EN
356 | USB_INTR_DEVICE_SUSPEND | USB_INTR_SYS_ERR_EN;
357
358 fsl_writel(temp, &dr_regs->usbintr);
359
360 /* Clear stopped bit */
361 udc->stopped = 0;
362
363 /* Set the controller as device mode */
364 temp = fsl_readl(&dr_regs->usbmode);
365 temp |= USB_MODE_CTRL_MODE_DEVICE;
366 fsl_writel(temp, &dr_regs->usbmode);
367
368 /* Set controller to Run */
369 temp = fsl_readl(&dr_regs->usbcmd);
370 temp |= USB_CMD_RUN_STOP;
371 fsl_writel(temp, &dr_regs->usbcmd);
372 }
373
dr_controller_stop(struct fsl_udc * udc)374 static void dr_controller_stop(struct fsl_udc *udc)
375 {
376 unsigned int tmp;
377
378 pr_debug("%s\n", __func__);
379
380 /* if we're in OTG mode, and the Host is currently using the port,
381 * stop now and don't rip the controller out from under the
382 * ehci driver
383 */
384 if (udc->gadget.is_otg) {
385 if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
386 pr_debug("udc: Leaving early\n");
387 return;
388 }
389 }
390
391 /* disable all INTR */
392 fsl_writel(0, &dr_regs->usbintr);
393
394 /* Set stopped bit for isr */
395 udc->stopped = 1;
396
397 /* disable IO output */
398 /* usb_sys_regs->control = 0; */
399
400 /* set controller to Stop */
401 tmp = fsl_readl(&dr_regs->usbcmd);
402 tmp &= ~USB_CMD_RUN_STOP;
403 fsl_writel(tmp, &dr_regs->usbcmd);
404 }
405
dr_ep_setup(unsigned char ep_num,unsigned char dir,unsigned char ep_type)406 static void dr_ep_setup(unsigned char ep_num, unsigned char dir,
407 unsigned char ep_type)
408 {
409 unsigned int tmp_epctrl = 0;
410
411 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
412 if (dir) {
413 if (ep_num)
414 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
415 tmp_epctrl |= EPCTRL_TX_ENABLE;
416 tmp_epctrl &= ~EPCTRL_TX_TYPE;
417 tmp_epctrl |= ((unsigned int)(ep_type)
418 << EPCTRL_TX_EP_TYPE_SHIFT);
419 } else {
420 if (ep_num)
421 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
422 tmp_epctrl |= EPCTRL_RX_ENABLE;
423 tmp_epctrl &= ~EPCTRL_RX_TYPE;
424 tmp_epctrl |= ((unsigned int)(ep_type)
425 << EPCTRL_RX_EP_TYPE_SHIFT);
426 }
427
428 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
429 }
430
431 static void
dr_ep_change_stall(unsigned char ep_num,unsigned char dir,int value)432 dr_ep_change_stall(unsigned char ep_num, unsigned char dir, int value)
433 {
434 u32 tmp_epctrl = 0;
435
436 tmp_epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
437
438 if (value) {
439 /* set the stall bit */
440 if (dir)
441 tmp_epctrl |= EPCTRL_TX_EP_STALL;
442 else
443 tmp_epctrl |= EPCTRL_RX_EP_STALL;
444 } else {
445 /* clear the stall bit and reset data toggle */
446 if (dir) {
447 tmp_epctrl &= ~EPCTRL_TX_EP_STALL;
448 tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
449 } else {
450 tmp_epctrl &= ~EPCTRL_RX_EP_STALL;
451 tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
452 }
453 }
454 fsl_writel(tmp_epctrl, &dr_regs->endptctrl[ep_num]);
455 }
456
457 /* Get stall status of a specific ep
458 Return: 0: not stalled; 1:stalled */
dr_ep_get_stall(unsigned char ep_num,unsigned char dir)459 static int dr_ep_get_stall(unsigned char ep_num, unsigned char dir)
460 {
461 u32 epctrl;
462
463 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
464 if (dir)
465 return (epctrl & EPCTRL_TX_EP_STALL) ? 1 : 0;
466 else
467 return (epctrl & EPCTRL_RX_EP_STALL) ? 1 : 0;
468 }
469
470 /********************************************************************
471 Internal Structure Build up functions
472 ********************************************************************/
473
474 /*------------------------------------------------------------------
475 * struct_ep_qh_setup(): set the Endpoint Capabilites field of QH
476 * @zlt: Zero Length Termination Select (1: disable; 0: enable)
477 * @mult: Mult field
478 ------------------------------------------------------------------*/
struct_ep_qh_setup(struct fsl_udc * udc,unsigned char ep_num,unsigned char dir,unsigned char ep_type,unsigned int max_pkt_len,unsigned int zlt,unsigned char mult)479 static void struct_ep_qh_setup(struct fsl_udc *udc, unsigned char ep_num,
480 unsigned char dir, unsigned char ep_type,
481 unsigned int max_pkt_len,
482 unsigned int zlt, unsigned char mult)
483 {
484 struct ep_queue_head *p_QH = &udc->ep_qh[2 * ep_num + dir];
485 unsigned int tmp = 0;
486
487 /* set the Endpoint Capabilites in QH */
488 switch (ep_type) {
489 case USB_ENDPOINT_XFER_CONTROL:
490 /* Interrupt On Setup (IOS). for control ep */
491 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
492 | EP_QUEUE_HEAD_IOS;
493 break;
494 case USB_ENDPOINT_XFER_ISOC:
495 tmp = (max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS)
496 | (mult << EP_QUEUE_HEAD_MULT_POS);
497 break;
498 case USB_ENDPOINT_XFER_BULK:
499 case USB_ENDPOINT_XFER_INT:
500 tmp = max_pkt_len << EP_QUEUE_HEAD_MAX_PKT_LEN_POS;
501 break;
502 default:
503 dev_vdbg(udc->dev, "error ep type is %d\n", ep_type);
504 return;
505 }
506 if (zlt)
507 tmp |= EP_QUEUE_HEAD_ZLT_SEL;
508
509 p_QH->max_pkt_length = cpu_to_hc32(tmp);
510 p_QH->next_dtd_ptr = 1;
511 p_QH->size_ioc_int_sts = 0;
512 }
513
514 /* Setup qh structure and ep register for ep0. */
ep0_setup(struct fsl_udc * udc)515 static void ep0_setup(struct fsl_udc *udc)
516 {
517 /* the initialization of an ep includes: fields in QH, Regs,
518 * fsl_ep struct */
519 struct_ep_qh_setup(udc, 0, USB_RECV, USB_ENDPOINT_XFER_CONTROL,
520 USB_MAX_CTRL_PAYLOAD, 0, 0);
521 struct_ep_qh_setup(udc, 0, USB_SEND, USB_ENDPOINT_XFER_CONTROL,
522 USB_MAX_CTRL_PAYLOAD, 0, 0);
523 dr_ep_setup(0, USB_RECV, USB_ENDPOINT_XFER_CONTROL);
524 dr_ep_setup(0, USB_SEND, USB_ENDPOINT_XFER_CONTROL);
525
526 return;
527
528 }
529
530 /***********************************************************************
531 Endpoint Management Functions
532 ***********************************************************************/
533
534 /*-------------------------------------------------------------------------
535 * when configurations are set, or when interface settings change
536 * for example the do_set_interface() in gadget layer,
537 * the driver will enable or disable the relevant endpoints
538 * ep0 doesn't use this routine. It is always enabled.
539 -------------------------------------------------------------------------*/
fsl_ep_enable(struct usb_ep * _ep,const struct usb_endpoint_descriptor * desc)540 static int fsl_ep_enable(struct usb_ep *_ep,
541 const struct usb_endpoint_descriptor *desc)
542 {
543 struct fsl_udc *udc = NULL;
544 struct fsl_ep *ep = NULL;
545 unsigned short max = 0;
546 unsigned char mult = 0, zlt;
547 int retval = -EINVAL;
548 unsigned long flags;
549
550 ep = container_of(_ep, struct fsl_ep, ep);
551
552 /* catch various bogus parameters */
553 if (!_ep || !desc
554 || (desc->bDescriptorType != USB_DT_ENDPOINT))
555 return -EINVAL;
556
557 udc = ep->udc;
558
559 if (!udc->driver || (udc->gadget.speed == USB_SPEED_UNKNOWN))
560 return -ESHUTDOWN;
561
562 max = usb_endpoint_maxp(desc);
563
564 /* Disable automatic zlp generation. Driver is responsible to indicate
565 * explicitly through req->req.zero. This is needed to enable multi-td
566 * request. */
567 zlt = 1;
568
569 /* Assume the max packet size from gadget is always correct */
570 switch (desc->bmAttributes & 0x03) {
571 case USB_ENDPOINT_XFER_CONTROL:
572 case USB_ENDPOINT_XFER_BULK:
573 case USB_ENDPOINT_XFER_INT:
574 /* mult = 0. Execute N Transactions as demonstrated by
575 * the USB variable length packet protocol where N is
576 * computed using the Maximum Packet Length (dQH) and
577 * the Total Bytes field (dTD) */
578 mult = 0;
579 break;
580 case USB_ENDPOINT_XFER_ISOC:
581 /* Calculate transactions needed for high bandwidth iso */
582 mult = usb_endpoint_maxp_mult(desc);
583 /* 3 transactions at most */
584 if (mult > 3)
585 goto en_done;
586 break;
587 default:
588 goto en_done;
589 }
590
591 spin_lock_irqsave(&udc->lock, flags);
592 ep->ep.maxpacket = max;
593 ep->ep.desc = desc;
594 ep->stopped = 0;
595
596 /* Controller related setup */
597 /* Init EPx Queue Head (Ep Capabilites field in QH
598 * according to max, zlt, mult) */
599 struct_ep_qh_setup(udc, (unsigned char) ep_index(ep),
600 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
601 ? USB_SEND : USB_RECV),
602 (unsigned char) (desc->bmAttributes
603 & USB_ENDPOINT_XFERTYPE_MASK),
604 max, zlt, mult);
605
606 /* Init endpoint ctrl register */
607 dr_ep_setup((unsigned char) ep_index(ep),
608 (unsigned char) ((desc->bEndpointAddress & USB_DIR_IN)
609 ? USB_SEND : USB_RECV),
610 (unsigned char) (desc->bmAttributes
611 & USB_ENDPOINT_XFERTYPE_MASK));
612
613 spin_unlock_irqrestore(&udc->lock, flags);
614 retval = 0;
615
616 dev_vdbg(udc->dev, "enabled %s (ep%d%s) maxpacket %d\n",
617 ep->ep.name, ep->ep.desc->bEndpointAddress & 0x0f,
618 (desc->bEndpointAddress & USB_DIR_IN) ? "in" : "out",
619 max);
620 en_done:
621 return retval;
622 }
623
624 /*---------------------------------------------------------------------
625 * @ep : the ep being unconfigured. May not be ep0
626 * Any pending and uncomplete req will complete with status (-ESHUTDOWN)
627 *---------------------------------------------------------------------*/
fsl_ep_disable(struct usb_ep * _ep)628 static int fsl_ep_disable(struct usb_ep *_ep)
629 {
630 struct fsl_udc *udc = NULL;
631 struct fsl_ep *ep = NULL;
632 unsigned long flags;
633 u32 epctrl;
634 int ep_num;
635
636 ep = container_of(_ep, struct fsl_ep, ep);
637 if (!_ep || !ep->ep.desc)
638 return -EINVAL;
639
640 /* disable ep on controller */
641 ep_num = ep_index(ep);
642 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
643 if (ep_is_in(ep)) {
644 epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
645 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
646 } else {
647 epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
648 epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
649 }
650 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
651
652 udc = (struct fsl_udc *)ep->udc;
653 spin_lock_irqsave(&udc->lock, flags);
654
655 /* nuke all pending requests (does flush) */
656 nuke(ep, -ESHUTDOWN);
657
658 ep->ep.desc = NULL;
659 ep->stopped = 1;
660 spin_unlock_irqrestore(&udc->lock, flags);
661
662 dev_vdbg(udc->dev, "disabled %s OK\n", _ep->name);
663 return 0;
664 }
665
666 /*---------------------------------------------------------------------
667 * allocate a request object used by this endpoint
668 * the main operation is to insert the req->queue to the eq->queue
669 * Returns the request, or null if one could not be allocated
670 *---------------------------------------------------------------------*/
671 static struct usb_request *
fsl_alloc_request(struct usb_ep * _ep,gfp_t gfp_flags)672 fsl_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
673 {
674 struct fsl_req *req;
675
676 req = kzalloc_obj(*req, gfp_flags);
677 if (!req)
678 return NULL;
679
680 req->req.dma = DMA_ADDR_INVALID;
681 INIT_LIST_HEAD(&req->queue);
682
683 return &req->req;
684 }
685
fsl_free_request(struct usb_ep * _ep,struct usb_request * _req)686 static void fsl_free_request(struct usb_ep *_ep, struct usb_request *_req)
687 {
688 struct fsl_req *req = NULL;
689
690 req = container_of(_req, struct fsl_req, req);
691
692 if (_req)
693 kfree(req);
694 }
695
696 /* Actually add a dTD chain to an empty dQH and let go */
fsl_prime_ep(struct fsl_ep * ep,struct ep_td_struct * td)697 static void fsl_prime_ep(struct fsl_ep *ep, struct ep_td_struct *td)
698 {
699 struct ep_queue_head *qh = get_qh_by_ep(ep);
700
701 /* Write dQH next pointer and terminate bit to 0 */
702 qh->next_dtd_ptr = cpu_to_hc32(td->td_dma
703 & EP_QUEUE_HEAD_NEXT_POINTER_MASK);
704
705 /* Clear active and halt bit */
706 qh->size_ioc_int_sts &= cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
707 | EP_QUEUE_HEAD_STATUS_HALT));
708
709 /* Ensure that updates to the QH will occur before priming. */
710 wmb();
711
712 /* Prime endpoint by writing correct bit to ENDPTPRIME */
713 fsl_writel(ep_is_in(ep) ? (1 << (ep_index(ep) + 16))
714 : (1 << (ep_index(ep))), &dr_regs->endpointprime);
715 }
716
717 /* Add dTD chain to the dQH of an EP */
fsl_queue_td(struct fsl_ep * ep,struct fsl_req * req)718 static void fsl_queue_td(struct fsl_ep *ep, struct fsl_req *req)
719 {
720 u32 temp, bitmask, tmp_stat;
721
722 bitmask = ep_is_in(ep)
723 ? (1 << (ep_index(ep) + 16))
724 : (1 << (ep_index(ep)));
725
726 /* check if the pipe is empty */
727 if (!(list_empty(&ep->queue)) && !(ep_index(ep) == 0)) {
728 /* Add td to the end */
729 struct fsl_req *lastreq;
730 lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
731 lastreq->tail->next_td_ptr =
732 cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
733 /* Ensure dTD's next dtd pointer to be updated */
734 wmb();
735 /* Read prime bit, if 1 goto done */
736 if (fsl_readl(&dr_regs->endpointprime) & bitmask)
737 return;
738
739 do {
740 /* Set ATDTW bit in USBCMD */
741 temp = fsl_readl(&dr_regs->usbcmd);
742 fsl_writel(temp | USB_CMD_ATDTW, &dr_regs->usbcmd);
743
744 /* Read correct status bit */
745 tmp_stat = fsl_readl(&dr_regs->endptstatus) & bitmask;
746
747 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_ATDTW));
748
749 /* Write ATDTW bit to 0 */
750 temp = fsl_readl(&dr_regs->usbcmd);
751 fsl_writel(temp & ~USB_CMD_ATDTW, &dr_regs->usbcmd);
752
753 if (tmp_stat)
754 return;
755 }
756
757 fsl_prime_ep(ep, req->head);
758 }
759
760 /* Fill in the dTD structure
761 * @req: request that the transfer belongs to
762 * @length: return actually data length of the dTD
763 * @dma: return dma address of the dTD
764 * @is_last: return flag if it is the last dTD of the request
765 * return: pointer to the built dTD */
fsl_build_dtd(struct fsl_req * req,unsigned * length,dma_addr_t * dma,int * is_last,gfp_t gfp_flags)766 static struct ep_td_struct *fsl_build_dtd(struct fsl_req *req, unsigned *length,
767 dma_addr_t *dma, int *is_last, gfp_t gfp_flags)
768 {
769 u32 swap_temp;
770 struct ep_td_struct *dtd;
771
772 /* how big will this transfer be? */
773 *length = min(req->req.length - req->req.actual,
774 (unsigned)EP_MAX_LENGTH_TRANSFER);
775
776 dtd = dma_pool_alloc(udc_controller->td_pool, gfp_flags, dma);
777 if (dtd == NULL)
778 return dtd;
779
780 dtd->td_dma = *dma;
781 /* Clear reserved field */
782 swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
783 swap_temp &= ~DTD_RESERVED_FIELDS;
784 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
785
786 /* Init all of buffer page pointers */
787 swap_temp = (u32) (req->req.dma + req->req.actual);
788 dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
789 dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
790 dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
791 dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
792 dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
793
794 req->req.actual += *length;
795
796 /* zlp is needed if req->req.zero is set */
797 if (req->req.zero) {
798 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
799 *is_last = 1;
800 else
801 *is_last = 0;
802 } else if (req->req.length == req->req.actual)
803 *is_last = 1;
804 else
805 *is_last = 0;
806
807 if ((*is_last) == 0)
808 dev_vdbg(udc_controller->dev, "multi-dtd request!\n");
809 /* Fill in the transfer size; set active bit */
810 swap_temp = ((*length << DTD_LENGTH_BIT_POS) | DTD_STATUS_ACTIVE);
811
812 /* Enable interrupt for the last dtd of a request */
813 if (*is_last && !req->req.no_interrupt)
814 swap_temp |= DTD_IOC;
815
816 dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
817
818 mb();
819
820 dev_vdbg(udc_controller->dev, "length = %d address= 0x%x\n", *length, (int)*dma);
821
822 return dtd;
823 }
824
825 /* Generate dtd chain for a request */
fsl_req_to_dtd(struct fsl_req * req,gfp_t gfp_flags)826 static int fsl_req_to_dtd(struct fsl_req *req, gfp_t gfp_flags)
827 {
828 unsigned count;
829 int is_last;
830 int is_first =1;
831 struct ep_td_struct *last_dtd = NULL, *dtd;
832 dma_addr_t dma;
833
834 do {
835 dtd = fsl_build_dtd(req, &count, &dma, &is_last, gfp_flags);
836 if (dtd == NULL)
837 return -ENOMEM;
838
839 if (is_first) {
840 is_first = 0;
841 req->head = dtd;
842 } else {
843 last_dtd->next_td_ptr = cpu_to_hc32(dma);
844 last_dtd->next_td_virt = dtd;
845 }
846 last_dtd = dtd;
847
848 req->dtd_count++;
849 } while (!is_last);
850
851 dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
852
853 req->tail = dtd;
854
855 return 0;
856 }
857
858 /* queues (submits) an I/O request to an endpoint */
859 static int
fsl_ep_queue(struct usb_ep * _ep,struct usb_request * _req,gfp_t gfp_flags)860 fsl_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
861 {
862 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
863 struct fsl_req *req = container_of(_req, struct fsl_req, req);
864 struct fsl_udc *udc = ep->udc;
865 unsigned long flags;
866 int ret;
867
868 /* catch various bogus parameters */
869 if (!_req || !req->req.complete || !req->req.buf
870 || !list_empty(&req->queue)) {
871 dev_vdbg(udc->dev, "%s, bad params\n", __func__);
872 return -EINVAL;
873 }
874 if (unlikely(!ep->ep.desc)) {
875 dev_vdbg(udc->dev, "%s, bad ep\n", __func__);
876 return -EINVAL;
877 }
878 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
879 if (req->req.length > ep->ep.maxpacket)
880 return -EMSGSIZE;
881 }
882
883 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
884 return -ESHUTDOWN;
885
886 req->ep = ep;
887
888 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
889 if (ret)
890 return ret;
891
892 req->req.status = -EINPROGRESS;
893 req->req.actual = 0;
894 req->dtd_count = 0;
895
896 /* build dtds and push them to device queue */
897 if (!fsl_req_to_dtd(req, gfp_flags)) {
898 spin_lock_irqsave(&udc->lock, flags);
899 fsl_queue_td(ep, req);
900 } else {
901 return -ENOMEM;
902 }
903
904 /* irq handler advances the queue */
905 if (req != NULL)
906 list_add_tail(&req->queue, &ep->queue);
907 spin_unlock_irqrestore(&udc->lock, flags);
908
909 return 0;
910 }
911
912 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
fsl_ep_dequeue(struct usb_ep * _ep,struct usb_request * _req)913 static int fsl_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
914 {
915 struct fsl_ep *ep = container_of(_ep, struct fsl_ep, ep);
916 struct fsl_req *req = NULL;
917 struct fsl_req *iter;
918 unsigned long flags;
919 int ep_num, stopped, ret = 0;
920 u32 epctrl;
921
922 if (!_ep || !_req)
923 return -EINVAL;
924
925 spin_lock_irqsave(&ep->udc->lock, flags);
926 stopped = ep->stopped;
927
928 /* Stop the ep before we deal with the queue */
929 ep->stopped = 1;
930 ep_num = ep_index(ep);
931 epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
932 if (ep_is_in(ep))
933 epctrl &= ~EPCTRL_TX_ENABLE;
934 else
935 epctrl &= ~EPCTRL_RX_ENABLE;
936 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
937
938 /* make sure it's actually queued on this endpoint */
939 list_for_each_entry(iter, &ep->queue, queue) {
940 if (&iter->req != _req)
941 continue;
942 req = iter;
943 break;
944 }
945 if (!req) {
946 ret = -EINVAL;
947 goto out;
948 }
949
950 /* The request is in progress, or completed but not dequeued */
951 if (ep->queue.next == &req->queue) {
952 _req->status = -ECONNRESET;
953 fsl_ep_fifo_flush(_ep); /* flush current transfer */
954
955 /* The request isn't the last request in this ep queue */
956 if (req->queue.next != &ep->queue) {
957 struct fsl_req *next_req;
958
959 next_req = list_entry(req->queue.next, struct fsl_req,
960 queue);
961
962 /* prime with dTD of next request */
963 fsl_prime_ep(ep, next_req->head);
964 }
965 /* The request hasn't been processed, patch up the TD chain */
966 } else {
967 struct fsl_req *prev_req;
968
969 prev_req = list_entry(req->queue.prev, struct fsl_req, queue);
970 prev_req->tail->next_td_ptr = req->tail->next_td_ptr;
971 }
972
973 done(ep, req, -ECONNRESET);
974
975 /* Enable EP */
976 out: epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
977 if (ep_is_in(ep))
978 epctrl |= EPCTRL_TX_ENABLE;
979 else
980 epctrl |= EPCTRL_RX_ENABLE;
981 fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
982 ep->stopped = stopped;
983
984 spin_unlock_irqrestore(&ep->udc->lock, flags);
985 return ret;
986 }
987
988 /*-------------------------------------------------------------------------*/
989
990 /*-----------------------------------------------------------------
991 * modify the endpoint halt feature
992 * @ep: the non-isochronous endpoint being stalled
993 * @value: 1--set halt 0--clear halt
994 * Returns zero, or a negative error code.
995 *----------------------------------------------------------------*/
fsl_ep_set_halt(struct usb_ep * _ep,int value)996 static int fsl_ep_set_halt(struct usb_ep *_ep, int value)
997 {
998 struct fsl_ep *ep = NULL;
999 unsigned long flags;
1000 int status = -EOPNOTSUPP; /* operation not supported */
1001 unsigned char ep_dir = 0, ep_num = 0;
1002 struct fsl_udc *udc = NULL;
1003
1004 ep = container_of(_ep, struct fsl_ep, ep);
1005 udc = ep->udc;
1006 if (!_ep || !ep->ep.desc) {
1007 status = -EINVAL;
1008 goto out;
1009 }
1010
1011 if (usb_endpoint_xfer_isoc(ep->ep.desc)) {
1012 status = -EOPNOTSUPP;
1013 goto out;
1014 }
1015
1016 /* Attempt to halt IN ep will fail if any transfer requests
1017 * are still queue */
1018 if (value && ep_is_in(ep) && !list_empty(&ep->queue)) {
1019 status = -EAGAIN;
1020 goto out;
1021 }
1022
1023 status = 0;
1024 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1025 ep_num = (unsigned char)(ep_index(ep));
1026 spin_lock_irqsave(&ep->udc->lock, flags);
1027 dr_ep_change_stall(ep_num, ep_dir, value);
1028 spin_unlock_irqrestore(&ep->udc->lock, flags);
1029
1030 if (ep_index(ep) == 0) {
1031 udc->ep0_state = WAIT_FOR_SETUP;
1032 udc->ep0_dir = 0;
1033 }
1034 out:
1035 dev_vdbg(udc->dev, "%s %s halt stat %d\n", ep->ep.name,
1036 value ? "set" : "clear", status);
1037
1038 return status;
1039 }
1040
fsl_ep_fifo_status(struct usb_ep * _ep)1041 static int fsl_ep_fifo_status(struct usb_ep *_ep)
1042 {
1043 struct fsl_ep *ep;
1044 struct fsl_udc *udc;
1045 int size = 0;
1046 u32 bitmask;
1047 struct ep_queue_head *qh;
1048
1049 if (!_ep || !_ep->desc || !(_ep->desc->bEndpointAddress&0xF))
1050 return -ENODEV;
1051
1052 ep = container_of(_ep, struct fsl_ep, ep);
1053
1054 udc = (struct fsl_udc *)ep->udc;
1055
1056 if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
1057 return -ESHUTDOWN;
1058
1059 qh = get_qh_by_ep(ep);
1060
1061 bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
1062 (1 << (ep_index(ep)));
1063
1064 if (fsl_readl(&dr_regs->endptstatus) & bitmask)
1065 size = (qh->size_ioc_int_sts & DTD_PACKET_SIZE)
1066 >> DTD_LENGTH_BIT_POS;
1067
1068 pr_debug("%s %u\n", __func__, size);
1069 return size;
1070 }
1071
fsl_ep_fifo_flush(struct usb_ep * _ep)1072 static void fsl_ep_fifo_flush(struct usb_ep *_ep)
1073 {
1074 struct fsl_ep *ep;
1075 int ep_num, ep_dir;
1076 u32 bits;
1077 unsigned long timeout;
1078 #define FSL_UDC_FLUSH_TIMEOUT 1000
1079
1080 if (!_ep) {
1081 return;
1082 } else {
1083 ep = container_of(_ep, struct fsl_ep, ep);
1084 if (!ep->ep.desc)
1085 return;
1086 }
1087 ep_num = ep_index(ep);
1088 ep_dir = ep_is_in(ep) ? USB_SEND : USB_RECV;
1089
1090 if (ep_num == 0)
1091 bits = (1 << 16) | 1;
1092 else if (ep_dir == USB_SEND)
1093 bits = 1 << (16 + ep_num);
1094 else
1095 bits = 1 << ep_num;
1096
1097 timeout = jiffies + FSL_UDC_FLUSH_TIMEOUT;
1098 do {
1099 fsl_writel(bits, &dr_regs->endptflush);
1100
1101 /* Wait until flush complete */
1102 while (fsl_readl(&dr_regs->endptflush)) {
1103 if (time_after(jiffies, timeout)) {
1104 dev_err(udc_controller->dev,
1105 "ep flush timeout\n");
1106 return;
1107 }
1108 cpu_relax();
1109 }
1110 /* See if we need to flush again */
1111 } while (fsl_readl(&dr_regs->endptstatus) & bits);
1112 }
1113
1114 static const struct usb_ep_ops fsl_ep_ops = {
1115 .enable = fsl_ep_enable,
1116 .disable = fsl_ep_disable,
1117
1118 .alloc_request = fsl_alloc_request,
1119 .free_request = fsl_free_request,
1120
1121 .queue = fsl_ep_queue,
1122 .dequeue = fsl_ep_dequeue,
1123
1124 .set_halt = fsl_ep_set_halt,
1125 .fifo_status = fsl_ep_fifo_status,
1126 .fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
1127 };
1128
1129 /*-------------------------------------------------------------------------
1130 Gadget Driver Layer Operations
1131 -------------------------------------------------------------------------*/
1132
1133 /*----------------------------------------------------------------------
1134 * Get the current frame number (from DR frame_index Reg )
1135 *----------------------------------------------------------------------*/
fsl_get_frame(struct usb_gadget * gadget)1136 static int fsl_get_frame(struct usb_gadget *gadget)
1137 {
1138 return (int)(fsl_readl(&dr_regs->frindex) & USB_FRINDEX_MASKS);
1139 }
1140
1141 /*-----------------------------------------------------------------------
1142 * Tries to wake up the host connected to this gadget
1143 -----------------------------------------------------------------------*/
fsl_wakeup(struct usb_gadget * gadget)1144 static int fsl_wakeup(struct usb_gadget *gadget)
1145 {
1146 struct fsl_udc *udc = container_of(gadget, struct fsl_udc, gadget);
1147 u32 portsc;
1148
1149 /* Remote wakeup feature not enabled by host */
1150 if (!udc->remote_wakeup)
1151 return -ENOTSUPP;
1152
1153 portsc = fsl_readl(&dr_regs->portsc1);
1154 /* not suspended? */
1155 if (!(portsc & PORTSCX_PORT_SUSPEND))
1156 return 0;
1157 /* trigger force resume */
1158 portsc |= PORTSCX_PORT_FORCE_RESUME;
1159 fsl_writel(portsc, &dr_regs->portsc1);
1160 return 0;
1161 }
1162
can_pullup(struct fsl_udc * udc)1163 static int can_pullup(struct fsl_udc *udc)
1164 {
1165 return udc->driver && udc->softconnect && udc->vbus_active;
1166 }
1167
1168 /* Notify controller that VBUS is powered, Called by whatever
1169 detects VBUS sessions */
fsl_vbus_session(struct usb_gadget * gadget,int is_active)1170 static int fsl_vbus_session(struct usb_gadget *gadget, int is_active)
1171 {
1172 struct fsl_udc *udc;
1173 unsigned long flags;
1174
1175 udc = container_of(gadget, struct fsl_udc, gadget);
1176 spin_lock_irqsave(&udc->lock, flags);
1177 dev_vdbg(udc->dev, "VBUS %s\n", str_on_off(is_active));
1178 udc->vbus_active = (is_active != 0);
1179 if (can_pullup(udc))
1180 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1181 &dr_regs->usbcmd);
1182 else
1183 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1184 &dr_regs->usbcmd);
1185 spin_unlock_irqrestore(&udc->lock, flags);
1186 return 0;
1187 }
1188
1189 /* constrain controller's VBUS power usage
1190 * This call is used by gadget drivers during SET_CONFIGURATION calls,
1191 * reporting how much power the device may consume. For example, this
1192 * could affect how quickly batteries are recharged.
1193 *
1194 * Returns zero on success, else negative errno.
1195 */
fsl_vbus_draw(struct usb_gadget * gadget,unsigned mA)1196 static int fsl_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1197 {
1198 struct fsl_udc *udc;
1199
1200 udc = container_of(gadget, struct fsl_udc, gadget);
1201 if (!IS_ERR_OR_NULL(udc->transceiver))
1202 return usb_phy_set_power(udc->transceiver, mA);
1203 return -ENOTSUPP;
1204 }
1205
1206 /* Change Data+ pullup status
1207 * this func is used by usb_gadget_connect/disconnect
1208 */
fsl_pullup(struct usb_gadget * gadget,int is_on)1209 static int fsl_pullup(struct usb_gadget *gadget, int is_on)
1210 {
1211 struct fsl_udc *udc;
1212
1213 udc = container_of(gadget, struct fsl_udc, gadget);
1214
1215 if (!udc->vbus_active)
1216 return -EOPNOTSUPP;
1217
1218 udc->softconnect = (is_on != 0);
1219 if (can_pullup(udc))
1220 fsl_writel((fsl_readl(&dr_regs->usbcmd) | USB_CMD_RUN_STOP),
1221 &dr_regs->usbcmd);
1222 else
1223 fsl_writel((fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP),
1224 &dr_regs->usbcmd);
1225
1226 return 0;
1227 }
1228
1229 static int fsl_udc_start(struct usb_gadget *g,
1230 struct usb_gadget_driver *driver);
1231 static int fsl_udc_stop(struct usb_gadget *g);
1232
1233 static const struct usb_gadget_ops fsl_gadget_ops = {
1234 .get_frame = fsl_get_frame,
1235 .wakeup = fsl_wakeup,
1236 /* .set_selfpowered = fsl_set_selfpowered, */ /* Always selfpowered */
1237 .vbus_session = fsl_vbus_session,
1238 .vbus_draw = fsl_vbus_draw,
1239 .pullup = fsl_pullup,
1240 .udc_start = fsl_udc_start,
1241 .udc_stop = fsl_udc_stop,
1242 };
1243
1244 /*
1245 * Empty complete function used by this driver to fill in the req->complete
1246 * field when creating a request since the complete field is mandatory.
1247 */
fsl_noop_complete(struct usb_ep * ep,struct usb_request * req)1248 static void fsl_noop_complete(struct usb_ep *ep, struct usb_request *req) { }
1249
1250 /* Set protocol stall on ep0, protocol stall will automatically be cleared
1251 on new transaction */
ep0stall(struct fsl_udc * udc)1252 static void ep0stall(struct fsl_udc *udc)
1253 {
1254 u32 tmp;
1255
1256 /* must set tx and rx to stall at the same time */
1257 tmp = fsl_readl(&dr_regs->endptctrl[0]);
1258 tmp |= EPCTRL_TX_EP_STALL | EPCTRL_RX_EP_STALL;
1259 fsl_writel(tmp, &dr_regs->endptctrl[0]);
1260 udc->ep0_state = WAIT_FOR_SETUP;
1261 udc->ep0_dir = 0;
1262 }
1263
1264 /* Prime a status phase for ep0 */
ep0_prime_status(struct fsl_udc * udc,int direction)1265 static int ep0_prime_status(struct fsl_udc *udc, int direction)
1266 {
1267 struct fsl_req *req = udc->status_req;
1268 struct fsl_ep *ep;
1269 int ret;
1270
1271 if (direction == EP_DIR_IN)
1272 udc->ep0_dir = USB_DIR_IN;
1273 else
1274 udc->ep0_dir = USB_DIR_OUT;
1275
1276 ep = &udc->eps[0];
1277 if (udc->ep0_state != DATA_STATE_XMIT)
1278 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1279
1280 req->ep = ep;
1281 req->req.length = 0;
1282 req->req.status = -EINPROGRESS;
1283 req->req.actual = 0;
1284 req->req.complete = fsl_noop_complete;
1285 req->dtd_count = 0;
1286
1287 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1288 if (ret)
1289 return ret;
1290
1291 if (fsl_req_to_dtd(req, GFP_ATOMIC) == 0)
1292 fsl_queue_td(ep, req);
1293 else
1294 return -ENOMEM;
1295
1296 list_add_tail(&req->queue, &ep->queue);
1297
1298 return 0;
1299 }
1300
udc_reset_ep_queue(struct fsl_udc * udc,u8 pipe)1301 static void udc_reset_ep_queue(struct fsl_udc *udc, u8 pipe)
1302 {
1303 struct fsl_ep *ep = get_ep_by_pipe(udc, pipe);
1304
1305 if (ep->ep.name)
1306 nuke(ep, -ESHUTDOWN);
1307 }
1308
1309 /*
1310 * ch9 Set address
1311 */
ch9setaddress(struct fsl_udc * udc,u16 value,u16 index,u16 length)1312 static void ch9setaddress(struct fsl_udc *udc, u16 value, u16 index, u16 length)
1313 {
1314 /* Save the new address to device struct */
1315 udc->device_address = (u8) value;
1316 /* Update usb state */
1317 udc->usb_state = USB_STATE_ADDRESS;
1318 /* Status phase */
1319 if (ep0_prime_status(udc, EP_DIR_IN))
1320 ep0stall(udc);
1321 }
1322
1323 /*
1324 * ch9 Get status
1325 */
ch9getstatus(struct fsl_udc * udc,u8 request_type,u16 value,u16 index,u16 length)1326 static void ch9getstatus(struct fsl_udc *udc, u8 request_type, u16 value,
1327 u16 index, u16 length)
1328 {
1329 u16 tmp = 0; /* Status, cpu endian */
1330 struct fsl_req *req;
1331 struct fsl_ep *ep;
1332 int ret;
1333
1334 ep = &udc->eps[0];
1335
1336 if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
1337 /* Get device status */
1338 tmp = udc->gadget.is_selfpowered;
1339 tmp |= udc->remote_wakeup << USB_DEVICE_REMOTE_WAKEUP;
1340 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
1341 /* Get interface status */
1342 /* We don't have interface information in udc driver */
1343 tmp = 0;
1344 } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
1345 /* Get endpoint status */
1346 struct fsl_ep *target_ep;
1347
1348 target_ep = get_ep_by_pipe(udc, get_pipe_by_windex(index));
1349
1350 /* stall if endpoint doesn't exist */
1351 if (!target_ep->ep.desc)
1352 goto stall;
1353 tmp = dr_ep_get_stall(ep_index(target_ep), ep_is_in(target_ep))
1354 << USB_ENDPOINT_HALT;
1355 }
1356
1357 udc->ep0_dir = USB_DIR_IN;
1358 /* Borrow the per device status_req */
1359 req = udc->status_req;
1360 /* Fill in the request structure */
1361 *((u16 *) req->req.buf) = cpu_to_le16(tmp);
1362
1363 req->ep = ep;
1364 req->req.length = 2;
1365 req->req.status = -EINPROGRESS;
1366 req->req.actual = 0;
1367 req->req.complete = fsl_noop_complete;
1368 req->dtd_count = 0;
1369
1370 ret = usb_gadget_map_request(&ep->udc->gadget, &req->req, ep_is_in(ep));
1371 if (ret)
1372 goto stall;
1373
1374 /* prime the data phase */
1375 if ((fsl_req_to_dtd(req, GFP_ATOMIC) == 0))
1376 fsl_queue_td(ep, req);
1377 else /* no mem */
1378 goto stall;
1379
1380 list_add_tail(&req->queue, &ep->queue);
1381 udc->ep0_state = DATA_STATE_XMIT;
1382 if (ep0_prime_status(udc, EP_DIR_OUT))
1383 ep0stall(udc);
1384
1385 return;
1386 stall:
1387 ep0stall(udc);
1388 }
1389
setup_received_irq(struct fsl_udc * udc,struct usb_ctrlrequest * setup)1390 static void setup_received_irq(struct fsl_udc *udc,
1391 struct usb_ctrlrequest *setup)
1392 __releases(udc->lock)
1393 __acquires(udc->lock)
1394 {
1395 u16 wValue = le16_to_cpu(setup->wValue);
1396 u16 wIndex = le16_to_cpu(setup->wIndex);
1397 u16 wLength = le16_to_cpu(setup->wLength);
1398
1399 udc_reset_ep_queue(udc, 0);
1400
1401 /* We process some stardard setup requests here */
1402 switch (setup->bRequest) {
1403 case USB_REQ_GET_STATUS:
1404 /* Data+Status phase from udc */
1405 if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
1406 != (USB_DIR_IN | USB_TYPE_STANDARD))
1407 break;
1408 ch9getstatus(udc, setup->bRequestType, wValue, wIndex, wLength);
1409 return;
1410
1411 case USB_REQ_SET_ADDRESS:
1412 /* Status phase from udc */
1413 if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
1414 | USB_RECIP_DEVICE))
1415 break;
1416 ch9setaddress(udc, wValue, wIndex, wLength);
1417 return;
1418
1419 case USB_REQ_CLEAR_FEATURE:
1420 case USB_REQ_SET_FEATURE:
1421 /* Status phase from udc */
1422 {
1423 int rc = -EOPNOTSUPP;
1424 u16 ptc = 0;
1425
1426 if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
1427 == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
1428 int pipe = get_pipe_by_windex(wIndex);
1429 struct fsl_ep *ep;
1430
1431 if (wValue != 0 || wLength != 0 || pipe >= udc->max_ep)
1432 break;
1433 ep = get_ep_by_pipe(udc, pipe);
1434
1435 spin_unlock(&udc->lock);
1436 rc = fsl_ep_set_halt(&ep->ep,
1437 (setup->bRequest == USB_REQ_SET_FEATURE)
1438 ? 1 : 0);
1439 spin_lock(&udc->lock);
1440
1441 } else if ((setup->bRequestType & (USB_RECIP_MASK
1442 | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
1443 | USB_TYPE_STANDARD)) {
1444 /* Note: The driver has not include OTG support yet.
1445 * This will be set when OTG support is added */
1446 if (wValue == USB_DEVICE_TEST_MODE)
1447 ptc = wIndex >> 8;
1448 else if (gadget_is_otg(&udc->gadget)) {
1449 if (setup->bRequest ==
1450 USB_DEVICE_B_HNP_ENABLE)
1451 udc->gadget.b_hnp_enable = 1;
1452 else if (setup->bRequest ==
1453 USB_DEVICE_A_HNP_SUPPORT)
1454 udc->gadget.a_hnp_support = 1;
1455 else if (setup->bRequest ==
1456 USB_DEVICE_A_ALT_HNP_SUPPORT)
1457 udc->gadget.a_alt_hnp_support = 1;
1458 }
1459 rc = 0;
1460 } else
1461 break;
1462
1463 if (rc == 0) {
1464 if (ep0_prime_status(udc, EP_DIR_IN))
1465 ep0stall(udc);
1466 }
1467 if (ptc) {
1468 u32 tmp;
1469
1470 mdelay(10);
1471 tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
1472 fsl_writel(tmp, &dr_regs->portsc1);
1473 printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
1474 }
1475
1476 return;
1477 }
1478
1479 default:
1480 break;
1481 }
1482
1483 /* Requests handled by gadget */
1484 if (wLength) {
1485 /* Data phase from gadget, status phase from udc */
1486 udc->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1487 ? USB_DIR_IN : USB_DIR_OUT;
1488 spin_unlock(&udc->lock);
1489 if (udc->driver->setup(&udc->gadget,
1490 &udc->local_setup_buff) < 0)
1491 ep0stall(udc);
1492 spin_lock(&udc->lock);
1493 udc->ep0_state = (setup->bRequestType & USB_DIR_IN)
1494 ? DATA_STATE_XMIT : DATA_STATE_RECV;
1495 /*
1496 * If the data stage is IN, send status prime immediately.
1497 * See 2.0 Spec chapter 8.5.3.3 for detail.
1498 */
1499 if (udc->ep0_state == DATA_STATE_XMIT)
1500 if (ep0_prime_status(udc, EP_DIR_OUT))
1501 ep0stall(udc);
1502
1503 } else {
1504 /* No data phase, IN status from gadget */
1505 udc->ep0_dir = USB_DIR_IN;
1506 spin_unlock(&udc->lock);
1507 if (udc->driver->setup(&udc->gadget,
1508 &udc->local_setup_buff) < 0)
1509 ep0stall(udc);
1510 spin_lock(&udc->lock);
1511 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1512 }
1513 }
1514
1515 /* Process request for Data or Status phase of ep0
1516 * prime status phase if needed */
ep0_req_complete(struct fsl_udc * udc,struct fsl_ep * ep0,struct fsl_req * req)1517 static void ep0_req_complete(struct fsl_udc *udc, struct fsl_ep *ep0,
1518 struct fsl_req *req)
1519 {
1520 if (udc->usb_state == USB_STATE_ADDRESS) {
1521 /* Set the new address */
1522 u32 new_address = (u32) udc->device_address;
1523 fsl_writel(new_address << USB_DEVICE_ADDRESS_BIT_POS,
1524 &dr_regs->deviceaddr);
1525 }
1526
1527 done(ep0, req, 0);
1528
1529 switch (udc->ep0_state) {
1530 case DATA_STATE_XMIT:
1531 /* already primed at setup_received_irq */
1532 udc->ep0_state = WAIT_FOR_OUT_STATUS;
1533 break;
1534 case DATA_STATE_RECV:
1535 /* send status phase */
1536 if (ep0_prime_status(udc, EP_DIR_IN))
1537 ep0stall(udc);
1538 break;
1539 case WAIT_FOR_OUT_STATUS:
1540 udc->ep0_state = WAIT_FOR_SETUP;
1541 break;
1542 case WAIT_FOR_SETUP:
1543 dev_err(udc->dev, "Unexpected ep0 packets\n");
1544 break;
1545 default:
1546 ep0stall(udc);
1547 break;
1548 }
1549 }
1550
1551 /* Tripwire mechanism to ensure a setup packet payload is extracted without
1552 * being corrupted by another incoming setup packet */
tripwire_handler(struct fsl_udc * udc,u8 ep_num,u8 * buffer_ptr)1553 static void tripwire_handler(struct fsl_udc *udc, u8 ep_num, u8 *buffer_ptr)
1554 {
1555 u32 temp;
1556 struct ep_queue_head *qh;
1557 struct fsl_usb2_platform_data *pdata = udc->pdata;
1558
1559 qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
1560
1561 /* Clear bit in ENDPTSETUPSTAT */
1562 temp = fsl_readl(&dr_regs->endptsetupstat);
1563 fsl_writel(temp | (1 << ep_num), &dr_regs->endptsetupstat);
1564
1565 /* while a hazard exists when setup package arrives */
1566 do {
1567 /* Set Setup Tripwire */
1568 temp = fsl_readl(&dr_regs->usbcmd);
1569 fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
1570
1571 /* Copy the setup packet to local buffer */
1572 if (pdata->le_setup_buf) {
1573 u32 *p = (u32 *)buffer_ptr;
1574 u32 *s = (u32 *)qh->setup_buffer;
1575
1576 /* Convert little endian setup buffer to CPU endian */
1577 *p++ = le32_to_cpu(*s++);
1578 *p = le32_to_cpu(*s);
1579 } else {
1580 memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
1581 }
1582 } while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
1583
1584 /* Clear Setup Tripwire */
1585 temp = fsl_readl(&dr_regs->usbcmd);
1586 fsl_writel(temp & ~USB_CMD_SUTW, &dr_regs->usbcmd);
1587 }
1588
1589 /* process-ep_req(): free the completed Tds for this req */
process_ep_req(struct fsl_udc * udc,int pipe,struct fsl_req * curr_req)1590 static int process_ep_req(struct fsl_udc *udc, int pipe,
1591 struct fsl_req *curr_req)
1592 {
1593 struct ep_td_struct *curr_td;
1594 int actual, remaining_length, j, tmp;
1595 int status = 0;
1596 int errors = 0;
1597 struct ep_queue_head *curr_qh = &udc->ep_qh[pipe];
1598 int direction = pipe % 2;
1599
1600 curr_td = curr_req->head;
1601 actual = curr_req->req.length;
1602
1603 for (j = 0; j < curr_req->dtd_count; j++) {
1604 remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
1605 & DTD_PACKET_SIZE)
1606 >> DTD_LENGTH_BIT_POS;
1607 actual -= remaining_length;
1608
1609 errors = hc32_to_cpu(curr_td->size_ioc_sts);
1610 if (errors & DTD_ERROR_MASK) {
1611 if (errors & DTD_STATUS_HALTED) {
1612 dev_err(udc->dev, "dTD error %08x QH=%d\n", errors, pipe);
1613 /* Clear the errors and Halt condition */
1614 tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
1615 tmp &= ~errors;
1616 curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
1617 status = -EPIPE;
1618 /* FIXME: continue with next queued TD? */
1619
1620 break;
1621 }
1622 if (errors & DTD_STATUS_DATA_BUFF_ERR) {
1623 dev_vdbg(udc->dev, "Transfer overflow\n");
1624 status = -EPROTO;
1625 break;
1626 } else if (errors & DTD_STATUS_TRANSACTION_ERR) {
1627 dev_vdbg(udc->dev, "ISO error\n");
1628 status = -EILSEQ;
1629 break;
1630 } else
1631 dev_err(udc->dev,
1632 "Unknown error has occurred (0x%x)!\n",
1633 errors);
1634
1635 } else if (hc32_to_cpu(curr_td->size_ioc_sts)
1636 & DTD_STATUS_ACTIVE) {
1637 dev_vdbg(udc->dev, "Request not complete\n");
1638 status = REQ_UNCOMPLETE;
1639 return status;
1640 } else if (remaining_length) {
1641 if (direction) {
1642 dev_vdbg(udc->dev,
1643 "Transmit dTD remaining length not zero\n");
1644 status = -EPROTO;
1645 break;
1646 } else {
1647 break;
1648 }
1649 } else {
1650 dev_vdbg(udc->dev, "dTD transmitted successful\n");
1651 }
1652
1653 if (j != curr_req->dtd_count - 1)
1654 curr_td = (struct ep_td_struct *)curr_td->next_td_virt;
1655 }
1656
1657 if (status)
1658 return status;
1659
1660 curr_req->req.actual = actual;
1661
1662 return 0;
1663 }
1664
1665 /* Process a DTD completion interrupt */
dtd_complete_irq(struct fsl_udc * udc)1666 static void dtd_complete_irq(struct fsl_udc *udc)
1667 {
1668 u32 bit_pos;
1669 int i, ep_num, direction, bit_mask, status;
1670 struct fsl_ep *curr_ep;
1671 struct fsl_req *curr_req, *temp_req;
1672
1673 /* Clear the bits in the register */
1674 bit_pos = fsl_readl(&dr_regs->endptcomplete);
1675 fsl_writel(bit_pos, &dr_regs->endptcomplete);
1676
1677 if (!bit_pos)
1678 return;
1679
1680 for (i = 0; i < udc->max_ep; i++) {
1681 ep_num = i >> 1;
1682 direction = i % 2;
1683
1684 bit_mask = 1 << (ep_num + 16 * direction);
1685
1686 if (!(bit_pos & bit_mask))
1687 continue;
1688
1689 curr_ep = get_ep_by_pipe(udc, i);
1690
1691 /* If the ep is configured */
1692 if (!curr_ep->ep.name) {
1693 dev_warn(udc->dev, "Invalid EP?\n");
1694 continue;
1695 }
1696
1697 /* process the req queue until an uncomplete request */
1698 list_for_each_entry_safe(curr_req, temp_req, &curr_ep->queue,
1699 queue) {
1700 status = process_ep_req(udc, i, curr_req);
1701
1702 dev_vdbg(udc->dev,
1703 "status of process_ep_req= %d, ep = %d\n",
1704 status, ep_num);
1705 if (status == REQ_UNCOMPLETE)
1706 break;
1707 /* write back status to req */
1708 curr_req->req.status = status;
1709
1710 if (ep_num == 0) {
1711 ep0_req_complete(udc, curr_ep, curr_req);
1712 break;
1713 } else
1714 done(curr_ep, curr_req, status);
1715 }
1716 }
1717 }
1718
portscx_device_speed(u32 reg)1719 static inline enum usb_device_speed portscx_device_speed(u32 reg)
1720 {
1721 switch (reg & PORTSCX_PORT_SPEED_MASK) {
1722 case PORTSCX_PORT_SPEED_HIGH:
1723 return USB_SPEED_HIGH;
1724 case PORTSCX_PORT_SPEED_FULL:
1725 return USB_SPEED_FULL;
1726 case PORTSCX_PORT_SPEED_LOW:
1727 return USB_SPEED_LOW;
1728 default:
1729 return USB_SPEED_UNKNOWN;
1730 }
1731 }
1732
1733 /* Process a port change interrupt */
port_change_irq(struct fsl_udc * udc)1734 static void port_change_irq(struct fsl_udc *udc)
1735 {
1736 if (udc->bus_reset)
1737 udc->bus_reset = 0;
1738
1739 /* Bus resetting is finished */
1740 if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET))
1741 /* Get the speed */
1742 udc->gadget.speed =
1743 portscx_device_speed(fsl_readl(&dr_regs->portsc1));
1744
1745 /* Update USB state */
1746 if (!udc->resume_state)
1747 udc->usb_state = USB_STATE_DEFAULT;
1748 }
1749
1750 /* Process suspend interrupt */
suspend_irq(struct fsl_udc * udc)1751 static void suspend_irq(struct fsl_udc *udc)
1752 {
1753 udc->resume_state = udc->usb_state;
1754 udc->usb_state = USB_STATE_SUSPENDED;
1755
1756 /* report suspend to the driver, serial.c does not support this */
1757 if (udc->driver->suspend)
1758 udc->driver->suspend(&udc->gadget);
1759 }
1760
bus_resume(struct fsl_udc * udc)1761 static void bus_resume(struct fsl_udc *udc)
1762 {
1763 udc->usb_state = udc->resume_state;
1764 udc->resume_state = 0;
1765
1766 /* report resume to the driver, serial.c does not support this */
1767 if (udc->driver->resume)
1768 udc->driver->resume(&udc->gadget);
1769 }
1770
1771 /* Clear up all ep queues */
reset_queues(struct fsl_udc * udc,bool bus_reset)1772 static int reset_queues(struct fsl_udc *udc, bool bus_reset)
1773 {
1774 u8 pipe;
1775
1776 for (pipe = 0; pipe < udc->max_pipes; pipe++)
1777 udc_reset_ep_queue(udc, pipe);
1778
1779 /* report disconnect; the driver is already quiesced */
1780 spin_unlock(&udc->lock);
1781 if (bus_reset)
1782 usb_gadget_udc_reset(&udc->gadget, udc->driver);
1783 else
1784 udc->driver->disconnect(&udc->gadget);
1785 spin_lock(&udc->lock);
1786
1787 return 0;
1788 }
1789
1790 /* Process reset interrupt */
reset_irq(struct fsl_udc * udc)1791 static void reset_irq(struct fsl_udc *udc)
1792 {
1793 u32 temp;
1794 unsigned long timeout;
1795
1796 /* Clear the device address */
1797 temp = fsl_readl(&dr_regs->deviceaddr);
1798 fsl_writel(temp & ~USB_DEVICE_ADDRESS_MASK, &dr_regs->deviceaddr);
1799
1800 udc->device_address = 0;
1801
1802 /* Clear usb state */
1803 udc->resume_state = 0;
1804 udc->ep0_dir = 0;
1805 udc->ep0_state = WAIT_FOR_SETUP;
1806 udc->remote_wakeup = 0; /* default to 0 on reset */
1807 udc->gadget.b_hnp_enable = 0;
1808 udc->gadget.a_hnp_support = 0;
1809 udc->gadget.a_alt_hnp_support = 0;
1810
1811 /* Clear all the setup token semaphores */
1812 temp = fsl_readl(&dr_regs->endptsetupstat);
1813 fsl_writel(temp, &dr_regs->endptsetupstat);
1814
1815 /* Clear all the endpoint complete status bits */
1816 temp = fsl_readl(&dr_regs->endptcomplete);
1817 fsl_writel(temp, &dr_regs->endptcomplete);
1818
1819 timeout = jiffies + 100;
1820 while (fsl_readl(&dr_regs->endpointprime)) {
1821 /* Wait until all endptprime bits cleared */
1822 if (time_after(jiffies, timeout)) {
1823 dev_err(udc->dev, "Timeout for reset\n");
1824 break;
1825 }
1826 cpu_relax();
1827 }
1828
1829 /* Write 1s to the flush register */
1830 fsl_writel(0xffffffff, &dr_regs->endptflush);
1831
1832 if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
1833 dev_vdbg(udc->dev, "Bus reset\n");
1834 /* Bus is reseting */
1835 udc->bus_reset = 1;
1836 /* Reset all the queues, include XD, dTD, EP queue
1837 * head and TR Queue */
1838 reset_queues(udc, true);
1839 udc->usb_state = USB_STATE_DEFAULT;
1840 } else {
1841 dev_vdbg(udc->dev, "Controller reset\n");
1842 /* initialize usb hw reg except for regs for EP, not
1843 * touch usbintr reg */
1844 dr_controller_setup(udc);
1845
1846 /* Reset all internal used Queues */
1847 reset_queues(udc, false);
1848
1849 ep0_setup(udc);
1850
1851 /* Enable DR IRQ reg, Set Run bit, change udc state */
1852 dr_controller_run(udc);
1853 udc->usb_state = USB_STATE_ATTACHED;
1854 }
1855 }
1856
1857 /*
1858 * USB device controller interrupt handler
1859 */
fsl_udc_irq(int irq,void * _udc)1860 static irqreturn_t fsl_udc_irq(int irq, void *_udc)
1861 {
1862 struct fsl_udc *udc = _udc;
1863 u32 irq_src;
1864 irqreturn_t status = IRQ_NONE;
1865 unsigned long flags;
1866
1867 /* Disable ISR for OTG host mode */
1868 if (udc->stopped)
1869 return IRQ_NONE;
1870 spin_lock_irqsave(&udc->lock, flags);
1871 irq_src = fsl_readl(&dr_regs->usbsts) & fsl_readl(&dr_regs->usbintr);
1872 /* Clear notification bits */
1873 fsl_writel(irq_src, &dr_regs->usbsts);
1874
1875 /* dev_vdbg(udc->dev, "irq_src [0x%8x]", irq_src); */
1876
1877 /* Need to resume? */
1878 if (udc->usb_state == USB_STATE_SUSPENDED)
1879 if ((fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_SUSPEND) == 0)
1880 bus_resume(udc);
1881
1882 /* USB Interrupt */
1883 if (irq_src & USB_STS_INT) {
1884 dev_vdbg(udc->dev, "Packet int\n");
1885 /* Setup package, we only support ep0 as control ep */
1886 if (fsl_readl(&dr_regs->endptsetupstat) & EP_SETUP_STATUS_EP0) {
1887 tripwire_handler(udc, 0,
1888 (u8 *) (&udc->local_setup_buff));
1889 setup_received_irq(udc, &udc->local_setup_buff);
1890 status = IRQ_HANDLED;
1891 }
1892
1893 /* completion of dtd */
1894 if (fsl_readl(&dr_regs->endptcomplete)) {
1895 dtd_complete_irq(udc);
1896 status = IRQ_HANDLED;
1897 }
1898 }
1899
1900 /* SOF (for ISO transfer) */
1901 if (irq_src & USB_STS_SOF) {
1902 status = IRQ_HANDLED;
1903 }
1904
1905 /* Port Change */
1906 if (irq_src & USB_STS_PORT_CHANGE) {
1907 port_change_irq(udc);
1908 status = IRQ_HANDLED;
1909 }
1910
1911 /* Reset Received */
1912 if (irq_src & USB_STS_RESET) {
1913 dev_vdbg(udc->dev, "reset int\n");
1914 reset_irq(udc);
1915 status = IRQ_HANDLED;
1916 }
1917
1918 /* Sleep Enable (Suspend) */
1919 if (irq_src & USB_STS_SUSPEND) {
1920 suspend_irq(udc);
1921 status = IRQ_HANDLED;
1922 }
1923
1924 if (irq_src & (USB_STS_ERR | USB_STS_SYS_ERR)) {
1925 dev_vdbg(udc->dev, "Error IRQ %x\n", irq_src);
1926 }
1927
1928 spin_unlock_irqrestore(&udc->lock, flags);
1929 return status;
1930 }
1931
1932 /*----------------------------------------------------------------*
1933 * Hook to gadget drivers
1934 * Called by initialization code of gadget drivers
1935 *----------------------------------------------------------------*/
fsl_udc_start(struct usb_gadget * g,struct usb_gadget_driver * driver)1936 static int fsl_udc_start(struct usb_gadget *g,
1937 struct usb_gadget_driver *driver)
1938 {
1939 int retval = 0;
1940 unsigned long flags;
1941
1942 /* lock is needed but whether should use this lock or another */
1943 spin_lock_irqsave(&udc_controller->lock, flags);
1944
1945 /* hook up the driver */
1946 udc_controller->driver = driver;
1947 spin_unlock_irqrestore(&udc_controller->lock, flags);
1948 g->is_selfpowered = 1;
1949
1950 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1951 /* Suspend the controller until OTG enable it */
1952 udc_controller->stopped = 1;
1953 printk(KERN_INFO "Suspend udc for OTG auto detect\n");
1954
1955 /* connect to bus through transceiver */
1956 if (!IS_ERR_OR_NULL(udc_controller->transceiver)) {
1957 retval = otg_set_peripheral(
1958 udc_controller->transceiver->otg,
1959 &udc_controller->gadget);
1960 if (retval < 0) {
1961 dev_err(udc_controller->dev, "can't bind to transceiver\n");
1962 udc_controller->driver = NULL;
1963 return retval;
1964 }
1965 }
1966 } else {
1967 /* Enable DR IRQ reg and set USBCMD reg Run bit */
1968 dr_controller_run(udc_controller);
1969 udc_controller->usb_state = USB_STATE_ATTACHED;
1970 udc_controller->ep0_state = WAIT_FOR_SETUP;
1971 udc_controller->ep0_dir = 0;
1972 }
1973
1974 return retval;
1975 }
1976
1977 /* Disconnect from gadget driver */
fsl_udc_stop(struct usb_gadget * g)1978 static int fsl_udc_stop(struct usb_gadget *g)
1979 {
1980 struct fsl_ep *loop_ep;
1981 unsigned long flags;
1982
1983 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
1984 otg_set_peripheral(udc_controller->transceiver->otg, NULL);
1985
1986 /* stop DR, disable intr */
1987 dr_controller_stop(udc_controller);
1988
1989 /* in fact, no needed */
1990 udc_controller->usb_state = USB_STATE_ATTACHED;
1991 udc_controller->ep0_state = WAIT_FOR_SETUP;
1992 udc_controller->ep0_dir = 0;
1993
1994 /* stand operation */
1995 spin_lock_irqsave(&udc_controller->lock, flags);
1996 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
1997 nuke(&udc_controller->eps[0], -ESHUTDOWN);
1998 list_for_each_entry(loop_ep, &udc_controller->gadget.ep_list,
1999 ep.ep_list)
2000 nuke(loop_ep, -ESHUTDOWN);
2001 spin_unlock_irqrestore(&udc_controller->lock, flags);
2002
2003 udc_controller->driver = NULL;
2004
2005 return 0;
2006 }
2007
2008 /*-------------------------------------------------------------------------
2009 PROC File System Support
2010 -------------------------------------------------------------------------*/
2011 #ifdef CONFIG_USB_GADGET_DEBUG_FILES
2012
2013 #include <linux/seq_file.h>
2014
2015 static const char proc_filename[] = "driver/fsl_usb2_udc";
2016
fsl_proc_read(struct seq_file * m,void * v)2017 static int fsl_proc_read(struct seq_file *m, void *v)
2018 {
2019 unsigned long flags;
2020 int i;
2021 u32 tmp_reg;
2022 struct fsl_ep *ep = NULL;
2023 struct fsl_req *req;
2024
2025 struct fsl_udc *udc = udc_controller;
2026
2027 spin_lock_irqsave(&udc->lock, flags);
2028
2029 /* ------basic driver information ---- */
2030 seq_printf(m,
2031 DRIVER_DESC "\n"
2032 "%s version: %s\n"
2033 "Gadget driver: %s\n\n",
2034 driver_name, DRIVER_VERSION,
2035 udc->driver ? udc->driver->driver.name : "(none)");
2036
2037 /* ------ DR Registers ----- */
2038 tmp_reg = fsl_readl(&dr_regs->usbcmd);
2039 seq_printf(m,
2040 "USBCMD reg:\n"
2041 "SetupTW: %d\n"
2042 "Run/Stop: %s\n\n",
2043 (tmp_reg & USB_CMD_SUTW) ? 1 : 0,
2044 (tmp_reg & USB_CMD_RUN_STOP) ? "Run" : "Stop");
2045
2046 tmp_reg = fsl_readl(&dr_regs->usbsts);
2047 seq_printf(m,
2048 "USB Status Reg:\n"
2049 "Dr Suspend: %d Reset Received: %d System Error: %s "
2050 "USB Error Interrupt: %s\n\n",
2051 (tmp_reg & USB_STS_SUSPEND) ? 1 : 0,
2052 (tmp_reg & USB_STS_RESET) ? 1 : 0,
2053 (tmp_reg & USB_STS_SYS_ERR) ? "Err" : "Normal",
2054 (tmp_reg & USB_STS_ERR) ? "Err detected" : "No err");
2055
2056 tmp_reg = fsl_readl(&dr_regs->usbintr);
2057 seq_printf(m,
2058 "USB Interrupt Enable Reg:\n"
2059 "Sleep Enable: %d SOF Received Enable: %d "
2060 "Reset Enable: %d\n"
2061 "System Error Enable: %d "
2062 "Port Change Detected Enable: %d\n"
2063 "USB Error Intr Enable: %d USB Intr Enable: %d\n\n",
2064 (tmp_reg & USB_INTR_DEVICE_SUSPEND) ? 1 : 0,
2065 (tmp_reg & USB_INTR_SOF_EN) ? 1 : 0,
2066 (tmp_reg & USB_INTR_RESET_EN) ? 1 : 0,
2067 (tmp_reg & USB_INTR_SYS_ERR_EN) ? 1 : 0,
2068 (tmp_reg & USB_INTR_PTC_DETECT_EN) ? 1 : 0,
2069 (tmp_reg & USB_INTR_ERR_INT_EN) ? 1 : 0,
2070 (tmp_reg & USB_INTR_INT_EN) ? 1 : 0);
2071
2072 tmp_reg = fsl_readl(&dr_regs->frindex);
2073 seq_printf(m,
2074 "USB Frame Index Reg: Frame Number is 0x%x\n\n",
2075 (tmp_reg & USB_FRINDEX_MASKS));
2076
2077 tmp_reg = fsl_readl(&dr_regs->deviceaddr);
2078 seq_printf(m,
2079 "USB Device Address Reg: Device Addr is 0x%x\n\n",
2080 (tmp_reg & USB_DEVICE_ADDRESS_MASK));
2081
2082 tmp_reg = fsl_readl(&dr_regs->endpointlistaddr);
2083 seq_printf(m,
2084 "USB Endpoint List Address Reg: "
2085 "Device Addr is 0x%x\n\n",
2086 (tmp_reg & USB_EP_LIST_ADDRESS_MASK));
2087
2088 tmp_reg = fsl_readl(&dr_regs->portsc1);
2089 seq_printf(m,
2090 "USB Port Status&Control Reg:\n"
2091 "Port Transceiver Type : %s Port Speed: %s\n"
2092 "PHY Low Power Suspend: %s Port Reset: %s "
2093 "Port Suspend Mode: %s\n"
2094 "Over-current Change: %s "
2095 "Port Enable/Disable Change: %s\n"
2096 "Port Enabled/Disabled: %s "
2097 "Current Connect Status: %s\n\n", ( {
2098 const char *s;
2099 switch (tmp_reg & PORTSCX_PTS_FSLS) {
2100 case PORTSCX_PTS_UTMI:
2101 s = "UTMI"; break;
2102 case PORTSCX_PTS_ULPI:
2103 s = "ULPI "; break;
2104 case PORTSCX_PTS_FSLS:
2105 s = "FS/LS Serial"; break;
2106 default:
2107 s = "None"; break;
2108 }
2109 s;} ),
2110 usb_speed_string(portscx_device_speed(tmp_reg)),
2111 (tmp_reg & PORTSCX_PHY_LOW_POWER_SPD) ?
2112 "Normal PHY mode" : "Low power mode",
2113 (tmp_reg & PORTSCX_PORT_RESET) ? "In Reset" :
2114 "Not in Reset",
2115 (tmp_reg & PORTSCX_PORT_SUSPEND) ? "In " : "Not in",
2116 (tmp_reg & PORTSCX_OVER_CURRENT_CHG) ? "Dected" :
2117 "No",
2118 (tmp_reg & PORTSCX_PORT_EN_DIS_CHANGE) ? "Disable" :
2119 "Not change",
2120 (tmp_reg & PORTSCX_PORT_ENABLE) ? "Enable" :
2121 "Not correct",
2122 (tmp_reg & PORTSCX_CURRENT_CONNECT_STATUS) ?
2123 "Attached" : "Not-Att");
2124
2125 tmp_reg = fsl_readl(&dr_regs->usbmode);
2126 seq_printf(m,
2127 "USB Mode Reg: Controller Mode is: %s\n\n", ( {
2128 const char *s;
2129 switch (tmp_reg & USB_MODE_CTRL_MODE_HOST) {
2130 case USB_MODE_CTRL_MODE_IDLE:
2131 s = "Idle"; break;
2132 case USB_MODE_CTRL_MODE_DEVICE:
2133 s = "Device Controller"; break;
2134 case USB_MODE_CTRL_MODE_HOST:
2135 s = "Host Controller"; break;
2136 default:
2137 s = "None"; break;
2138 }
2139 s;
2140 } ));
2141
2142 tmp_reg = fsl_readl(&dr_regs->endptsetupstat);
2143 seq_printf(m,
2144 "Endpoint Setup Status Reg: SETUP on ep 0x%x\n\n",
2145 (tmp_reg & EP_SETUP_STATUS_MASK));
2146
2147 for (i = 0; i < udc->max_ep / 2; i++) {
2148 tmp_reg = fsl_readl(&dr_regs->endptctrl[i]);
2149 seq_printf(m, "EP Ctrl Reg [0x%x]: = [0x%x]\n", i, tmp_reg);
2150 }
2151 tmp_reg = fsl_readl(&dr_regs->endpointprime);
2152 seq_printf(m, "EP Prime Reg = [0x%x]\n\n", tmp_reg);
2153
2154 if (udc->pdata->have_sysif_regs) {
2155 tmp_reg = usb_sys_regs->snoop1;
2156 seq_printf(m, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
2157
2158 tmp_reg = usb_sys_regs->control;
2159 seq_printf(m, "General Control Reg : = [0x%x]\n\n", tmp_reg);
2160 }
2161
2162 /* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
2163 ep = &udc->eps[0];
2164 seq_printf(m, "For %s Maxpkt is 0x%x index is 0x%x\n",
2165 ep->ep.name, ep_maxpacket(ep), ep_index(ep));
2166
2167 if (list_empty(&ep->queue)) {
2168 seq_puts(m, "its req queue is empty\n\n");
2169 } else {
2170 list_for_each_entry(req, &ep->queue, queue) {
2171 seq_printf(m,
2172 "req %p actual 0x%x length 0x%x buf %p\n",
2173 &req->req, req->req.actual,
2174 req->req.length, req->req.buf);
2175 }
2176 }
2177 /* other gadget->eplist ep */
2178 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) {
2179 if (ep->ep.desc) {
2180 seq_printf(m,
2181 "\nFor %s Maxpkt is 0x%x "
2182 "index is 0x%x\n",
2183 ep->ep.name, ep_maxpacket(ep),
2184 ep_index(ep));
2185
2186 if (list_empty(&ep->queue)) {
2187 seq_puts(m, "its req queue is empty\n\n");
2188 } else {
2189 list_for_each_entry(req, &ep->queue, queue) {
2190 seq_printf(m,
2191 "req %p actual 0x%x length "
2192 "0x%x buf %p\n",
2193 &req->req, req->req.actual,
2194 req->req.length, req->req.buf);
2195 } /* end for each_entry of ep req */
2196 } /* end for else */
2197 } /* end for if(ep->queue) */
2198 } /* end (ep->desc) */
2199
2200 spin_unlock_irqrestore(&udc->lock, flags);
2201 return 0;
2202 }
2203
2204 #define create_proc_file() \
2205 proc_create_single(proc_filename, 0, NULL, fsl_proc_read)
2206 #define remove_proc_file() remove_proc_entry(proc_filename, NULL)
2207
2208 #else /* !CONFIG_USB_GADGET_DEBUG_FILES */
2209
2210 #define create_proc_file() do {} while (0)
2211 #define remove_proc_file() do {} while (0)
2212
2213 #endif /* CONFIG_USB_GADGET_DEBUG_FILES */
2214
2215 /*-------------------------------------------------------------------------*/
2216
2217 /* Release udc structures */
fsl_udc_release(struct device * dev)2218 static void fsl_udc_release(struct device *dev)
2219 {
2220 complete(udc_controller->done);
2221 dma_free_coherent(dev->parent, udc_controller->ep_qh_size,
2222 udc_controller->ep_qh, udc_controller->ep_qh_dma);
2223 kfree(udc_controller);
2224 }
2225
2226 /******************************************************************
2227 Internal structure setup functions
2228 *******************************************************************/
2229 /*------------------------------------------------------------------
2230 * init resource for global controller called by fsl_udc_probe()
2231 * On success the udc handle is initialized, on failure it is
2232 * unchanged (reset).
2233 * Return 0 on success and -1 on allocation failure
2234 ------------------------------------------------------------------*/
struct_udc_setup(struct fsl_udc * udc,struct platform_device * pdev)2235 static int struct_udc_setup(struct fsl_udc *udc,
2236 struct platform_device *pdev)
2237 {
2238 struct fsl_usb2_platform_data *pdata;
2239 size_t size;
2240
2241 pdata = dev_get_platdata(&pdev->dev);
2242 udc->phy_mode = pdata->phy_mode;
2243
2244 udc->eps = kzalloc_objs(struct fsl_ep, udc->max_ep);
2245 if (!udc->eps) {
2246 dev_err(udc->dev, "kmalloc udc endpoint status failed\n");
2247 goto eps_alloc_failed;
2248 }
2249
2250 /* initialized QHs, take care of alignment */
2251 size = udc->max_ep * sizeof(struct ep_queue_head);
2252 if (size < QH_ALIGNMENT)
2253 size = QH_ALIGNMENT;
2254 else if ((size % QH_ALIGNMENT) != 0) {
2255 size += QH_ALIGNMENT + 1;
2256 size &= ~(QH_ALIGNMENT - 1);
2257 }
2258 udc->ep_qh = dma_alloc_coherent(&pdev->dev, size,
2259 &udc->ep_qh_dma, GFP_KERNEL);
2260 if (!udc->ep_qh) {
2261 dev_err(udc->dev, "malloc QHs for udc failed\n");
2262 goto ep_queue_alloc_failed;
2263 }
2264
2265 udc->ep_qh_size = size;
2266
2267 /* Initialize ep0 status request structure */
2268 /* FIXME: fsl_alloc_request() ignores ep argument */
2269 udc->status_req = container_of(fsl_alloc_request(NULL, GFP_KERNEL),
2270 struct fsl_req, req);
2271 if (!udc->status_req) {
2272 dev_err(udc->dev, "kzalloc for udc status request failed\n");
2273 goto udc_status_alloc_failed;
2274 }
2275
2276 /* allocate a small amount of memory to get valid address */
2277 udc->status_req->req.buf = kmalloc(8, GFP_KERNEL);
2278 if (!udc->status_req->req.buf) {
2279 dev_err(udc->dev, "kzalloc for udc request buffer failed\n");
2280 goto udc_req_buf_alloc_failed;
2281 }
2282
2283 udc->resume_state = USB_STATE_NOTATTACHED;
2284 udc->usb_state = USB_STATE_POWERED;
2285 udc->ep0_dir = 0;
2286 udc->remote_wakeup = 0; /* default to 0 on reset */
2287
2288 return 0;
2289
2290 udc_req_buf_alloc_failed:
2291 kfree(udc->status_req);
2292 udc_status_alloc_failed:
2293 kfree(udc->ep_qh);
2294 udc->ep_qh_size = 0;
2295 ep_queue_alloc_failed:
2296 kfree(udc->eps);
2297 eps_alloc_failed:
2298 udc->phy_mode = 0;
2299 return -1;
2300
2301 }
2302
2303 /*----------------------------------------------------------------
2304 * Setup the fsl_ep struct for eps
2305 * Link fsl_ep->ep to gadget->ep_list
2306 * ep0out is not used so do nothing here
2307 * ep0in should be taken care
2308 *--------------------------------------------------------------*/
struct_ep_setup(struct fsl_udc * udc,unsigned char index,char * name,int link)2309 static int struct_ep_setup(struct fsl_udc *udc, unsigned char index,
2310 char *name, int link)
2311 {
2312 struct fsl_ep *ep = &udc->eps[index];
2313
2314 ep->udc = udc;
2315 strcpy(ep->name, name);
2316 ep->ep.name = ep->name;
2317
2318 ep->ep.ops = &fsl_ep_ops;
2319 ep->stopped = 0;
2320
2321 if (index == 0) {
2322 ep->ep.caps.type_control = true;
2323 } else {
2324 ep->ep.caps.type_iso = true;
2325 ep->ep.caps.type_bulk = true;
2326 ep->ep.caps.type_int = true;
2327 }
2328
2329 if (index & 1)
2330 ep->ep.caps.dir_in = true;
2331 else
2332 ep->ep.caps.dir_out = true;
2333
2334 /* for ep0: maxP defined in desc
2335 * for other eps, maxP is set by epautoconfig() called by gadget layer
2336 */
2337 usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
2338
2339 /* the queue lists any req for this ep */
2340 INIT_LIST_HEAD(&ep->queue);
2341
2342 /* gagdet.ep_list used for ep_autoconfig so no ep0 */
2343 if (link)
2344 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
2345 ep->gadget = &udc->gadget;
2346 ep->qh = &udc->ep_qh[index];
2347
2348 return 0;
2349 }
2350
2351 /* Driver probe function
2352 * all initialization operations implemented here except enabling usb_intr reg
2353 * board setup should have been done in the platform code
2354 */
fsl_udc_probe(struct platform_device * pdev)2355 static int fsl_udc_probe(struct platform_device *pdev)
2356 {
2357 struct fsl_usb2_platform_data *pdata;
2358 struct resource *res;
2359 int ret = -ENODEV;
2360 unsigned int i;
2361 u32 dccparams;
2362
2363 udc_controller = kzalloc_obj(struct fsl_udc);
2364 if (udc_controller == NULL)
2365 return -ENOMEM;
2366
2367 udc_controller->dev = &pdev->dev;
2368 pdata = dev_get_platdata(&pdev->dev);
2369 udc_controller->pdata = pdata;
2370 spin_lock_init(&udc_controller->lock);
2371 udc_controller->stopped = 1;
2372
2373 #ifdef CONFIG_USB_OTG
2374 if (pdata->operating_mode == FSL_USB2_DR_OTG) {
2375 udc_controller->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
2376 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2377 dev_err(&pdev->dev, "Can't find OTG driver!\n");
2378 ret = -ENODEV;
2379 goto err_kfree;
2380 }
2381 }
2382 #endif
2383
2384 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2385 if (!res) {
2386 ret = -ENXIO;
2387 goto err_kfree;
2388 }
2389
2390 if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
2391 if (!request_mem_region(res->start, resource_size(res),
2392 driver_name)) {
2393 dev_err(&pdev->dev, "failed to request mem region\n");
2394 ret = -EBUSY;
2395 goto err_kfree;
2396 }
2397 }
2398
2399 dr_regs = ioremap(res->start, resource_size(res));
2400 if (!dr_regs) {
2401 ret = -ENOMEM;
2402 goto err_release_mem_region;
2403 }
2404
2405 pdata->regs = (void __iomem *)dr_regs;
2406
2407 /*
2408 * do platform specific init: check the clock, grab/config pins, etc.
2409 */
2410 if (pdata->init && pdata->init(pdev)) {
2411 ret = -ENODEV;
2412 goto err_iounmap;
2413 }
2414
2415 /* Set accessors only after pdata->init() ! */
2416 fsl_set_accessors(pdata);
2417
2418 if (pdata->have_sysif_regs)
2419 usb_sys_regs = (void *)dr_regs + USB_DR_SYS_OFFSET;
2420
2421 /* Read Device Controller Capability Parameters register */
2422 dccparams = fsl_readl(&dr_regs->dccparams);
2423 if (!(dccparams & DCCPARAMS_DC)) {
2424 dev_err(&pdev->dev, "This SOC doesn't support device role\n");
2425 ret = -ENODEV;
2426 goto err_exit;
2427 }
2428 /* Get max device endpoints */
2429 /* DEN is bidirectional ep number, max_ep doubles the number */
2430 udc_controller->max_ep = (dccparams & DCCPARAMS_DEN_MASK) * 2;
2431
2432 ret = platform_get_irq(pdev, 0);
2433 if (ret <= 0) {
2434 ret = ret ? : -ENODEV;
2435 goto err_exit;
2436 }
2437 udc_controller->irq = ret;
2438
2439 ret = request_irq(udc_controller->irq, fsl_udc_irq, IRQF_SHARED,
2440 driver_name, udc_controller);
2441 if (ret != 0) {
2442 dev_err(&pdev->dev, "cannot request irq %d err %d\n",
2443 udc_controller->irq, ret);
2444 goto err_exit;
2445 }
2446
2447 /* Initialize the udc structure including QH member and other member */
2448 if (struct_udc_setup(udc_controller, pdev)) {
2449 dev_err(&pdev->dev, "Can't initialize udc data structure\n");
2450 ret = -ENOMEM;
2451 goto err_free_irq;
2452 }
2453
2454 if (IS_ERR_OR_NULL(udc_controller->transceiver)) {
2455 /* initialize usb hw reg except for regs for EP,
2456 * leave usbintr reg untouched */
2457 dr_controller_setup(udc_controller);
2458 }
2459
2460 /* Setup gadget structure */
2461 udc_controller->gadget.ops = &fsl_gadget_ops;
2462 udc_controller->gadget.max_speed = USB_SPEED_HIGH;
2463 udc_controller->gadget.ep0 = &udc_controller->eps[0].ep;
2464 INIT_LIST_HEAD(&udc_controller->gadget.ep_list);
2465 udc_controller->gadget.speed = USB_SPEED_UNKNOWN;
2466 udc_controller->gadget.name = driver_name;
2467
2468 /* Setup gadget.dev and register with kernel */
2469 udc_controller->gadget.dev.of_node = pdev->dev.of_node;
2470
2471 if (!IS_ERR_OR_NULL(udc_controller->transceiver))
2472 udc_controller->gadget.is_otg = 1;
2473
2474 /* setup QH and epctrl for ep0 */
2475 ep0_setup(udc_controller);
2476
2477 /* setup udc->eps[] for ep0 */
2478 struct_ep_setup(udc_controller, 0, "ep0", 0);
2479 /* for ep0: the desc defined here;
2480 * for other eps, gadget layer called ep_enable with defined desc
2481 */
2482 udc_controller->eps[0].ep.desc = &fsl_ep0_desc;
2483 usb_ep_set_maxpacket_limit(&udc_controller->eps[0].ep,
2484 USB_MAX_CTRL_PAYLOAD);
2485
2486 /* setup the udc->eps[] for non-control endpoints and link
2487 * to gadget.ep_list */
2488 for (i = 1; i < (int)(udc_controller->max_ep / 2); i++) {
2489 char name[16];
2490
2491 sprintf(name, "ep%dout", i);
2492 struct_ep_setup(udc_controller, i * 2, name, 1);
2493 sprintf(name, "ep%din", i);
2494 struct_ep_setup(udc_controller, i * 2 + 1, name, 1);
2495 }
2496
2497 /* use dma_pool for TD management */
2498 udc_controller->td_pool = dma_pool_create("udc_td", &pdev->dev,
2499 sizeof(struct ep_td_struct),
2500 DTD_ALIGNMENT, UDC_DMA_BOUNDARY);
2501 if (udc_controller->td_pool == NULL) {
2502 ret = -ENOMEM;
2503 goto err_free_irq;
2504 }
2505
2506 ret = usb_add_gadget_udc_release(&pdev->dev, &udc_controller->gadget,
2507 fsl_udc_release);
2508 if (ret)
2509 goto err_del_udc;
2510
2511 create_proc_file();
2512 return 0;
2513
2514 err_del_udc:
2515 dma_pool_destroy(udc_controller->td_pool);
2516 err_free_irq:
2517 free_irq(udc_controller->irq, udc_controller);
2518 err_exit:
2519 if (pdata->exit)
2520 pdata->exit(pdev);
2521 err_iounmap:
2522 iounmap(dr_regs);
2523 err_release_mem_region:
2524 if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
2525 release_mem_region(res->start, resource_size(res));
2526 err_kfree:
2527 kfree(udc_controller);
2528 udc_controller = NULL;
2529 return ret;
2530 }
2531
2532 /* Driver removal function
2533 * Free resources and finish pending transactions
2534 */
fsl_udc_remove(struct platform_device * pdev)2535 static void fsl_udc_remove(struct platform_device *pdev)
2536 {
2537 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2538 struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
2539
2540 DECLARE_COMPLETION_ONSTACK(done);
2541
2542 udc_controller->done = &done;
2543 usb_del_gadget_udc(&udc_controller->gadget);
2544
2545 /* DR has been stopped in usb_gadget_unregister_driver() */
2546 remove_proc_file();
2547
2548 /* Free allocated memory */
2549 kfree(udc_controller->status_req->req.buf);
2550 kfree(udc_controller->status_req);
2551 kfree(udc_controller->eps);
2552
2553 dma_pool_destroy(udc_controller->td_pool);
2554 free_irq(udc_controller->irq, udc_controller);
2555 iounmap(dr_regs);
2556 if (res && (pdata->operating_mode == FSL_USB2_DR_DEVICE))
2557 release_mem_region(res->start, resource_size(res));
2558
2559 /* free udc --wait for the release() finished */
2560 wait_for_completion(&done);
2561
2562 /*
2563 * do platform specific un-initialization:
2564 * release iomux pins, etc.
2565 */
2566 if (pdata->exit)
2567 pdata->exit(pdev);
2568 }
2569
2570 /*-----------------------------------------------------------------
2571 * Modify Power management attributes
2572 * Used by OTG statemachine to disable gadget temporarily
2573 -----------------------------------------------------------------*/
fsl_udc_suspend(struct platform_device * pdev,pm_message_t state)2574 static int fsl_udc_suspend(struct platform_device *pdev, pm_message_t state)
2575 {
2576 dr_controller_stop(udc_controller);
2577 return 0;
2578 }
2579
2580 /*-----------------------------------------------------------------
2581 * Invoked on USB resume. May be called in_interrupt.
2582 * Here we start the DR controller and enable the irq
2583 *-----------------------------------------------------------------*/
fsl_udc_resume(struct platform_device * pdev)2584 static int fsl_udc_resume(struct platform_device *pdev)
2585 {
2586 /* Enable DR irq reg and set controller Run */
2587 if (udc_controller->stopped) {
2588 dr_controller_setup(udc_controller);
2589 dr_controller_run(udc_controller);
2590 }
2591 udc_controller->usb_state = USB_STATE_ATTACHED;
2592 udc_controller->ep0_state = WAIT_FOR_SETUP;
2593 udc_controller->ep0_dir = 0;
2594 return 0;
2595 }
2596
fsl_udc_otg_suspend(struct device * dev,pm_message_t state)2597 static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
2598 {
2599 struct fsl_udc *udc = udc_controller;
2600 u32 mode, usbcmd;
2601
2602 mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
2603
2604 pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
2605
2606 /*
2607 * If the controller is already stopped, then this must be a
2608 * PM suspend. Remember this fact, so that we will leave the
2609 * controller stopped at PM resume time.
2610 */
2611 if (udc->stopped) {
2612 pr_debug("gadget already stopped, leaving early\n");
2613 udc->already_stopped = 1;
2614 return 0;
2615 }
2616
2617 if (mode != USB_MODE_CTRL_MODE_DEVICE) {
2618 pr_debug("gadget not in device mode, leaving early\n");
2619 return 0;
2620 }
2621
2622 /* stop the controller */
2623 usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
2624 fsl_writel(usbcmd, &dr_regs->usbcmd);
2625
2626 udc->stopped = 1;
2627
2628 pr_info("USB Gadget suspended\n");
2629
2630 return 0;
2631 }
2632
fsl_udc_otg_resume(struct device * dev)2633 static int fsl_udc_otg_resume(struct device *dev)
2634 {
2635 pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
2636 udc_controller->stopped, udc_controller->already_stopped);
2637
2638 /*
2639 * If the controller was stopped at suspend time, then
2640 * don't resume it now.
2641 */
2642 if (udc_controller->already_stopped) {
2643 udc_controller->already_stopped = 0;
2644 pr_debug("gadget was already stopped, leaving early\n");
2645 return 0;
2646 }
2647
2648 pr_info("USB Gadget resume\n");
2649
2650 return fsl_udc_resume(NULL);
2651 }
2652 /*-------------------------------------------------------------------------
2653 Register entry point for the peripheral controller driver
2654 --------------------------------------------------------------------------*/
2655 static const struct platform_device_id fsl_udc_devtype[] = {
2656 {
2657 .name = "fsl-usb2-udc",
2658 }, {
2659 /* sentinel */
2660 }
2661 };
2662 MODULE_DEVICE_TABLE(platform, fsl_udc_devtype);
2663
2664 static const struct of_device_id fsl_udc_dt_ids[] = {
2665 { .compatible = "fsl-usb2-dr" },
2666 { .compatible = "fsl-usb2-mph" },
2667 { .compatible = "fsl,mpc5121-usb2-dr" },
2668 { /* sentinel */ }
2669 };
2670 MODULE_DEVICE_TABLE(of, fsl_udc_dt_ids);
2671
2672 static struct platform_driver udc_driver = {
2673 .probe = fsl_udc_probe,
2674 .remove = fsl_udc_remove,
2675 .id_table = fsl_udc_devtype,
2676 /* these suspend and resume are not usb suspend and resume */
2677 .suspend = fsl_udc_suspend,
2678 .resume = fsl_udc_resume,
2679 .driver = {
2680 .name = driver_name,
2681 .of_match_table = fsl_udc_dt_ids,
2682 /* udc suspend/resume called from OTG driver */
2683 .suspend = fsl_udc_otg_suspend,
2684 .resume = fsl_udc_otg_resume,
2685 },
2686 };
2687
2688 module_platform_driver(udc_driver);
2689
2690 MODULE_DESCRIPTION(DRIVER_DESC);
2691 MODULE_AUTHOR(DRIVER_AUTHOR);
2692 MODULE_LICENSE("GPL");
2693 MODULE_ALIAS("platform:fsl-usb2-udc");
2694