1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 NVIDIA Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/debugfs.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/reset.h> 16 #include <linux/string_choices.h> 17 18 #include <soc/tegra/pmc.h> 19 20 #include <drm/display/drm_dp_helper.h> 21 #include <drm/display/drm_scdc_helper.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_debugfs.h> 24 #include <drm/drm_edid.h> 25 #include <drm/drm_eld.h> 26 #include <drm/drm_encoder.h> 27 #include <drm/drm_file.h> 28 #include <drm/drm_panel.h> 29 #include <drm/drm_print.h> 30 31 #include "dc.h" 32 #include "dp.h" 33 #include "drm.h" 34 #include "hda.h" 35 #include "sor.h" 36 #include "trace.h" 37 38 #define SOR_REKEY 0x38 39 40 struct tegra_sor_hdmi_settings { 41 unsigned long frequency; 42 43 u8 vcocap; 44 u8 filter; 45 u8 ichpmp; 46 u8 loadadj; 47 u8 tmds_termadj; 48 u8 tx_pu_value; 49 u8 bg_temp_coef; 50 u8 bg_vref_level; 51 u8 avdd10_level; 52 u8 avdd14_level; 53 u8 sparepll; 54 55 u8 drive_current[4]; 56 u8 preemphasis[4]; 57 }; 58 59 #if 1 60 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 61 { 62 .frequency = 54000000, 63 .vcocap = 0x0, 64 .filter = 0x0, 65 .ichpmp = 0x1, 66 .loadadj = 0x3, 67 .tmds_termadj = 0x9, 68 .tx_pu_value = 0x10, 69 .bg_temp_coef = 0x3, 70 .bg_vref_level = 0x8, 71 .avdd10_level = 0x4, 72 .avdd14_level = 0x4, 73 .sparepll = 0x0, 74 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 75 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 76 }, { 77 .frequency = 75000000, 78 .vcocap = 0x3, 79 .filter = 0x0, 80 .ichpmp = 0x1, 81 .loadadj = 0x3, 82 .tmds_termadj = 0x9, 83 .tx_pu_value = 0x40, 84 .bg_temp_coef = 0x3, 85 .bg_vref_level = 0x8, 86 .avdd10_level = 0x4, 87 .avdd14_level = 0x4, 88 .sparepll = 0x0, 89 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 90 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 91 }, { 92 .frequency = 150000000, 93 .vcocap = 0x3, 94 .filter = 0x0, 95 .ichpmp = 0x1, 96 .loadadj = 0x3, 97 .tmds_termadj = 0x9, 98 .tx_pu_value = 0x66, 99 .bg_temp_coef = 0x3, 100 .bg_vref_level = 0x8, 101 .avdd10_level = 0x4, 102 .avdd14_level = 0x4, 103 .sparepll = 0x0, 104 .drive_current = { 0x33, 0x3a, 0x3a, 0x3a }, 105 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 106 }, { 107 .frequency = 300000000, 108 .vcocap = 0x3, 109 .filter = 0x0, 110 .ichpmp = 0x1, 111 .loadadj = 0x3, 112 .tmds_termadj = 0x9, 113 .tx_pu_value = 0x66, 114 .bg_temp_coef = 0x3, 115 .bg_vref_level = 0xa, 116 .avdd10_level = 0x4, 117 .avdd14_level = 0x4, 118 .sparepll = 0x0, 119 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 120 .preemphasis = { 0x00, 0x17, 0x17, 0x17 }, 121 }, { 122 .frequency = 600000000, 123 .vcocap = 0x3, 124 .filter = 0x0, 125 .ichpmp = 0x1, 126 .loadadj = 0x3, 127 .tmds_termadj = 0x9, 128 .tx_pu_value = 0x66, 129 .bg_temp_coef = 0x3, 130 .bg_vref_level = 0x8, 131 .avdd10_level = 0x4, 132 .avdd14_level = 0x4, 133 .sparepll = 0x0, 134 .drive_current = { 0x33, 0x3f, 0x3f, 0x3f }, 135 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 136 }, 137 }; 138 #else 139 static const struct tegra_sor_hdmi_settings tegra210_sor_hdmi_defaults[] = { 140 { 141 .frequency = 75000000, 142 .vcocap = 0x3, 143 .filter = 0x0, 144 .ichpmp = 0x1, 145 .loadadj = 0x3, 146 .tmds_termadj = 0x9, 147 .tx_pu_value = 0x40, 148 .bg_temp_coef = 0x3, 149 .bg_vref_level = 0x8, 150 .avdd10_level = 0x4, 151 .avdd14_level = 0x4, 152 .sparepll = 0x0, 153 .drive_current = { 0x29, 0x29, 0x29, 0x29 }, 154 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 155 }, { 156 .frequency = 150000000, 157 .vcocap = 0x3, 158 .filter = 0x0, 159 .ichpmp = 0x1, 160 .loadadj = 0x3, 161 .tmds_termadj = 0x9, 162 .tx_pu_value = 0x66, 163 .bg_temp_coef = 0x3, 164 .bg_vref_level = 0x8, 165 .avdd10_level = 0x4, 166 .avdd14_level = 0x4, 167 .sparepll = 0x0, 168 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 169 .preemphasis = { 0x01, 0x02, 0x02, 0x02 }, 170 }, { 171 .frequency = 300000000, 172 .vcocap = 0x3, 173 .filter = 0x0, 174 .ichpmp = 0x6, 175 .loadadj = 0x3, 176 .tmds_termadj = 0x9, 177 .tx_pu_value = 0x66, 178 .bg_temp_coef = 0x3, 179 .bg_vref_level = 0xf, 180 .avdd10_level = 0x4, 181 .avdd14_level = 0x4, 182 .sparepll = 0x0, 183 .drive_current = { 0x30, 0x37, 0x37, 0x37 }, 184 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e }, 185 }, { 186 .frequency = 600000000, 187 .vcocap = 0x3, 188 .filter = 0x0, 189 .ichpmp = 0xa, 190 .loadadj = 0x3, 191 .tmds_termadj = 0xb, 192 .tx_pu_value = 0x66, 193 .bg_temp_coef = 0x3, 194 .bg_vref_level = 0xe, 195 .avdd10_level = 0x4, 196 .avdd14_level = 0x4, 197 .sparepll = 0x0, 198 .drive_current = { 0x35, 0x3e, 0x3e, 0x3e }, 199 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f }, 200 }, 201 }; 202 #endif 203 204 static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = { 205 { 206 .frequency = 54000000, 207 .vcocap = 0, 208 .filter = 5, 209 .ichpmp = 5, 210 .loadadj = 3, 211 .tmds_termadj = 0xf, 212 .tx_pu_value = 0, 213 .bg_temp_coef = 3, 214 .bg_vref_level = 8, 215 .avdd10_level = 4, 216 .avdd14_level = 4, 217 .sparepll = 0x54, 218 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 219 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 220 }, { 221 .frequency = 75000000, 222 .vcocap = 1, 223 .filter = 5, 224 .ichpmp = 5, 225 .loadadj = 3, 226 .tmds_termadj = 0xf, 227 .tx_pu_value = 0, 228 .bg_temp_coef = 3, 229 .bg_vref_level = 8, 230 .avdd10_level = 4, 231 .avdd14_level = 4, 232 .sparepll = 0x44, 233 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 234 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 235 }, { 236 .frequency = 150000000, 237 .vcocap = 3, 238 .filter = 5, 239 .ichpmp = 5, 240 .loadadj = 3, 241 .tmds_termadj = 15, 242 .tx_pu_value = 0x66 /* 0 */, 243 .bg_temp_coef = 3, 244 .bg_vref_level = 8, 245 .avdd10_level = 4, 246 .avdd14_level = 4, 247 .sparepll = 0x00, /* 0x34 */ 248 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 249 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 250 }, { 251 .frequency = 300000000, 252 .vcocap = 3, 253 .filter = 5, 254 .ichpmp = 5, 255 .loadadj = 3, 256 .tmds_termadj = 15, 257 .tx_pu_value = 64, 258 .bg_temp_coef = 3, 259 .bg_vref_level = 8, 260 .avdd10_level = 4, 261 .avdd14_level = 4, 262 .sparepll = 0x34, 263 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 264 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 265 }, { 266 .frequency = 600000000, 267 .vcocap = 3, 268 .filter = 5, 269 .ichpmp = 5, 270 .loadadj = 3, 271 .tmds_termadj = 12, 272 .tx_pu_value = 96, 273 .bg_temp_coef = 3, 274 .bg_vref_level = 8, 275 .avdd10_level = 4, 276 .avdd14_level = 4, 277 .sparepll = 0x34, 278 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 279 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 280 } 281 }; 282 283 static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = { 284 { 285 .frequency = 54000000, 286 .vcocap = 0, 287 .filter = 5, 288 .ichpmp = 5, 289 .loadadj = 3, 290 .tmds_termadj = 0xf, 291 .tx_pu_value = 0, 292 .bg_temp_coef = 3, 293 .bg_vref_level = 8, 294 .avdd10_level = 4, 295 .avdd14_level = 4, 296 .sparepll = 0x54, 297 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 298 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 299 }, { 300 .frequency = 75000000, 301 .vcocap = 1, 302 .filter = 5, 303 .ichpmp = 5, 304 .loadadj = 3, 305 .tmds_termadj = 0xf, 306 .tx_pu_value = 0, 307 .bg_temp_coef = 3, 308 .bg_vref_level = 8, 309 .avdd10_level = 4, 310 .avdd14_level = 4, 311 .sparepll = 0x44, 312 .drive_current = { 0x3a, 0x3a, 0x3a, 0x33 }, 313 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 314 }, { 315 .frequency = 150000000, 316 .vcocap = 3, 317 .filter = 5, 318 .ichpmp = 5, 319 .loadadj = 3, 320 .tmds_termadj = 15, 321 .tx_pu_value = 0x66 /* 0 */, 322 .bg_temp_coef = 3, 323 .bg_vref_level = 8, 324 .avdd10_level = 4, 325 .avdd14_level = 4, 326 .sparepll = 0x00, /* 0x34 */ 327 .drive_current = { 0x3a, 0x3a, 0x3a, 0x37 }, 328 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 329 }, { 330 .frequency = 300000000, 331 .vcocap = 3, 332 .filter = 5, 333 .ichpmp = 5, 334 .loadadj = 3, 335 .tmds_termadj = 15, 336 .tx_pu_value = 64, 337 .bg_temp_coef = 3, 338 .bg_vref_level = 8, 339 .avdd10_level = 4, 340 .avdd14_level = 4, 341 .sparepll = 0x34, 342 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 343 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 344 }, { 345 .frequency = 600000000, 346 .vcocap = 3, 347 .filter = 5, 348 .ichpmp = 5, 349 .loadadj = 3, 350 .tmds_termadj = 12, 351 .tx_pu_value = 96, 352 .bg_temp_coef = 3, 353 .bg_vref_level = 8, 354 .avdd10_level = 4, 355 .avdd14_level = 4, 356 .sparepll = 0x34, 357 .drive_current = { 0x3d, 0x3d, 0x3d, 0x33 }, 358 .preemphasis = { 0x00, 0x00, 0x00, 0x00 }, 359 } 360 }; 361 362 struct tegra_sor_regs { 363 unsigned int head_state0; 364 unsigned int head_state1; 365 unsigned int head_state2; 366 unsigned int head_state3; 367 unsigned int head_state4; 368 unsigned int head_state5; 369 unsigned int pll0; 370 unsigned int pll1; 371 unsigned int pll2; 372 unsigned int pll3; 373 unsigned int dp_padctl0; 374 unsigned int dp_padctl2; 375 }; 376 377 struct tegra_sor_soc { 378 bool supports_lvds; 379 bool supports_hdmi; 380 bool supports_dp; 381 bool supports_audio; 382 bool supports_hdcp; 383 384 const struct tegra_sor_regs *regs; 385 bool has_nvdisplay; 386 387 const struct tegra_sor_hdmi_settings *settings; 388 unsigned int num_settings; 389 390 const u8 *xbar_cfg; 391 const u8 *lane_map; 392 393 const u8 (*voltage_swing)[4][4]; 394 const u8 (*pre_emphasis)[4][4]; 395 const u8 (*post_cursor)[4][4]; 396 const u8 (*tx_pu)[4][4]; 397 }; 398 399 struct tegra_sor; 400 401 struct tegra_sor_ops { 402 const char *name; 403 int (*probe)(struct tegra_sor *sor); 404 void (*audio_enable)(struct tegra_sor *sor); 405 void (*audio_disable)(struct tegra_sor *sor); 406 }; 407 408 struct tegra_sor { 409 struct host1x_client client; 410 struct tegra_output output; 411 struct device *dev; 412 413 const struct tegra_sor_soc *soc; 414 void __iomem *regs; 415 unsigned int index; 416 unsigned int irq; 417 418 struct reset_control *rst; 419 struct clk *clk_parent; 420 struct clk *clk_safe; 421 struct clk *clk_out; 422 struct clk *clk_pad; 423 struct clk *clk_dp; 424 struct clk *clk; 425 426 struct tegra_pmc *pmc; 427 428 u8 xbar_cfg[5]; 429 430 struct drm_dp_link link; 431 struct drm_dp_aux *aux; 432 433 struct drm_info_list *debugfs_files; 434 435 const struct tegra_sor_ops *ops; 436 enum tegra_io_pad pad; 437 438 /* for HDMI 2.0 */ 439 struct tegra_sor_hdmi_settings *settings; 440 unsigned int num_settings; 441 442 struct regulator *avdd_io_supply; 443 struct regulator *vdd_pll_supply; 444 struct regulator *hdmi_supply; 445 446 struct delayed_work scdc; 447 bool scdc_enabled; 448 449 struct tegra_hda_format format; 450 }; 451 452 struct tegra_sor_state { 453 struct drm_connector_state base; 454 455 unsigned int link_speed; 456 unsigned long pclk; 457 unsigned int bpc; 458 }; 459 460 static inline struct tegra_sor_state * 461 to_sor_state(struct drm_connector_state *state) 462 { 463 return container_of(state, struct tegra_sor_state, base); 464 } 465 466 struct tegra_sor_config { 467 u32 bits_per_pixel; 468 469 u32 active_polarity; 470 u32 active_count; 471 u32 tu_size; 472 u32 active_frac; 473 u32 watermark; 474 475 u32 hblank_symbols; 476 u32 vblank_symbols; 477 }; 478 479 static inline struct tegra_sor * 480 host1x_client_to_sor(struct host1x_client *client) 481 { 482 return container_of(client, struct tegra_sor, client); 483 } 484 485 static inline struct tegra_sor *to_sor(struct tegra_output *output) 486 { 487 return container_of(output, struct tegra_sor, output); 488 } 489 490 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) 491 { 492 u32 value = readl(sor->regs + (offset << 2)); 493 494 trace_sor_readl(sor->dev, offset, value); 495 496 return value; 497 } 498 499 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, 500 unsigned int offset) 501 { 502 trace_sor_writel(sor->dev, offset, value); 503 writel(value, sor->regs + (offset << 2)); 504 } 505 506 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) 507 { 508 int err; 509 510 clk_disable_unprepare(sor->clk); 511 512 err = clk_set_parent(sor->clk_out, parent); 513 if (err < 0) 514 return err; 515 516 err = clk_prepare_enable(sor->clk); 517 if (err < 0) 518 return err; 519 520 return 0; 521 } 522 523 struct tegra_clk_sor_pad { 524 struct clk_hw hw; 525 struct tegra_sor *sor; 526 }; 527 528 static inline struct tegra_clk_sor_pad *to_pad(struct clk_hw *hw) 529 { 530 return container_of(hw, struct tegra_clk_sor_pad, hw); 531 } 532 533 static const char * const tegra_clk_sor_pad_parents[2][2] = { 534 { "pll_d_out0", "pll_dp" }, 535 { "pll_d2_out0", "pll_dp" }, 536 }; 537 538 /* 539 * Implementing ->set_parent() here isn't really required because the parent 540 * will be explicitly selected in the driver code via the DP_CLK_SEL mux in 541 * the SOR_CLK_CNTRL register. This is primarily for compatibility with the 542 * Tegra186 and later SoC generations where the BPMP implements this clock 543 * and doesn't expose the mux via the common clock framework. 544 */ 545 546 static int tegra_clk_sor_pad_set_parent(struct clk_hw *hw, u8 index) 547 { 548 struct tegra_clk_sor_pad *pad = to_pad(hw); 549 struct tegra_sor *sor = pad->sor; 550 u32 value; 551 552 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 553 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 554 555 switch (index) { 556 case 0: 557 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 558 break; 559 560 case 1: 561 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 562 break; 563 } 564 565 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 566 567 return 0; 568 } 569 570 static u8 tegra_clk_sor_pad_get_parent(struct clk_hw *hw) 571 { 572 struct tegra_clk_sor_pad *pad = to_pad(hw); 573 struct tegra_sor *sor = pad->sor; 574 u8 parent = U8_MAX; 575 u32 value; 576 577 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 578 579 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { 580 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK: 581 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK: 582 parent = 0; 583 break; 584 585 case SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK: 586 case SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK: 587 parent = 1; 588 break; 589 } 590 591 return parent; 592 } 593 594 static const struct clk_ops tegra_clk_sor_pad_ops = { 595 .determine_rate = clk_hw_determine_rate_no_reparent, 596 .set_parent = tegra_clk_sor_pad_set_parent, 597 .get_parent = tegra_clk_sor_pad_get_parent, 598 }; 599 600 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, 601 const char *name) 602 { 603 struct tegra_clk_sor_pad *pad; 604 struct clk_init_data init; 605 struct clk *clk; 606 607 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); 608 if (!pad) 609 return ERR_PTR(-ENOMEM); 610 611 pad->sor = sor; 612 613 init.name = name; 614 init.flags = 0; 615 init.parent_names = tegra_clk_sor_pad_parents[sor->index]; 616 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]); 617 init.ops = &tegra_clk_sor_pad_ops; 618 619 pad->hw.init = &init; 620 621 clk = devm_clk_register(sor->dev, &pad->hw); 622 623 return clk; 624 } 625 626 static void tegra_sor_filter_rates(struct tegra_sor *sor) 627 { 628 struct drm_dp_link *link = &sor->link; 629 unsigned int i; 630 631 /* Tegra only supports RBR, HBR and HBR2 */ 632 for (i = 0; i < link->num_rates; i++) { 633 switch (link->rates[i]) { 634 case 1620000: 635 case 2700000: 636 case 5400000: 637 break; 638 639 default: 640 DRM_DEBUG_KMS("link rate %lu kHz not supported\n", 641 link->rates[i]); 642 link->rates[i] = 0; 643 break; 644 } 645 } 646 647 drm_dp_link_update_rates(link); 648 } 649 650 static int tegra_sor_power_up_lanes(struct tegra_sor *sor, unsigned int lanes) 651 { 652 unsigned long timeout; 653 u32 value; 654 655 /* 656 * Clear or set the PD_TXD bit corresponding to each lane, depending 657 * on whether it is used or not. 658 */ 659 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 660 661 if (lanes <= 2) 662 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | 663 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); 664 else 665 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | 666 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); 667 668 if (lanes <= 1) 669 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); 670 else 671 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); 672 673 if (lanes == 0) 674 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); 675 else 676 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); 677 678 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 679 680 /* start lane sequencer */ 681 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 682 SOR_LANE_SEQ_CTL_POWER_STATE_UP; 683 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 684 685 timeout = jiffies + msecs_to_jiffies(250); 686 687 while (time_before(jiffies, timeout)) { 688 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 689 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 690 break; 691 692 usleep_range(250, 1000); 693 } 694 695 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 696 return -ETIMEDOUT; 697 698 return 0; 699 } 700 701 static int tegra_sor_power_down_lanes(struct tegra_sor *sor) 702 { 703 unsigned long timeout; 704 u32 value; 705 706 /* power down all lanes */ 707 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 708 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 709 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2); 710 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 711 712 /* start lane sequencer */ 713 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | 714 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN; 715 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 716 717 timeout = jiffies + msecs_to_jiffies(250); 718 719 while (time_before(jiffies, timeout)) { 720 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 721 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 722 break; 723 724 usleep_range(25, 100); 725 } 726 727 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) 728 return -ETIMEDOUT; 729 730 return 0; 731 } 732 733 static void tegra_sor_dp_precharge(struct tegra_sor *sor, unsigned int lanes) 734 { 735 u32 value; 736 737 /* pre-charge all used lanes */ 738 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 739 740 if (lanes <= 2) 741 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | 742 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); 743 else 744 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | 745 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); 746 747 if (lanes <= 1) 748 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); 749 else 750 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); 751 752 if (lanes == 0) 753 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); 754 else 755 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); 756 757 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 758 759 usleep_range(15, 100); 760 761 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 762 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | 763 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0); 764 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 765 } 766 767 static void tegra_sor_dp_term_calibrate(struct tegra_sor *sor) 768 { 769 u32 mask = 0x08, adj = 0, value; 770 771 /* enable pad calibration logic */ 772 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 773 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 774 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 775 776 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 777 value |= SOR_PLL1_TMDS_TERM; 778 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 779 780 while (mask) { 781 adj |= mask; 782 783 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 784 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 785 value |= SOR_PLL1_TMDS_TERMADJ(adj); 786 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 787 788 usleep_range(100, 200); 789 790 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 791 if (value & SOR_PLL1_TERM_COMPOUT) 792 adj &= ~mask; 793 794 mask >>= 1; 795 } 796 797 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 798 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 799 value |= SOR_PLL1_TMDS_TERMADJ(adj); 800 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 801 802 /* disable pad calibration logic */ 803 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 804 value |= SOR_DP_PADCTL_PAD_CAL_PD; 805 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 806 } 807 808 static int tegra_sor_dp_link_apply_training(struct drm_dp_link *link) 809 { 810 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); 811 u32 voltage_swing = 0, pre_emphasis = 0, post_cursor = 0; 812 const struct tegra_sor_soc *soc = sor->soc; 813 u32 pattern = 0, tx_pu = 0, value; 814 unsigned int i; 815 816 for (value = 0, i = 0; i < link->lanes; i++) { 817 u8 vs = link->train.request.voltage_swing[i]; 818 u8 pe = link->train.request.pre_emphasis[i]; 819 u8 pc = link->train.request.post_cursor[i]; 820 u8 shift = sor->soc->lane_map[i] << 3; 821 822 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift; 823 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift; 824 post_cursor |= soc->post_cursor[pc][vs][pe] << shift; 825 826 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) 827 tx_pu = sor->soc->tx_pu[pc][vs][pe]; 828 829 switch (link->train.pattern) { 830 case DP_TRAINING_PATTERN_DISABLE: 831 value = SOR_DP_TPG_SCRAMBLER_GALIOS | 832 SOR_DP_TPG_PATTERN_NONE; 833 break; 834 835 case DP_TRAINING_PATTERN_1: 836 value = SOR_DP_TPG_SCRAMBLER_NONE | 837 SOR_DP_TPG_PATTERN_TRAIN1; 838 break; 839 840 case DP_TRAINING_PATTERN_2: 841 value = SOR_DP_TPG_SCRAMBLER_NONE | 842 SOR_DP_TPG_PATTERN_TRAIN2; 843 break; 844 845 case DP_TRAINING_PATTERN_3: 846 value = SOR_DP_TPG_SCRAMBLER_NONE | 847 SOR_DP_TPG_PATTERN_TRAIN3; 848 break; 849 850 default: 851 return -EINVAL; 852 } 853 854 if (link->caps.channel_coding) 855 value |= SOR_DP_TPG_CHANNEL_CODING; 856 857 pattern = pattern << 8 | value; 858 } 859 860 tegra_sor_writel(sor, voltage_swing, SOR_LANE_DRIVE_CURRENT0); 861 tegra_sor_writel(sor, pre_emphasis, SOR_LANE_PREEMPHASIS0); 862 863 if (link->caps.tps3_supported) 864 tegra_sor_writel(sor, post_cursor, SOR_LANE_POSTCURSOR0); 865 866 tegra_sor_writel(sor, pattern, SOR_DP_TPG); 867 868 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 869 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 870 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 871 value |= SOR_DP_PADCTL_TX_PU(tx_pu); 872 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 873 874 usleep_range(20, 100); 875 876 return 0; 877 } 878 879 static int tegra_sor_dp_link_configure(struct drm_dp_link *link) 880 { 881 struct tegra_sor *sor = container_of(link, struct tegra_sor, link); 882 unsigned int rate, lanes; 883 u32 value; 884 int err; 885 886 rate = drm_dp_link_rate_to_bw_code(link->rate); 887 lanes = link->lanes; 888 889 /* configure link speed and lane count */ 890 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 891 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 892 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); 893 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 894 895 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 896 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 897 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); 898 899 if (link->caps.enhanced_framing) 900 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; 901 902 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 903 904 usleep_range(400, 1000); 905 906 /* configure load pulse position adjustment */ 907 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 908 value &= ~SOR_PLL1_LOADADJ_MASK; 909 910 switch (rate) { 911 case DP_LINK_BW_1_62: 912 value |= SOR_PLL1_LOADADJ(0x3); 913 break; 914 915 case DP_LINK_BW_2_7: 916 value |= SOR_PLL1_LOADADJ(0x4); 917 break; 918 919 case DP_LINK_BW_5_4: 920 value |= SOR_PLL1_LOADADJ(0x6); 921 break; 922 } 923 924 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 925 926 /* use alternate scrambler reset for eDP */ 927 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 928 929 if (link->edp == 0) 930 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 931 else 932 value |= SOR_DP_SPARE_PANEL_INTERNAL; 933 934 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 935 936 err = tegra_sor_power_down_lanes(sor); 937 if (err < 0) { 938 dev_err(sor->dev, "failed to power down lanes: %d\n", err); 939 return err; 940 } 941 942 /* power up and pre-charge lanes */ 943 err = tegra_sor_power_up_lanes(sor, lanes); 944 if (err < 0) { 945 dev_err(sor->dev, "failed to power up %u lane%s: %d\n", 946 lanes, str_plural(lanes), err); 947 return err; 948 } 949 950 tegra_sor_dp_precharge(sor, lanes); 951 952 return 0; 953 } 954 955 static const struct drm_dp_link_ops tegra_sor_dp_link_ops = { 956 .apply_training = tegra_sor_dp_link_apply_training, 957 .configure = tegra_sor_dp_link_configure, 958 }; 959 960 static void tegra_sor_super_update(struct tegra_sor *sor) 961 { 962 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 963 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); 964 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); 965 } 966 967 static void tegra_sor_update(struct tegra_sor *sor) 968 { 969 tegra_sor_writel(sor, 0, SOR_STATE0); 970 tegra_sor_writel(sor, 1, SOR_STATE0); 971 tegra_sor_writel(sor, 0, SOR_STATE0); 972 } 973 974 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) 975 { 976 u32 value; 977 978 value = tegra_sor_readl(sor, SOR_PWM_DIV); 979 value &= ~SOR_PWM_DIV_MASK; 980 value |= 0x400; /* period */ 981 tegra_sor_writel(sor, value, SOR_PWM_DIV); 982 983 value = tegra_sor_readl(sor, SOR_PWM_CTL); 984 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; 985 value |= 0x400; /* duty cycle */ 986 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ 987 value |= SOR_PWM_CTL_TRIGGER; 988 tegra_sor_writel(sor, value, SOR_PWM_CTL); 989 990 timeout = jiffies + msecs_to_jiffies(timeout); 991 992 while (time_before(jiffies, timeout)) { 993 value = tegra_sor_readl(sor, SOR_PWM_CTL); 994 if ((value & SOR_PWM_CTL_TRIGGER) == 0) 995 return 0; 996 997 usleep_range(25, 100); 998 } 999 1000 return -ETIMEDOUT; 1001 } 1002 1003 static int tegra_sor_attach(struct tegra_sor *sor) 1004 { 1005 unsigned long value, timeout; 1006 1007 /* wake up in normal mode */ 1008 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1009 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; 1010 value |= SOR_SUPER_STATE_MODE_NORMAL; 1011 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1012 tegra_sor_super_update(sor); 1013 1014 /* attach */ 1015 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1016 value |= SOR_SUPER_STATE_ATTACHED; 1017 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1018 tegra_sor_super_update(sor); 1019 1020 timeout = jiffies + msecs_to_jiffies(250); 1021 1022 while (time_before(jiffies, timeout)) { 1023 value = tegra_sor_readl(sor, SOR_TEST); 1024 if ((value & SOR_TEST_ATTACHED) != 0) 1025 return 0; 1026 1027 usleep_range(25, 100); 1028 } 1029 1030 return -ETIMEDOUT; 1031 } 1032 1033 static int tegra_sor_wakeup(struct tegra_sor *sor) 1034 { 1035 unsigned long value, timeout; 1036 1037 timeout = jiffies + msecs_to_jiffies(250); 1038 1039 /* wait for head to wake up */ 1040 while (time_before(jiffies, timeout)) { 1041 value = tegra_sor_readl(sor, SOR_TEST); 1042 value &= SOR_TEST_HEAD_MODE_MASK; 1043 1044 if (value == SOR_TEST_HEAD_MODE_AWAKE) 1045 return 0; 1046 1047 usleep_range(25, 100); 1048 } 1049 1050 return -ETIMEDOUT; 1051 } 1052 1053 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) 1054 { 1055 u32 value; 1056 1057 value = tegra_sor_readl(sor, SOR_PWR); 1058 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; 1059 tegra_sor_writel(sor, value, SOR_PWR); 1060 1061 timeout = jiffies + msecs_to_jiffies(timeout); 1062 1063 while (time_before(jiffies, timeout)) { 1064 value = tegra_sor_readl(sor, SOR_PWR); 1065 if ((value & SOR_PWR_TRIGGER) == 0) 1066 return 0; 1067 1068 usleep_range(25, 100); 1069 } 1070 1071 return -ETIMEDOUT; 1072 } 1073 1074 struct tegra_sor_params { 1075 /* number of link clocks per line */ 1076 unsigned int num_clocks; 1077 /* ratio between input and output */ 1078 u64 ratio; 1079 /* precision factor */ 1080 u64 precision; 1081 1082 unsigned int active_polarity; 1083 unsigned int active_count; 1084 unsigned int active_frac; 1085 unsigned int tu_size; 1086 unsigned int error; 1087 }; 1088 1089 static int tegra_sor_compute_params(struct tegra_sor *sor, 1090 struct tegra_sor_params *params, 1091 unsigned int tu_size) 1092 { 1093 u64 active_sym, active_count, frac, approx; 1094 u32 active_polarity, active_frac = 0; 1095 const u64 f = params->precision; 1096 s64 error; 1097 1098 active_sym = params->ratio * tu_size; 1099 active_count = div_u64(active_sym, f) * f; 1100 frac = active_sym - active_count; 1101 1102 /* fraction < 0.5 */ 1103 if (frac >= (f / 2)) { 1104 active_polarity = 1; 1105 frac = f - frac; 1106 } else { 1107 active_polarity = 0; 1108 } 1109 1110 if (frac != 0) { 1111 frac = div_u64(f * f, frac); /* 1/fraction */ 1112 if (frac <= (15 * f)) { 1113 active_frac = div_u64(frac, f); 1114 1115 /* round up */ 1116 if (active_polarity) 1117 active_frac++; 1118 } else { 1119 active_frac = active_polarity ? 1 : 15; 1120 } 1121 } 1122 1123 if (active_frac == 1) 1124 active_polarity = 0; 1125 1126 if (active_polarity == 1) { 1127 if (active_frac) { 1128 approx = active_count + (active_frac * (f - 1)) * f; 1129 approx = div_u64(approx, active_frac * f); 1130 } else { 1131 approx = active_count + f; 1132 } 1133 } else { 1134 if (active_frac) 1135 approx = active_count + div_u64(f, active_frac); 1136 else 1137 approx = active_count; 1138 } 1139 1140 error = div_s64(active_sym - approx, tu_size); 1141 error *= params->num_clocks; 1142 1143 if (error <= 0 && abs(error) < params->error) { 1144 params->active_count = div_u64(active_count, f); 1145 params->active_polarity = active_polarity; 1146 params->active_frac = active_frac; 1147 params->error = abs(error); 1148 params->tu_size = tu_size; 1149 1150 if (error == 0) 1151 return true; 1152 } 1153 1154 return false; 1155 } 1156 1157 static int tegra_sor_compute_config(struct tegra_sor *sor, 1158 const struct drm_display_mode *mode, 1159 struct tegra_sor_config *config, 1160 struct drm_dp_link *link) 1161 { 1162 const u64 f = 100000, link_rate = link->rate * 1000; 1163 const u64 pclk = (u64)mode->clock * 1000; 1164 u64 input, output, watermark, num; 1165 struct tegra_sor_params params; 1166 u32 num_syms_per_line; 1167 unsigned int i; 1168 1169 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel) 1170 return -EINVAL; 1171 1172 input = pclk * config->bits_per_pixel; 1173 output = link_rate * 8 * link->lanes; 1174 1175 if (input >= output) 1176 return -ERANGE; 1177 1178 memset(¶ms, 0, sizeof(params)); 1179 params.ratio = div64_u64(input * f, output); 1180 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); 1181 params.precision = f; 1182 params.error = 64 * f; 1183 params.tu_size = 64; 1184 1185 for (i = params.tu_size; i >= 32; i--) 1186 if (tegra_sor_compute_params(sor, ¶ms, i)) 1187 break; 1188 1189 if (params.active_frac == 0) { 1190 config->active_polarity = 0; 1191 config->active_count = params.active_count; 1192 1193 if (!params.active_polarity) 1194 config->active_count--; 1195 1196 config->tu_size = params.tu_size; 1197 config->active_frac = 1; 1198 } else { 1199 config->active_polarity = params.active_polarity; 1200 config->active_count = params.active_count; 1201 config->active_frac = params.active_frac; 1202 config->tu_size = params.tu_size; 1203 } 1204 1205 dev_dbg(sor->dev, 1206 "polarity: %d active count: %d tu size: %d active frac: %d\n", 1207 config->active_polarity, config->active_count, 1208 config->tu_size, config->active_frac); 1209 1210 watermark = params.ratio * config->tu_size * (f - params.ratio); 1211 watermark = div_u64(watermark, f); 1212 1213 watermark = div_u64(watermark + params.error, f); 1214 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; 1215 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * 1216 (link->lanes * 8); 1217 1218 if (config->watermark > 30) { 1219 config->watermark = 30; 1220 dev_err(sor->dev, 1221 "unable to compute TU size, forcing watermark to %u\n", 1222 config->watermark); 1223 } else if (config->watermark > num_syms_per_line) { 1224 config->watermark = num_syms_per_line; 1225 dev_err(sor->dev, "watermark too high, forcing to %u\n", 1226 config->watermark); 1227 } 1228 1229 /* compute the number of symbols per horizontal blanking interval */ 1230 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; 1231 config->hblank_symbols = div_u64(num, pclk); 1232 1233 if (link->caps.enhanced_framing) 1234 config->hblank_symbols -= 3; 1235 1236 config->hblank_symbols -= 12 / link->lanes; 1237 1238 /* compute the number of symbols per vertical blanking interval */ 1239 num = (mode->hdisplay - 25) * link_rate; 1240 config->vblank_symbols = div_u64(num, pclk); 1241 config->vblank_symbols -= 36 / link->lanes + 4; 1242 1243 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, 1244 config->vblank_symbols); 1245 1246 return 0; 1247 } 1248 1249 static void tegra_sor_apply_config(struct tegra_sor *sor, 1250 const struct tegra_sor_config *config) 1251 { 1252 u32 value; 1253 1254 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 1255 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; 1256 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); 1257 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 1258 1259 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); 1260 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; 1261 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); 1262 1263 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; 1264 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); 1265 1266 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; 1267 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); 1268 1269 if (config->active_polarity) 1270 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1271 else 1272 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; 1273 1274 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; 1275 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; 1276 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); 1277 1278 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1279 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; 1280 value |= config->hblank_symbols & 0xffff; 1281 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); 1282 1283 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1284 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; 1285 value |= config->vblank_symbols & 0xffff; 1286 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); 1287 } 1288 1289 static void tegra_sor_mode_set(struct tegra_sor *sor, 1290 const struct drm_display_mode *mode, 1291 struct tegra_sor_state *state) 1292 { 1293 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); 1294 unsigned int vbe, vse, hbe, hse, vbs, hbs; 1295 u32 value; 1296 1297 value = tegra_sor_readl(sor, SOR_STATE1); 1298 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; 1299 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1300 value &= ~SOR_STATE_ASY_OWNER_MASK; 1301 1302 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | 1303 SOR_STATE_ASY_OWNER(dc->pipe + 1); 1304 1305 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 1306 value &= ~SOR_STATE_ASY_HSYNCPOL; 1307 1308 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1309 value |= SOR_STATE_ASY_HSYNCPOL; 1310 1311 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 1312 value &= ~SOR_STATE_ASY_VSYNCPOL; 1313 1314 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1315 value |= SOR_STATE_ASY_VSYNCPOL; 1316 1317 switch (state->bpc) { 1318 case 16: 1319 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; 1320 break; 1321 1322 case 12: 1323 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; 1324 break; 1325 1326 case 10: 1327 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; 1328 break; 1329 1330 case 8: 1331 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 1332 break; 1333 1334 case 6: 1335 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; 1336 break; 1337 1338 default: 1339 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; 1340 break; 1341 } 1342 1343 tegra_sor_writel(sor, value, SOR_STATE1); 1344 1345 /* 1346 * TODO: The video timing programming below doesn't seem to match the 1347 * register definitions. 1348 */ 1349 1350 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); 1351 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); 1352 1353 /* sync end = sync width - 1 */ 1354 vse = mode->vsync_end - mode->vsync_start - 1; 1355 hse = mode->hsync_end - mode->hsync_start - 1; 1356 1357 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); 1358 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); 1359 1360 /* blank end = sync end + back porch */ 1361 vbe = vse + (mode->vtotal - mode->vsync_end); 1362 hbe = hse + (mode->htotal - mode->hsync_end); 1363 1364 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); 1365 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); 1366 1367 /* blank start = blank end + active */ 1368 vbs = vbe + mode->vdisplay; 1369 hbs = hbe + mode->hdisplay; 1370 1371 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); 1372 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); 1373 1374 /* XXX interlacing support */ 1375 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); 1376 } 1377 1378 static int tegra_sor_detach(struct tegra_sor *sor) 1379 { 1380 unsigned long value, timeout; 1381 1382 /* switch to safe mode */ 1383 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1384 value &= ~SOR_SUPER_STATE_MODE_NORMAL; 1385 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1386 tegra_sor_super_update(sor); 1387 1388 timeout = jiffies + msecs_to_jiffies(250); 1389 1390 while (time_before(jiffies, timeout)) { 1391 value = tegra_sor_readl(sor, SOR_PWR); 1392 if (value & SOR_PWR_MODE_SAFE) 1393 break; 1394 } 1395 1396 if ((value & SOR_PWR_MODE_SAFE) == 0) 1397 return -ETIMEDOUT; 1398 1399 /* go to sleep */ 1400 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1401 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; 1402 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1403 tegra_sor_super_update(sor); 1404 1405 /* detach */ 1406 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); 1407 value &= ~SOR_SUPER_STATE_ATTACHED; 1408 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); 1409 tegra_sor_super_update(sor); 1410 1411 timeout = jiffies + msecs_to_jiffies(250); 1412 1413 while (time_before(jiffies, timeout)) { 1414 value = tegra_sor_readl(sor, SOR_TEST); 1415 if ((value & SOR_TEST_ATTACHED) == 0) 1416 break; 1417 1418 usleep_range(25, 100); 1419 } 1420 1421 if ((value & SOR_TEST_ATTACHED) != 0) 1422 return -ETIMEDOUT; 1423 1424 return 0; 1425 } 1426 1427 static int tegra_sor_power_down(struct tegra_sor *sor) 1428 { 1429 unsigned long value, timeout; 1430 int err; 1431 1432 value = tegra_sor_readl(sor, SOR_PWR); 1433 value &= ~SOR_PWR_NORMAL_STATE_PU; 1434 value |= SOR_PWR_TRIGGER; 1435 tegra_sor_writel(sor, value, SOR_PWR); 1436 1437 timeout = jiffies + msecs_to_jiffies(250); 1438 1439 while (time_before(jiffies, timeout)) { 1440 value = tegra_sor_readl(sor, SOR_PWR); 1441 if ((value & SOR_PWR_TRIGGER) == 0) 1442 return 0; 1443 1444 usleep_range(25, 100); 1445 } 1446 1447 if ((value & SOR_PWR_TRIGGER) != 0) 1448 return -ETIMEDOUT; 1449 1450 /* switch to safe parent clock */ 1451 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 1452 if (err < 0) { 1453 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 1454 return err; 1455 } 1456 1457 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1458 value |= SOR_PLL2_PORT_POWERDOWN; 1459 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1460 1461 usleep_range(20, 100); 1462 1463 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 1464 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; 1465 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 1466 1467 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 1468 value |= SOR_PLL2_SEQ_PLLCAPPD; 1469 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 1470 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 1471 1472 usleep_range(20, 100); 1473 1474 return 0; 1475 } 1476 1477 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) 1478 { 1479 u32 value; 1480 1481 timeout = jiffies + msecs_to_jiffies(timeout); 1482 1483 while (time_before(jiffies, timeout)) { 1484 value = tegra_sor_readl(sor, SOR_CRCA); 1485 if (value & SOR_CRCA_VALID) 1486 return 0; 1487 1488 usleep_range(100, 200); 1489 } 1490 1491 return -ETIMEDOUT; 1492 } 1493 1494 static int tegra_sor_show_crc(struct seq_file *s, void *data) 1495 { 1496 struct drm_info_node *node = s->private; 1497 struct tegra_sor *sor = node->info_ent->data; 1498 struct drm_crtc *crtc = sor->output.encoder.crtc; 1499 struct drm_device *drm = node->minor->dev; 1500 int err = 0; 1501 u32 value; 1502 1503 drm_modeset_lock_all(drm); 1504 1505 if (!crtc || !crtc->state->active) { 1506 err = -EBUSY; 1507 goto unlock; 1508 } 1509 1510 value = tegra_sor_readl(sor, SOR_STATE1); 1511 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; 1512 tegra_sor_writel(sor, value, SOR_STATE1); 1513 1514 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); 1515 value |= SOR_CRC_CNTRL_ENABLE; 1516 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); 1517 1518 value = tegra_sor_readl(sor, SOR_TEST); 1519 value &= ~SOR_TEST_CRC_POST_SERIALIZE; 1520 tegra_sor_writel(sor, value, SOR_TEST); 1521 1522 err = tegra_sor_crc_wait(sor, 100); 1523 if (err < 0) 1524 goto unlock; 1525 1526 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); 1527 value = tegra_sor_readl(sor, SOR_CRCB); 1528 1529 seq_printf(s, "%08x\n", value); 1530 1531 unlock: 1532 drm_modeset_unlock_all(drm); 1533 return err; 1534 } 1535 1536 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1537 1538 static const struct debugfs_reg32 tegra_sor_regs[] = { 1539 DEBUGFS_REG32(SOR_CTXSW), 1540 DEBUGFS_REG32(SOR_SUPER_STATE0), 1541 DEBUGFS_REG32(SOR_SUPER_STATE1), 1542 DEBUGFS_REG32(SOR_STATE0), 1543 DEBUGFS_REG32(SOR_STATE1), 1544 DEBUGFS_REG32(SOR_HEAD_STATE0(0)), 1545 DEBUGFS_REG32(SOR_HEAD_STATE0(1)), 1546 DEBUGFS_REG32(SOR_HEAD_STATE1(0)), 1547 DEBUGFS_REG32(SOR_HEAD_STATE1(1)), 1548 DEBUGFS_REG32(SOR_HEAD_STATE2(0)), 1549 DEBUGFS_REG32(SOR_HEAD_STATE2(1)), 1550 DEBUGFS_REG32(SOR_HEAD_STATE3(0)), 1551 DEBUGFS_REG32(SOR_HEAD_STATE3(1)), 1552 DEBUGFS_REG32(SOR_HEAD_STATE4(0)), 1553 DEBUGFS_REG32(SOR_HEAD_STATE4(1)), 1554 DEBUGFS_REG32(SOR_HEAD_STATE5(0)), 1555 DEBUGFS_REG32(SOR_HEAD_STATE5(1)), 1556 DEBUGFS_REG32(SOR_CRC_CNTRL), 1557 DEBUGFS_REG32(SOR_DP_DEBUG_MVID), 1558 DEBUGFS_REG32(SOR_CLK_CNTRL), 1559 DEBUGFS_REG32(SOR_CAP), 1560 DEBUGFS_REG32(SOR_PWR), 1561 DEBUGFS_REG32(SOR_TEST), 1562 DEBUGFS_REG32(SOR_PLL0), 1563 DEBUGFS_REG32(SOR_PLL1), 1564 DEBUGFS_REG32(SOR_PLL2), 1565 DEBUGFS_REG32(SOR_PLL3), 1566 DEBUGFS_REG32(SOR_CSTM), 1567 DEBUGFS_REG32(SOR_LVDS), 1568 DEBUGFS_REG32(SOR_CRCA), 1569 DEBUGFS_REG32(SOR_CRCB), 1570 DEBUGFS_REG32(SOR_BLANK), 1571 DEBUGFS_REG32(SOR_SEQ_CTL), 1572 DEBUGFS_REG32(SOR_LANE_SEQ_CTL), 1573 DEBUGFS_REG32(SOR_SEQ_INST(0)), 1574 DEBUGFS_REG32(SOR_SEQ_INST(1)), 1575 DEBUGFS_REG32(SOR_SEQ_INST(2)), 1576 DEBUGFS_REG32(SOR_SEQ_INST(3)), 1577 DEBUGFS_REG32(SOR_SEQ_INST(4)), 1578 DEBUGFS_REG32(SOR_SEQ_INST(5)), 1579 DEBUGFS_REG32(SOR_SEQ_INST(6)), 1580 DEBUGFS_REG32(SOR_SEQ_INST(7)), 1581 DEBUGFS_REG32(SOR_SEQ_INST(8)), 1582 DEBUGFS_REG32(SOR_SEQ_INST(9)), 1583 DEBUGFS_REG32(SOR_SEQ_INST(10)), 1584 DEBUGFS_REG32(SOR_SEQ_INST(11)), 1585 DEBUGFS_REG32(SOR_SEQ_INST(12)), 1586 DEBUGFS_REG32(SOR_SEQ_INST(13)), 1587 DEBUGFS_REG32(SOR_SEQ_INST(14)), 1588 DEBUGFS_REG32(SOR_SEQ_INST(15)), 1589 DEBUGFS_REG32(SOR_PWM_DIV), 1590 DEBUGFS_REG32(SOR_PWM_CTL), 1591 DEBUGFS_REG32(SOR_VCRC_A0), 1592 DEBUGFS_REG32(SOR_VCRC_A1), 1593 DEBUGFS_REG32(SOR_VCRC_B0), 1594 DEBUGFS_REG32(SOR_VCRC_B1), 1595 DEBUGFS_REG32(SOR_CCRC_A0), 1596 DEBUGFS_REG32(SOR_CCRC_A1), 1597 DEBUGFS_REG32(SOR_CCRC_B0), 1598 DEBUGFS_REG32(SOR_CCRC_B1), 1599 DEBUGFS_REG32(SOR_EDATA_A0), 1600 DEBUGFS_REG32(SOR_EDATA_A1), 1601 DEBUGFS_REG32(SOR_EDATA_B0), 1602 DEBUGFS_REG32(SOR_EDATA_B1), 1603 DEBUGFS_REG32(SOR_COUNT_A0), 1604 DEBUGFS_REG32(SOR_COUNT_A1), 1605 DEBUGFS_REG32(SOR_COUNT_B0), 1606 DEBUGFS_REG32(SOR_COUNT_B1), 1607 DEBUGFS_REG32(SOR_DEBUG_A0), 1608 DEBUGFS_REG32(SOR_DEBUG_A1), 1609 DEBUGFS_REG32(SOR_DEBUG_B0), 1610 DEBUGFS_REG32(SOR_DEBUG_B1), 1611 DEBUGFS_REG32(SOR_TRIG), 1612 DEBUGFS_REG32(SOR_MSCHECK), 1613 DEBUGFS_REG32(SOR_XBAR_CTRL), 1614 DEBUGFS_REG32(SOR_XBAR_POL), 1615 DEBUGFS_REG32(SOR_DP_LINKCTL0), 1616 DEBUGFS_REG32(SOR_DP_LINKCTL1), 1617 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT0), 1618 DEBUGFS_REG32(SOR_LANE_DRIVE_CURRENT1), 1619 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT0), 1620 DEBUGFS_REG32(SOR_LANE4_DRIVE_CURRENT1), 1621 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS0), 1622 DEBUGFS_REG32(SOR_LANE_PREEMPHASIS1), 1623 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS0), 1624 DEBUGFS_REG32(SOR_LANE4_PREEMPHASIS1), 1625 DEBUGFS_REG32(SOR_LANE_POSTCURSOR0), 1626 DEBUGFS_REG32(SOR_LANE_POSTCURSOR1), 1627 DEBUGFS_REG32(SOR_DP_CONFIG0), 1628 DEBUGFS_REG32(SOR_DP_CONFIG1), 1629 DEBUGFS_REG32(SOR_DP_MN0), 1630 DEBUGFS_REG32(SOR_DP_MN1), 1631 DEBUGFS_REG32(SOR_DP_PADCTL0), 1632 DEBUGFS_REG32(SOR_DP_PADCTL1), 1633 DEBUGFS_REG32(SOR_DP_PADCTL2), 1634 DEBUGFS_REG32(SOR_DP_DEBUG0), 1635 DEBUGFS_REG32(SOR_DP_DEBUG1), 1636 DEBUGFS_REG32(SOR_DP_SPARE0), 1637 DEBUGFS_REG32(SOR_DP_SPARE1), 1638 DEBUGFS_REG32(SOR_DP_AUDIO_CTRL), 1639 DEBUGFS_REG32(SOR_DP_AUDIO_HBLANK_SYMBOLS), 1640 DEBUGFS_REG32(SOR_DP_AUDIO_VBLANK_SYMBOLS), 1641 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_HEADER), 1642 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK0), 1643 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK1), 1644 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK2), 1645 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK3), 1646 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK4), 1647 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK5), 1648 DEBUGFS_REG32(SOR_DP_GENERIC_INFOFRAME_SUBPACK6), 1649 DEBUGFS_REG32(SOR_DP_TPG), 1650 DEBUGFS_REG32(SOR_DP_TPG_CONFIG), 1651 DEBUGFS_REG32(SOR_DP_LQ_CSTM0), 1652 DEBUGFS_REG32(SOR_DP_LQ_CSTM1), 1653 DEBUGFS_REG32(SOR_DP_LQ_CSTM2), 1654 }; 1655 1656 static int tegra_sor_show_regs(struct seq_file *s, void *data) 1657 { 1658 struct drm_info_node *node = s->private; 1659 struct tegra_sor *sor = node->info_ent->data; 1660 struct drm_crtc *crtc = sor->output.encoder.crtc; 1661 struct drm_device *drm = node->minor->dev; 1662 unsigned int i; 1663 int err = 0; 1664 1665 drm_modeset_lock_all(drm); 1666 1667 if (!crtc || !crtc->state->active) { 1668 err = -EBUSY; 1669 goto unlock; 1670 } 1671 1672 for (i = 0; i < ARRAY_SIZE(tegra_sor_regs); i++) { 1673 unsigned int offset = tegra_sor_regs[i].offset; 1674 1675 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name, 1676 offset, tegra_sor_readl(sor, offset)); 1677 } 1678 1679 unlock: 1680 drm_modeset_unlock_all(drm); 1681 return err; 1682 } 1683 1684 static const struct drm_info_list debugfs_files[] = { 1685 { "crc", tegra_sor_show_crc, 0, NULL }, 1686 { "regs", tegra_sor_show_regs, 0, NULL }, 1687 }; 1688 1689 static int tegra_sor_late_register(struct drm_connector *connector) 1690 { 1691 struct tegra_output *output = connector_to_output(connector); 1692 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1693 struct drm_minor *minor = connector->dev->primary; 1694 struct dentry *root = connector->debugfs_entry; 1695 struct tegra_sor *sor = to_sor(output); 1696 1697 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1698 GFP_KERNEL); 1699 if (!sor->debugfs_files) 1700 return -ENOMEM; 1701 1702 for (i = 0; i < count; i++) 1703 sor->debugfs_files[i].data = sor; 1704 1705 drm_debugfs_create_files(sor->debugfs_files, count, root, minor); 1706 1707 return 0; 1708 } 1709 1710 static void tegra_sor_early_unregister(struct drm_connector *connector) 1711 { 1712 struct tegra_output *output = connector_to_output(connector); 1713 unsigned int count = ARRAY_SIZE(debugfs_files); 1714 struct tegra_sor *sor = to_sor(output); 1715 1716 drm_debugfs_remove_files(sor->debugfs_files, count, 1717 connector->debugfs_entry, 1718 connector->dev->primary); 1719 kfree(sor->debugfs_files); 1720 sor->debugfs_files = NULL; 1721 } 1722 1723 static void tegra_sor_connector_reset(struct drm_connector *connector) 1724 { 1725 struct tegra_sor_state *state; 1726 1727 state = kzalloc_obj(*state); 1728 if (!state) 1729 return; 1730 1731 if (connector->state) { 1732 __drm_atomic_helper_connector_destroy_state(connector->state); 1733 kfree(connector->state); 1734 } 1735 1736 __drm_atomic_helper_connector_reset(connector, &state->base); 1737 } 1738 1739 static enum drm_connector_status 1740 tegra_sor_connector_detect(struct drm_connector *connector, bool force) 1741 { 1742 struct tegra_output *output = connector_to_output(connector); 1743 struct tegra_sor *sor = to_sor(output); 1744 1745 if (sor->aux) 1746 return drm_dp_aux_detect(sor->aux); 1747 1748 return tegra_output_connector_detect(connector, force); 1749 } 1750 1751 static struct drm_connector_state * 1752 tegra_sor_connector_duplicate_state(struct drm_connector *connector) 1753 { 1754 struct tegra_sor_state *state = to_sor_state(connector->state); 1755 struct tegra_sor_state *copy; 1756 1757 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 1758 if (!copy) 1759 return NULL; 1760 1761 __drm_atomic_helper_connector_duplicate_state(connector, ©->base); 1762 1763 return ©->base; 1764 } 1765 1766 static const struct drm_connector_funcs tegra_sor_connector_funcs = { 1767 .reset = tegra_sor_connector_reset, 1768 .detect = tegra_sor_connector_detect, 1769 .fill_modes = drm_helper_probe_single_connector_modes, 1770 .destroy = tegra_output_connector_destroy, 1771 .atomic_duplicate_state = tegra_sor_connector_duplicate_state, 1772 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1773 .late_register = tegra_sor_late_register, 1774 .early_unregister = tegra_sor_early_unregister, 1775 }; 1776 1777 static int tegra_sor_connector_get_modes(struct drm_connector *connector) 1778 { 1779 struct tegra_output *output = connector_to_output(connector); 1780 struct tegra_sor *sor = to_sor(output); 1781 int err; 1782 1783 if (sor->aux) 1784 drm_dp_aux_enable(sor->aux); 1785 1786 err = tegra_output_connector_get_modes(connector); 1787 1788 if (sor->aux) 1789 drm_dp_aux_disable(sor->aux); 1790 1791 return err; 1792 } 1793 1794 static enum drm_mode_status 1795 tegra_sor_connector_mode_valid(struct drm_connector *connector, 1796 const struct drm_display_mode *mode) 1797 { 1798 return MODE_OK; 1799 } 1800 1801 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = { 1802 .get_modes = tegra_sor_connector_get_modes, 1803 .mode_valid = tegra_sor_connector_mode_valid, 1804 }; 1805 1806 static int 1807 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder, 1808 struct drm_crtc_state *crtc_state, 1809 struct drm_connector_state *conn_state) 1810 { 1811 struct tegra_output *output = encoder_to_output(encoder); 1812 struct tegra_sor_state *state = to_sor_state(conn_state); 1813 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 1814 unsigned long pclk = crtc_state->mode.clock * 1000; 1815 struct tegra_sor *sor = to_sor(output); 1816 struct drm_display_info *info; 1817 int err; 1818 1819 info = &output->connector.display_info; 1820 1821 /* 1822 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so 1823 * the pixel clock must be corrected accordingly. 1824 */ 1825 if (pclk >= 340000000) { 1826 state->link_speed = 20; 1827 state->pclk = pclk / 2; 1828 } else { 1829 state->link_speed = 10; 1830 state->pclk = pclk; 1831 } 1832 1833 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, 1834 pclk, 0); 1835 if (err < 0) { 1836 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1837 return err; 1838 } 1839 1840 switch (info->bpc) { 1841 case 8: 1842 case 6: 1843 state->bpc = info->bpc; 1844 break; 1845 1846 default: 1847 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); 1848 state->bpc = 8; 1849 break; 1850 } 1851 1852 return 0; 1853 } 1854 1855 static inline u32 tegra_sor_hdmi_subpack(const u8 *ptr, size_t size) 1856 { 1857 u32 value = 0; 1858 size_t i; 1859 1860 for (i = size; i > 0; i--) 1861 value = (value << 8) | ptr[i - 1]; 1862 1863 return value; 1864 } 1865 1866 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, 1867 const void *data, size_t size) 1868 { 1869 const u8 *ptr = data; 1870 unsigned long offset; 1871 size_t i; 1872 u32 value; 1873 1874 switch (ptr[0]) { 1875 case HDMI_INFOFRAME_TYPE_AVI: 1876 offset = SOR_HDMI_AVI_INFOFRAME_HEADER; 1877 break; 1878 1879 case HDMI_INFOFRAME_TYPE_AUDIO: 1880 offset = SOR_HDMI_AUDIO_INFOFRAME_HEADER; 1881 break; 1882 1883 case HDMI_INFOFRAME_TYPE_VENDOR: 1884 offset = SOR_HDMI_VSI_INFOFRAME_HEADER; 1885 break; 1886 1887 default: 1888 dev_err(sor->dev, "unsupported infoframe type: %02x\n", 1889 ptr[0]); 1890 return; 1891 } 1892 1893 value = INFOFRAME_HEADER_TYPE(ptr[0]) | 1894 INFOFRAME_HEADER_VERSION(ptr[1]) | 1895 INFOFRAME_HEADER_LEN(ptr[2]); 1896 tegra_sor_writel(sor, value, offset); 1897 offset++; 1898 1899 /* 1900 * Each subpack contains 7 bytes, divided into: 1901 * - subpack_low: bytes 0 - 3 1902 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) 1903 */ 1904 for (i = 3; i < size; i += 7) { 1905 size_t rem = size - i, num = min_t(size_t, rem, 4); 1906 1907 value = tegra_sor_hdmi_subpack(&ptr[i], num); 1908 tegra_sor_writel(sor, value, offset++); 1909 1910 num = min_t(size_t, rem - num, 3); 1911 1912 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); 1913 tegra_sor_writel(sor, value, offset++); 1914 } 1915 } 1916 1917 static int 1918 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, 1919 const struct drm_display_mode *mode) 1920 { 1921 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 1922 struct hdmi_avi_infoframe frame; 1923 u32 value; 1924 int err; 1925 1926 /* disable AVI infoframe */ 1927 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 1928 value &= ~INFOFRAME_CTRL_SINGLE; 1929 value &= ~INFOFRAME_CTRL_OTHER; 1930 value &= ~INFOFRAME_CTRL_ENABLE; 1931 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 1932 1933 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, 1934 &sor->output.connector, mode); 1935 if (err < 0) { 1936 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 1937 return err; 1938 } 1939 1940 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 1941 if (err < 0) { 1942 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); 1943 return err; 1944 } 1945 1946 tegra_sor_hdmi_write_infopack(sor, buffer, err); 1947 1948 /* enable AVI infoframe */ 1949 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); 1950 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 1951 value |= INFOFRAME_CTRL_ENABLE; 1952 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); 1953 1954 return 0; 1955 } 1956 1957 static void tegra_sor_write_eld(struct tegra_sor *sor) 1958 { 1959 size_t length = drm_eld_size(sor->output.connector.eld), i; 1960 1961 for (i = 0; i < length; i++) 1962 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], 1963 SOR_AUDIO_HDA_ELD_BUFWR); 1964 1965 /* 1966 * The HDA codec will always report an ELD buffer size of 96 bytes and 1967 * the HDA codec driver will check that each byte read from the buffer 1968 * is valid. Therefore every byte must be written, even if no 96 bytes 1969 * were parsed from EDID. 1970 */ 1971 for (i = length; i < 96; i++) 1972 tegra_sor_writel(sor, i << 8 | 0, SOR_AUDIO_HDA_ELD_BUFWR); 1973 } 1974 1975 static void tegra_sor_audio_prepare(struct tegra_sor *sor) 1976 { 1977 u32 value; 1978 1979 /* 1980 * Enable and unmask the HDA codec SCRATCH0 register interrupt. This 1981 * is used for interoperability between the HDA codec driver and the 1982 * HDMI/DP driver. 1983 */ 1984 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0; 1985 tegra_sor_writel(sor, value, SOR_INT_ENABLE); 1986 tegra_sor_writel(sor, value, SOR_INT_MASK); 1987 1988 tegra_sor_write_eld(sor); 1989 1990 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD; 1991 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); 1992 } 1993 1994 static void tegra_sor_audio_unprepare(struct tegra_sor *sor) 1995 { 1996 tegra_sor_writel(sor, 0, SOR_AUDIO_HDA_PRESENSE); 1997 tegra_sor_writel(sor, 0, SOR_INT_MASK); 1998 tegra_sor_writel(sor, 0, SOR_INT_ENABLE); 1999 } 2000 2001 static void tegra_sor_audio_enable(struct tegra_sor *sor) 2002 { 2003 u32 value; 2004 2005 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); 2006 2007 /* select HDA audio input */ 2008 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); 2009 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); 2010 2011 /* inject null samples */ 2012 if (sor->format.channels != 2) 2013 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; 2014 else 2015 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; 2016 2017 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; 2018 2019 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); 2020 2021 /* enable advertising HBR capability */ 2022 tegra_sor_writel(sor, SOR_AUDIO_SPARE_HBR_ENABLE, SOR_AUDIO_SPARE); 2023 } 2024 2025 static int tegra_sor_hdmi_enable_audio_infoframe(struct tegra_sor *sor) 2026 { 2027 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)]; 2028 struct hdmi_audio_infoframe frame; 2029 u32 value; 2030 int err; 2031 2032 err = hdmi_audio_infoframe_init(&frame); 2033 if (err < 0) { 2034 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); 2035 return err; 2036 } 2037 2038 frame.channels = sor->format.channels; 2039 2040 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer)); 2041 if (err < 0) { 2042 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); 2043 return err; 2044 } 2045 2046 tegra_sor_hdmi_write_infopack(sor, buffer, err); 2047 2048 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2049 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; 2050 value |= INFOFRAME_CTRL_ENABLE; 2051 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2052 2053 return 0; 2054 } 2055 2056 static void tegra_sor_hdmi_audio_enable(struct tegra_sor *sor) 2057 { 2058 u32 value; 2059 2060 tegra_sor_audio_enable(sor); 2061 2062 tegra_sor_writel(sor, 0, SOR_HDMI_ACR_CTRL); 2063 2064 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH | 2065 SOR_HDMI_SPARE_CTS_RESET(1) | 2066 SOR_HDMI_SPARE_HW_CTS_ENABLE; 2067 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); 2068 2069 /* enable HW CTS */ 2070 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); 2071 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); 2072 2073 /* allow packet to be sent */ 2074 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE; 2075 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); 2076 2077 /* reset N counter and enable lookup */ 2078 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; 2079 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); 2080 2081 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); 2082 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); 2083 tegra_sor_writel(sor, 4096, SOR_AUDIO_NVAL_0320); 2084 2085 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0441); 2086 tegra_sor_writel(sor, 4704, SOR_AUDIO_NVAL_0441); 2087 2088 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_0882); 2089 tegra_sor_writel(sor, 9408, SOR_AUDIO_NVAL_0882); 2090 2091 tegra_sor_writel(sor, 20000, SOR_AUDIO_AVAL_1764); 2092 tegra_sor_writel(sor, 18816, SOR_AUDIO_NVAL_1764); 2093 2094 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); 2095 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); 2096 tegra_sor_writel(sor, 6144, SOR_AUDIO_NVAL_0480); 2097 2098 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); 2099 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); 2100 tegra_sor_writel(sor, 12288, SOR_AUDIO_NVAL_0960); 2101 2102 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); 2103 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); 2104 tegra_sor_writel(sor, 24576, SOR_AUDIO_NVAL_1920); 2105 2106 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); 2107 value &= ~SOR_HDMI_AUDIO_N_RESET; 2108 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); 2109 2110 tegra_sor_hdmi_enable_audio_infoframe(sor); 2111 } 2112 2113 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) 2114 { 2115 u32 value; 2116 2117 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2118 value &= ~INFOFRAME_CTRL_ENABLE; 2119 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); 2120 } 2121 2122 static void tegra_sor_hdmi_audio_disable(struct tegra_sor *sor) 2123 { 2124 tegra_sor_hdmi_disable_audio_infoframe(sor); 2125 } 2126 2127 static struct tegra_sor_hdmi_settings * 2128 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) 2129 { 2130 unsigned int i; 2131 2132 for (i = 0; i < sor->num_settings; i++) 2133 if (frequency <= sor->settings[i].frequency) 2134 return &sor->settings[i]; 2135 2136 return NULL; 2137 } 2138 2139 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) 2140 { 2141 u32 value; 2142 2143 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 2144 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 2145 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; 2146 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 2147 } 2148 2149 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) 2150 { 2151 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false); 2152 drm_scdc_set_scrambling(&sor->output.connector, false); 2153 2154 tegra_sor_hdmi_disable_scrambling(sor); 2155 } 2156 2157 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) 2158 { 2159 if (sor->scdc_enabled) { 2160 cancel_delayed_work_sync(&sor->scdc); 2161 tegra_sor_hdmi_scdc_disable(sor); 2162 } 2163 } 2164 2165 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) 2166 { 2167 u32 value; 2168 2169 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); 2170 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; 2171 value |= SOR_HDMI2_CTRL_SCRAMBLE; 2172 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); 2173 } 2174 2175 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) 2176 { 2177 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true); 2178 drm_scdc_set_scrambling(&sor->output.connector, true); 2179 2180 tegra_sor_hdmi_enable_scrambling(sor); 2181 } 2182 2183 static void tegra_sor_hdmi_scdc_work(struct work_struct *work) 2184 { 2185 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); 2186 2187 if (!drm_scdc_get_scrambling_status(&sor->output.connector)) { 2188 DRM_DEBUG_KMS("SCDC not scrambled\n"); 2189 tegra_sor_hdmi_scdc_enable(sor); 2190 } 2191 2192 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 2193 } 2194 2195 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) 2196 { 2197 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; 2198 struct drm_display_mode *mode; 2199 2200 mode = &sor->output.encoder.crtc->state->adjusted_mode; 2201 2202 if (mode->clock >= 340000 && scdc->supported) { 2203 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); 2204 tegra_sor_hdmi_scdc_enable(sor); 2205 sor->scdc_enabled = true; 2206 } 2207 } 2208 2209 static void tegra_sor_hdmi_disable(struct drm_encoder *encoder) 2210 { 2211 struct tegra_output *output = encoder_to_output(encoder); 2212 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2213 struct tegra_sor *sor = to_sor(output); 2214 u32 value; 2215 int err; 2216 2217 tegra_sor_audio_unprepare(sor); 2218 tegra_sor_hdmi_scdc_stop(sor); 2219 2220 err = tegra_sor_detach(sor); 2221 if (err < 0) 2222 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 2223 2224 tegra_sor_writel(sor, 0, SOR_STATE1); 2225 tegra_sor_update(sor); 2226 2227 /* disable display to SOR clock */ 2228 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2229 2230 if (!sor->soc->has_nvdisplay) 2231 value &= ~SOR1_TIMING_CYA; 2232 2233 value &= ~SOR_ENABLE(sor->index); 2234 2235 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2236 2237 tegra_dc_commit(dc); 2238 2239 err = tegra_sor_power_down(sor); 2240 if (err < 0) 2241 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 2242 2243 err = tegra_pmc_io_pad_power_disable(sor->pmc, sor->pad); 2244 if (err < 0) 2245 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 2246 2247 host1x_client_suspend(&sor->client); 2248 } 2249 2250 static void tegra_sor_hdmi_enable(struct drm_encoder *encoder) 2251 { 2252 struct tegra_output *output = encoder_to_output(encoder); 2253 unsigned int h_ref_to_sync = 1, pulse_start, max_ac; 2254 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2255 struct tegra_sor_hdmi_settings *settings; 2256 struct tegra_sor *sor = to_sor(output); 2257 struct tegra_sor_state *state; 2258 struct drm_display_mode *mode; 2259 unsigned long rate, pclk; 2260 unsigned int div, i; 2261 u32 value; 2262 int err; 2263 2264 state = to_sor_state(output->connector.state); 2265 mode = &encoder->crtc->state->adjusted_mode; 2266 pclk = mode->clock * 1000; 2267 2268 err = host1x_client_resume(&sor->client); 2269 if (err < 0) { 2270 dev_err(sor->dev, "failed to resume: %d\n", err); 2271 return; 2272 } 2273 2274 /* switch to safe parent clock */ 2275 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2276 if (err < 0) { 2277 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 2278 return; 2279 } 2280 2281 div = clk_get_rate(sor->clk) / 1000000 * 4; 2282 2283 err = tegra_pmc_io_pad_power_enable(sor->pmc, sor->pad); 2284 if (err < 0) 2285 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); 2286 2287 usleep_range(20, 100); 2288 2289 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2290 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2291 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2292 2293 usleep_range(20, 100); 2294 2295 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2296 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; 2297 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2298 2299 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2300 value &= ~SOR_PLL0_VCOPD; 2301 value &= ~SOR_PLL0_PWR; 2302 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2303 2304 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2305 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2306 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2307 2308 usleep_range(200, 400); 2309 2310 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2311 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2312 value &= ~SOR_PLL2_PORT_POWERDOWN; 2313 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2314 2315 usleep_range(20, 100); 2316 2317 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2318 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | 2319 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2; 2320 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2321 2322 while (true) { 2323 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2324 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) 2325 break; 2326 2327 usleep_range(250, 1000); 2328 } 2329 2330 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | 2331 SOR_LANE_SEQ_CTL_POWER_STATE_UP | SOR_LANE_SEQ_CTL_DELAY(5); 2332 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); 2333 2334 while (true) { 2335 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); 2336 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) 2337 break; 2338 2339 usleep_range(250, 1000); 2340 } 2341 2342 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 2343 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; 2344 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2345 2346 if (mode->clock < 340000) { 2347 DRM_DEBUG_KMS("setting 2.7 GHz link speed\n"); 2348 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; 2349 } else { 2350 DRM_DEBUG_KMS("setting 5.4 GHz link speed\n"); 2351 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; 2352 } 2353 2354 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; 2355 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2356 2357 /* SOR pad PLL stabilization time */ 2358 usleep_range(250, 1000); 2359 2360 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 2361 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; 2362 value |= SOR_DP_LINKCTL_LANE_COUNT(4); 2363 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 2364 2365 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2366 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2367 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2368 value &= ~SOR_DP_SPARE_SEQ_ENABLE; 2369 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; 2370 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2371 2372 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | 2373 SOR_SEQ_CTL_PD_PC(8) | SOR_SEQ_CTL_PD_PC_ALT(8); 2374 tegra_sor_writel(sor, value, SOR_SEQ_CTL); 2375 2376 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | 2377 SOR_SEQ_INST_WAIT_VSYNC | SOR_SEQ_INST_WAIT(1); 2378 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); 2379 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); 2380 2381 if (!sor->soc->has_nvdisplay) { 2382 /* program the reference clock */ 2383 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); 2384 tegra_sor_writel(sor, value, SOR_REFCLK); 2385 } 2386 2387 /* XXX not in TRM */ 2388 for (value = 0, i = 0; i < 5; i++) 2389 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | 2390 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 2391 2392 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 2393 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2394 2395 /* 2396 * Switch the pad clock to the DP clock. Note that we cannot actually 2397 * do this because Tegra186 and later don't support clk_set_parent() 2398 * on the sorX_pad_clkout clocks. We already do the equivalent above 2399 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register. 2400 */ 2401 #if 0 2402 err = clk_set_parent(sor->clk_pad, sor->clk_dp); 2403 if (err < 0) { 2404 dev_err(sor->dev, "failed to select pad parent clock: %d\n", 2405 err); 2406 return; 2407 } 2408 #endif 2409 2410 /* switch the SOR clock to the pad clock */ 2411 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); 2412 if (err < 0) { 2413 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", 2414 err); 2415 return; 2416 } 2417 2418 /* switch the output clock to the parent pixel clock */ 2419 err = clk_set_parent(sor->clk, sor->clk_parent); 2420 if (err < 0) { 2421 dev_err(sor->dev, "failed to select output parent clock: %d\n", 2422 err); 2423 return; 2424 } 2425 2426 /* adjust clock rate for HDMI 2.0 modes */ 2427 rate = clk_get_rate(sor->clk_parent); 2428 2429 if (mode->clock >= 340000) 2430 rate /= 2; 2431 2432 DRM_DEBUG_KMS("setting clock to %lu Hz, mode: %lu Hz\n", rate, pclk); 2433 2434 clk_set_rate(sor->clk, rate); 2435 2436 if (!sor->soc->has_nvdisplay) { 2437 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); 2438 2439 /* XXX is this the proper check? */ 2440 if (mode->clock < 75000) 2441 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; 2442 2443 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); 2444 } 2445 2446 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; 2447 2448 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | 2449 SOR_HDMI_CTRL_AUDIO_LAYOUT | SOR_HDMI_CTRL_REKEY(SOR_REKEY); 2450 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); 2451 2452 if (!dc->soc->has_nvdisplay) { 2453 /* H_PULSE2 setup */ 2454 pulse_start = h_ref_to_sync + 2455 (mode->hsync_end - mode->hsync_start) + 2456 (mode->htotal - mode->hsync_end) - 10; 2457 2458 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | 2459 PULSE_POLARITY_HIGH | PULSE_MODE_NORMAL; 2460 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); 2461 2462 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); 2463 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); 2464 2465 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); 2466 value |= H_PULSE2_ENABLE; 2467 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); 2468 } 2469 2470 /* infoframe setup */ 2471 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); 2472 if (err < 0) 2473 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); 2474 2475 /* XXX HDMI audio support not implemented yet */ 2476 tegra_sor_hdmi_disable_audio_infoframe(sor); 2477 2478 /* use single TMDS protocol */ 2479 value = tegra_sor_readl(sor, SOR_STATE1); 2480 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2481 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; 2482 tegra_sor_writel(sor, value, SOR_STATE1); 2483 2484 /* power up pad calibration */ 2485 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2486 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; 2487 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2488 2489 /* production settings */ 2490 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); 2491 if (!settings) { 2492 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", 2493 mode->clock * 1000); 2494 return; 2495 } 2496 2497 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2498 value &= ~SOR_PLL0_ICHPMP_MASK; 2499 value &= ~SOR_PLL0_FILTER_MASK; 2500 value &= ~SOR_PLL0_VCOCAP_MASK; 2501 value |= SOR_PLL0_ICHPMP(settings->ichpmp); 2502 value |= SOR_PLL0_FILTER(settings->filter); 2503 value |= SOR_PLL0_VCOCAP(settings->vcocap); 2504 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2505 2506 /* XXX not in TRM */ 2507 value = tegra_sor_readl(sor, sor->soc->regs->pll1); 2508 value &= ~SOR_PLL1_LOADADJ_MASK; 2509 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; 2510 value |= SOR_PLL1_LOADADJ(settings->loadadj); 2511 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); 2512 value |= SOR_PLL1_TMDS_TERM; 2513 tegra_sor_writel(sor, value, sor->soc->regs->pll1); 2514 2515 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2516 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; 2517 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; 2518 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; 2519 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; 2520 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); 2521 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); 2522 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); 2523 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); 2524 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2525 2526 value = settings->drive_current[3] << 24 | 2527 settings->drive_current[2] << 16 | 2528 settings->drive_current[1] << 8 | 2529 settings->drive_current[0] << 0; 2530 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); 2531 2532 value = settings->preemphasis[3] << 24 | 2533 settings->preemphasis[2] << 16 | 2534 settings->preemphasis[1] << 8 | 2535 settings->preemphasis[0] << 0; 2536 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); 2537 2538 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2539 value &= ~SOR_DP_PADCTL_TX_PU_MASK; 2540 value |= SOR_DP_PADCTL_TX_PU_ENABLE; 2541 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); 2542 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2543 2544 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); 2545 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; 2546 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); 2547 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); 2548 2549 /* power down pad calibration */ 2550 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); 2551 value |= SOR_DP_PADCTL_PAD_CAL_PD; 2552 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); 2553 2554 if (!dc->soc->has_nvdisplay) { 2555 /* miscellaneous display controller settings */ 2556 value = VSYNC_H_POSITION(1); 2557 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); 2558 } 2559 2560 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); 2561 value &= ~DITHER_CONTROL_MASK; 2562 value &= ~BASE_COLOR_SIZE_MASK; 2563 if (dc->soc->has_nvdisplay) { 2564 tegra_dc_writel(dc, lower_32_bits(dc->cmu_output_lut_phys), 2565 DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE); 2566 tegra_dc_writel(dc, upper_32_bits(dc->cmu_output_lut_phys), 2567 DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI); 2568 2569 tegra_dc_writel(dc, OUTPUT_LUT_MODE_INTERPOLATE | OUTPUT_LUT_SIZE_SIZE_1025, 2570 DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT); 2571 2572 value |= CMU_ENABLE_ENABLE; 2573 } 2574 2575 switch (state->bpc) { 2576 case 6: 2577 value |= BASE_COLOR_SIZE_666; 2578 break; 2579 2580 case 8: 2581 value |= BASE_COLOR_SIZE_888; 2582 break; 2583 2584 case 10: 2585 value |= BASE_COLOR_SIZE_101010; 2586 break; 2587 2588 case 12: 2589 value |= BASE_COLOR_SIZE_121212; 2590 break; 2591 2592 default: 2593 WARN(1, "%u bits-per-color not supported\n", state->bpc); 2594 value |= BASE_COLOR_SIZE_888; 2595 break; 2596 } 2597 2598 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); 2599 2600 /* XXX set display head owner */ 2601 value = tegra_sor_readl(sor, SOR_STATE1); 2602 value &= ~SOR_STATE_ASY_OWNER_MASK; 2603 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); 2604 tegra_sor_writel(sor, value, SOR_STATE1); 2605 2606 err = tegra_sor_power_up(sor, 250); 2607 if (err < 0) 2608 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2609 2610 /* configure dynamic range of output */ 2611 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2612 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; 2613 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; 2614 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2615 2616 /* configure colorspace */ 2617 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); 2618 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; 2619 value |= SOR_HEAD_STATE_COLORSPACE_RGB; 2620 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); 2621 2622 tegra_sor_mode_set(sor, mode, state); 2623 2624 tegra_sor_update(sor); 2625 2626 /* program preamble timing in SOR (XXX) */ 2627 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2628 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; 2629 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2630 2631 err = tegra_sor_attach(sor); 2632 if (err < 0) 2633 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2634 2635 /* enable display to SOR clock and generate HDMI preamble */ 2636 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2637 2638 if (!sor->soc->has_nvdisplay) 2639 value |= SOR1_TIMING_CYA; 2640 2641 value |= SOR_ENABLE(sor->index); 2642 2643 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2644 2645 if (dc->soc->has_nvdisplay) { 2646 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2647 value &= ~PROTOCOL_MASK; 2648 value |= PROTOCOL_SINGLE_TMDS_A; 2649 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); 2650 } 2651 2652 tegra_dc_commit(dc); 2653 2654 err = tegra_sor_wakeup(sor); 2655 if (err < 0) 2656 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 2657 2658 tegra_sor_hdmi_scdc_start(sor); 2659 tegra_sor_audio_prepare(sor); 2660 } 2661 2662 static const struct drm_encoder_helper_funcs tegra_sor_hdmi_helpers = { 2663 .disable = tegra_sor_hdmi_disable, 2664 .enable = tegra_sor_hdmi_enable, 2665 .atomic_check = tegra_sor_encoder_atomic_check, 2666 }; 2667 2668 static void tegra_sor_dp_disable(struct drm_encoder *encoder) 2669 { 2670 struct tegra_output *output = encoder_to_output(encoder); 2671 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2672 struct tegra_sor *sor = to_sor(output); 2673 u32 value; 2674 int err; 2675 2676 if (output->panel) 2677 drm_panel_disable(output->panel); 2678 2679 /* 2680 * Do not attempt to power down a DP link if we're not connected since 2681 * the AUX transactions would just be timing out. 2682 */ 2683 if (output->connector.status != connector_status_disconnected) { 2684 err = drm_dp_link_power_down(sor->aux, sor->link.revision); 2685 if (err < 0) 2686 dev_err(sor->dev, "failed to power down link: %d\n", 2687 err); 2688 } 2689 2690 err = tegra_sor_detach(sor); 2691 if (err < 0) 2692 dev_err(sor->dev, "failed to detach SOR: %d\n", err); 2693 2694 tegra_sor_writel(sor, 0, SOR_STATE1); 2695 tegra_sor_update(sor); 2696 2697 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2698 value &= ~SOR_ENABLE(sor->index); 2699 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2700 tegra_dc_commit(dc); 2701 2702 value = tegra_sor_readl(sor, SOR_STATE1); 2703 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2704 value &= ~SOR_STATE_ASY_SUBOWNER_MASK; 2705 value &= ~SOR_STATE_ASY_OWNER_MASK; 2706 tegra_sor_writel(sor, value, SOR_STATE1); 2707 tegra_sor_update(sor); 2708 2709 /* switch to safe parent clock */ 2710 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2711 if (err < 0) 2712 dev_err(sor->dev, "failed to set safe clock: %d\n", err); 2713 2714 err = tegra_sor_power_down(sor); 2715 if (err < 0) 2716 dev_err(sor->dev, "failed to power down SOR: %d\n", err); 2717 2718 err = tegra_pmc_io_pad_power_disable(sor->pmc, sor->pad); 2719 if (err < 0) 2720 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); 2721 2722 err = drm_dp_aux_disable(sor->aux); 2723 if (err < 0) 2724 dev_err(sor->dev, "failed disable DPAUX: %d\n", err); 2725 2726 if (output->panel) 2727 drm_panel_unprepare(output->panel); 2728 2729 host1x_client_suspend(&sor->client); 2730 } 2731 2732 static void tegra_sor_dp_enable(struct drm_encoder *encoder) 2733 { 2734 struct tegra_output *output = encoder_to_output(encoder); 2735 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 2736 struct tegra_sor *sor = to_sor(output); 2737 struct tegra_sor_config config; 2738 struct tegra_sor_state *state; 2739 struct drm_display_mode *mode; 2740 struct drm_display_info *info; 2741 unsigned int i; 2742 u32 value; 2743 int err; 2744 2745 state = to_sor_state(output->connector.state); 2746 mode = &encoder->crtc->state->adjusted_mode; 2747 info = &output->connector.display_info; 2748 2749 err = host1x_client_resume(&sor->client); 2750 if (err < 0) { 2751 dev_err(sor->dev, "failed to resume: %d\n", err); 2752 return; 2753 } 2754 2755 /* switch to safe parent clock */ 2756 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); 2757 if (err < 0) 2758 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); 2759 2760 err = tegra_pmc_io_pad_power_enable(sor->pmc, sor->pad); 2761 if (err < 0) 2762 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); 2763 2764 usleep_range(20, 100); 2765 2766 err = drm_dp_aux_enable(sor->aux); 2767 if (err < 0) 2768 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); 2769 2770 err = drm_dp_link_probe(sor->aux, &sor->link); 2771 if (err < 0) 2772 dev_err(sor->dev, "failed to probe DP link: %d\n", err); 2773 2774 tegra_sor_filter_rates(sor); 2775 2776 err = drm_dp_link_choose(&sor->link, mode, info); 2777 if (err < 0) 2778 dev_err(sor->dev, "failed to choose link: %d\n", err); 2779 2780 if (output->panel) 2781 drm_panel_prepare(output->panel); 2782 2783 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2784 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; 2785 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2786 2787 usleep_range(20, 40); 2788 2789 value = tegra_sor_readl(sor, sor->soc->regs->pll3); 2790 value |= SOR_PLL3_PLL_VDD_MODE_3V3; 2791 tegra_sor_writel(sor, value, sor->soc->regs->pll3); 2792 2793 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2794 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR); 2795 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2796 2797 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2798 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; 2799 value |= SOR_PLL2_SEQ_PLLCAPPD; 2800 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2801 2802 usleep_range(200, 400); 2803 2804 value = tegra_sor_readl(sor, sor->soc->regs->pll2); 2805 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; 2806 value &= ~SOR_PLL2_PORT_POWERDOWN; 2807 tegra_sor_writel(sor, value, sor->soc->regs->pll2); 2808 2809 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); 2810 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; 2811 2812 if (output->panel) 2813 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; 2814 else 2815 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK; 2816 2817 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); 2818 2819 usleep_range(200, 400); 2820 2821 value = tegra_sor_readl(sor, SOR_DP_SPARE0); 2822 /* XXX not in TRM */ 2823 if (output->panel) 2824 value |= SOR_DP_SPARE_PANEL_INTERNAL; 2825 else 2826 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; 2827 2828 value |= SOR_DP_SPARE_SEQ_ENABLE; 2829 tegra_sor_writel(sor, value, SOR_DP_SPARE0); 2830 2831 /* XXX not in TRM */ 2832 tegra_sor_writel(sor, 0, SOR_LVDS); 2833 2834 value = tegra_sor_readl(sor, sor->soc->regs->pll0); 2835 value &= ~SOR_PLL0_ICHPMP_MASK; 2836 value &= ~SOR_PLL0_VCOCAP_MASK; 2837 value |= SOR_PLL0_ICHPMP(0x1); 2838 value |= SOR_PLL0_VCOCAP(0x3); 2839 value |= SOR_PLL0_RESISTOR_EXT; 2840 tegra_sor_writel(sor, value, sor->soc->regs->pll0); 2841 2842 /* XXX not in TRM */ 2843 for (value = 0, i = 0; i < 5; i++) 2844 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | 2845 SOR_XBAR_CTRL_LINK1_XSEL(i, i); 2846 2847 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); 2848 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); 2849 2850 /* 2851 * Switch the pad clock to the DP clock. Note that we cannot actually 2852 * do this because Tegra186 and later don't support clk_set_parent() 2853 * on the sorX_pad_clkout clocks. We already do the equivalent above 2854 * using the DP_CLK_SEL mux of the SOR_CLK_CNTRL register. 2855 */ 2856 #if 0 2857 err = clk_set_parent(sor->clk_pad, sor->clk_parent); 2858 if (err < 0) { 2859 dev_err(sor->dev, "failed to select pad parent clock: %d\n", 2860 err); 2861 return; 2862 } 2863 #endif 2864 2865 /* switch the SOR clock to the pad clock */ 2866 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); 2867 if (err < 0) { 2868 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", 2869 err); 2870 return; 2871 } 2872 2873 /* switch the output clock to the parent pixel clock */ 2874 err = clk_set_parent(sor->clk, sor->clk_parent); 2875 if (err < 0) { 2876 dev_err(sor->dev, "failed to select output parent clock: %d\n", 2877 err); 2878 return; 2879 } 2880 2881 /* use DP-A protocol */ 2882 value = tegra_sor_readl(sor, SOR_STATE1); 2883 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; 2884 value |= SOR_STATE_ASY_PROTOCOL_DP_A; 2885 tegra_sor_writel(sor, value, SOR_STATE1); 2886 2887 /* enable port */ 2888 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); 2889 value |= SOR_DP_LINKCTL_ENABLE; 2890 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); 2891 2892 tegra_sor_dp_term_calibrate(sor); 2893 2894 err = drm_dp_link_train(&sor->link); 2895 if (err < 0) 2896 dev_err(sor->dev, "link training failed: %d\n", err); 2897 else 2898 dev_dbg(sor->dev, "link training succeeded\n"); 2899 2900 err = drm_dp_link_power_up(sor->aux, sor->link.revision); 2901 if (err < 0) 2902 dev_err(sor->dev, "failed to power up DP link: %d\n", err); 2903 2904 /* compute configuration */ 2905 memset(&config, 0, sizeof(config)); 2906 config.bits_per_pixel = state->bpc * 3; 2907 2908 err = tegra_sor_compute_config(sor, mode, &config, &sor->link); 2909 if (err < 0) 2910 dev_err(sor->dev, "failed to compute configuration: %d\n", err); 2911 2912 tegra_sor_apply_config(sor, &config); 2913 tegra_sor_mode_set(sor, mode, state); 2914 2915 if (output->panel) { 2916 /* CSTM (LVDS, link A/B, upper) */ 2917 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | 2918 SOR_CSTM_UPPER; 2919 tegra_sor_writel(sor, value, SOR_CSTM); 2920 2921 /* PWM setup */ 2922 err = tegra_sor_setup_pwm(sor, 250); 2923 if (err < 0) 2924 dev_err(sor->dev, "failed to setup PWM: %d\n", err); 2925 } 2926 2927 tegra_sor_update(sor); 2928 2929 err = tegra_sor_power_up(sor, 250); 2930 if (err < 0) 2931 dev_err(sor->dev, "failed to power up SOR: %d\n", err); 2932 2933 /* attach and wake up */ 2934 err = tegra_sor_attach(sor); 2935 if (err < 0) 2936 dev_err(sor->dev, "failed to attach SOR: %d\n", err); 2937 2938 if (dc->soc->has_nvdisplay) { 2939 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); 2940 tegra_dc_writel(dc, lower_32_bits(dc->cmu_output_lut_phys), 2941 DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE); 2942 tegra_dc_writel(dc, upper_32_bits(dc->cmu_output_lut_phys), 2943 DC_DISP_COREPVT_HEAD_SET_OUTPUT_LUT_BASE_HI); 2944 2945 tegra_dc_writel(dc, OUTPUT_LUT_MODE_INTERPOLATE | OUTPUT_LUT_SIZE_SIZE_1025, 2946 DC_DISP_CORE_HEAD_SET_CONTROL_OUTPUT_LUT); 2947 2948 value |= CMU_ENABLE_ENABLE; 2949 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); 2950 } 2951 2952 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 2953 value |= SOR_ENABLE(sor->index); 2954 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 2955 2956 tegra_dc_commit(dc); 2957 2958 err = tegra_sor_wakeup(sor); 2959 if (err < 0) 2960 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); 2961 2962 if (output->panel) 2963 drm_panel_enable(output->panel); 2964 } 2965 2966 static const struct drm_encoder_helper_funcs tegra_sor_dp_helpers = { 2967 .disable = tegra_sor_dp_disable, 2968 .enable = tegra_sor_dp_enable, 2969 .atomic_check = tegra_sor_encoder_atomic_check, 2970 }; 2971 2972 static void tegra_sor_disable_regulator(void *data) 2973 { 2974 struct regulator *reg = data; 2975 2976 regulator_disable(reg); 2977 } 2978 2979 static int tegra_sor_enable_regulator(struct tegra_sor *sor, struct regulator *reg) 2980 { 2981 int err; 2982 2983 err = regulator_enable(reg); 2984 if (err) 2985 return err; 2986 2987 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg); 2988 } 2989 2990 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) 2991 { 2992 int err; 2993 2994 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); 2995 if (IS_ERR(sor->avdd_io_supply)) 2996 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply), 2997 "cannot get AVDD I/O supply\n"); 2998 2999 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); 3000 if (err < 0) { 3001 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", 3002 err); 3003 return err; 3004 } 3005 3006 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); 3007 if (IS_ERR(sor->vdd_pll_supply)) 3008 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply), 3009 "cannot get VDD PLL supply\n"); 3010 3011 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); 3012 if (err < 0) { 3013 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", 3014 err); 3015 return err; 3016 } 3017 3018 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); 3019 if (IS_ERR(sor->hdmi_supply)) 3020 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply), 3021 "cannot get HDMI supply\n"); 3022 3023 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply); 3024 if (err < 0) { 3025 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); 3026 return err; 3027 } 3028 3029 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); 3030 3031 return 0; 3032 } 3033 3034 static const struct tegra_sor_ops tegra_sor_hdmi_ops = { 3035 .name = "HDMI", 3036 .probe = tegra_sor_hdmi_probe, 3037 .audio_enable = tegra_sor_hdmi_audio_enable, 3038 .audio_disable = tegra_sor_hdmi_audio_disable, 3039 }; 3040 3041 static int tegra_sor_dp_probe(struct tegra_sor *sor) 3042 { 3043 int err; 3044 3045 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); 3046 if (IS_ERR(sor->avdd_io_supply)) 3047 return PTR_ERR(sor->avdd_io_supply); 3048 3049 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); 3050 if (err < 0) 3051 return err; 3052 3053 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); 3054 if (IS_ERR(sor->vdd_pll_supply)) 3055 return PTR_ERR(sor->vdd_pll_supply); 3056 3057 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); 3058 if (err < 0) 3059 return err; 3060 3061 return 0; 3062 } 3063 3064 static const struct tegra_sor_ops tegra_sor_dp_ops = { 3065 .name = "DP", 3066 .probe = tegra_sor_dp_probe, 3067 }; 3068 3069 static const struct drm_encoder_funcs tegra_sor_encoder_funcs_cleanup = { 3070 .destroy = drm_encoder_cleanup, 3071 }; 3072 3073 static int tegra_sor_init(struct host1x_client *client) 3074 { 3075 struct drm_device *drm = dev_get_drvdata(client->host); 3076 const struct drm_encoder_helper_funcs *helpers = NULL; 3077 struct tegra_sor *sor = host1x_client_to_sor(client); 3078 int connector = DRM_MODE_CONNECTOR_Unknown; 3079 int encoder = DRM_MODE_ENCODER_NONE; 3080 int err; 3081 3082 if (!sor->aux) { 3083 if (sor->ops == &tegra_sor_hdmi_ops) { 3084 connector = DRM_MODE_CONNECTOR_HDMIA; 3085 encoder = DRM_MODE_ENCODER_TMDS; 3086 helpers = &tegra_sor_hdmi_helpers; 3087 } else if (sor->soc->supports_lvds) { 3088 connector = DRM_MODE_CONNECTOR_LVDS; 3089 encoder = DRM_MODE_ENCODER_LVDS; 3090 } 3091 } else { 3092 if (sor->output.panel) { 3093 connector = DRM_MODE_CONNECTOR_eDP; 3094 encoder = DRM_MODE_ENCODER_TMDS; 3095 helpers = &tegra_sor_dp_helpers; 3096 } else { 3097 connector = DRM_MODE_CONNECTOR_DisplayPort; 3098 encoder = DRM_MODE_ENCODER_TMDS; 3099 helpers = &tegra_sor_dp_helpers; 3100 } 3101 3102 sor->link.ops = &tegra_sor_dp_link_ops; 3103 sor->link.aux = sor->aux; 3104 } 3105 3106 sor->output.dev = sor->dev; 3107 3108 drm_connector_init_with_ddc(drm, &sor->output.connector, 3109 &tegra_sor_connector_funcs, 3110 connector, 3111 sor->output.ddc); 3112 drm_connector_helper_add(&sor->output.connector, 3113 &tegra_sor_connector_helper_funcs); 3114 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; 3115 3116 drm_encoder_init(drm, &sor->output.encoder, 3117 &tegra_sor_encoder_funcs_cleanup, encoder, NULL); 3118 drm_encoder_helper_add(&sor->output.encoder, helpers); 3119 3120 drm_connector_attach_encoder(&sor->output.connector, 3121 &sor->output.encoder); 3122 drm_connector_register(&sor->output.connector); 3123 3124 err = tegra_output_init(drm, &sor->output); 3125 if (err < 0) { 3126 dev_err(client->dev, "failed to initialize output: %d\n", err); 3127 return err; 3128 } 3129 3130 tegra_output_find_possible_crtcs(&sor->output, drm); 3131 3132 if (sor->aux) { 3133 err = drm_dp_aux_attach(sor->aux, &sor->output); 3134 if (err < 0) { 3135 dev_err(sor->dev, "failed to attach DP: %d\n", err); 3136 return err; 3137 } 3138 } 3139 3140 /* 3141 * XXX: Remove this reset once proper hand-over from firmware to 3142 * kernel is possible. 3143 */ 3144 if (sor->rst) { 3145 err = pm_runtime_resume_and_get(sor->dev); 3146 if (err < 0) { 3147 dev_err(sor->dev, "failed to get runtime PM: %d\n", err); 3148 return err; 3149 } 3150 3151 err = reset_control_acquire(sor->rst); 3152 if (err < 0) { 3153 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", 3154 err); 3155 goto rpm_put; 3156 } 3157 3158 err = reset_control_assert(sor->rst); 3159 if (err < 0) { 3160 dev_err(sor->dev, "failed to assert SOR reset: %d\n", 3161 err); 3162 goto rpm_put; 3163 } 3164 } 3165 3166 err = clk_prepare_enable(sor->clk); 3167 if (err < 0) { 3168 dev_err(sor->dev, "failed to enable clock: %d\n", err); 3169 goto rpm_put; 3170 } 3171 3172 usleep_range(1000, 3000); 3173 3174 if (sor->rst) { 3175 err = reset_control_deassert(sor->rst); 3176 if (err < 0) { 3177 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", 3178 err); 3179 clk_disable_unprepare(sor->clk); 3180 goto rpm_put; 3181 } 3182 3183 reset_control_release(sor->rst); 3184 pm_runtime_put(sor->dev); 3185 } 3186 3187 err = clk_prepare_enable(sor->clk_safe); 3188 if (err < 0) { 3189 clk_disable_unprepare(sor->clk); 3190 return err; 3191 } 3192 3193 err = clk_prepare_enable(sor->clk_dp); 3194 if (err < 0) { 3195 clk_disable_unprepare(sor->clk_safe); 3196 clk_disable_unprepare(sor->clk); 3197 return err; 3198 } 3199 3200 return 0; 3201 3202 rpm_put: 3203 if (sor->rst) 3204 pm_runtime_put(sor->dev); 3205 3206 return err; 3207 } 3208 3209 static int tegra_sor_exit(struct host1x_client *client) 3210 { 3211 struct tegra_sor *sor = host1x_client_to_sor(client); 3212 int err; 3213 3214 tegra_output_exit(&sor->output); 3215 3216 if (sor->aux) { 3217 err = drm_dp_aux_detach(sor->aux); 3218 if (err < 0) { 3219 dev_err(sor->dev, "failed to detach DP: %d\n", err); 3220 return err; 3221 } 3222 } 3223 3224 clk_disable_unprepare(sor->clk_safe); 3225 clk_disable_unprepare(sor->clk_dp); 3226 clk_disable_unprepare(sor->clk); 3227 3228 return 0; 3229 } 3230 3231 static int tegra_sor_runtime_suspend(struct host1x_client *client) 3232 { 3233 struct tegra_sor *sor = host1x_client_to_sor(client); 3234 struct device *dev = client->dev; 3235 int err; 3236 3237 if (sor->rst) { 3238 err = reset_control_assert(sor->rst); 3239 if (err < 0) { 3240 dev_err(dev, "failed to assert reset: %d\n", err); 3241 return err; 3242 } 3243 3244 reset_control_release(sor->rst); 3245 } 3246 3247 usleep_range(1000, 2000); 3248 3249 clk_disable_unprepare(sor->clk); 3250 pm_runtime_put_sync(dev); 3251 3252 return 0; 3253 } 3254 3255 static int tegra_sor_runtime_resume(struct host1x_client *client) 3256 { 3257 struct tegra_sor *sor = host1x_client_to_sor(client); 3258 struct device *dev = client->dev; 3259 int err; 3260 3261 err = pm_runtime_resume_and_get(dev); 3262 if (err < 0) { 3263 dev_err(dev, "failed to get runtime PM: %d\n", err); 3264 return err; 3265 } 3266 3267 err = clk_prepare_enable(sor->clk); 3268 if (err < 0) { 3269 dev_err(dev, "failed to enable clock: %d\n", err); 3270 goto put_rpm; 3271 } 3272 3273 usleep_range(1000, 2000); 3274 3275 if (sor->rst) { 3276 err = reset_control_acquire(sor->rst); 3277 if (err < 0) { 3278 dev_err(dev, "failed to acquire reset: %d\n", err); 3279 goto disable_clk; 3280 } 3281 3282 err = reset_control_deassert(sor->rst); 3283 if (err < 0) { 3284 dev_err(dev, "failed to deassert reset: %d\n", err); 3285 goto release_reset; 3286 } 3287 } 3288 3289 return 0; 3290 3291 release_reset: 3292 reset_control_release(sor->rst); 3293 disable_clk: 3294 clk_disable_unprepare(sor->clk); 3295 put_rpm: 3296 pm_runtime_put_sync(dev); 3297 return err; 3298 } 3299 3300 static const struct host1x_client_ops sor_client_ops = { 3301 .init = tegra_sor_init, 3302 .exit = tegra_sor_exit, 3303 .suspend = tegra_sor_runtime_suspend, 3304 .resume = tegra_sor_runtime_resume, 3305 }; 3306 3307 static const u8 tegra124_sor_xbar_cfg[5] = { 3308 0, 1, 2, 3, 4 3309 }; 3310 3311 static const struct tegra_sor_regs tegra124_sor_regs = { 3312 .head_state0 = 0x05, 3313 .head_state1 = 0x07, 3314 .head_state2 = 0x09, 3315 .head_state3 = 0x0b, 3316 .head_state4 = 0x0d, 3317 .head_state5 = 0x0f, 3318 .pll0 = 0x17, 3319 .pll1 = 0x18, 3320 .pll2 = 0x19, 3321 .pll3 = 0x1a, 3322 .dp_padctl0 = 0x5c, 3323 .dp_padctl2 = 0x73, 3324 }; 3325 3326 /* Tegra124 and Tegra132 have lanes 0 and 2 swapped. */ 3327 static const u8 tegra124_sor_lane_map[4] = { 3328 2, 1, 0, 3, 3329 }; 3330 3331 static const u8 tegra124_sor_voltage_swing[4][4][4] = { 3332 { 3333 { 0x13, 0x19, 0x1e, 0x28 }, 3334 { 0x1e, 0x25, 0x2d, }, 3335 { 0x28, 0x32, }, 3336 { 0x3c, }, 3337 }, { 3338 { 0x12, 0x17, 0x1b, 0x25 }, 3339 { 0x1c, 0x23, 0x2a, }, 3340 { 0x25, 0x2f, }, 3341 { 0x39, } 3342 }, { 3343 { 0x12, 0x16, 0x1a, 0x22 }, 3344 { 0x1b, 0x20, 0x27, }, 3345 { 0x24, 0x2d, }, 3346 { 0x36, }, 3347 }, { 3348 { 0x11, 0x14, 0x17, 0x1f }, 3349 { 0x19, 0x1e, 0x24, }, 3350 { 0x22, 0x2a, }, 3351 { 0x32, }, 3352 }, 3353 }; 3354 3355 static const u8 tegra124_sor_pre_emphasis[4][4][4] = { 3356 { 3357 { 0x00, 0x09, 0x13, 0x25 }, 3358 { 0x00, 0x0f, 0x1e, }, 3359 { 0x00, 0x14, }, 3360 { 0x00, }, 3361 }, { 3362 { 0x00, 0x0a, 0x14, 0x28 }, 3363 { 0x00, 0x0f, 0x1e, }, 3364 { 0x00, 0x14, }, 3365 { 0x00 }, 3366 }, { 3367 { 0x00, 0x0a, 0x14, 0x28 }, 3368 { 0x00, 0x0f, 0x1e, }, 3369 { 0x00, 0x14, }, 3370 { 0x00, }, 3371 }, { 3372 { 0x00, 0x0a, 0x14, 0x28 }, 3373 { 0x00, 0x0f, 0x1e, }, 3374 { 0x00, 0x14, }, 3375 { 0x00, }, 3376 }, 3377 }; 3378 3379 static const u8 tegra124_sor_post_cursor[4][4][4] = { 3380 { 3381 { 0x00, 0x00, 0x00, 0x00 }, 3382 { 0x00, 0x00, 0x00, }, 3383 { 0x00, 0x00, }, 3384 { 0x00, }, 3385 }, { 3386 { 0x02, 0x02, 0x04, 0x05 }, 3387 { 0x02, 0x04, 0x05, }, 3388 { 0x04, 0x05, }, 3389 { 0x05, }, 3390 }, { 3391 { 0x04, 0x05, 0x08, 0x0b }, 3392 { 0x05, 0x09, 0x0b, }, 3393 { 0x08, 0x0a, }, 3394 { 0x0b, }, 3395 }, { 3396 { 0x05, 0x09, 0x0b, 0x12 }, 3397 { 0x09, 0x0d, 0x12, }, 3398 { 0x0b, 0x0f, }, 3399 { 0x12, }, 3400 }, 3401 }; 3402 3403 static const u8 tegra124_sor_tx_pu[4][4][4] = { 3404 { 3405 { 0x20, 0x30, 0x40, 0x60 }, 3406 { 0x30, 0x40, 0x60, }, 3407 { 0x40, 0x60, }, 3408 { 0x60, }, 3409 }, { 3410 { 0x20, 0x20, 0x30, 0x50 }, 3411 { 0x30, 0x40, 0x50, }, 3412 { 0x40, 0x50, }, 3413 { 0x60, }, 3414 }, { 3415 { 0x20, 0x20, 0x30, 0x40, }, 3416 { 0x30, 0x30, 0x40, }, 3417 { 0x40, 0x50, }, 3418 { 0x60, }, 3419 }, { 3420 { 0x20, 0x20, 0x20, 0x40, }, 3421 { 0x30, 0x30, 0x40, }, 3422 { 0x40, 0x40, }, 3423 { 0x60, }, 3424 }, 3425 }; 3426 3427 static const struct tegra_sor_soc tegra124_sor = { 3428 .supports_lvds = true, 3429 .supports_hdmi = false, 3430 .supports_dp = true, 3431 .supports_audio = false, 3432 .supports_hdcp = false, 3433 .regs = &tegra124_sor_regs, 3434 .has_nvdisplay = false, 3435 .xbar_cfg = tegra124_sor_xbar_cfg, 3436 .lane_map = tegra124_sor_lane_map, 3437 .voltage_swing = tegra124_sor_voltage_swing, 3438 .pre_emphasis = tegra124_sor_pre_emphasis, 3439 .post_cursor = tegra124_sor_post_cursor, 3440 .tx_pu = tegra124_sor_tx_pu, 3441 }; 3442 3443 static const u8 tegra132_sor_pre_emphasis[4][4][4] = { 3444 { 3445 { 0x00, 0x08, 0x12, 0x24 }, 3446 { 0x01, 0x0e, 0x1d, }, 3447 { 0x01, 0x13, }, 3448 { 0x00, }, 3449 }, { 3450 { 0x00, 0x08, 0x12, 0x24 }, 3451 { 0x00, 0x0e, 0x1d, }, 3452 { 0x00, 0x13, }, 3453 { 0x00 }, 3454 }, { 3455 { 0x00, 0x08, 0x12, 0x24 }, 3456 { 0x00, 0x0e, 0x1d, }, 3457 { 0x00, 0x13, }, 3458 { 0x00, }, 3459 }, { 3460 { 0x00, 0x08, 0x12, 0x24 }, 3461 { 0x00, 0x0e, 0x1d, }, 3462 { 0x00, 0x13, }, 3463 { 0x00, }, 3464 }, 3465 }; 3466 3467 static const struct tegra_sor_soc tegra132_sor = { 3468 .supports_lvds = true, 3469 .supports_hdmi = false, 3470 .supports_dp = true, 3471 .supports_audio = false, 3472 .supports_hdcp = false, 3473 .regs = &tegra124_sor_regs, 3474 .has_nvdisplay = false, 3475 .xbar_cfg = tegra124_sor_xbar_cfg, 3476 .lane_map = tegra124_sor_lane_map, 3477 .voltage_swing = tegra124_sor_voltage_swing, 3478 .pre_emphasis = tegra132_sor_pre_emphasis, 3479 .post_cursor = tegra124_sor_post_cursor, 3480 .tx_pu = tegra124_sor_tx_pu, 3481 }; 3482 3483 static const struct tegra_sor_regs tegra210_sor_regs = { 3484 .head_state0 = 0x05, 3485 .head_state1 = 0x07, 3486 .head_state2 = 0x09, 3487 .head_state3 = 0x0b, 3488 .head_state4 = 0x0d, 3489 .head_state5 = 0x0f, 3490 .pll0 = 0x17, 3491 .pll1 = 0x18, 3492 .pll2 = 0x19, 3493 .pll3 = 0x1a, 3494 .dp_padctl0 = 0x5c, 3495 .dp_padctl2 = 0x73, 3496 }; 3497 3498 static const u8 tegra210_sor_xbar_cfg[5] = { 3499 2, 1, 0, 3, 4 3500 }; 3501 3502 static const u8 tegra210_sor_lane_map[4] = { 3503 0, 1, 2, 3, 3504 }; 3505 3506 static const struct tegra_sor_soc tegra210_sor = { 3507 .supports_lvds = false, 3508 .supports_hdmi = false, 3509 .supports_dp = true, 3510 .supports_audio = false, 3511 .supports_hdcp = false, 3512 3513 .regs = &tegra210_sor_regs, 3514 .has_nvdisplay = false, 3515 3516 .xbar_cfg = tegra210_sor_xbar_cfg, 3517 .lane_map = tegra210_sor_lane_map, 3518 .voltage_swing = tegra124_sor_voltage_swing, 3519 .pre_emphasis = tegra124_sor_pre_emphasis, 3520 .post_cursor = tegra124_sor_post_cursor, 3521 .tx_pu = tegra124_sor_tx_pu, 3522 }; 3523 3524 static const struct tegra_sor_soc tegra210_sor1 = { 3525 .supports_lvds = false, 3526 .supports_hdmi = true, 3527 .supports_dp = true, 3528 .supports_audio = true, 3529 .supports_hdcp = true, 3530 3531 .regs = &tegra210_sor_regs, 3532 .has_nvdisplay = false, 3533 3534 .num_settings = ARRAY_SIZE(tegra210_sor_hdmi_defaults), 3535 .settings = tegra210_sor_hdmi_defaults, 3536 .xbar_cfg = tegra210_sor_xbar_cfg, 3537 .lane_map = tegra210_sor_lane_map, 3538 .voltage_swing = tegra124_sor_voltage_swing, 3539 .pre_emphasis = tegra124_sor_pre_emphasis, 3540 .post_cursor = tegra124_sor_post_cursor, 3541 .tx_pu = tegra124_sor_tx_pu, 3542 }; 3543 3544 static const struct tegra_sor_regs tegra186_sor_regs = { 3545 .head_state0 = 0x151, 3546 .head_state1 = 0x154, 3547 .head_state2 = 0x157, 3548 .head_state3 = 0x15a, 3549 .head_state4 = 0x15d, 3550 .head_state5 = 0x160, 3551 .pll0 = 0x163, 3552 .pll1 = 0x164, 3553 .pll2 = 0x165, 3554 .pll3 = 0x166, 3555 .dp_padctl0 = 0x168, 3556 .dp_padctl2 = 0x16a, 3557 }; 3558 3559 static const u8 tegra186_sor_voltage_swing[4][4][4] = { 3560 { 3561 { 0x13, 0x19, 0x1e, 0x28 }, 3562 { 0x1e, 0x25, 0x2d, }, 3563 { 0x28, 0x32, }, 3564 { 0x39, }, 3565 }, { 3566 { 0x12, 0x16, 0x1b, 0x25 }, 3567 { 0x1c, 0x23, 0x2a, }, 3568 { 0x25, 0x2f, }, 3569 { 0x37, } 3570 }, { 3571 { 0x12, 0x16, 0x1a, 0x22 }, 3572 { 0x1b, 0x20, 0x27, }, 3573 { 0x24, 0x2d, }, 3574 { 0x35, }, 3575 }, { 3576 { 0x11, 0x14, 0x17, 0x1f }, 3577 { 0x19, 0x1e, 0x24, }, 3578 { 0x22, 0x2a, }, 3579 { 0x32, }, 3580 }, 3581 }; 3582 3583 static const u8 tegra186_sor_pre_emphasis[4][4][4] = { 3584 { 3585 { 0x00, 0x08, 0x12, 0x24 }, 3586 { 0x01, 0x0e, 0x1d, }, 3587 { 0x01, 0x13, }, 3588 { 0x00, }, 3589 }, { 3590 { 0x00, 0x08, 0x12, 0x24 }, 3591 { 0x00, 0x0e, 0x1d, }, 3592 { 0x00, 0x13, }, 3593 { 0x00 }, 3594 }, { 3595 { 0x00, 0x08, 0x14, 0x24 }, 3596 { 0x00, 0x0e, 0x1d, }, 3597 { 0x00, 0x13, }, 3598 { 0x00, }, 3599 }, { 3600 { 0x00, 0x08, 0x12, 0x24 }, 3601 { 0x00, 0x0e, 0x1d, }, 3602 { 0x00, 0x13, }, 3603 { 0x00, }, 3604 }, 3605 }; 3606 3607 static const struct tegra_sor_soc tegra186_sor = { 3608 .supports_lvds = false, 3609 .supports_hdmi = true, 3610 .supports_dp = true, 3611 .supports_audio = true, 3612 .supports_hdcp = true, 3613 3614 .regs = &tegra186_sor_regs, 3615 .has_nvdisplay = true, 3616 3617 .num_settings = ARRAY_SIZE(tegra186_sor_hdmi_defaults), 3618 .settings = tegra186_sor_hdmi_defaults, 3619 .xbar_cfg = tegra124_sor_xbar_cfg, 3620 .lane_map = tegra124_sor_lane_map, 3621 .voltage_swing = tegra186_sor_voltage_swing, 3622 .pre_emphasis = tegra186_sor_pre_emphasis, 3623 .post_cursor = tegra124_sor_post_cursor, 3624 .tx_pu = tegra124_sor_tx_pu, 3625 }; 3626 3627 static const struct tegra_sor_regs tegra194_sor_regs = { 3628 .head_state0 = 0x151, 3629 .head_state1 = 0x155, 3630 .head_state2 = 0x159, 3631 .head_state3 = 0x15d, 3632 .head_state4 = 0x161, 3633 .head_state5 = 0x165, 3634 .pll0 = 0x169, 3635 .pll1 = 0x16a, 3636 .pll2 = 0x16b, 3637 .pll3 = 0x16c, 3638 .dp_padctl0 = 0x16e, 3639 .dp_padctl2 = 0x16f, 3640 }; 3641 3642 static const struct tegra_sor_soc tegra194_sor = { 3643 .supports_lvds = false, 3644 .supports_hdmi = true, 3645 .supports_dp = true, 3646 .supports_audio = true, 3647 .supports_hdcp = true, 3648 3649 .regs = &tegra194_sor_regs, 3650 .has_nvdisplay = true, 3651 3652 .num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults), 3653 .settings = tegra194_sor_hdmi_defaults, 3654 3655 .xbar_cfg = tegra210_sor_xbar_cfg, 3656 .lane_map = tegra124_sor_lane_map, 3657 .voltage_swing = tegra186_sor_voltage_swing, 3658 .pre_emphasis = tegra186_sor_pre_emphasis, 3659 .post_cursor = tegra124_sor_post_cursor, 3660 .tx_pu = tegra124_sor_tx_pu, 3661 }; 3662 3663 static const struct of_device_id tegra_sor_of_match[] = { 3664 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor }, 3665 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor }, 3666 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 }, 3667 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor }, 3668 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor }, 3669 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor }, 3670 { }, 3671 }; 3672 MODULE_DEVICE_TABLE(of, tegra_sor_of_match); 3673 3674 static int tegra_sor_parse_dt(struct tegra_sor *sor) 3675 { 3676 struct device_node *np = sor->dev->of_node; 3677 u32 xbar_cfg[5]; 3678 unsigned int i; 3679 u32 value; 3680 int err; 3681 3682 if (sor->soc->has_nvdisplay) { 3683 err = of_property_read_u32(np, "nvidia,interface", &value); 3684 if (err < 0) 3685 return err; 3686 3687 sor->index = value; 3688 3689 /* 3690 * override the default that we already set for Tegra210 and 3691 * earlier 3692 */ 3693 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; 3694 } else { 3695 if (!sor->soc->supports_audio) 3696 sor->index = 0; 3697 else 3698 sor->index = 1; 3699 } 3700 3701 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5); 3702 if (err < 0) { 3703 /* fall back to default per-SoC XBAR configuration */ 3704 for (i = 0; i < 5; i++) 3705 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; 3706 } else { 3707 /* copy cells to SOR XBAR configuration */ 3708 for (i = 0; i < 5; i++) 3709 sor->xbar_cfg[i] = xbar_cfg[i]; 3710 } 3711 3712 return 0; 3713 } 3714 3715 static irqreturn_t tegra_sor_irq(int irq, void *data) 3716 { 3717 struct tegra_sor *sor = data; 3718 u32 value; 3719 3720 value = tegra_sor_readl(sor, SOR_INT_STATUS); 3721 tegra_sor_writel(sor, value, SOR_INT_STATUS); 3722 3723 if (value & SOR_INT_CODEC_SCRATCH0) { 3724 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); 3725 3726 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { 3727 unsigned int format; 3728 3729 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; 3730 3731 tegra_hda_parse_format(format, &sor->format); 3732 3733 if (sor->ops->audio_enable) 3734 sor->ops->audio_enable(sor); 3735 } else { 3736 if (sor->ops->audio_disable) 3737 sor->ops->audio_disable(sor); 3738 } 3739 } 3740 3741 return IRQ_HANDLED; 3742 } 3743 3744 static int tegra_sor_probe(struct platform_device *pdev) 3745 { 3746 struct device_node *np; 3747 struct tegra_sor *sor; 3748 int err; 3749 3750 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); 3751 if (!sor) 3752 return -ENOMEM; 3753 3754 sor->soc = of_device_get_match_data(&pdev->dev); 3755 sor->output.dev = sor->dev = &pdev->dev; 3756 3757 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, 3758 sor->soc->num_settings * 3759 sizeof(*sor->settings), 3760 GFP_KERNEL); 3761 if (!sor->settings) 3762 return -ENOMEM; 3763 3764 sor->num_settings = sor->soc->num_settings; 3765 3766 sor->pmc = devm_tegra_pmc_get(&pdev->dev); 3767 if (IS_ERR(sor->pmc)) { 3768 err = PTR_ERR(sor->pmc); 3769 goto put_aux; 3770 } 3771 3772 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); 3773 if (np) { 3774 sor->aux = drm_dp_aux_find_by_of_node(np); 3775 of_node_put(np); 3776 3777 if (!sor->aux) 3778 return -EPROBE_DEFER; 3779 3780 if (get_device(sor->aux->dev)) 3781 sor->output.ddc = &sor->aux->ddc; 3782 } 3783 3784 if (!sor->aux) { 3785 if (sor->soc->supports_hdmi) { 3786 sor->ops = &tegra_sor_hdmi_ops; 3787 sor->pad = TEGRA_IO_PAD_HDMI; 3788 } else if (sor->soc->supports_lvds) { 3789 dev_err(&pdev->dev, "LVDS not supported yet\n"); 3790 return -ENODEV; 3791 } else { 3792 dev_err(&pdev->dev, "unknown (non-DP) support\n"); 3793 return -ENODEV; 3794 } 3795 } else { 3796 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0); 3797 /* 3798 * No need to keep this around since we only use it as a check 3799 * to see if a panel is connected (eDP) or not (DP). 3800 */ 3801 of_node_put(np); 3802 3803 sor->ops = &tegra_sor_dp_ops; 3804 sor->pad = TEGRA_IO_PAD_LVDS; 3805 } 3806 3807 err = tegra_sor_parse_dt(sor); 3808 if (err < 0) 3809 goto put_aux; 3810 3811 err = tegra_output_probe(&sor->output); 3812 if (err < 0) { 3813 dev_err_probe(&pdev->dev, err, "failed to probe output\n"); 3814 goto put_aux; 3815 } 3816 3817 if (sor->ops && sor->ops->probe) { 3818 err = sor->ops->probe(sor); 3819 if (err < 0) { 3820 dev_err(&pdev->dev, "failed to probe %s: %d\n", 3821 sor->ops->name, err); 3822 goto remove; 3823 } 3824 } 3825 3826 sor->regs = devm_platform_ioremap_resource(pdev, 0); 3827 if (IS_ERR(sor->regs)) { 3828 err = PTR_ERR(sor->regs); 3829 goto remove; 3830 } 3831 3832 err = platform_get_irq(pdev, 0); 3833 if (err < 0) 3834 goto remove; 3835 3836 sor->irq = err; 3837 3838 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, 3839 dev_name(sor->dev), sor); 3840 if (err < 0) { 3841 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); 3842 goto remove; 3843 } 3844 3845 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); 3846 if (IS_ERR(sor->rst)) { 3847 err = PTR_ERR(sor->rst); 3848 3849 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) { 3850 dev_err(&pdev->dev, "failed to get reset control: %d\n", 3851 err); 3852 goto remove; 3853 } 3854 3855 /* 3856 * At this point, the reset control is most likely being used 3857 * by the generic power domain implementation. With any luck 3858 * the power domain will have taken care of resetting the SOR 3859 * and we don't have to do anything. 3860 */ 3861 sor->rst = NULL; 3862 } 3863 3864 sor->clk = devm_clk_get(&pdev->dev, NULL); 3865 if (IS_ERR(sor->clk)) { 3866 err = PTR_ERR(sor->clk); 3867 dev_err(&pdev->dev, "failed to get module clock: %d\n", err); 3868 goto remove; 3869 } 3870 3871 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { 3872 struct device_node *np = pdev->dev.of_node; 3873 const char *name; 3874 3875 /* 3876 * For backwards compatibility with Tegra210 device trees, 3877 * fall back to the old clock name "source" if the new "out" 3878 * clock is not available. 3879 */ 3880 if (of_property_match_string(np, "clock-names", "out") < 0) 3881 name = "source"; 3882 else 3883 name = "out"; 3884 3885 sor->clk_out = devm_clk_get(&pdev->dev, name); 3886 if (IS_ERR(sor->clk_out)) { 3887 err = PTR_ERR(sor->clk_out); 3888 dev_err(sor->dev, "failed to get %s clock: %d\n", 3889 name, err); 3890 goto remove; 3891 } 3892 } else { 3893 /* fall back to the module clock on SOR0 (eDP/LVDS only) */ 3894 sor->clk_out = sor->clk; 3895 } 3896 3897 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); 3898 if (IS_ERR(sor->clk_parent)) { 3899 err = PTR_ERR(sor->clk_parent); 3900 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); 3901 goto remove; 3902 } 3903 3904 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); 3905 if (IS_ERR(sor->clk_safe)) { 3906 err = PTR_ERR(sor->clk_safe); 3907 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); 3908 goto remove; 3909 } 3910 3911 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); 3912 if (IS_ERR(sor->clk_dp)) { 3913 err = PTR_ERR(sor->clk_dp); 3914 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); 3915 goto remove; 3916 } 3917 3918 /* 3919 * Starting with Tegra186, the BPMP provides an implementation for 3920 * the pad output clock, so we have to look it up from device tree. 3921 */ 3922 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); 3923 if (IS_ERR(sor->clk_pad)) { 3924 if (sor->clk_pad != ERR_PTR(-ENOENT)) { 3925 err = PTR_ERR(sor->clk_pad); 3926 goto remove; 3927 } 3928 3929 /* 3930 * If the pad output clock is not available, then we assume 3931 * we're on Tegra210 or earlier and have to provide our own 3932 * implementation. 3933 */ 3934 sor->clk_pad = NULL; 3935 } 3936 3937 /* 3938 * The bootloader may have set up the SOR such that it's module clock 3939 * is sourced by one of the display PLLs. However, that doesn't work 3940 * without properly having set up other bits of the SOR. 3941 */ 3942 err = clk_set_parent(sor->clk_out, sor->clk_safe); 3943 if (err < 0) { 3944 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); 3945 goto remove; 3946 } 3947 3948 platform_set_drvdata(pdev, sor); 3949 pm_runtime_enable(&pdev->dev); 3950 3951 host1x_client_init(&sor->client); 3952 sor->client.ops = &sor_client_ops; 3953 sor->client.dev = &pdev->dev; 3954 3955 /* 3956 * On Tegra210 and earlier, provide our own implementation for the 3957 * pad output clock. 3958 */ 3959 if (!sor->clk_pad) { 3960 char *name; 3961 3962 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout", 3963 sor->index); 3964 if (!name) { 3965 err = -ENOMEM; 3966 goto uninit; 3967 } 3968 3969 err = host1x_client_resume(&sor->client); 3970 if (err < 0) { 3971 dev_err(sor->dev, "failed to resume: %d\n", err); 3972 goto uninit; 3973 } 3974 3975 sor->clk_pad = tegra_clk_sor_pad_register(sor, name); 3976 host1x_client_suspend(&sor->client); 3977 } 3978 3979 if (IS_ERR(sor->clk_pad)) { 3980 err = PTR_ERR(sor->clk_pad); 3981 dev_err(sor->dev, "failed to register SOR pad clock: %d\n", 3982 err); 3983 goto uninit; 3984 } 3985 3986 err = __host1x_client_register(&sor->client); 3987 if (err < 0) { 3988 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 3989 err); 3990 goto uninit; 3991 } 3992 3993 return 0; 3994 3995 uninit: 3996 host1x_client_exit(&sor->client); 3997 pm_runtime_disable(&pdev->dev); 3998 remove: 3999 if (sor->aux) 4000 sor->output.ddc = NULL; 4001 4002 tegra_output_remove(&sor->output); 4003 put_aux: 4004 if (sor->aux) 4005 put_device(sor->aux->dev); 4006 4007 return err; 4008 } 4009 4010 static void tegra_sor_remove(struct platform_device *pdev) 4011 { 4012 struct tegra_sor *sor = platform_get_drvdata(pdev); 4013 4014 host1x_client_unregister(&sor->client); 4015 4016 pm_runtime_disable(&pdev->dev); 4017 4018 if (sor->aux) { 4019 put_device(sor->aux->dev); 4020 sor->output.ddc = NULL; 4021 } 4022 4023 tegra_output_remove(&sor->output); 4024 } 4025 4026 static int __maybe_unused tegra_sor_suspend(struct device *dev) 4027 { 4028 struct tegra_sor *sor = dev_get_drvdata(dev); 4029 int err; 4030 4031 err = tegra_output_suspend(&sor->output); 4032 if (err < 0) { 4033 dev_err(dev, "failed to suspend output: %d\n", err); 4034 return err; 4035 } 4036 4037 if (sor->hdmi_supply) { 4038 err = regulator_disable(sor->hdmi_supply); 4039 if (err < 0) { 4040 tegra_output_resume(&sor->output); 4041 return err; 4042 } 4043 } 4044 4045 return 0; 4046 } 4047 4048 static int __maybe_unused tegra_sor_resume(struct device *dev) 4049 { 4050 struct tegra_sor *sor = dev_get_drvdata(dev); 4051 int err; 4052 4053 if (sor->hdmi_supply) { 4054 err = regulator_enable(sor->hdmi_supply); 4055 if (err < 0) 4056 return err; 4057 } 4058 4059 err = tegra_output_resume(&sor->output); 4060 if (err < 0) { 4061 dev_err(dev, "failed to resume output: %d\n", err); 4062 4063 if (sor->hdmi_supply) 4064 regulator_disable(sor->hdmi_supply); 4065 4066 return err; 4067 } 4068 4069 return 0; 4070 } 4071 4072 static const struct dev_pm_ops tegra_sor_pm_ops = { 4073 SET_SYSTEM_SLEEP_PM_OPS(tegra_sor_suspend, tegra_sor_resume) 4074 }; 4075 4076 struct platform_driver tegra_sor_driver = { 4077 .driver = { 4078 .name = "tegra-sor", 4079 .of_match_table = tegra_sor_of_match, 4080 .pm = &tegra_sor_pm_ops, 4081 }, 4082 .probe = tegra_sor_probe, 4083 .remove = tegra_sor_remove, 4084 }; 4085