1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * drivers/i2c/busses/i2c-tegra.c
4 *
5 * Copyright (C) 2010 Google, Inc.
6 * Author: Colin Cross <ccross@android.com>
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dmaengine.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/i2c.h>
17 #include <linux/init.h>
18 #include <linux/interrupt.h>
19 #include <linux/io.h>
20 #include <linux/iopoll.h>
21 #include <linux/irq.h>
22 #include <linux/kernel.h>
23 #include <linux/ktime.h>
24 #include <linux/module.h>
25 #include <linux/of.h>
26 #include <linux/pinctrl/consumer.h>
27 #include <linux/platform_device.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/reset.h>
30
31 #define BYTES_PER_FIFO_WORD 4
32
33 #define I2C_CNFG_DEBOUNCE_CNT GENMASK(14, 12)
34 #define I2C_CNFG_PACKET_MODE_EN BIT(10)
35 #define I2C_CNFG_NEW_MASTER_FSM BIT(11)
36 #define I2C_CNFG_MULTI_MASTER_MODE BIT(17)
37
38 #define I2C_SL_CNFG_NACK BIT(1)
39 #define I2C_SL_CNFG_NEWSL BIT(2)
40
41 #define I2C_FIFO_CONTROL_TX_FLUSH BIT(1)
42 #define I2C_FIFO_CONTROL_RX_FLUSH BIT(0)
43 #define I2C_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 5)
44 #define I2C_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 2)
45
46 #define I2C_FIFO_STATUS_TX GENMASK(7, 4)
47 #define I2C_FIFO_STATUS_RX GENMASK(3, 0)
48
49 #define I2C_INT_BUS_CLR_DONE BIT(11)
50 #define I2C_INT_PACKET_XFER_COMPLETE BIT(7)
51 #define I2C_INT_NO_ACK BIT(3)
52 #define I2C_INT_ARBITRATION_LOST BIT(2)
53 #define I2C_INT_TX_FIFO_DATA_REQ BIT(1)
54 #define I2C_INT_RX_FIFO_DATA_REQ BIT(0)
55
56 #define I2C_CLK_DIVISOR_STD_FAST_MODE GENMASK(31, 16)
57 #define I2C_CLK_DIVISOR_HSMODE GENMASK(15, 0)
58
59 #define DVC_CTRL_REG1 0x000
60 #define DVC_CTRL_REG1_INTR_EN BIT(10)
61 #define DVC_CTRL_REG3 0x008
62 #define DVC_CTRL_REG3_SW_PROG BIT(26)
63 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN BIT(30)
64 #define DVC_STATUS 0x00c
65 #define DVC_STATUS_I2C_DONE_INTR BIT(30)
66
67 #define I2C_ERR_NONE 0x00
68 #define I2C_ERR_NO_ACK BIT(0)
69 #define I2C_ERR_ARBITRATION_LOST BIT(1)
70 #define I2C_ERR_UNKNOWN_INTERRUPT BIT(2)
71 #define I2C_ERR_RX_BUFFER_OVERFLOW BIT(3)
72
73 #define PACKET_HEADER0_HEADER_SIZE GENMASK(29, 28)
74 #define PACKET_HEADER0_PACKET_ID GENMASK(23, 16)
75 #define PACKET_HEADER0_CONT_ID GENMASK(15, 12)
76 #define PACKET_HEADER0_PROTOCOL GENMASK(7, 4)
77 #define PACKET_HEADER0_PROTOCOL_I2C 1
78
79 #define I2C_HEADER_HS_MODE BIT(22)
80 #define I2C_HEADER_CONT_ON_NAK BIT(21)
81 #define I2C_HEADER_READ BIT(19)
82 #define I2C_HEADER_10BIT_ADDR BIT(18)
83 #define I2C_HEADER_IE_ENABLE BIT(17)
84 #define I2C_HEADER_REPEAT_START BIT(16)
85 #define I2C_HEADER_CONTINUE_XFER BIT(15)
86 #define I2C_HEADER_SLAVE_ADDR_SHIFT 1
87
88 #define I2C_BC_SCLK_THRESHOLD GENMASK(23, 16)
89 #define I2C_BC_STOP_COND BIT(2)
90 #define I2C_BC_TERMINATE BIT(1)
91 #define I2C_BC_ENABLE BIT(0)
92
93 #define I2C_BC_STATUS BIT(0)
94
95 #define I2C_MSTR_CONFIG_LOAD BIT(0)
96
97 #define I2C_MST_CORE_CLKEN_OVR BIT(0)
98
99 #define I2C_INTERFACE_TIMING_THIGH GENMASK(13, 8)
100 #define I2C_INTERFACE_TIMING_TLOW GENMASK(5, 0)
101 #define I2C_INTERFACE_TIMING_TBUF GENMASK(29, 24)
102 #define I2C_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
103 #define I2C_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
104 #define I2C_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
105
106 #define I2C_HS_INTERFACE_TIMING_THIGH GENMASK(13, 8)
107 #define I2C_HS_INTERFACE_TIMING_TLOW GENMASK(5, 0)
108 #define I2C_HS_INTERFACE_TIMING_TSU_STO GENMASK(21, 16)
109 #define I2C_HS_INTERFACE_TIMING_THD_STA GENMASK(13, 8)
110 #define I2C_HS_INTERFACE_TIMING_TSU_STA GENMASK(5, 0)
111
112 #define I2C_MST_FIFO_CONTROL_RX_FLUSH BIT(0)
113 #define I2C_MST_FIFO_CONTROL_TX_FLUSH BIT(1)
114 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
115 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
116
117 #define I2C_MST_FIFO_STATUS_TX GENMASK(23, 16)
118 #define I2C_MST_FIFO_STATUS_RX GENMASK(7, 0)
119
120 #define I2C_SW_MUTEX_REQUEST GENMASK(3, 0)
121 #define I2C_SW_MUTEX_GRANT GENMASK(7, 4)
122 #define I2C_SW_MUTEX_ID_CCPLEX 9
123
124 /* SW mutex acquire timeout value in microseconds. */
125 #define I2C_SW_MUTEX_TIMEOUT_US (25 * USEC_PER_MSEC)
126
127 /* configuration load timeout in microseconds */
128 #define I2C_CONFIG_LOAD_TIMEOUT 1000000
129
130 /* packet header size in bytes */
131 #define I2C_PACKET_HEADER_SIZE 12
132
133 /*
134 * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
135 * avoid DMA overhead, otherwise external APB DMA controller will be used.
136 * Note that the actual MAX PIO length is 20 bytes because 32 bytes include
137 * I2C_PACKET_HEADER_SIZE.
138 */
139 #define I2C_PIO_MODE_PREFERRED_LEN 32
140
141 struct tegra_i2c_regs {
142 unsigned int cnfg;
143 unsigned int status;
144 unsigned int sl_cnfg;
145 unsigned int sl_addr1;
146 unsigned int sl_addr2;
147 unsigned int tlow_sext;
148 unsigned int tx_fifo;
149 unsigned int rx_fifo;
150 unsigned int packet_transfer_status;
151 unsigned int fifo_control;
152 unsigned int fifo_status;
153 unsigned int int_mask;
154 unsigned int int_status;
155 unsigned int clk_divisor;
156 unsigned int bus_clear_cnfg;
157 unsigned int bus_clear_status;
158 unsigned int config_load;
159 unsigned int clken_override;
160 unsigned int interface_timing_0;
161 unsigned int interface_timing_1;
162 unsigned int hs_interface_timing_0;
163 unsigned int hs_interface_timing_1;
164 unsigned int master_reset_cntrl;
165 unsigned int mst_fifo_control;
166 unsigned int mst_fifo_status;
167 unsigned int sw_mutex;
168 };
169
170 static const struct tegra_i2c_regs tegra20_i2c_regs = {
171 .cnfg = 0x000,
172 .status = 0x01c,
173 .sl_cnfg = 0x020,
174 .sl_addr1 = 0x02c,
175 .sl_addr2 = 0x030,
176 .tx_fifo = 0x050,
177 .rx_fifo = 0x054,
178 .packet_transfer_status = 0x058,
179 .fifo_control = 0x05c,
180 .fifo_status = 0x060,
181 .int_mask = 0x064,
182 .int_status = 0x068,
183 .clk_divisor = 0x06c,
184 .bus_clear_cnfg = 0x084,
185 .bus_clear_status = 0x088,
186 .config_load = 0x08c,
187 .clken_override = 0x090,
188 .interface_timing_0 = 0x094,
189 .interface_timing_1 = 0x098,
190 .hs_interface_timing_0 = 0x09c,
191 .hs_interface_timing_1 = 0x0a0,
192 .master_reset_cntrl = 0x0a8,
193 .mst_fifo_control = 0x0b4,
194 .mst_fifo_status = 0x0b8,
195 };
196
197 #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
198 static const struct tegra_i2c_regs tegra20_dvc_i2c_regs = {
199 .cnfg = 0x040,
200 .status = 0x05c,
201 .tx_fifo = 0x060,
202 .rx_fifo = 0x064,
203 .packet_transfer_status = 0x068,
204 .fifo_control = 0x06c,
205 .fifo_status = 0x070,
206 .int_mask = 0x074,
207 .int_status = 0x078,
208 .clk_divisor = 0x07c,
209 .bus_clear_cnfg = 0x094,
210 .bus_clear_status = 0x098,
211 .config_load = 0x09c,
212 .clken_override = 0x0a0,
213 .interface_timing_0 = 0x0a4,
214 .interface_timing_1 = 0x0a8,
215 .hs_interface_timing_0 = 0x0ac,
216 .hs_interface_timing_1 = 0x0b0,
217 .master_reset_cntrl = 0x0b8,
218 .mst_fifo_control = 0x0c4,
219 .mst_fifo_status = 0x0c8,
220 };
221 #endif
222
223 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
224 static const struct tegra_i2c_regs tegra210_vi_i2c_regs = {
225 .cnfg = 0x0c00,
226 .status = 0x0c70,
227 .tlow_sext = 0x0cd0,
228 .tx_fifo = 0x0d40,
229 .rx_fifo = 0x0d50,
230 .packet_transfer_status = 0x0d60,
231 .fifo_control = 0x0d70,
232 .fifo_status = 0x0d80,
233 .int_mask = 0x0d90,
234 .int_status = 0x0da0,
235 .clk_divisor = 0x0db0,
236 .bus_clear_cnfg = 0x0e10,
237 .bus_clear_status = 0x0e20,
238 .config_load = 0x0e30,
239 .clken_override = 0x0e40,
240 .interface_timing_0 = 0x0e50,
241 .interface_timing_1 = 0x0e60,
242 .hs_interface_timing_0 = 0x0e70,
243 .hs_interface_timing_1 = 0x0e80,
244 .master_reset_cntrl = 0x0ea0,
245 .mst_fifo_control = 0x0ed0,
246 .mst_fifo_status = 0x0ee0,
247 };
248 #endif
249
250 static const struct tegra_i2c_regs tegra264_i2c_regs = {
251 .cnfg = 0x000,
252 .status = 0x01c,
253 .sl_cnfg = 0x020,
254 .sl_addr1 = 0x02c,
255 .sl_addr2 = 0x030,
256 .tx_fifo = 0x050,
257 .rx_fifo = 0x054,
258 .packet_transfer_status = 0x058,
259 .fifo_control = 0x05c,
260 .fifo_status = 0x060,
261 .int_mask = 0x064,
262 .int_status = 0x068,
263 .clk_divisor = 0x06c,
264 .bus_clear_cnfg = 0x084,
265 .bus_clear_status = 0x088,
266 .config_load = 0x08c,
267 .clken_override = 0x090,
268 .interface_timing_0 = 0x094,
269 .interface_timing_1 = 0x098,
270 .hs_interface_timing_0 = 0x09c,
271 .hs_interface_timing_1 = 0x0a0,
272 .master_reset_cntrl = 0x0a8,
273 .mst_fifo_control = 0x0b4,
274 .mst_fifo_status = 0x0b8,
275 .sw_mutex = 0x0ec,
276 };
277
278 static const struct tegra_i2c_regs tegra410_i2c_regs = {
279 .cnfg = 0x000,
280 .status = 0x01c,
281 .sl_cnfg = 0x020,
282 .sl_addr1 = 0x02c,
283 .sl_addr2 = 0x030,
284 .tx_fifo = 0x054,
285 .rx_fifo = 0x058,
286 .packet_transfer_status = 0x05c,
287 .fifo_control = 0x060,
288 .fifo_status = 0x064,
289 .int_mask = 0x068,
290 .int_status = 0x06c,
291 .clk_divisor = 0x070,
292 .bus_clear_cnfg = 0x088,
293 .bus_clear_status = 0x08c,
294 .config_load = 0x090,
295 .clken_override = 0x094,
296 .interface_timing_0 = 0x098,
297 .interface_timing_1 = 0x09c,
298 .hs_interface_timing_0 = 0x0a0,
299 .hs_interface_timing_1 = 0x0a4,
300 .master_reset_cntrl = 0x0ac,
301 .mst_fifo_control = 0x0b8,
302 .mst_fifo_status = 0x0bc,
303 .sw_mutex = 0x0f0,
304 };
305
306 /*
307 * msg_end_type: The bus control which needs to be sent at end of transfer.
308 * @MSG_END_STOP: Send stop pulse.
309 * @MSG_END_REPEAT_START: Send repeat-start.
310 * @MSG_END_CONTINUE: Don't send stop or repeat-start.
311 */
312 enum msg_end_type {
313 MSG_END_STOP,
314 MSG_END_REPEAT_START,
315 MSG_END_CONTINUE,
316 };
317
318 /*
319 * tegra_i2c_variant: Identifies the variant of I2C controller.
320 * @TEGRA_I2C_VARIANT_DEFAULT: Identifies the default I2C controller.
321 * @TEGRA_I2C_VARIANT_DVC: Identifies the DVC I2C controller, has a different register layout.
322 * @TEGRA_I2C_VARIANT_VI: Identifies the VI I2C controller, has a different register layout.
323 */
324 enum tegra_i2c_variant {
325 TEGRA_I2C_VARIANT_DEFAULT,
326 TEGRA_I2C_VARIANT_DVC,
327 TEGRA_I2C_VARIANT_VI,
328 };
329
330 /**
331 * struct tegra_i2c_hw_feature : per hardware generation features
332 * @has_continue_xfer_support: continue-transfer supported
333 * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
334 * completion interrupt on per packet basis.
335 * @has_config_load_reg: Has the config load register to load the new
336 * configuration.
337 * @clk_divisor_hs_mode: Clock divisor in HS mode.
338 * @clk_divisor_std_mode: Clock divisor in standard mode. It is
339 * applicable if there is no fast clock source i.e. single clock
340 * source.
341 * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
342 * applicable if there is no fast clock source i.e. single clock
343 * source.
344 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
345 * applicable if there is no fast clock source (i.e. single
346 * clock source).
347 * @has_multi_master_mode: The I2C controller supports running in single-master
348 * or multi-master mode.
349 * @has_slcg_override_reg: The I2C controller supports a register that
350 * overrides the second level clock gating.
351 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
352 * provides additional features and allows for longer messages to
353 * be transferred in one go.
354 * @has_mst_reset: The I2C controller contains MASTER_RESET_CTRL register which
355 * provides an alternative to controller reset when configured as
356 * I2C master
357 * @quirks: I2C adapter quirks for limiting write/read transfer size and not
358 * allowing 0 length transfers.
359 * @supports_bus_clear: Bus Clear support to recover from bus hang during
360 * SDA stuck low from device for some unknown reasons.
361 * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
362 * @tlow_std_mode: Low period of the clock in standard mode.
363 * @thigh_std_mode: High period of the clock in standard mode.
364 * @tlow_fast_mode: Low period of the clock in fast mode.
365 * @thigh_fast_mode: High period of the clock in fast mode.
366 * @tlow_fastplus_mode: Low period of the clock in fast-plus mode.
367 * @thigh_fastplus_mode: High period of the clock in fast-plus mode.
368 * @tlow_hs_mode: Low period of the clock in HS mode.
369 * @thigh_hs_mode: High period of the clock in HS mode.
370 * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
371 * in standard mode.
372 * @setup_hold_time_fast_mode: Setup and hold time for start and stop
373 * conditions in fast mode.
374 * @setup_hold_time_fastplus_mode: Setup and hold time for start and stop
375 * conditions in fast-plus mode.
376 * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
377 * in HS mode.
378 * @has_interface_timing_reg: Has interface timing register to program the tuned
379 * timing settings.
380 * @enable_hs_mode_support: Enable support for high speed (HS) mode transfers.
381 * @has_mutex: Has mutex register for mutual exclusion with other firmwares or VMs.
382 * @variant: This represents the I2C controller variant.
383 * @regs: Register offsets for the specific SoC variant.
384 */
385 struct tegra_i2c_hw_feature {
386 bool has_continue_xfer_support;
387 bool has_per_pkt_xfer_complete_irq;
388 bool has_config_load_reg;
389 u32 clk_divisor_hs_mode;
390 u32 clk_divisor_std_mode;
391 u32 clk_divisor_fast_mode;
392 u32 clk_divisor_fast_plus_mode;
393 bool has_multi_master_mode;
394 bool has_slcg_override_reg;
395 bool has_mst_fifo;
396 bool has_mst_reset;
397 const struct i2c_adapter_quirks *quirks;
398 bool supports_bus_clear;
399 bool has_apb_dma;
400 u32 tlow_std_mode;
401 u32 thigh_std_mode;
402 u32 tlow_fast_mode;
403 u32 thigh_fast_mode;
404 u32 tlow_fastplus_mode;
405 u32 thigh_fastplus_mode;
406 u32 tlow_hs_mode;
407 u32 thigh_hs_mode;
408 u32 setup_hold_time_std_mode;
409 u32 setup_hold_time_fast_mode;
410 u32 setup_hold_time_fastplus_mode;
411 u32 setup_hold_time_hs_mode;
412 bool has_interface_timing_reg;
413 bool enable_hs_mode_support;
414 bool has_mutex;
415 enum tegra_i2c_variant variant;
416 const struct tegra_i2c_regs *regs;
417 };
418
419 /**
420 * struct tegra_i2c_dev - per device I2C context
421 * @dev: device reference for power management
422 * @hw: Tegra I2C HW feature
423 * @adapter: core I2C layer adapter information
424 * @div_clk: clock reference for div clock of I2C controller
425 * @clocks: array of I2C controller clocks
426 * @nclocks: number of clocks in the array
427 * @base: ioremapped registers cookie
428 * @base_phys: physical base address of the I2C controller
429 * @cont_id: I2C controller ID, used for packet header
430 * @irq: IRQ number of transfer complete interrupt
431 * @msg_complete: transfer completion notifier
432 * @msg_buf_remaining: size of unsent data in the message buffer
433 * @msg_len: length of message in current transfer
434 * @msg_err: error code for completed message
435 * @msg_buf: pointer to current message data
436 * @msg_read: indicates that the transfer is a read access
437 * @timings: i2c timings information like bus frequency
438 * @multimaster_mode: indicates that I2C controller is in multi-master mode
439 * @dma_chan: DMA channel
440 * @dma_phys: handle to DMA resources
441 * @dma_buf: pointer to allocated DMA buffer
442 * @dma_buf_size: DMA buffer size
443 * @dma_dev: DMA device used for transfers
444 * @dma_mode: indicates active DMA transfer
445 * @dma_complete: DMA completion notifier
446 * @atomic_mode: indicates active atomic transfer
447 */
448 struct tegra_i2c_dev {
449 struct device *dev;
450 struct i2c_adapter adapter;
451
452 const struct tegra_i2c_hw_feature *hw;
453 unsigned int cont_id;
454 unsigned int irq;
455
456 phys_addr_t base_phys;
457 void __iomem *base;
458
459 struct clk_bulk_data clocks[2];
460 unsigned int nclocks;
461
462 struct clk *div_clk;
463 struct i2c_timings timings;
464
465 struct completion msg_complete;
466 size_t msg_buf_remaining;
467 unsigned int msg_len;
468 int msg_err;
469 u8 *msg_buf;
470
471 struct completion dma_complete;
472 struct dma_chan *dma_chan;
473 unsigned int dma_buf_size;
474 struct device *dma_dev;
475 dma_addr_t dma_phys;
476 void *dma_buf;
477
478 bool multimaster_mode;
479 bool atomic_mode;
480 bool dma_mode;
481 bool msg_read;
482 };
483
484 #define IS_DVC(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && \
485 (dev)->hw->variant == TEGRA_I2C_VARIANT_DVC)
486 #define IS_VI(dev) (IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC) && \
487 (dev)->hw->variant == TEGRA_I2C_VARIANT_VI)
488
dvc_writel(struct tegra_i2c_dev * i2c_dev,u32 val,unsigned int reg)489 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
490 unsigned int reg)
491 {
492 writel_relaxed(val, i2c_dev->base + reg);
493 }
494
dvc_readl(struct tegra_i2c_dev * i2c_dev,unsigned int reg)495 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
496 {
497 return readl_relaxed(i2c_dev->base + reg);
498 }
499
i2c_writel(struct tegra_i2c_dev * i2c_dev,u32 val,unsigned int reg)500 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg)
501 {
502 writel_relaxed(val, i2c_dev->base + reg);
503
504 /* read back register to make sure that register writes completed */
505 if (reg != i2c_dev->hw->regs->tx_fifo)
506 readl_relaxed(i2c_dev->base + reg);
507 else if (IS_VI(i2c_dev))
508 readl_relaxed(i2c_dev->base + i2c_dev->hw->regs->int_status);
509 }
510
i2c_readl(struct tegra_i2c_dev * i2c_dev,unsigned int reg)511 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
512 {
513 return readl_relaxed(i2c_dev->base + reg);
514 }
515
i2c_writesl(struct tegra_i2c_dev * i2c_dev,void * data,unsigned int reg,unsigned int len)516 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
517 unsigned int reg, unsigned int len)
518 {
519 writesl(i2c_dev->base + reg, data, len);
520 }
521
i2c_writesl_vi(struct tegra_i2c_dev * i2c_dev,void * data,unsigned int reg,unsigned int len)522 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data,
523 unsigned int reg, unsigned int len)
524 {
525 u32 *data32 = data;
526
527 /*
528 * VI I2C controller has known hardware bug where writes get stuck
529 * when immediate multiple writes happen to TX_FIFO register.
530 * Recommended software work around is to read I2C register after
531 * each write to TX_FIFO register to flush out the data.
532 */
533 while (len--)
534 i2c_writel(i2c_dev, *data32++, reg);
535 }
536
i2c_readsl(struct tegra_i2c_dev * i2c_dev,void * data,unsigned int reg,unsigned int len)537 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
538 unsigned int reg, unsigned int len)
539 {
540 readsl(i2c_dev->base + reg, data, len);
541 }
542
tegra_i2c_mutex_acquired(struct tegra_i2c_dev * i2c_dev)543 static bool tegra_i2c_mutex_acquired(struct tegra_i2c_dev *i2c_dev)
544 {
545 unsigned int reg = i2c_dev->hw->regs->sw_mutex;
546 u32 val, id;
547
548 val = readl(i2c_dev->base + reg);
549 id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
550
551 return id == I2C_SW_MUTEX_ID_CCPLEX;
552 }
553
tegra_i2c_mutex_trylock(struct tegra_i2c_dev * i2c_dev)554 static bool tegra_i2c_mutex_trylock(struct tegra_i2c_dev *i2c_dev)
555 {
556 unsigned int reg = i2c_dev->hw->regs->sw_mutex;
557 u32 val, id;
558
559 val = readl(i2c_dev->base + reg);
560 id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
561 if (id != 0 && id != I2C_SW_MUTEX_ID_CCPLEX)
562 return false;
563
564 val = FIELD_PREP(I2C_SW_MUTEX_REQUEST, I2C_SW_MUTEX_ID_CCPLEX);
565 writel(val, i2c_dev->base + reg);
566
567 return tegra_i2c_mutex_acquired(i2c_dev);
568 }
569
tegra_i2c_mutex_lock(struct tegra_i2c_dev * i2c_dev)570 static int tegra_i2c_mutex_lock(struct tegra_i2c_dev *i2c_dev)
571 {
572 bool locked;
573 int ret;
574
575 if (!i2c_dev->hw->has_mutex)
576 return 0;
577
578 if (i2c_dev->atomic_mode)
579 ret = read_poll_timeout_atomic(tegra_i2c_mutex_trylock, locked, locked,
580 USEC_PER_MSEC, I2C_SW_MUTEX_TIMEOUT_US,
581 false, i2c_dev);
582 else
583 ret = read_poll_timeout(tegra_i2c_mutex_trylock, locked, locked, USEC_PER_MSEC,
584 I2C_SW_MUTEX_TIMEOUT_US, false, i2c_dev);
585
586 if (ret)
587 dev_warn(i2c_dev->dev, "failed to acquire mutex\n");
588
589 return ret;
590 }
591
tegra_i2c_mutex_unlock(struct tegra_i2c_dev * i2c_dev)592 static int tegra_i2c_mutex_unlock(struct tegra_i2c_dev *i2c_dev)
593 {
594 unsigned int reg = i2c_dev->hw->regs->sw_mutex;
595 u32 val, id;
596
597 if (!i2c_dev->hw->has_mutex)
598 return 0;
599
600 val = readl(i2c_dev->base + reg);
601
602 id = FIELD_GET(I2C_SW_MUTEX_GRANT, val);
603 if (id && id != I2C_SW_MUTEX_ID_CCPLEX) {
604 dev_warn(i2c_dev->dev, "unable to unlock mutex, mutex is owned by: %u\n", id);
605 return -EPERM;
606 }
607
608 writel(0, i2c_dev->base + reg);
609
610 return 0;
611 }
612
tegra_i2c_mask_irq(struct tegra_i2c_dev * i2c_dev,u32 mask)613 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
614 {
615 u32 int_mask;
616
617 int_mask = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask) & ~mask;
618 i2c_writel(i2c_dev, int_mask, i2c_dev->hw->regs->int_mask);
619 }
620
tegra_i2c_unmask_irq(struct tegra_i2c_dev * i2c_dev,u32 mask)621 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
622 {
623 u32 int_mask;
624
625 int_mask = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask) | mask;
626 i2c_writel(i2c_dev, int_mask, i2c_dev->hw->regs->int_mask);
627 }
628
tegra_i2c_dma_complete(void * args)629 static void tegra_i2c_dma_complete(void *args)
630 {
631 struct tegra_i2c_dev *i2c_dev = args;
632
633 complete(&i2c_dev->dma_complete);
634 }
635
tegra_i2c_dma_submit(struct tegra_i2c_dev * i2c_dev,size_t len)636 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
637 {
638 struct dma_async_tx_descriptor *dma_desc;
639 enum dma_transfer_direction dir;
640
641 dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
642
643 reinit_completion(&i2c_dev->dma_complete);
644
645 dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
646
647 dma_desc = dmaengine_prep_slave_single(i2c_dev->dma_chan, i2c_dev->dma_phys,
648 len, dir, DMA_PREP_INTERRUPT |
649 DMA_CTRL_ACK);
650 if (!dma_desc) {
651 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n",
652 i2c_dev->msg_read ? "RX" : "TX");
653 return -EINVAL;
654 }
655
656 dma_desc->callback = tegra_i2c_dma_complete;
657 dma_desc->callback_param = i2c_dev;
658
659 dmaengine_submit(dma_desc);
660 dma_async_issue_pending(i2c_dev->dma_chan);
661
662 return 0;
663 }
664
tegra_i2c_release_dma(struct tegra_i2c_dev * i2c_dev)665 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
666 {
667 if (i2c_dev->dma_buf) {
668 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
669 i2c_dev->dma_buf, i2c_dev->dma_phys);
670 i2c_dev->dma_buf = NULL;
671 }
672
673 if (i2c_dev->dma_chan) {
674 dma_release_channel(i2c_dev->dma_chan);
675 i2c_dev->dma_chan = NULL;
676 }
677 }
678
tegra_i2c_init_dma(struct tegra_i2c_dev * i2c_dev)679 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
680 {
681 dma_addr_t dma_phys;
682 u32 *dma_buf;
683 int err;
684
685 if (IS_VI(i2c_dev))
686 return 0;
687
688 if (!of_property_present(i2c_dev->dev->of_node, "dmas")) {
689 dev_dbg(i2c_dev->dev, "DMA not available, falling back to PIO\n");
690 return 0;
691 }
692
693 if (i2c_dev->hw->has_apb_dma) {
694 if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
695 dev_dbg(i2c_dev->dev, "APB DMA support not enabled\n");
696 return 0;
697 }
698 } else if (!IS_ENABLED(CONFIG_TEGRA186_GPC_DMA)) {
699 dev_dbg(i2c_dev->dev, "GPC DMA support not enabled\n");
700 return 0;
701 }
702
703 /*
704 * The same channel will be used for both RX and TX.
705 * Keeping the name as "tx" for backward compatibility
706 * with existing devicetrees.
707 */
708 i2c_dev->dma_chan = dma_request_chan(i2c_dev->dev, "tx");
709 if (IS_ERR(i2c_dev->dma_chan)) {
710 err = PTR_ERR(i2c_dev->dma_chan);
711 i2c_dev->dma_chan = NULL;
712 goto err_out;
713 }
714
715 i2c_dev->dma_dev = i2c_dev->dma_chan->device->dev;
716 i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +
717 I2C_PACKET_HEADER_SIZE;
718
719 dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
720 &dma_phys, GFP_KERNEL | __GFP_NOWARN);
721 if (!dma_buf) {
722 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n");
723 err = -ENOMEM;
724 goto err_out;
725 }
726
727 i2c_dev->dma_buf = dma_buf;
728 i2c_dev->dma_phys = dma_phys;
729
730 return 0;
731
732 err_out:
733 tegra_i2c_release_dma(i2c_dev);
734 if (err != -EPROBE_DEFER) {
735 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
736 dev_err(i2c_dev->dev, "falling back to PIO\n");
737 return 0;
738 }
739
740 return err;
741 }
742
743 /*
744 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
745 * block. This block is identical to the rest of the I2C blocks, except that
746 * it only supports master mode, it has registers moved around, and it needs
747 * some extra init to get it into I2C mode. The register moves are handled
748 * by i2c_readl() and i2c_writel().
749 */
tegra_dvc_init(struct tegra_i2c_dev * i2c_dev)750 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
751 {
752 u32 val;
753
754 val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
755 val |= DVC_CTRL_REG3_SW_PROG;
756 val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
757 dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
758
759 val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
760 val |= DVC_CTRL_REG1_INTR_EN;
761 dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
762 }
763
tegra_i2c_vi_init(struct tegra_i2c_dev * i2c_dev)764 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
765 {
766 u32 value;
767
768 value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) |
769 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4);
770 i2c_writel(i2c_dev, value, i2c_dev->hw->regs->interface_timing_0);
771
772 value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) |
773 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) |
774 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) |
775 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4);
776 i2c_writel(i2c_dev, value, i2c_dev->hw->regs->interface_timing_1);
777
778 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) |
779 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8);
780 i2c_writel(i2c_dev, value, i2c_dev->hw->regs->hs_interface_timing_0);
781
782 value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) |
783 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) |
784 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11);
785 i2c_writel(i2c_dev, value, i2c_dev->hw->regs->hs_interface_timing_1);
786
787 value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND;
788 i2c_writel(i2c_dev, value, i2c_dev->hw->regs->bus_clear_cnfg);
789
790 i2c_writel(i2c_dev, 0x0, i2c_dev->hw->regs->tlow_sext);
791 }
792
tegra_i2c_poll_register(struct tegra_i2c_dev * i2c_dev,u32 reg,u32 mask,u32 delay_us,u32 timeout_us)793 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
794 u32 reg, u32 mask, u32 delay_us,
795 u32 timeout_us)
796 {
797 void __iomem *addr = i2c_dev->base + reg;
798 u32 val;
799
800 if (!i2c_dev->atomic_mode)
801 return readl_relaxed_poll_timeout(addr, val, !(val & mask),
802 delay_us, timeout_us);
803
804 return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask),
805 delay_us, timeout_us);
806 }
807
tegra_i2c_flush_fifos(struct tegra_i2c_dev * i2c_dev)808 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
809 {
810 u32 mask, val, offset;
811 int err;
812
813 if (i2c_dev->hw->has_mst_fifo) {
814 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
815 I2C_MST_FIFO_CONTROL_RX_FLUSH;
816 offset = i2c_dev->hw->regs->mst_fifo_control;
817 } else {
818 mask = I2C_FIFO_CONTROL_TX_FLUSH |
819 I2C_FIFO_CONTROL_RX_FLUSH;
820 offset = i2c_dev->hw->regs->fifo_control;
821 }
822
823 val = i2c_readl(i2c_dev, offset);
824 val |= mask;
825 i2c_writel(i2c_dev, val, offset);
826
827 err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000);
828 if (err) {
829 dev_err(i2c_dev->dev, "failed to flush FIFO\n");
830 return err;
831 }
832
833 return 0;
834 }
835
tegra_i2c_wait_for_config_load(struct tegra_i2c_dev * i2c_dev)836 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
837 {
838 int err;
839
840 if (!i2c_dev->hw->has_config_load_reg)
841 return 0;
842
843 i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, i2c_dev->hw->regs->config_load);
844
845 err = tegra_i2c_poll_register(i2c_dev, i2c_dev->hw->regs->config_load, 0xffffffff,
846 1000, I2C_CONFIG_LOAD_TIMEOUT);
847 if (err) {
848 dev_err(i2c_dev->dev, "failed to load config\n");
849 return err;
850 }
851
852 return 0;
853 }
854
tegra_i2c_master_reset(struct tegra_i2c_dev * i2c_dev)855 static int tegra_i2c_master_reset(struct tegra_i2c_dev *i2c_dev)
856 {
857 if (!i2c_dev->hw->has_mst_reset)
858 return -EOPNOTSUPP;
859
860 /*
861 * Writing 1 to I2C_MASTER_RESET_CNTRL will reset all internal state of
862 * Master logic including FIFOs. Clear this bit to 0 for normal operation.
863 * SW needs to wait for 2us after assertion and de-assertion of this soft
864 * reset.
865 */
866 i2c_writel(i2c_dev, 0x1, i2c_dev->hw->regs->master_reset_cntrl);
867 fsleep(2);
868
869 i2c_writel(i2c_dev, 0x0, i2c_dev->hw->regs->master_reset_cntrl);
870 fsleep(2);
871
872 return 0;
873 }
874
tegra_i2c_init(struct tegra_i2c_dev * i2c_dev)875 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
876 {
877 u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
878 u32 max_bus_freq_hz;
879 struct i2c_timings *t = &i2c_dev->timings;
880 int err;
881
882 /*
883 * Reset the controller before initializing it.
884 * In case if device_reset() returns -ENOENT, i.e. when the reset is
885 * not available, the internal software reset will be used if it is
886 * supported by the controller.
887 */
888 err = device_reset(i2c_dev->dev);
889 if (err == -ENOENT)
890 err = tegra_i2c_master_reset(i2c_dev);
891
892 /*
893 * The reset shouldn't ever fail in practice. The failure will be a
894 * sign of a severe problem that needs to be resolved. Still we don't
895 * want to fail the initialization completely because this may break
896 * kernel boot up since voltage regulators use I2C. Hence, we will
897 * emit a noisy warning on error, which won't stay unnoticed and
898 * won't hose machine entirely.
899 */
900 WARN_ON_ONCE(err);
901
902 if (IS_DVC(i2c_dev))
903 tegra_dvc_init(i2c_dev);
904
905 val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
906 FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);
907
908 if (i2c_dev->hw->has_multi_master_mode)
909 val |= I2C_CNFG_MULTI_MASTER_MODE;
910
911 i2c_writel(i2c_dev, val, i2c_dev->hw->regs->cnfg);
912 i2c_writel(i2c_dev, 0, i2c_dev->hw->regs->int_mask);
913
914 if (IS_VI(i2c_dev))
915 tegra_i2c_vi_init(i2c_dev);
916
917 if (i2c_dev->hw->enable_hs_mode_support)
918 max_bus_freq_hz = I2C_MAX_HIGH_SPEED_MODE_FREQ;
919 else
920 max_bus_freq_hz = I2C_MAX_FAST_MODE_PLUS_FREQ;
921
922 if (WARN_ON(t->bus_freq_hz > max_bus_freq_hz))
923 t->bus_freq_hz = max_bus_freq_hz;
924
925 if (t->bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
926 tlow = i2c_dev->hw->tlow_std_mode;
927 thigh = i2c_dev->hw->thigh_std_mode;
928 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
929 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
930 } else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
931 tlow = i2c_dev->hw->tlow_fast_mode;
932 thigh = i2c_dev->hw->thigh_fast_mode;
933 tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode;
934 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
935 } else if (t->bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
936 tlow = i2c_dev->hw->tlow_fastplus_mode;
937 thigh = i2c_dev->hw->thigh_fastplus_mode;
938 tsu_thd = i2c_dev->hw->setup_hold_time_fastplus_mode;
939 non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
940 } else {
941 /*
942 * When using HS mode, i.e. when the bus frequency is greater than fast plus mode,
943 * the non-hs timing registers will be used for sending the master code byte for
944 * transition to HS mode. Configure the non-hs timing registers for Fast Mode to
945 * send the master code byte at 400kHz.
946 */
947 tlow = i2c_dev->hw->tlow_fast_mode;
948 thigh = i2c_dev->hw->thigh_fast_mode;
949 tsu_thd = i2c_dev->hw->setup_hold_time_fast_mode;
950 non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
951 }
952
953 /* make sure clock divisor programmed correctly */
954 clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
955 i2c_dev->hw->clk_divisor_hs_mode) |
956 FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
957 i2c_writel(i2c_dev, clk_divisor, i2c_dev->hw->regs->clk_divisor);
958
959 if (i2c_dev->hw->has_interface_timing_reg) {
960 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
961 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
962 i2c_writel(i2c_dev, val, i2c_dev->hw->regs->interface_timing_0);
963 }
964
965 /*
966 * Configure setup and hold times only when tsu_thd is non-zero.
967 * Otherwise, preserve the chip default values.
968 */
969 if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
970 i2c_writel(i2c_dev, tsu_thd, i2c_dev->hw->regs->interface_timing_1);
971
972 /* Write HS mode registers. These will get used only for HS mode*/
973 if (i2c_dev->hw->enable_hs_mode_support) {
974 tlow = i2c_dev->hw->tlow_hs_mode;
975 thigh = i2c_dev->hw->thigh_hs_mode;
976 tsu_thd = i2c_dev->hw->setup_hold_time_hs_mode;
977
978 val = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, thigh) |
979 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, tlow);
980 i2c_writel(i2c_dev, val, i2c_dev->hw->regs->hs_interface_timing_0);
981 i2c_writel(i2c_dev, tsu_thd, i2c_dev->hw->regs->hs_interface_timing_1);
982 }
983
984 clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
985
986 err = clk_set_rate(i2c_dev->div_clk,
987 t->bus_freq_hz * clk_multiplier);
988 if (err) {
989 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
990 return err;
991 }
992
993 if (!IS_DVC(i2c_dev) && !IS_VI(i2c_dev)) {
994 u32 sl_cfg = i2c_readl(i2c_dev, i2c_dev->hw->regs->sl_cnfg);
995
996 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
997 i2c_writel(i2c_dev, sl_cfg, i2c_dev->hw->regs->sl_cnfg);
998 i2c_writel(i2c_dev, 0xfc, i2c_dev->hw->regs->sl_addr1);
999 i2c_writel(i2c_dev, 0x00, i2c_dev->hw->regs->sl_addr2);
1000 }
1001
1002 err = tegra_i2c_flush_fifos(i2c_dev);
1003 if (err)
1004 return err;
1005
1006 if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
1007 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, i2c_dev->hw->regs->clken_override);
1008
1009 err = tegra_i2c_wait_for_config_load(i2c_dev);
1010 if (err)
1011 return err;
1012
1013 return 0;
1014 }
1015
tegra_i2c_disable_packet_mode(struct tegra_i2c_dev * i2c_dev)1016 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
1017 {
1018 u32 cnfg;
1019
1020 /*
1021 * NACK interrupt is generated before the I2C controller generates
1022 * the STOP condition on the bus. So, wait for 2 clock periods
1023 * before disabling the controller so that the STOP condition has
1024 * been delivered properly.
1025 */
1026 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->timings.bus_freq_hz));
1027
1028 cnfg = i2c_readl(i2c_dev, i2c_dev->hw->regs->cnfg);
1029 if (cnfg & I2C_CNFG_PACKET_MODE_EN)
1030 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, i2c_dev->hw->regs->cnfg);
1031
1032 return tegra_i2c_wait_for_config_load(i2c_dev);
1033 }
1034
tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev * i2c_dev)1035 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
1036 {
1037 size_t buf_remaining = i2c_dev->msg_buf_remaining;
1038 unsigned int words_to_transfer, rx_fifo_avail;
1039 u8 *buf = i2c_dev->msg_buf;
1040 u32 val;
1041
1042 /*
1043 * Catch overflow due to message fully sent before the check for
1044 * RX FIFO availability.
1045 */
1046 if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
1047 return -EINVAL;
1048
1049 if (i2c_dev->hw->has_mst_fifo) {
1050 val = i2c_readl(i2c_dev, i2c_dev->hw->regs->mst_fifo_status);
1051 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val);
1052 } else {
1053 val = i2c_readl(i2c_dev, i2c_dev->hw->regs->fifo_status);
1054 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
1055 }
1056
1057 /* round down to exclude partial word at the end of buffer */
1058 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
1059 if (words_to_transfer > rx_fifo_avail)
1060 words_to_transfer = rx_fifo_avail;
1061
1062 i2c_readsl(i2c_dev, buf, i2c_dev->hw->regs->rx_fifo, words_to_transfer);
1063
1064 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
1065 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
1066 rx_fifo_avail -= words_to_transfer;
1067
1068 /*
1069 * If there is a partial word at the end of buffer, handle it
1070 * manually to prevent overwriting past the end of buffer.
1071 */
1072 if (rx_fifo_avail > 0 && buf_remaining > 0) {
1073 /*
1074 * buf_remaining > 3 check not needed as rx_fifo_avail == 0
1075 * when (words_to_transfer was > rx_fifo_avail) earlier
1076 * in this function.
1077 */
1078 val = i2c_readl(i2c_dev, i2c_dev->hw->regs->rx_fifo);
1079 val = cpu_to_le32(val);
1080 memcpy(buf, &val, buf_remaining);
1081 buf_remaining = 0;
1082 rx_fifo_avail--;
1083 }
1084
1085 /* RX FIFO must be drained, otherwise it's an Overflow case. */
1086 if (WARN_ON_ONCE(rx_fifo_avail))
1087 return -EINVAL;
1088
1089 i2c_dev->msg_buf_remaining = buf_remaining;
1090 i2c_dev->msg_buf = buf;
1091
1092 return 0;
1093 }
1094
tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev * i2c_dev)1095 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
1096 {
1097 size_t buf_remaining = i2c_dev->msg_buf_remaining;
1098 unsigned int words_to_transfer, tx_fifo_avail;
1099 u8 *buf = i2c_dev->msg_buf;
1100 u32 val;
1101
1102 if (i2c_dev->hw->has_mst_fifo) {
1103 val = i2c_readl(i2c_dev, i2c_dev->hw->regs->mst_fifo_status);
1104 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val);
1105 } else {
1106 val = i2c_readl(i2c_dev, i2c_dev->hw->regs->fifo_status);
1107 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
1108 }
1109
1110 /* round down to exclude partial word at the end of buffer */
1111 words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
1112
1113 /*
1114 * This hunk pushes 4 bytes at a time into the TX FIFO.
1115 *
1116 * It's very common to have < 4 bytes, hence there is no word
1117 * to push if we have less than 4 bytes to transfer.
1118 */
1119 if (words_to_transfer) {
1120 if (words_to_transfer > tx_fifo_avail)
1121 words_to_transfer = tx_fifo_avail;
1122
1123 /*
1124 * Update state before writing to FIFO. Note that this may
1125 * cause us to finish writing all bytes (AKA buf_remaining
1126 * goes to 0), hence we have a potential for an interrupt
1127 * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt
1128 * is disabled at this point.
1129 */
1130 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
1131 tx_fifo_avail -= words_to_transfer;
1132
1133 i2c_dev->msg_buf_remaining = buf_remaining;
1134 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD;
1135
1136 if (IS_VI(i2c_dev))
1137 i2c_writesl_vi(i2c_dev, buf, i2c_dev->hw->regs->tx_fifo, words_to_transfer);
1138 else
1139 i2c_writesl(i2c_dev, buf, i2c_dev->hw->regs->tx_fifo, words_to_transfer);
1140
1141 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
1142 }
1143
1144 /*
1145 * If there is a partial word at the end of buffer, handle it manually
1146 * to prevent reading past the end of buffer, which could cross a page
1147 * boundary and fault.
1148 */
1149 if (tx_fifo_avail > 0 && buf_remaining > 0) {
1150 /*
1151 * buf_remaining > 3 check not needed as tx_fifo_avail == 0
1152 * when (words_to_transfer was > tx_fifo_avail) earlier
1153 * in this function for non-zero words_to_transfer.
1154 */
1155 memcpy(&val, buf, buf_remaining);
1156 val = le32_to_cpu(val);
1157
1158 i2c_dev->msg_buf_remaining = 0;
1159 i2c_dev->msg_buf = NULL;
1160
1161 i2c_writel(i2c_dev, val, i2c_dev->hw->regs->tx_fifo);
1162 }
1163
1164 return 0;
1165 }
1166
tegra_i2c_isr(int irq,void * dev_id)1167 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
1168 {
1169 const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1170 struct tegra_i2c_dev *i2c_dev = dev_id;
1171 u32 status;
1172
1173 status = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_status);
1174
1175 if (status == 0) {
1176 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n",
1177 i2c_readl(i2c_dev, i2c_dev->hw->regs->packet_transfer_status),
1178 i2c_readl(i2c_dev, i2c_dev->hw->regs->status),
1179 i2c_readl(i2c_dev, i2c_dev->hw->regs->cnfg));
1180 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
1181 goto err;
1182 }
1183
1184 if (status & status_err) {
1185 tegra_i2c_disable_packet_mode(i2c_dev);
1186 if (status & I2C_INT_NO_ACK)
1187 i2c_dev->msg_err |= I2C_ERR_NO_ACK;
1188 if (status & I2C_INT_ARBITRATION_LOST)
1189 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
1190 goto err;
1191 }
1192
1193 /*
1194 * I2C transfer is terminated during the bus clear, so skip
1195 * processing the other interrupts.
1196 */
1197 if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
1198 goto err;
1199
1200 if (!i2c_dev->dma_mode) {
1201 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
1202 if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
1203 /*
1204 * Overflow error condition: message fully sent,
1205 * with no XFER_COMPLETE interrupt but hardware
1206 * asks to transfer more.
1207 */
1208 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
1209 goto err;
1210 }
1211 }
1212
1213 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
1214 if (i2c_dev->msg_buf_remaining)
1215 tegra_i2c_fill_tx_fifo(i2c_dev);
1216 else
1217 tegra_i2c_mask_irq(i2c_dev,
1218 I2C_INT_TX_FIFO_DATA_REQ);
1219 }
1220 }
1221
1222 i2c_writel(i2c_dev, status, i2c_dev->hw->regs->int_status);
1223 if (IS_DVC(i2c_dev))
1224 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
1225
1226 /*
1227 * During message read XFER_COMPLETE interrupt is triggered prior to
1228 * DMA completion and during message write XFER_COMPLETE interrupt is
1229 * triggered after DMA completion.
1230 *
1231 * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer,
1232 * so forcing msg_buf_remaining to 0 in DMA mode.
1233 */
1234 if (status & I2C_INT_PACKET_XFER_COMPLETE) {
1235 if (i2c_dev->dma_mode)
1236 i2c_dev->msg_buf_remaining = 0;
1237 /*
1238 * Underflow error condition: XFER_COMPLETE before message
1239 * fully sent.
1240 */
1241 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
1242 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
1243 goto err;
1244 }
1245 complete(&i2c_dev->msg_complete);
1246 }
1247 goto done;
1248 err:
1249 /* mask all interrupts on error */
1250 tegra_i2c_mask_irq(i2c_dev,
1251 I2C_INT_NO_ACK |
1252 I2C_INT_ARBITRATION_LOST |
1253 I2C_INT_PACKET_XFER_COMPLETE |
1254 I2C_INT_TX_FIFO_DATA_REQ |
1255 I2C_INT_RX_FIFO_DATA_REQ);
1256
1257 if (i2c_dev->hw->supports_bus_clear)
1258 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1259
1260 i2c_writel(i2c_dev, status, i2c_dev->hw->regs->int_status);
1261
1262 if (IS_DVC(i2c_dev))
1263 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
1264
1265 if (i2c_dev->dma_mode) {
1266 dmaengine_terminate_async(i2c_dev->dma_chan);
1267 complete(&i2c_dev->dma_complete);
1268 }
1269
1270 complete(&i2c_dev->msg_complete);
1271 done:
1272 return IRQ_HANDLED;
1273 }
1274
tegra_i2c_config_fifo_trig(struct tegra_i2c_dev * i2c_dev,size_t len)1275 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
1276 size_t len)
1277 {
1278 struct dma_slave_config slv_config = {0};
1279 u32 val, reg, dma_burst, reg_offset;
1280 int err;
1281
1282 if (i2c_dev->hw->has_mst_fifo)
1283 reg = i2c_dev->hw->regs->mst_fifo_control;
1284 else
1285 reg = i2c_dev->hw->regs->fifo_control;
1286
1287 if (i2c_dev->dma_mode) {
1288 if (len & 0xF)
1289 dma_burst = 1;
1290 else if (len & 0x10)
1291 dma_burst = 4;
1292 else
1293 dma_burst = 8;
1294
1295 if (i2c_dev->msg_read) {
1296 reg_offset = i2c_dev->hw->regs->rx_fifo;
1297
1298 slv_config.src_addr = i2c_dev->base_phys + reg_offset;
1299 slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1300 slv_config.src_maxburst = dma_burst;
1301
1302 if (i2c_dev->hw->has_mst_fifo)
1303 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
1304 else
1305 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
1306 } else {
1307 reg_offset = i2c_dev->hw->regs->tx_fifo;
1308
1309 slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
1310 slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1311 slv_config.dst_maxburst = dma_burst;
1312
1313 if (i2c_dev->hw->has_mst_fifo)
1314 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
1315 else
1316 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
1317 }
1318
1319 slv_config.device_fc = true;
1320 err = dmaengine_slave_config(i2c_dev->dma_chan, &slv_config);
1321 if (err) {
1322 dev_err(i2c_dev->dev, "DMA config failed: %d\n", err);
1323 dev_err(i2c_dev->dev, "falling back to PIO\n");
1324
1325 tegra_i2c_release_dma(i2c_dev);
1326 i2c_dev->dma_mode = false;
1327 } else {
1328 goto out;
1329 }
1330 }
1331
1332 if (i2c_dev->hw->has_mst_fifo)
1333 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
1334 I2C_MST_FIFO_CONTROL_RX_TRIG(1);
1335 else
1336 val = I2C_FIFO_CONTROL_TX_TRIG(8) |
1337 I2C_FIFO_CONTROL_RX_TRIG(1);
1338 out:
1339 i2c_writel(i2c_dev, val, reg);
1340 }
1341
tegra_i2c_poll_completion(struct tegra_i2c_dev * i2c_dev,struct completion * complete,unsigned int timeout_ms)1342 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev,
1343 struct completion *complete,
1344 unsigned int timeout_ms)
1345 {
1346 ktime_t ktime = ktime_get();
1347 ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms);
1348
1349 do {
1350 u32 status = i2c_readl(i2c_dev, i2c_dev->hw->regs->int_status);
1351
1352 if (status)
1353 tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1354
1355 if (completion_done(complete)) {
1356 s64 delta = ktime_ms_delta(ktimeout, ktime);
1357
1358 return msecs_to_jiffies(delta) ?: 1;
1359 }
1360
1361 ktime = ktime_get();
1362
1363 } while (ktime_before(ktime, ktimeout));
1364
1365 return 0;
1366 }
1367
tegra_i2c_wait_completion(struct tegra_i2c_dev * i2c_dev,struct completion * complete,unsigned int timeout_ms)1368 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev,
1369 struct completion *complete,
1370 unsigned int timeout_ms)
1371 {
1372 unsigned long ret;
1373
1374 if (i2c_dev->atomic_mode) {
1375 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms);
1376 } else {
1377 enable_irq(i2c_dev->irq);
1378 ret = wait_for_completion_timeout(complete,
1379 msecs_to_jiffies(timeout_ms));
1380 disable_irq(i2c_dev->irq);
1381
1382 /*
1383 * Under some rare circumstances (like running KASAN +
1384 * NFS root) CPU, which handles interrupt, may stuck in
1385 * uninterruptible state for a significant time. In this
1386 * case we will get timeout if I2C transfer is running on
1387 * a sibling CPU, despite of IRQ being raised.
1388 *
1389 * In order to handle this rare condition, the IRQ status
1390 * needs to be checked after timeout.
1391 */
1392 if (ret == 0)
1393 ret = tegra_i2c_poll_completion(i2c_dev, complete, 0);
1394 }
1395
1396 return ret;
1397 }
1398
tegra_i2c_issue_bus_clear(struct i2c_adapter * adap)1399 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
1400 {
1401 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1402 u32 val, time_left;
1403 int err;
1404
1405 reinit_completion(&i2c_dev->msg_complete);
1406
1407 val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
1408 I2C_BC_TERMINATE;
1409 i2c_writel(i2c_dev, val, i2c_dev->hw->regs->bus_clear_cnfg);
1410
1411 err = tegra_i2c_wait_for_config_load(i2c_dev);
1412 if (err)
1413 return err;
1414
1415 val |= I2C_BC_ENABLE;
1416 i2c_writel(i2c_dev, val, i2c_dev->hw->regs->bus_clear_cnfg);
1417 tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1418
1419 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50);
1420 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1421
1422 if (time_left == 0) {
1423 dev_err(i2c_dev->dev, "failed to clear bus\n");
1424 return -ETIMEDOUT;
1425 }
1426
1427 val = i2c_readl(i2c_dev, i2c_dev->hw->regs->bus_clear_status);
1428 if (!(val & I2C_BC_STATUS)) {
1429 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n");
1430 return -EIO;
1431 }
1432
1433 return -EAGAIN;
1434 }
1435
tegra_i2c_push_packet_header(struct tegra_i2c_dev * i2c_dev,struct i2c_msg * msg,enum msg_end_type end_state)1436 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
1437 struct i2c_msg *msg,
1438 enum msg_end_type end_state)
1439 {
1440 u32 *dma_buf = i2c_dev->dma_buf;
1441 u32 packet_header;
1442
1443 packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) |
1444 FIELD_PREP(PACKET_HEADER0_PROTOCOL,
1445 PACKET_HEADER0_PROTOCOL_I2C) |
1446 FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
1447 FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1);
1448
1449 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1450 *dma_buf++ = packet_header;
1451 else
1452 i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo);
1453
1454 packet_header = i2c_dev->msg_len - 1;
1455
1456 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1457 *dma_buf++ = packet_header;
1458 else
1459 i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo);
1460
1461 packet_header = I2C_HEADER_IE_ENABLE;
1462
1463 if (end_state == MSG_END_CONTINUE)
1464 packet_header |= I2C_HEADER_CONTINUE_XFER;
1465 else if (end_state == MSG_END_REPEAT_START)
1466 packet_header |= I2C_HEADER_REPEAT_START;
1467
1468 if (msg->flags & I2C_M_TEN) {
1469 packet_header |= msg->addr;
1470 packet_header |= I2C_HEADER_10BIT_ADDR;
1471 } else {
1472 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1473 }
1474
1475 if (msg->flags & I2C_M_IGNORE_NAK)
1476 packet_header |= I2C_HEADER_CONT_ON_NAK;
1477
1478 if (msg->flags & I2C_M_RD)
1479 packet_header |= I2C_HEADER_READ;
1480
1481 if (i2c_dev->timings.bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ)
1482 packet_header |= I2C_HEADER_HS_MODE;
1483
1484 if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1485 *dma_buf++ = packet_header;
1486 else
1487 i2c_writel(i2c_dev, packet_header, i2c_dev->hw->regs->tx_fifo);
1488 }
1489
tegra_i2c_error_recover(struct tegra_i2c_dev * i2c_dev,struct i2c_msg * msg)1490 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev,
1491 struct i2c_msg *msg)
1492 {
1493 if (i2c_dev->msg_err == I2C_ERR_NONE)
1494 return 0;
1495
1496 tegra_i2c_init(i2c_dev);
1497
1498 /* start recovery upon arbitration loss in single master mode */
1499 if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1500 if (!i2c_dev->multimaster_mode)
1501 return i2c_recover_bus(&i2c_dev->adapter);
1502
1503 return -EAGAIN;
1504 }
1505
1506 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1507 if (msg->flags & I2C_M_IGNORE_NAK)
1508 return 0;
1509
1510 return -EREMOTEIO;
1511 }
1512
1513 return -EIO;
1514 }
1515
tegra_i2c_xfer_msg(struct tegra_i2c_dev * i2c_dev,struct i2c_msg * msg,enum msg_end_type end_state)1516 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1517 struct i2c_msg *msg,
1518 enum msg_end_type end_state)
1519 {
1520 unsigned long time_left, xfer_time = 100;
1521 size_t xfer_size;
1522 u32 int_mask;
1523 int err;
1524
1525 err = tegra_i2c_flush_fifos(i2c_dev);
1526 if (err)
1527 return err;
1528
1529 i2c_dev->msg_buf = msg->buf;
1530 i2c_dev->msg_len = msg->len;
1531
1532 i2c_dev->msg_err = I2C_ERR_NONE;
1533 i2c_dev->msg_read = !!(msg->flags & I2C_M_RD);
1534 reinit_completion(&i2c_dev->msg_complete);
1535
1536 /*
1537 * For SMBUS block read command, read only 1 byte in the first transfer.
1538 * Adjust that 1 byte for the next transfer in the msg buffer and msg
1539 * length.
1540 */
1541 if (msg->flags & I2C_M_RECV_LEN) {
1542 if (end_state == MSG_END_CONTINUE) {
1543 i2c_dev->msg_len = 1;
1544 } else {
1545 i2c_dev->msg_buf += 1;
1546 i2c_dev->msg_len -= 1;
1547 }
1548 }
1549
1550 i2c_dev->msg_buf_remaining = i2c_dev->msg_len;
1551
1552 if (i2c_dev->msg_read)
1553 xfer_size = i2c_dev->msg_len;
1554 else
1555 xfer_size = i2c_dev->msg_len + I2C_PACKET_HEADER_SIZE;
1556
1557 xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1558
1559 i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN &&
1560 i2c_dev->dma_buf && !i2c_dev->atomic_mode;
1561
1562 tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1563
1564 /*
1565 * Transfer time in mSec = Total bits / transfer rate
1566 * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1567 */
1568 xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1569 i2c_dev->timings.bus_freq_hz);
1570
1571 int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1572 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1573
1574 if (i2c_dev->dma_mode) {
1575 if (i2c_dev->msg_read) {
1576 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1577 if (err)
1578 return err;
1579 }
1580 }
1581
1582 tegra_i2c_push_packet_header(i2c_dev, msg, end_state);
1583
1584 if (!i2c_dev->msg_read) {
1585 if (i2c_dev->dma_mode) {
1586 memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE,
1587 msg->buf, i2c_dev->msg_len);
1588 err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1589 if (err)
1590 return err;
1591 } else {
1592 tegra_i2c_fill_tx_fifo(i2c_dev);
1593 }
1594 }
1595
1596 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1597 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1598
1599 if (!i2c_dev->dma_mode) {
1600 if (msg->flags & I2C_M_RD)
1601 int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1602 else if (i2c_dev->msg_buf_remaining)
1603 int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1604 }
1605
1606 tegra_i2c_unmask_irq(i2c_dev, int_mask);
1607 dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n",
1608 i2c_readl(i2c_dev, i2c_dev->hw->regs->int_mask));
1609
1610 if (i2c_dev->dma_mode) {
1611 time_left = tegra_i2c_wait_completion(i2c_dev,
1612 &i2c_dev->dma_complete,
1613 xfer_time);
1614
1615 /*
1616 * Synchronize DMA first, since dmaengine_terminate_sync()
1617 * performs synchronization after the transfer's termination
1618 * and we want to get a completion if transfer succeeded.
1619 */
1620 dmaengine_synchronize(i2c_dev->dma_chan);
1621 dmaengine_terminate_sync(i2c_dev->dma_chan);
1622
1623 if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
1624 tegra_i2c_init(i2c_dev);
1625 return -ETIMEDOUT;
1626 }
1627
1628 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE)
1629 memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, i2c_dev->msg_len);
1630 }
1631
1632 time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete,
1633 xfer_time);
1634
1635 tegra_i2c_mask_irq(i2c_dev, int_mask);
1636
1637 if (time_left == 0) {
1638 tegra_i2c_init(i2c_dev);
1639 return -ETIMEDOUT;
1640 }
1641
1642 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1643 time_left, completion_done(&i2c_dev->msg_complete),
1644 i2c_dev->msg_err);
1645
1646 i2c_dev->dma_mode = false;
1647
1648 err = tegra_i2c_error_recover(i2c_dev, msg);
1649 if (err)
1650 return err;
1651
1652 return 0;
1653 }
1654
tegra_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1655 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1656 int num)
1657 {
1658 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1659 int i, ret;
1660
1661 ret = pm_runtime_get_sync(i2c_dev->dev);
1662 if (ret < 0) {
1663 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1664 pm_runtime_put_noidle(i2c_dev->dev);
1665 return ret;
1666 }
1667
1668 ret = tegra_i2c_mutex_lock(i2c_dev);
1669 if (ret)
1670 return ret;
1671
1672 for (i = 0; i < num; i++) {
1673 enum msg_end_type end_type = MSG_END_STOP;
1674
1675 if (i < (num - 1)) {
1676 /* check whether follow up message is coming */
1677 if (msgs[i + 1].flags & I2C_M_NOSTART)
1678 end_type = MSG_END_CONTINUE;
1679 else
1680 end_type = MSG_END_REPEAT_START;
1681 }
1682 /* If M_RECV_LEN use ContinueXfer to read the first byte */
1683 if (msgs[i].flags & I2C_M_RECV_LEN) {
1684 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], MSG_END_CONTINUE);
1685 if (ret)
1686 break;
1687
1688 /* Validate message length before proceeding */
1689 if (msgs[i].buf[0] == 0 || msgs[i].buf[0] > I2C_SMBUS_BLOCK_MAX)
1690 break;
1691
1692 /* Set the msg length from first byte */
1693 msgs[i].len += msgs[i].buf[0];
1694 dev_dbg(i2c_dev->dev, "reading %d bytes\n", msgs[i].len);
1695 }
1696 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1697 if (ret)
1698 break;
1699 }
1700
1701 ret = tegra_i2c_mutex_unlock(i2c_dev);
1702 pm_runtime_put(i2c_dev->dev);
1703
1704 return ret ?: i;
1705 }
1706
tegra_i2c_xfer_atomic(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)1707 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap,
1708 struct i2c_msg msgs[], int num)
1709 {
1710 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1711 int ret;
1712
1713 i2c_dev->atomic_mode = true;
1714 ret = tegra_i2c_xfer(adap, msgs, num);
1715 i2c_dev->atomic_mode = false;
1716
1717 return ret;
1718 }
1719
tegra_i2c_func(struct i2c_adapter * adap)1720 static u32 tegra_i2c_func(struct i2c_adapter *adap)
1721 {
1722 struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1723 u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1724 I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
1725
1726 if (i2c_dev->hw->has_continue_xfer_support)
1727 ret |= I2C_FUNC_NOSTART | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
1728
1729 return ret;
1730 }
1731
1732 static const struct i2c_algorithm tegra_i2c_algo = {
1733 .xfer = tegra_i2c_xfer,
1734 .xfer_atomic = tegra_i2c_xfer_atomic,
1735 .functionality = tegra_i2c_func,
1736 };
1737
1738 /* payload size is only 12 bit */
1739 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1740 .flags = I2C_AQ_NO_ZERO_LEN,
1741 .max_read_len = SZ_4K,
1742 .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1743 };
1744
1745 static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1746 .flags = I2C_AQ_NO_ZERO_LEN,
1747 .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1748 };
1749
1750 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1751 .recover_bus = tegra_i2c_issue_bus_clear,
1752 };
1753
1754 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1755 .has_continue_xfer_support = false,
1756 .has_per_pkt_xfer_complete_irq = false,
1757 .clk_divisor_hs_mode = 3,
1758 .clk_divisor_std_mode = 0,
1759 .clk_divisor_fast_mode = 0,
1760 .clk_divisor_fast_plus_mode = 0,
1761 .has_config_load_reg = false,
1762 .has_multi_master_mode = false,
1763 .has_slcg_override_reg = false,
1764 .has_mst_fifo = false,
1765 .has_mst_reset = false,
1766 .quirks = &tegra_i2c_quirks,
1767 .supports_bus_clear = false,
1768 .has_apb_dma = true,
1769 .tlow_std_mode = 0x4,
1770 .thigh_std_mode = 0x2,
1771 .tlow_fast_mode = 0x4,
1772 .thigh_fast_mode = 0x2,
1773 .tlow_fastplus_mode = 0x4,
1774 .thigh_fastplus_mode = 0x2,
1775 .setup_hold_time_std_mode = 0x0,
1776 .setup_hold_time_fast_mode = 0x0,
1777 .setup_hold_time_fastplus_mode = 0x0,
1778 .setup_hold_time_hs_mode = 0x0,
1779 .has_interface_timing_reg = false,
1780 .enable_hs_mode_support = false,
1781 .has_mutex = false,
1782 .variant = TEGRA_I2C_VARIANT_DEFAULT,
1783 .regs = &tegra20_i2c_regs,
1784 };
1785
1786 #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
1787 static const struct tegra_i2c_hw_feature tegra20_dvc_i2c_hw = {
1788 .has_continue_xfer_support = false,
1789 .has_per_pkt_xfer_complete_irq = false,
1790 .clk_divisor_hs_mode = 3,
1791 .clk_divisor_std_mode = 0,
1792 .clk_divisor_fast_mode = 0,
1793 .clk_divisor_fast_plus_mode = 0,
1794 .has_config_load_reg = false,
1795 .has_multi_master_mode = false,
1796 .has_slcg_override_reg = false,
1797 .has_mst_fifo = false,
1798 .has_mst_reset = false,
1799 .quirks = &tegra_i2c_quirks,
1800 .supports_bus_clear = false,
1801 .has_apb_dma = true,
1802 .tlow_std_mode = 0x4,
1803 .thigh_std_mode = 0x2,
1804 .tlow_fast_mode = 0x4,
1805 .thigh_fast_mode = 0x2,
1806 .tlow_fastplus_mode = 0x4,
1807 .thigh_fastplus_mode = 0x2,
1808 .setup_hold_time_std_mode = 0x0,
1809 .setup_hold_time_fast_mode = 0x0,
1810 .setup_hold_time_fastplus_mode = 0x0,
1811 .setup_hold_time_hs_mode = 0x0,
1812 .has_interface_timing_reg = false,
1813 .enable_hs_mode_support = false,
1814 .has_mutex = false,
1815 .variant = TEGRA_I2C_VARIANT_DVC,
1816 .regs = &tegra20_dvc_i2c_regs,
1817 };
1818 #endif
1819
1820 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1821 .has_continue_xfer_support = true,
1822 .has_per_pkt_xfer_complete_irq = false,
1823 .clk_divisor_hs_mode = 3,
1824 .clk_divisor_std_mode = 0,
1825 .clk_divisor_fast_mode = 0,
1826 .clk_divisor_fast_plus_mode = 0,
1827 .has_config_load_reg = false,
1828 .has_multi_master_mode = false,
1829 .has_slcg_override_reg = false,
1830 .has_mst_fifo = false,
1831 .has_mst_reset = false,
1832 .quirks = &tegra_i2c_quirks,
1833 .supports_bus_clear = false,
1834 .has_apb_dma = true,
1835 .tlow_std_mode = 0x4,
1836 .thigh_std_mode = 0x2,
1837 .tlow_fast_mode = 0x4,
1838 .thigh_fast_mode = 0x2,
1839 .tlow_fastplus_mode = 0x4,
1840 .thigh_fastplus_mode = 0x2,
1841 .setup_hold_time_std_mode = 0x0,
1842 .setup_hold_time_fast_mode = 0x0,
1843 .setup_hold_time_fastplus_mode = 0x0,
1844 .setup_hold_time_hs_mode = 0x0,
1845 .has_interface_timing_reg = false,
1846 .enable_hs_mode_support = false,
1847 .has_mutex = false,
1848 .variant = TEGRA_I2C_VARIANT_DEFAULT,
1849 .regs = &tegra20_i2c_regs,
1850 };
1851
1852 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1853 .has_continue_xfer_support = true,
1854 .has_per_pkt_xfer_complete_irq = true,
1855 .clk_divisor_hs_mode = 1,
1856 .clk_divisor_std_mode = 0x19,
1857 .clk_divisor_fast_mode = 0x19,
1858 .clk_divisor_fast_plus_mode = 0x10,
1859 .has_config_load_reg = false,
1860 .has_multi_master_mode = false,
1861 .has_slcg_override_reg = false,
1862 .has_mst_fifo = false,
1863 .has_mst_reset = false,
1864 .quirks = &tegra_i2c_quirks,
1865 .supports_bus_clear = true,
1866 .has_apb_dma = true,
1867 .tlow_std_mode = 0x4,
1868 .thigh_std_mode = 0x2,
1869 .tlow_fast_mode = 0x4,
1870 .thigh_fast_mode = 0x2,
1871 .tlow_fastplus_mode = 0x4,
1872 .thigh_fastplus_mode = 0x2,
1873 .setup_hold_time_std_mode = 0x0,
1874 .setup_hold_time_fast_mode = 0x0,
1875 .setup_hold_time_fastplus_mode = 0x0,
1876 .setup_hold_time_hs_mode = 0x0,
1877 .has_interface_timing_reg = false,
1878 .enable_hs_mode_support = false,
1879 .has_mutex = false,
1880 .variant = TEGRA_I2C_VARIANT_DEFAULT,
1881 .regs = &tegra20_i2c_regs,
1882 };
1883
1884 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1885 .has_continue_xfer_support = true,
1886 .has_per_pkt_xfer_complete_irq = true,
1887 .clk_divisor_hs_mode = 1,
1888 .clk_divisor_std_mode = 0x19,
1889 .clk_divisor_fast_mode = 0x19,
1890 .clk_divisor_fast_plus_mode = 0x10,
1891 .has_config_load_reg = true,
1892 .has_multi_master_mode = false,
1893 .has_slcg_override_reg = true,
1894 .has_mst_fifo = false,
1895 .has_mst_reset = false,
1896 .quirks = &tegra_i2c_quirks,
1897 .supports_bus_clear = true,
1898 .has_apb_dma = true,
1899 .tlow_std_mode = 0x4,
1900 .thigh_std_mode = 0x2,
1901 .tlow_fast_mode = 0x4,
1902 .thigh_fast_mode = 0x2,
1903 .tlow_fastplus_mode = 0x4,
1904 .thigh_fastplus_mode = 0x2,
1905 .setup_hold_time_std_mode = 0x0,
1906 .setup_hold_time_fast_mode = 0x0,
1907 .setup_hold_time_fastplus_mode = 0x0,
1908 .setup_hold_time_hs_mode = 0x0,
1909 .has_interface_timing_reg = true,
1910 .enable_hs_mode_support = false,
1911 .has_mutex = false,
1912 .variant = TEGRA_I2C_VARIANT_DEFAULT,
1913 .regs = &tegra20_i2c_regs,
1914 };
1915
1916 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1917 .has_continue_xfer_support = true,
1918 .has_per_pkt_xfer_complete_irq = true,
1919 .clk_divisor_hs_mode = 1,
1920 .clk_divisor_std_mode = 0x19,
1921 .clk_divisor_fast_mode = 0x19,
1922 .clk_divisor_fast_plus_mode = 0x10,
1923 .has_config_load_reg = true,
1924 .has_multi_master_mode = false,
1925 .has_slcg_override_reg = true,
1926 .has_mst_fifo = false,
1927 .has_mst_reset = false,
1928 .quirks = &tegra_i2c_quirks,
1929 .supports_bus_clear = true,
1930 .has_apb_dma = true,
1931 .tlow_std_mode = 0x4,
1932 .thigh_std_mode = 0x2,
1933 .tlow_fast_mode = 0x4,
1934 .thigh_fast_mode = 0x2,
1935 .tlow_fastplus_mode = 0x4,
1936 .thigh_fastplus_mode = 0x2,
1937 .setup_hold_time_std_mode = 0,
1938 .setup_hold_time_fast_mode = 0,
1939 .setup_hold_time_fastplus_mode = 0,
1940 .setup_hold_time_hs_mode = 0,
1941 .has_interface_timing_reg = true,
1942 .enable_hs_mode_support = false,
1943 .has_mutex = false,
1944 .variant = TEGRA_I2C_VARIANT_DEFAULT,
1945 .regs = &tegra20_i2c_regs,
1946 };
1947
1948 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
1949 static const struct tegra_i2c_hw_feature tegra210_vi_i2c_hw = {
1950 .has_continue_xfer_support = true,
1951 .has_per_pkt_xfer_complete_irq = true,
1952 .clk_divisor_hs_mode = 1,
1953 .clk_divisor_std_mode = 0x19,
1954 .clk_divisor_fast_mode = 0x19,
1955 .clk_divisor_fast_plus_mode = 0x10,
1956 .has_config_load_reg = true,
1957 .has_multi_master_mode = false,
1958 .has_slcg_override_reg = true,
1959 .has_mst_fifo = false,
1960 .has_mst_reset = false,
1961 .quirks = &tegra_i2c_quirks,
1962 .supports_bus_clear = true,
1963 .has_apb_dma = true,
1964 .tlow_std_mode = 0x4,
1965 .thigh_std_mode = 0x2,
1966 .tlow_fast_mode = 0x4,
1967 .thigh_fast_mode = 0x2,
1968 .tlow_fastplus_mode = 0x4,
1969 .thigh_fastplus_mode = 0x2,
1970 .setup_hold_time_std_mode = 0,
1971 .setup_hold_time_fast_mode = 0,
1972 .setup_hold_time_fastplus_mode = 0,
1973 .setup_hold_time_hs_mode = 0,
1974 .has_interface_timing_reg = true,
1975 .enable_hs_mode_support = false,
1976 .has_mutex = false,
1977 .variant = TEGRA_I2C_VARIANT_VI,
1978 .regs = &tegra210_vi_i2c_regs,
1979 };
1980 #endif
1981
1982 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1983 .has_continue_xfer_support = true,
1984 .has_per_pkt_xfer_complete_irq = true,
1985 .clk_divisor_hs_mode = 1,
1986 .clk_divisor_std_mode = 0x16,
1987 .clk_divisor_fast_mode = 0x19,
1988 .clk_divisor_fast_plus_mode = 0x10,
1989 .has_config_load_reg = true,
1990 .has_multi_master_mode = false,
1991 .has_slcg_override_reg = true,
1992 .has_mst_fifo = false,
1993 .has_mst_reset = false,
1994 .quirks = &tegra_i2c_quirks,
1995 .supports_bus_clear = true,
1996 .has_apb_dma = false,
1997 .tlow_std_mode = 0x4,
1998 .thigh_std_mode = 0x3,
1999 .tlow_fast_mode = 0x4,
2000 .thigh_fast_mode = 0x2,
2001 .tlow_fastplus_mode = 0x4,
2002 .thigh_fastplus_mode = 0x2,
2003 .setup_hold_time_std_mode = 0,
2004 .setup_hold_time_fast_mode = 0,
2005 .setup_hold_time_fastplus_mode = 0,
2006 .setup_hold_time_hs_mode = 0,
2007 .has_interface_timing_reg = true,
2008 .enable_hs_mode_support = false,
2009 .has_mutex = false,
2010 .variant = TEGRA_I2C_VARIANT_DEFAULT,
2011 .regs = &tegra20_i2c_regs,
2012 };
2013
2014 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
2015 .has_continue_xfer_support = true,
2016 .has_per_pkt_xfer_complete_irq = true,
2017 .clk_divisor_hs_mode = 1,
2018 .clk_divisor_std_mode = 0x4f,
2019 .clk_divisor_fast_mode = 0x3c,
2020 .clk_divisor_fast_plus_mode = 0x16,
2021 .has_config_load_reg = true,
2022 .has_multi_master_mode = true,
2023 .has_slcg_override_reg = true,
2024 .has_mst_fifo = true,
2025 .has_mst_reset = true,
2026 .quirks = &tegra194_i2c_quirks,
2027 .supports_bus_clear = true,
2028 .has_apb_dma = false,
2029 .tlow_std_mode = 0x8,
2030 .thigh_std_mode = 0x7,
2031 .tlow_fast_mode = 0x2,
2032 .thigh_fast_mode = 0x2,
2033 .tlow_fastplus_mode = 0x2,
2034 .thigh_fastplus_mode = 0x2,
2035 .tlow_hs_mode = 0x8,
2036 .thigh_hs_mode = 0x3,
2037 .setup_hold_time_std_mode = 0x08080808,
2038 .setup_hold_time_fast_mode = 0x02020202,
2039 .setup_hold_time_fastplus_mode = 0x02020202,
2040 .setup_hold_time_hs_mode = 0x090909,
2041 .has_interface_timing_reg = true,
2042 .enable_hs_mode_support = true,
2043 .has_mutex = false,
2044 .variant = TEGRA_I2C_VARIANT_DEFAULT,
2045 .regs = &tegra20_i2c_regs,
2046 };
2047
2048 static const struct tegra_i2c_hw_feature tegra256_i2c_hw = {
2049 .has_continue_xfer_support = true,
2050 .has_per_pkt_xfer_complete_irq = true,
2051 .clk_divisor_hs_mode = 9,
2052 .clk_divisor_std_mode = 0x7a,
2053 .clk_divisor_fast_mode = 0x40,
2054 .clk_divisor_fast_plus_mode = 0x14,
2055 .has_config_load_reg = true,
2056 .has_multi_master_mode = true,
2057 .has_slcg_override_reg = true,
2058 .has_mst_fifo = true,
2059 .has_mst_reset = true,
2060 .quirks = &tegra194_i2c_quirks,
2061 .supports_bus_clear = true,
2062 .has_apb_dma = false,
2063 .tlow_std_mode = 0x8,
2064 .thigh_std_mode = 0x7,
2065 .tlow_fast_mode = 0x4,
2066 .thigh_fast_mode = 0x2,
2067 .tlow_fastplus_mode = 0x4,
2068 .thigh_fastplus_mode = 0x4,
2069 .tlow_hs_mode = 0x3,
2070 .thigh_hs_mode = 0x2,
2071 .setup_hold_time_std_mode = 0x08080808,
2072 .setup_hold_time_fast_mode = 0x04010101,
2073 .setup_hold_time_fastplus_mode = 0x04020202,
2074 .setup_hold_time_hs_mode = 0x030303,
2075 .has_interface_timing_reg = true,
2076 .enable_hs_mode_support = true,
2077 .has_mutex = true,
2078 .variant = TEGRA_I2C_VARIANT_DEFAULT,
2079 .regs = &tegra264_i2c_regs,
2080 };
2081
2082 static const struct tegra_i2c_hw_feature tegra264_i2c_hw = {
2083 .has_continue_xfer_support = true,
2084 .has_per_pkt_xfer_complete_irq = true,
2085 .clk_divisor_hs_mode = 1,
2086 .clk_divisor_std_mode = 0x1d,
2087 .clk_divisor_fast_mode = 0x15,
2088 .clk_divisor_fast_plus_mode = 0x8,
2089 .has_config_load_reg = true,
2090 .has_multi_master_mode = true,
2091 .has_slcg_override_reg = true,
2092 .has_mst_fifo = true,
2093 .has_mst_reset = true,
2094 .quirks = &tegra194_i2c_quirks,
2095 .supports_bus_clear = true,
2096 .has_apb_dma = false,
2097 .tlow_std_mode = 0x8,
2098 .thigh_std_mode = 0x7,
2099 .tlow_fast_mode = 0x2,
2100 .thigh_fast_mode = 0x2,
2101 .tlow_fastplus_mode = 0x2,
2102 .thigh_fastplus_mode = 0x2,
2103 .tlow_hs_mode = 0x4,
2104 .thigh_hs_mode = 0x2,
2105 .setup_hold_time_std_mode = 0x08080808,
2106 .setup_hold_time_fast_mode = 0x02020202,
2107 .setup_hold_time_fastplus_mode = 0x02020202,
2108 .setup_hold_time_hs_mode = 0x090909,
2109 .has_interface_timing_reg = true,
2110 .enable_hs_mode_support = true,
2111 .has_mutex = true,
2112 .variant = TEGRA_I2C_VARIANT_DEFAULT,
2113 .regs = &tegra264_i2c_regs,
2114 };
2115
2116 static const struct tegra_i2c_hw_feature tegra410_i2c_hw = {
2117 .has_continue_xfer_support = true,
2118 .has_per_pkt_xfer_complete_irq = true,
2119 .clk_divisor_hs_mode = 1,
2120 .clk_divisor_std_mode = 0x3f,
2121 .clk_divisor_fast_mode = 0x2c,
2122 .clk_divisor_fast_plus_mode = 0x11,
2123 .has_config_load_reg = true,
2124 .has_multi_master_mode = true,
2125 .has_slcg_override_reg = true,
2126 .has_mst_fifo = true,
2127 .has_mst_reset = true,
2128 .quirks = &tegra194_i2c_quirks,
2129 .supports_bus_clear = true,
2130 .has_apb_dma = false,
2131 .tlow_std_mode = 0x8,
2132 .thigh_std_mode = 0x7,
2133 .tlow_fast_mode = 0x2,
2134 .thigh_fast_mode = 0x2,
2135 .tlow_fastplus_mode = 0x2,
2136 .thigh_fastplus_mode = 0x2,
2137 .tlow_hs_mode = 0x8,
2138 .thigh_hs_mode = 0x6,
2139 .setup_hold_time_std_mode = 0x08080808,
2140 .setup_hold_time_fast_mode = 0x02020202,
2141 .setup_hold_time_fastplus_mode = 0x02020202,
2142 .setup_hold_time_hs_mode = 0x0b0b0b,
2143 .has_interface_timing_reg = true,
2144 .enable_hs_mode_support = true,
2145 .has_mutex = true,
2146 .variant = TEGRA_I2C_VARIANT_DEFAULT,
2147 .regs = &tegra410_i2c_regs,
2148 };
2149
2150 static const struct of_device_id tegra_i2c_of_match[] = {
2151 { .compatible = "nvidia,tegra264-i2c", .data = &tegra264_i2c_hw, },
2152 { .compatible = "nvidia,tegra256-i2c", .data = &tegra256_i2c_hw, },
2153 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
2154 { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
2155 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
2156 { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_vi_i2c_hw, },
2157 #endif
2158 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
2159 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
2160 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
2161 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
2162 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
2163 #if IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)
2164 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_dvc_i2c_hw, },
2165 #endif
2166 {},
2167 };
2168 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
2169
tegra_i2c_parse_dt(struct tegra_i2c_dev * i2c_dev)2170 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
2171 {
2172 bool multi_mode;
2173
2174 i2c_parse_fw_timings(i2c_dev->dev, &i2c_dev->timings, true);
2175
2176 multi_mode = device_property_read_bool(i2c_dev->dev, "multi-master");
2177 i2c_dev->multimaster_mode = multi_mode;
2178 }
2179
tegra_i2c_init_clocks(struct tegra_i2c_dev * i2c_dev)2180 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)
2181 {
2182 int err;
2183
2184 if (ACPI_HANDLE(i2c_dev->dev))
2185 return 0;
2186
2187 i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk";
2188
2189 if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw)
2190 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk";
2191
2192 if (IS_VI(i2c_dev))
2193 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow";
2194
2195 err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks,
2196 i2c_dev->clocks);
2197 if (err)
2198 return err;
2199
2200 err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks);
2201 if (err)
2202 return err;
2203
2204 i2c_dev->div_clk = i2c_dev->clocks[0].clk;
2205
2206 if (!i2c_dev->multimaster_mode)
2207 return 0;
2208
2209 err = clk_enable(i2c_dev->div_clk);
2210 if (err) {
2211 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err);
2212 goto unprepare_clocks;
2213 }
2214
2215 return 0;
2216
2217 unprepare_clocks:
2218 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
2219
2220 return err;
2221 }
2222
tegra_i2c_release_clocks(struct tegra_i2c_dev * i2c_dev)2223 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev)
2224 {
2225 if (i2c_dev->multimaster_mode)
2226 clk_disable(i2c_dev->div_clk);
2227
2228 clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
2229 }
2230
tegra_i2c_init_hardware(struct tegra_i2c_dev * i2c_dev)2231 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev)
2232 {
2233 int ret;
2234
2235 ret = pm_runtime_get_sync(i2c_dev->dev);
2236 if (ret < 0)
2237 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret);
2238 else
2239 ret = tegra_i2c_init(i2c_dev);
2240
2241 pm_runtime_put_sync(i2c_dev->dev);
2242
2243 return ret;
2244 }
2245
tegra_i2c_probe(struct platform_device * pdev)2246 static int tegra_i2c_probe(struct platform_device *pdev)
2247 {
2248 struct tegra_i2c_dev *i2c_dev;
2249 struct resource *res;
2250 int err;
2251
2252 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2253 if (!i2c_dev)
2254 return -ENOMEM;
2255
2256 platform_set_drvdata(pdev, i2c_dev);
2257
2258 init_completion(&i2c_dev->msg_complete);
2259 init_completion(&i2c_dev->dma_complete);
2260
2261 i2c_dev->hw = device_get_match_data(&pdev->dev);
2262 i2c_dev->cont_id = pdev->id;
2263 i2c_dev->dev = &pdev->dev;
2264
2265 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2266 if (IS_ERR(i2c_dev->base))
2267 return PTR_ERR(i2c_dev->base);
2268
2269 i2c_dev->base_phys = res->start;
2270
2271 err = platform_get_irq(pdev, 0);
2272 if (err < 0)
2273 return err;
2274
2275 i2c_dev->irq = err;
2276
2277 /* interrupt will be enabled during of transfer time */
2278 irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
2279
2280 err = devm_request_threaded_irq(i2c_dev->dev, i2c_dev->irq,
2281 NULL, tegra_i2c_isr,
2282 IRQF_NO_SUSPEND | IRQF_ONESHOT,
2283 dev_name(i2c_dev->dev), i2c_dev);
2284 if (err)
2285 return err;
2286
2287 tegra_i2c_parse_dt(i2c_dev);
2288
2289 err = tegra_i2c_init_clocks(i2c_dev);
2290 if (err)
2291 return err;
2292
2293 err = tegra_i2c_init_dma(i2c_dev);
2294 if (err)
2295 goto release_clocks;
2296
2297 /*
2298 * VI I2C is in VE power domain which is not always ON and not
2299 * IRQ-safe. Thus, IRQ-safe device shouldn't be attached to a
2300 * non IRQ-safe domain because this prevents powering off the power
2301 * domain.
2302 *
2303 * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't
2304 * be used for atomic transfers. ACPI device is not IRQ safe also.
2305 *
2306 * Devices with pinctrl states cannot be marked IRQ-safe as the pinctrl
2307 * state transitions during runtime PM require mutexes.
2308 */
2309 if (!IS_VI(i2c_dev) && !has_acpi_companion(i2c_dev->dev) && !i2c_dev->dev->pins)
2310 pm_runtime_irq_safe(i2c_dev->dev);
2311
2312 pm_runtime_enable(i2c_dev->dev);
2313
2314 err = tegra_i2c_init_hardware(i2c_dev);
2315 if (err)
2316 goto release_rpm;
2317
2318 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
2319 i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node;
2320 i2c_dev->adapter.dev.parent = i2c_dev->dev;
2321 i2c_dev->adapter.retries = 1;
2322 i2c_dev->adapter.timeout = 6 * HZ;
2323 i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
2324 i2c_dev->adapter.owner = THIS_MODULE;
2325 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
2326 i2c_dev->adapter.algo = &tegra_i2c_algo;
2327 i2c_dev->adapter.nr = pdev->id;
2328 ACPI_COMPANION_SET(&i2c_dev->adapter.dev, ACPI_COMPANION(&pdev->dev));
2329
2330 if (i2c_dev->hw->supports_bus_clear)
2331 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
2332
2333 strscpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
2334 sizeof(i2c_dev->adapter.name));
2335
2336 err = i2c_add_numbered_adapter(&i2c_dev->adapter);
2337 if (err)
2338 goto release_rpm;
2339
2340 return 0;
2341
2342 release_rpm:
2343 pm_runtime_disable(i2c_dev->dev);
2344
2345 tegra_i2c_release_dma(i2c_dev);
2346 release_clocks:
2347 tegra_i2c_release_clocks(i2c_dev);
2348
2349 return err;
2350 }
2351
tegra_i2c_remove(struct platform_device * pdev)2352 static void tegra_i2c_remove(struct platform_device *pdev)
2353 {
2354 struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2355
2356 i2c_del_adapter(&i2c_dev->adapter);
2357 pm_runtime_force_suspend(i2c_dev->dev);
2358
2359 tegra_i2c_release_dma(i2c_dev);
2360 tegra_i2c_release_clocks(i2c_dev);
2361 }
2362
tegra_i2c_runtime_resume(struct device * dev)2363 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
2364 {
2365 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2366 int err;
2367
2368 err = pinctrl_pm_select_default_state(dev);
2369 if (err)
2370 return err;
2371
2372 err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks);
2373 if (err)
2374 return err;
2375
2376 /*
2377 * VI I2C device is attached to VE power domain which goes through
2378 * power ON/OFF during runtime PM resume/suspend, meaning that
2379 * controller needs to be re-initialized after power ON.
2380 */
2381 if (IS_VI(i2c_dev)) {
2382 err = tegra_i2c_init(i2c_dev);
2383 if (err)
2384 goto disable_clocks;
2385 }
2386
2387 return 0;
2388
2389 disable_clocks:
2390 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
2391
2392 return err;
2393 }
2394
tegra_i2c_runtime_suspend(struct device * dev)2395 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)
2396 {
2397 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2398
2399 clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
2400
2401 return pinctrl_pm_select_idle_state(dev);
2402 }
2403
tegra_i2c_suspend(struct device * dev)2404 static int __maybe_unused tegra_i2c_suspend(struct device *dev)
2405 {
2406 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2407 int err;
2408
2409 i2c_mark_adapter_suspended(&i2c_dev->adapter);
2410
2411 if (!pm_runtime_status_suspended(dev)) {
2412 err = tegra_i2c_runtime_suspend(dev);
2413 if (err)
2414 return err;
2415 }
2416
2417 return 0;
2418 }
2419
tegra_i2c_resume(struct device * dev)2420 static int __maybe_unused tegra_i2c_resume(struct device *dev)
2421 {
2422 struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2423 int err;
2424
2425 /*
2426 * We need to ensure that clocks are enabled so that registers can be
2427 * restored in tegra_i2c_init().
2428 */
2429 err = tegra_i2c_runtime_resume(dev);
2430 if (err)
2431 return err;
2432
2433 err = tegra_i2c_init(i2c_dev);
2434 if (err)
2435 return err;
2436
2437 /*
2438 * In case we are runtime suspended, disable clocks again so that we
2439 * don't unbalance the clock reference counts during the next runtime
2440 * resume transition.
2441 */
2442 if (pm_runtime_status_suspended(dev)) {
2443 err = tegra_i2c_runtime_suspend(dev);
2444 if (err)
2445 return err;
2446 }
2447
2448 i2c_mark_adapter_resumed(&i2c_dev->adapter);
2449
2450 return 0;
2451 }
2452
2453 static const struct dev_pm_ops tegra_i2c_pm = {
2454 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
2455 SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
2456 NULL)
2457 };
2458
2459 static const struct acpi_device_id tegra_i2c_acpi_match[] = {
2460 {.id = "NVDA0101", .driver_data = (kernel_ulong_t)&tegra210_i2c_hw},
2461 {.id = "NVDA0201", .driver_data = (kernel_ulong_t)&tegra186_i2c_hw},
2462 {.id = "NVDA0301", .driver_data = (kernel_ulong_t)&tegra194_i2c_hw},
2463 {.id = "NVDA2017", .driver_data = (kernel_ulong_t)&tegra410_i2c_hw},
2464 { }
2465 };
2466 MODULE_DEVICE_TABLE(acpi, tegra_i2c_acpi_match);
2467
2468 static struct platform_driver tegra_i2c_driver = {
2469 .probe = tegra_i2c_probe,
2470 .remove = tegra_i2c_remove,
2471 .driver = {
2472 .name = "tegra-i2c",
2473 .of_match_table = tegra_i2c_of_match,
2474 .acpi_match_table = tegra_i2c_acpi_match,
2475 .pm = &tegra_i2c_pm,
2476 },
2477 };
2478 module_platform_driver(tegra_i2c_driver);
2479
2480 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver");
2481 MODULE_AUTHOR("Colin Cross");
2482 MODULE_LICENSE("GPL v2");
2483