1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra20-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra20-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/soc/tegra-pmc.h> 8 9#include "tegra20-peripherals-opp.dtsi" 10 11/ { 12 compatible = "nvidia,tegra20"; 13 interrupt-parent = <&lic>; 14 #address-cells = <1>; 15 #size-cells = <1>; 16 17 memory@0 { 18 device_type = "memory"; 19 reg = <0 0>; 20 }; 21 22 sram@40000000 { 23 compatible = "mmio-sram"; 24 reg = <0x40000000 0x40000>; 25 #address-cells = <1>; 26 #size-cells = <1>; 27 ranges = <0 0x40000000 0x40000>; 28 29 vde_pool: sram@400 { 30 reg = <0x400 0x3fc00>; 31 pool; 32 }; 33 }; 34 35 host1x@50000000 { 36 compatible = "nvidia,tegra20-host1x"; 37 reg = <0x50000000 0x00024000>; 38 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 39 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 40 interrupt-names = "syncpt", "host1x"; 41 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 42 clock-names = "host1x"; 43 resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>; 44 reset-names = "host1x", "mc"; 45 power-domains = <&pd_core>; 46 operating-points-v2 = <&host1x_dvfs_opp_table>; 47 48 #address-cells = <1>; 49 #size-cells = <1>; 50 51 ranges = <0x54000000 0x54000000 0x04000000>; 52 53 mpe@54040000 { 54 compatible = "nvidia,tegra20-mpe"; 55 reg = <0x54040000 0x00040000>; 56 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 57 clocks = <&tegra_car TEGRA20_CLK_MPE>; 58 resets = <&tegra_car 60>; 59 reset-names = "mpe"; 60 power-domains = <&pd_mpe>; 61 operating-points-v2 = <&mpe_dvfs_opp_table>; 62 status = "disabled"; 63 }; 64 65 vi@54080000 { 66 compatible = "nvidia,tegra20-vi"; 67 reg = <0x54080000 0x00000800>; 68 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 69 clocks = <&tegra_car TEGRA20_CLK_VI>; 70 resets = <&tegra_car 20>; 71 reset-names = "vi"; 72 power-domains = <&pd_venc>; 73 operating-points-v2 = <&vi_dvfs_opp_table>; 74 status = "disabled"; 75 76 #address-cells = <1>; 77 #size-cells = <1>; 78 79 ranges = <0x0 0x54080000 0x4000>; 80 81 csi: csi@800 { 82 compatible = "nvidia,tegra20-csi"; 83 reg = <0x800 0x200>; 84 clocks = <&tegra_car TEGRA20_CLK_CSI>; 85 power-domains = <&pd_venc>; 86 #nvidia,mipi-calibrate-cells = <1>; 87 status = "disabled"; 88 89 #address-cells = <1>; 90 #size-cells = <0>; 91 }; 92 }; 93 94 epp@540c0000 { 95 compatible = "nvidia,tegra20-epp"; 96 reg = <0x540c0000 0x00040000>; 97 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 98 clocks = <&tegra_car TEGRA20_CLK_EPP>; 99 resets = <&tegra_car 19>; 100 reset-names = "epp"; 101 power-domains = <&pd_core>; 102 operating-points-v2 = <&epp_dvfs_opp_table>; 103 status = "disabled"; 104 }; 105 106 isp@54100000 { 107 compatible = "nvidia,tegra20-isp"; 108 reg = <0x54100000 0x00040000>; 109 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&tegra_car TEGRA20_CLK_ISP>; 111 resets = <&tegra_car 23>; 112 reset-names = "isp"; 113 power-domains = <&pd_venc>; 114 status = "disabled"; 115 }; 116 117 gr2d@54140000 { 118 compatible = "nvidia,tegra20-gr2d"; 119 reg = <0x54140000 0x00040000>; 120 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 122 resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>; 123 reset-names = "2d", "mc"; 124 power-domains = <&pd_core>; 125 operating-points-v2 = <&gr2d_dvfs_opp_table>; 126 }; 127 128 gr3d@54180000 { 129 compatible = "nvidia,tegra20-gr3d"; 130 reg = <0x54180000 0x00040000>; 131 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 132 resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>; 133 reset-names = "3d", "mc"; 134 power-domains = <&pd_3d>; 135 operating-points-v2 = <&gr3d_dvfs_opp_table>; 136 }; 137 138 dc@54200000 { 139 compatible = "nvidia,tegra20-dc"; 140 reg = <0x54200000 0x00040000>; 141 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 142 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 143 <&tegra_car TEGRA20_CLK_PLL_P>; 144 clock-names = "dc", "parent"; 145 resets = <&tegra_car 27>; 146 reset-names = "dc"; 147 power-domains = <&pd_core>; 148 operating-points-v2 = <&disp1_dvfs_opp_table>; 149 150 nvidia,head = <0>; 151 152 interconnects = <&mc TEGRA20_MC_DISPLAY0A &emc>, 153 <&mc TEGRA20_MC_DISPLAY0B &emc>, 154 <&mc TEGRA20_MC_DISPLAY1B &emc>, 155 <&mc TEGRA20_MC_DISPLAY0C &emc>, 156 <&mc TEGRA20_MC_DISPLAYHC &emc>; 157 interconnect-names = "wina", 158 "winb", 159 "winb-vfilter", 160 "winc", 161 "cursor"; 162 163 rgb { 164 status = "disabled"; 165 }; 166 }; 167 168 dc@54240000 { 169 compatible = "nvidia,tegra20-dc"; 170 reg = <0x54240000 0x00040000>; 171 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 172 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 173 <&tegra_car TEGRA20_CLK_PLL_P>; 174 clock-names = "dc", "parent"; 175 resets = <&tegra_car 26>; 176 reset-names = "dc"; 177 power-domains = <&pd_core>; 178 operating-points-v2 = <&disp2_dvfs_opp_table>; 179 180 nvidia,head = <1>; 181 182 interconnects = <&mc TEGRA20_MC_DISPLAY0AB &emc>, 183 <&mc TEGRA20_MC_DISPLAY0BB &emc>, 184 <&mc TEGRA20_MC_DISPLAY1BB &emc>, 185 <&mc TEGRA20_MC_DISPLAY0CB &emc>, 186 <&mc TEGRA20_MC_DISPLAYHCB &emc>; 187 interconnect-names = "wina", 188 "winb", 189 "winb-vfilter", 190 "winc", 191 "cursor"; 192 193 rgb { 194 status = "disabled"; 195 }; 196 }; 197 198 tegra_hdmi: hdmi@54280000 { 199 compatible = "nvidia,tegra20-hdmi"; 200 reg = <0x54280000 0x00040000>; 201 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 203 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 204 clock-names = "hdmi", "parent"; 205 resets = <&tegra_car 51>; 206 reset-names = "hdmi"; 207 power-domains = <&pd_core>; 208 operating-points-v2 = <&hdmi_dvfs_opp_table>; 209 #sound-dai-cells = <0>; 210 status = "disabled"; 211 }; 212 213 tvo@542c0000 { 214 compatible = "nvidia,tegra20-tvo"; 215 reg = <0x542c0000 0x00040000>; 216 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 217 clocks = <&tegra_car TEGRA20_CLK_TVO>; 218 power-domains = <&pd_core>; 219 operating-points-v2 = <&tvo_dvfs_opp_table>; 220 status = "disabled"; 221 }; 222 223 dsi@54300000 { 224 compatible = "nvidia,tegra20-dsi"; 225 reg = <0x54300000 0x00040000>; 226 clocks = <&tegra_car TEGRA20_CLK_DSI>, 227 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 228 clock-names = "dsi", "parent"; 229 resets = <&tegra_car 48>; 230 reset-names = "dsi"; 231 power-domains = <&pd_core>; 232 operating-points-v2 = <&dsi_dvfs_opp_table>; 233 status = "disabled"; 234 }; 235 }; 236 237 timer@50040600 { 238 compatible = "arm,cortex-a9-twd-timer"; 239 interrupt-parent = <&intc>; 240 reg = <0x50040600 0x20>; 241 interrupts = <GIC_PPI 13 242 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; 243 clocks = <&tegra_car TEGRA20_CLK_TWD>; 244 }; 245 246 intc: interrupt-controller@50041000 { 247 compatible = "arm,cortex-a9-gic"; 248 reg = <0x50041000 0x1000>, 249 <0x50040100 0x0100>; 250 interrupt-controller; 251 #interrupt-cells = <3>; 252 interrupt-parent = <&intc>; 253 }; 254 255 cache-controller@50043000 { 256 compatible = "arm,pl310-cache"; 257 reg = <0x50043000 0x1000>; 258 arm,data-latency = <5 5 2>; 259 arm,tag-latency = <4 4 2>; 260 cache-unified; 261 cache-level = <2>; 262 }; 263 264 lic: interrupt-controller@60004000 { 265 compatible = "nvidia,tegra20-ictlr"; 266 reg = <0x60004000 0x100>, 267 <0x60004100 0x50>, 268 <0x60004200 0x50>, 269 <0x60004300 0x50>; 270 interrupt-controller; 271 #interrupt-cells = <3>; 272 interrupt-parent = <&intc>; 273 }; 274 275 timer@60005000 { 276 compatible = "nvidia,tegra20-timer"; 277 reg = <0x60005000 0x60>; 278 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&tegra_car TEGRA20_CLK_TIMER>; 283 }; 284 285 tegra_car: clock@60006000 { 286 compatible = "nvidia,tegra20-car"; 287 reg = <0x60006000 0x1000>; 288 #clock-cells = <1>; 289 #reset-cells = <1>; 290 291 sclk { 292 compatible = "nvidia,tegra20-sclk"; 293 clocks = <&tegra_car TEGRA20_CLK_SCLK>; 294 power-domains = <&pd_core>; 295 operating-points-v2 = <&sclk_dvfs_opp_table>; 296 }; 297 }; 298 299 flow-controller@60007000 { 300 compatible = "nvidia,tegra20-flowctrl"; 301 reg = <0x60007000 0x1000>; 302 }; 303 304 apbdma: dma-controller@6000a000 { 305 compatible = "nvidia,tegra20-apbdma"; 306 reg = <0x6000a000 0x1200>; 307 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 310 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 311 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 314 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 315 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 316 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 322 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&tegra_car TEGRA20_CLK_APBDMA>; 324 resets = <&tegra_car 34>; 325 reset-names = "dma"; 326 #dma-cells = <1>; 327 }; 328 329 ahb@6000c000 { 330 compatible = "nvidia,tegra20-ahb"; 331 reg = <0x6000c000 0x110>; /* AHB Arbitration + Gizmo Controller */ 332 }; 333 334 gpio: gpio@6000d000 { 335 compatible = "nvidia,tegra20-gpio"; 336 reg = <0x6000d000 0x1000>; 337 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 338 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 339 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 340 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 341 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 344 #gpio-cells = <2>; 345 gpio-controller; 346 #interrupt-cells = <2>; 347 interrupt-controller; 348 gpio-ranges = <&pinmux 0 0 224>; 349 }; 350 351 vde@6001a000 { 352 compatible = "nvidia,tegra20-vde"; 353 reg = <0x6001a000 0x1000>, /* Syntax Engine */ 354 <0x6001b000 0x1000>, /* Video Bitstream Engine */ 355 <0x6001c000 0x100>, /* Macroblock Engine */ 356 <0x6001c200 0x100>, /* Post-processing Engine */ 357 <0x6001c400 0x100>, /* Motion Compensation Engine */ 358 <0x6001c600 0x100>, /* Transform Engine */ 359 <0x6001c800 0x100>, /* Pixel prediction block */ 360 <0x6001ca00 0x100>, /* Video DMA */ 361 <0x6001d800 0x300>; /* Video frame controls */ 362 reg-names = "sxe", "bsev", "mbe", "ppe", "mce", 363 "tfe", "ppb", "vdma", "frameid"; 364 iram = <&vde_pool>; /* IRAM region */ 365 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */ 366 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */ 367 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */ 368 interrupt-names = "sync-token", "bsev", "sxe"; 369 clocks = <&tegra_car TEGRA20_CLK_VDE>; 370 reset-names = "vde", "mc"; 371 resets = <&tegra_car 61>, <&mc TEGRA20_MC_RESET_VDE>; 372 power-domains = <&pd_vde>; 373 operating-points-v2 = <&vde_dvfs_opp_table>; 374 }; 375 376 pinmux: pinmux@70000014 { 377 compatible = "nvidia,tegra20-pinmux"; 378 reg = <0x70000014 0x10>, /* Tri-state registers */ 379 <0x70000080 0x20>, /* Mux registers */ 380 <0x700000a0 0x14>, /* Pull-up/down registers */ 381 <0x70000868 0xa8>; /* Pad control registers */ 382 }; 383 384 apbmisc@70000800 { 385 compatible = "nvidia,tegra20-apbmisc"; 386 reg = <0x70000800 0x64>, /* Chip revision */ 387 <0x70000008 0x04>; /* Strapping options */ 388 }; 389 390 das@70000c00 { 391 compatible = "nvidia,tegra20-das"; 392 reg = <0x70000c00 0x80>; 393 }; 394 395 tegra_ac97: ac97@70002000 { 396 compatible = "nvidia,tegra20-ac97"; 397 reg = <0x70002000 0x200>; 398 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&tegra_car TEGRA20_CLK_AC97>; 400 resets = <&tegra_car 3>; 401 reset-names = "ac97"; 402 dmas = <&apbdma 12>, <&apbdma 12>; 403 dma-names = "rx", "tx"; 404 status = "disabled"; 405 }; 406 407 tegra_spdif: spdif@70002400 { 408 compatible = "nvidia,tegra20-spdif"; 409 reg = <0x70002400 0x200>; 410 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 411 clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>, 412 <&tegra_car TEGRA20_CLK_SPDIF_IN>; 413 clock-names = "out", "in"; 414 resets = <&tegra_car 10>; 415 dmas = <&apbdma 3>, <&apbdma 3>; 416 dma-names = "rx", "tx"; 417 #sound-dai-cells = <0>; 418 status = "disabled"; 419 420 assigned-clocks = <&tegra_car TEGRA20_CLK_SPDIF_OUT>; 421 assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_A_OUT0>; 422 }; 423 424 tegra_i2s1: i2s@70002800 { 425 compatible = "nvidia,tegra20-i2s"; 426 reg = <0x70002800 0x200>; 427 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&tegra_car TEGRA20_CLK_I2S1>; 429 resets = <&tegra_car 11>; 430 reset-names = "i2s"; 431 dmas = <&apbdma 2>, <&apbdma 2>; 432 dma-names = "rx", "tx"; 433 status = "disabled"; 434 }; 435 436 tegra_i2s2: i2s@70002a00 { 437 compatible = "nvidia,tegra20-i2s"; 438 reg = <0x70002a00 0x200>; 439 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 440 clocks = <&tegra_car TEGRA20_CLK_I2S2>; 441 resets = <&tegra_car 18>; 442 reset-names = "i2s"; 443 dmas = <&apbdma 1>, <&apbdma 1>; 444 dma-names = "rx", "tx"; 445 status = "disabled"; 446 }; 447 448 /* 449 * There are two serial driver i.e. 8250 based simple serial 450 * driver and APB DMA based serial driver for higher baudrate 451 * and performace. To enable the 8250 based driver, the compatible 452 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial 453 * driver, the compatible is "nvidia,tegra20-hsuart". 454 */ 455 uarta: serial@70006000 { 456 compatible = "nvidia,tegra20-uart"; 457 reg = <0x70006000 0x40>; 458 reg-shift = <2>; 459 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&tegra_car TEGRA20_CLK_UARTA>; 461 resets = <&tegra_car 6>; 462 dmas = <&apbdma 8>, <&apbdma 8>; 463 dma-names = "rx", "tx"; 464 status = "disabled"; 465 }; 466 467 uartb: serial@70006040 { 468 compatible = "nvidia,tegra20-uart"; 469 reg = <0x70006040 0x40>; 470 reg-shift = <2>; 471 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&tegra_car TEGRA20_CLK_UARTB>; 473 resets = <&tegra_car 7>; 474 dmas = <&apbdma 9>, <&apbdma 9>; 475 dma-names = "rx", "tx"; 476 status = "disabled"; 477 }; 478 479 uartc: serial@70006200 { 480 compatible = "nvidia,tegra20-uart"; 481 reg = <0x70006200 0x100>; 482 reg-shift = <2>; 483 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&tegra_car TEGRA20_CLK_UARTC>; 485 resets = <&tegra_car 55>; 486 dmas = <&apbdma 10>, <&apbdma 10>; 487 dma-names = "rx", "tx"; 488 status = "disabled"; 489 }; 490 491 uartd: serial@70006300 { 492 compatible = "nvidia,tegra20-uart"; 493 reg = <0x70006300 0x100>; 494 reg-shift = <2>; 495 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&tegra_car TEGRA20_CLK_UARTD>; 497 resets = <&tegra_car 65>; 498 dmas = <&apbdma 19>, <&apbdma 19>; 499 dma-names = "rx", "tx"; 500 status = "disabled"; 501 }; 502 503 uarte: serial@70006400 { 504 compatible = "nvidia,tegra20-uart"; 505 reg = <0x70006400 0x100>; 506 reg-shift = <2>; 507 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 508 clocks = <&tegra_car TEGRA20_CLK_UARTE>; 509 resets = <&tegra_car 66>; 510 dmas = <&apbdma 20>, <&apbdma 20>; 511 dma-names = "rx", "tx"; 512 status = "disabled"; 513 }; 514 515 nand-controller@70008000 { 516 compatible = "nvidia,tegra20-nand"; 517 reg = <0x70008000 0x100>; 518 #address-cells = <1>; 519 #size-cells = <0>; 520 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; 522 clock-names = "nand"; 523 resets = <&tegra_car 13>; 524 reset-names = "nand"; 525 assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; 526 assigned-clock-rates = <150000000>; 527 power-domains = <&pd_core>; 528 operating-points-v2 = <&ndflash_dvfs_opp_table>; 529 status = "disabled"; 530 }; 531 532 gmi@70009000 { 533 compatible = "nvidia,tegra20-gmi"; 534 reg = <0x70009000 0x1000>; 535 #address-cells = <2>; 536 #size-cells = <1>; 537 ranges = <0 0 0xd0000000 0xfffffff>; 538 clocks = <&tegra_car TEGRA20_CLK_NOR>; 539 clock-names = "gmi"; 540 resets = <&tegra_car 42>; 541 reset-names = "gmi"; 542 power-domains = <&pd_core>; 543 operating-points-v2 = <&nor_dvfs_opp_table>; 544 status = "disabled"; 545 }; 546 547 pwm: pwm@7000a000 { 548 compatible = "nvidia,tegra20-pwm"; 549 reg = <0x7000a000 0x100>; 550 #pwm-cells = <2>; 551 clocks = <&tegra_car TEGRA20_CLK_PWM>; 552 resets = <&tegra_car 17>; 553 reset-names = "pwm"; 554 status = "disabled"; 555 }; 556 557 i2c@7000c000 { 558 compatible = "nvidia,tegra20-i2c"; 559 reg = <0x7000c000 0x100>; 560 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 clocks = <&tegra_car TEGRA20_CLK_I2C1>, 564 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 565 clock-names = "div-clk", "fast-clk"; 566 resets = <&tegra_car 12>; 567 reset-names = "i2c"; 568 dmas = <&apbdma 21>, <&apbdma 21>; 569 dma-names = "rx", "tx"; 570 status = "disabled"; 571 }; 572 573 spi@7000c380 { 574 compatible = "nvidia,tegra20-sflash"; 575 reg = <0x7000c380 0x80>; 576 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 clocks = <&tegra_car TEGRA20_CLK_SPI>; 580 resets = <&tegra_car 43>; 581 reset-names = "spi"; 582 dmas = <&apbdma 11>, <&apbdma 11>; 583 dma-names = "rx", "tx"; 584 status = "disabled"; 585 }; 586 587 i2c2: i2c@7000c400 { 588 compatible = "nvidia,tegra20-i2c"; 589 reg = <0x7000c400 0x100>; 590 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 clocks = <&tegra_car TEGRA20_CLK_I2C2>, 594 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 595 clock-names = "div-clk", "fast-clk"; 596 resets = <&tegra_car 54>; 597 reset-names = "i2c"; 598 dmas = <&apbdma 22>, <&apbdma 22>; 599 dma-names = "rx", "tx"; 600 status = "disabled"; 601 }; 602 603 i2c@7000c500 { 604 compatible = "nvidia,tegra20-i2c"; 605 reg = <0x7000c500 0x100>; 606 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 607 #address-cells = <1>; 608 #size-cells = <0>; 609 clocks = <&tegra_car TEGRA20_CLK_I2C3>, 610 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 611 clock-names = "div-clk", "fast-clk"; 612 resets = <&tegra_car 67>; 613 reset-names = "i2c"; 614 dmas = <&apbdma 23>, <&apbdma 23>; 615 dma-names = "rx", "tx"; 616 status = "disabled"; 617 }; 618 619 i2c@7000d000 { 620 compatible = "nvidia,tegra20-i2c-dvc"; 621 reg = <0x7000d000 0x200>; 622 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 clocks = <&tegra_car TEGRA20_CLK_DVC>, 626 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>; 627 clock-names = "div-clk", "fast-clk"; 628 resets = <&tegra_car 47>; 629 reset-names = "i2c"; 630 dmas = <&apbdma 24>, <&apbdma 24>; 631 dma-names = "rx", "tx"; 632 status = "disabled"; 633 }; 634 635 spi@7000d400 { 636 compatible = "nvidia,tegra20-slink"; 637 reg = <0x7000d400 0x200>; 638 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 639 #address-cells = <1>; 640 #size-cells = <0>; 641 clocks = <&tegra_car TEGRA20_CLK_SBC1>; 642 resets = <&tegra_car 41>; 643 reset-names = "spi"; 644 dmas = <&apbdma 15>, <&apbdma 15>; 645 dma-names = "rx", "tx"; 646 status = "disabled"; 647 }; 648 649 spi@7000d600 { 650 compatible = "nvidia,tegra20-slink"; 651 reg = <0x7000d600 0x200>; 652 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 clocks = <&tegra_car TEGRA20_CLK_SBC2>; 656 resets = <&tegra_car 44>; 657 reset-names = "spi"; 658 dmas = <&apbdma 16>, <&apbdma 16>; 659 dma-names = "rx", "tx"; 660 status = "disabled"; 661 }; 662 663 spi@7000d800 { 664 compatible = "nvidia,tegra20-slink"; 665 reg = <0x7000d800 0x200>; 666 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 667 #address-cells = <1>; 668 #size-cells = <0>; 669 clocks = <&tegra_car TEGRA20_CLK_SBC3>; 670 resets = <&tegra_car 46>; 671 reset-names = "spi"; 672 dmas = <&apbdma 17>, <&apbdma 17>; 673 dma-names = "rx", "tx"; 674 status = "disabled"; 675 }; 676 677 spi@7000da00 { 678 compatible = "nvidia,tegra20-slink"; 679 reg = <0x7000da00 0x200>; 680 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 clocks = <&tegra_car TEGRA20_CLK_SBC4>; 684 resets = <&tegra_car 68>; 685 reset-names = "spi"; 686 dmas = <&apbdma 18>, <&apbdma 18>; 687 dma-names = "rx", "tx"; 688 status = "disabled"; 689 }; 690 691 rtc@7000e000 { 692 compatible = "nvidia,tegra20-rtc"; 693 reg = <0x7000e000 0x100>; 694 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&tegra_car TEGRA20_CLK_RTC>; 696 }; 697 698 kbc@7000e200 { 699 compatible = "nvidia,tegra20-kbc"; 700 reg = <0x7000e200 0x100>; 701 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&tegra_car TEGRA20_CLK_KBC>; 703 resets = <&tegra_car 36>; 704 reset-names = "kbc"; 705 status = "disabled"; 706 }; 707 708 tegra_pmc: pmc@7000e400 { 709 compatible = "nvidia,tegra20-pmc"; 710 reg = <0x7000e400 0x400>; 711 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>; 712 clock-names = "pclk", "clk32k_in"; 713 #clock-cells = <1>; 714 715 pd_core: core-domain { 716 #power-domain-cells = <0>; 717 operating-points-v2 = <&core_opp_table>; 718 }; 719 720 powergates { 721 pd_mpe: mpe { 722 clocks = <&tegra_car TEGRA20_CLK_MPE>; 723 resets = <&mc TEGRA20_MC_RESET_MPEA>, 724 <&mc TEGRA20_MC_RESET_MPEB>, 725 <&mc TEGRA20_MC_RESET_MPEC>, 726 <&tegra_car TEGRA20_CLK_MPE>; 727 power-domains = <&pd_core>; 728 #power-domain-cells = <0>; 729 }; 730 731 pd_3d: td { 732 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 733 resets = <&mc TEGRA20_MC_RESET_3D>, 734 <&tegra_car TEGRA20_CLK_GR3D>; 735 power-domains = <&pd_core>; 736 #power-domain-cells = <0>; 737 }; 738 739 pd_vde: vdec { 740 clocks = <&tegra_car TEGRA20_CLK_VDE>; 741 resets = <&mc TEGRA20_MC_RESET_VDE>, 742 <&tegra_car TEGRA20_CLK_VDE>; 743 power-domains = <&pd_core>; 744 #power-domain-cells = <0>; 745 }; 746 747 pd_venc: venc { 748 clocks = <&tegra_car TEGRA20_CLK_ISP>, 749 <&tegra_car TEGRA20_CLK_VI>, 750 <&tegra_car TEGRA20_CLK_CSI>; 751 resets = <&mc TEGRA20_MC_RESET_ISP>, 752 <&mc TEGRA20_MC_RESET_VI>, 753 <&tegra_car TEGRA20_CLK_ISP>, 754 <&tegra_car 20 /* VI */>, 755 <&tegra_car TEGRA20_CLK_CSI>; 756 power-domains = <&pd_core>; 757 #power-domain-cells = <0>; 758 }; 759 }; 760 }; 761 762 mc: memory-controller@7000f000 { 763 compatible = "nvidia,tegra20-mc-gart"; 764 reg = <0x7000f000 0x00000400>, /* controller registers */ 765 <0x58000000 0x02000000>; /* GART aperture */ 766 clocks = <&tegra_car TEGRA20_CLK_MC>; 767 clock-names = "mc"; 768 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 769 #reset-cells = <1>; 770 #iommu-cells = <0>; 771 #interconnect-cells = <1>; 772 }; 773 774 emc: memory-controller@7000f400 { 775 compatible = "nvidia,tegra20-emc"; 776 reg = <0x7000f400 0x400>; 777 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 778 clocks = <&tegra_car TEGRA20_CLK_EMC>; 779 power-domains = <&pd_core>; 780 #address-cells = <1>; 781 #size-cells = <0>; 782 #interconnect-cells = <0>; 783 784 nvidia,memory-controller = <&mc>; 785 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 786 }; 787 788 fuse@7000f800 { 789 compatible = "nvidia,tegra20-efuse"; 790 reg = <0x7000f800 0x400>; 791 clocks = <&tegra_car TEGRA20_CLK_FUSE>; 792 clock-names = "fuse"; 793 resets = <&tegra_car 39>; 794 reset-names = "fuse"; 795 }; 796 797 pcie@80003000 { 798 compatible = "nvidia,tegra20-pcie"; 799 device_type = "pci"; 800 reg = <0x80003000 0x00000800>, /* PADS registers */ 801 <0x80003800 0x00000200>, /* AFI registers */ 802 <0x90000000 0x10000000>; /* configuration space */ 803 reg-names = "pads", "afi", "cs"; 804 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 805 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 806 interrupt-names = "intr", "msi"; 807 808 #interrupt-cells = <1>; 809 interrupt-map-mask = <0 0 0 0>; 810 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 811 812 bus-range = <0x00 0xff>; 813 #address-cells = <3>; 814 #size-cells = <2>; 815 816 ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */ 817 <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */ 818 <0x01000000 0 0 0x82000000 0 0x00010000>, /* downstream I/O */ 819 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */ 820 <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */ 821 822 clocks = <&tegra_car TEGRA20_CLK_PEX>, 823 <&tegra_car TEGRA20_CLK_AFI>, 824 <&tegra_car TEGRA20_CLK_PLL_E>; 825 clock-names = "pex", "afi", "pll_e"; 826 resets = <&tegra_car 70>, 827 <&tegra_car 72>, 828 <&tegra_car 74>; 829 reset-names = "pex", "afi", "pcie_x"; 830 power-domains = <&pd_core>; 831 operating-points-v2 = <&pcie_dvfs_opp_table>; 832 833 status = "disabled"; 834 835 pci@1,0 { 836 device_type = "pci"; 837 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>; 838 reg = <0x000800 0 0 0 0>; 839 bus-range = <0x00 0xff>; 840 status = "disabled"; 841 842 #address-cells = <3>; 843 #size-cells = <2>; 844 ranges; 845 846 nvidia,num-lanes = <2>; 847 }; 848 849 pci@2,0 { 850 device_type = "pci"; 851 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>; 852 reg = <0x001000 0 0 0 0>; 853 bus-range = <0x00 0xff>; 854 status = "disabled"; 855 856 #address-cells = <3>; 857 #size-cells = <2>; 858 ranges; 859 860 nvidia,num-lanes = <2>; 861 }; 862 }; 863 864 usb@c5000000 { 865 compatible = "nvidia,tegra20-ehci"; 866 reg = <0xc5000000 0x4000>; 867 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 868 phy_type = "utmi"; 869 clocks = <&tegra_car TEGRA20_CLK_USBD>; 870 resets = <&tegra_car 22>; 871 reset-names = "usb"; 872 nvidia,needs-double-reset; 873 nvidia,phy = <&phy1>; 874 power-domains = <&pd_core>; 875 operating-points-v2 = <&usbd_dvfs_opp_table>; 876 status = "disabled"; 877 }; 878 879 phy1: usb-phy@c5000000 { 880 compatible = "nvidia,tegra20-usb-phy"; 881 reg = <0xc5000000 0x4000>, 882 <0xc5000000 0x4000>; 883 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 884 phy_type = "utmi"; 885 clocks = <&tegra_car TEGRA20_CLK_USBD>, 886 <&tegra_car TEGRA20_CLK_PLL_U>, 887 <&tegra_car TEGRA20_CLK_CLK_M>, 888 <&tegra_car TEGRA20_CLK_USBD>; 889 clock-names = "reg", "pll_u", "timer", "utmi-pads"; 890 resets = <&tegra_car 22>, <&tegra_car 22>; 891 reset-names = "usb", "utmi-pads"; 892 #phy-cells = <0>; 893 nvidia,has-legacy-mode; 894 nvidia,hssync-start-delay = <9>; 895 nvidia,idle-wait-delay = <17>; 896 nvidia,elastic-limit = <16>; 897 nvidia,term-range-adj = <6>; 898 nvidia,xcvr-setup = <9>; 899 nvidia,xcvr-lsfslew = <1>; 900 nvidia,xcvr-lsrslew = <1>; 901 nvidia,has-utmi-pad-registers; 902 nvidia,pmc = <&tegra_pmc 0>; 903 status = "disabled"; 904 }; 905 906 usb@c5004000 { 907 compatible = "nvidia,tegra20-ehci"; 908 reg = <0xc5004000 0x4000>; 909 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 910 phy_type = "ulpi"; 911 clocks = <&tegra_car TEGRA20_CLK_USB2>; 912 resets = <&tegra_car 58>; 913 reset-names = "usb"; 914 nvidia,phy = <&phy2>; 915 power-domains = <&pd_core>; 916 operating-points-v2 = <&usb2_dvfs_opp_table>; 917 status = "disabled"; 918 }; 919 920 phy2: usb-phy@c5004000 { 921 compatible = "nvidia,tegra20-usb-phy"; 922 reg = <0xc5004000 0x4000>; 923 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 924 phy_type = "ulpi"; 925 clocks = <&tegra_car TEGRA20_CLK_USB2>, 926 <&tegra_car TEGRA20_CLK_PLL_U>, 927 <&tegra_car TEGRA20_CLK_CDEV2>; 928 clock-names = "reg", "pll_u", "ulpi-link"; 929 resets = <&tegra_car 58>, <&tegra_car 22>; 930 reset-names = "usb", "utmi-pads"; 931 #phy-cells = <0>; 932 nvidia,pmc = <&tegra_pmc 1>; 933 status = "disabled"; 934 }; 935 936 usb@c5008000 { 937 compatible = "nvidia,tegra20-ehci"; 938 reg = <0xc5008000 0x4000>; 939 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 940 phy_type = "utmi"; 941 clocks = <&tegra_car TEGRA20_CLK_USB3>; 942 resets = <&tegra_car 59>; 943 reset-names = "usb"; 944 nvidia,phy = <&phy3>; 945 power-domains = <&pd_core>; 946 operating-points-v2 = <&usb3_dvfs_opp_table>; 947 status = "disabled"; 948 }; 949 950 phy3: usb-phy@c5008000 { 951 compatible = "nvidia,tegra20-usb-phy"; 952 reg = <0xc5008000 0x4000>, 953 <0xc5000000 0x4000>; 954 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 955 phy_type = "utmi"; 956 clocks = <&tegra_car TEGRA20_CLK_USB3>, 957 <&tegra_car TEGRA20_CLK_PLL_U>, 958 <&tegra_car TEGRA20_CLK_CLK_M>, 959 <&tegra_car TEGRA20_CLK_USBD>; 960 clock-names = "reg", "pll_u", "timer", "utmi-pads"; 961 resets = <&tegra_car 59>, <&tegra_car 22>; 962 reset-names = "usb", "utmi-pads"; 963 #phy-cells = <0>; 964 nvidia,hssync-start-delay = <9>; 965 nvidia,idle-wait-delay = <17>; 966 nvidia,elastic-limit = <16>; 967 nvidia,term-range-adj = <6>; 968 nvidia,xcvr-setup = <9>; 969 nvidia,xcvr-lsfslew = <2>; 970 nvidia,xcvr-lsrslew = <2>; 971 nvidia,pmc = <&tegra_pmc 2>; 972 status = "disabled"; 973 }; 974 975 mmc@c8000000 { 976 compatible = "nvidia,tegra20-sdhci"; 977 reg = <0xc8000000 0x200>; 978 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 979 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; 980 clock-names = "sdhci"; 981 resets = <&tegra_car 14>; 982 reset-names = "sdhci"; 983 power-domains = <&pd_core>; 984 operating-points-v2 = <&sdmmc1_dvfs_opp_table>; 985 status = "disabled"; 986 }; 987 988 mmc@c8000200 { 989 compatible = "nvidia,tegra20-sdhci"; 990 reg = <0xc8000200 0x200>; 991 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 992 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>; 993 clock-names = "sdhci"; 994 resets = <&tegra_car 9>; 995 reset-names = "sdhci"; 996 power-domains = <&pd_core>; 997 operating-points-v2 = <&sdmmc2_dvfs_opp_table>; 998 status = "disabled"; 999 }; 1000 1001 mmc@c8000400 { 1002 compatible = "nvidia,tegra20-sdhci"; 1003 reg = <0xc8000400 0x200>; 1004 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>; 1006 clock-names = "sdhci"; 1007 resets = <&tegra_car 69>; 1008 reset-names = "sdhci"; 1009 power-domains = <&pd_core>; 1010 operating-points-v2 = <&sdmmc3_dvfs_opp_table>; 1011 status = "disabled"; 1012 }; 1013 1014 mmc@c8000600 { 1015 compatible = "nvidia,tegra20-sdhci"; 1016 reg = <0xc8000600 0x200>; 1017 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>; 1019 clock-names = "sdhci"; 1020 resets = <&tegra_car 15>; 1021 reset-names = "sdhci"; 1022 power-domains = <&pd_core>; 1023 operating-points-v2 = <&sdmmc4_dvfs_opp_table>; 1024 status = "disabled"; 1025 }; 1026 1027 cpus { 1028 #address-cells = <1>; 1029 #size-cells = <0>; 1030 1031 cpu@0 { 1032 device_type = "cpu"; 1033 compatible = "arm,cortex-a9"; 1034 reg = <0>; 1035 clocks = <&tegra_car TEGRA20_CLK_CCLK>; 1036 }; 1037 1038 cpu@1 { 1039 device_type = "cpu"; 1040 compatible = "arm,cortex-a9"; 1041 reg = <1>; 1042 clocks = <&tegra_car TEGRA20_CLK_CCLK>; 1043 }; 1044 }; 1045 1046 pmu { 1047 compatible = "arm,cortex-a9-pmu"; 1048 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1050 interrupt-affinity = <&{/cpus/cpu@0}>, 1051 <&{/cpus/cpu@1}>; 1052 }; 1053 1054 sound-hdmi { 1055 compatible = "simple-audio-card"; 1056 simple-audio-card,name = "NVIDIA Tegra20 HDMI"; 1057 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 1061 simple-audio-card,dai-link@0 { 1062 reg = <0>; 1063 1064 codec { 1065 sound-dai = <&tegra_hdmi>; 1066 }; 1067 1068 cpu { 1069 sound-dai = <&tegra_spdif>; 1070 }; 1071 }; 1072 }; 1073}; 1074