1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/arm-smccc.h>
8 #include <linux/export.h>
9 #include <linux/io.h>
10 #include <linux/kernel.h>
11 #include <linux/of.h>
12 #include <linux/of_address.h>
13
14 #include <soc/tegra/common.h>
15 #include <soc/tegra/fuse.h>
16
17 #include "fuse.h"
18
19 #define FUSE_SKU_INFO 0x10
20
21 #define ERD_ERR_CONFIG 0x120c
22 #define ERD_MASK_INBAND_ERR 0x1
23
24 #define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 4
25 #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG \
26 (0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
27 #define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT \
28 (0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
29
30 #define TEGRA_SMCCC_PLATFORM(x) (((x) >> 8) & 0xff)
31 #define TEGRA_SMCCC_CHIP_ID(x) (((x) >> 4) & 0xff)
32 #define TEGRA_SMCCC_MAJOR_REV(x) ((x) & 0xf)
33 #define TEGRA_SMCCC_MINOR_REV(x) ((x) & 0xf)
34
35 static void __iomem *apbmisc_base;
36 static bool long_ram_code;
37 static u32 strapping;
38 static u32 chipid;
39
tegra_read_chipid(void)40 u32 tegra_read_chipid(void)
41 {
42 WARN(!apbmisc_base, "Tegra APB MISC not yet available\n");
43
44 if (!chipid)
45 chipid = readl_relaxed(apbmisc_base + 4);
46
47 return chipid;
48 }
49
tegra_get_chip_id(void)50 u8 tegra_get_chip_id(void)
51 {
52 #if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY)
53 s32 soc_id = arm_smccc_get_soc_id_version();
54
55 if (soc_id >= 0)
56 return TEGRA_SMCCC_CHIP_ID(soc_id);
57 #endif
58 return (tegra_read_chipid() >> 8) & 0xff;
59 }
60
tegra_get_major_rev(void)61 u8 tegra_get_major_rev(void)
62 {
63 #if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY)
64 s32 soc_id = arm_smccc_get_soc_id_version();
65
66 if (soc_id >= 0)
67 return TEGRA_SMCCC_MAJOR_REV(soc_id);
68 #endif
69 return (tegra_read_chipid() >> 4) & 0xf;
70 }
71
tegra_get_minor_rev(void)72 u8 tegra_get_minor_rev(void)
73 {
74 #if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY)
75 s32 revision = arm_smccc_get_soc_id_revision();
76
77 if (revision >= 0)
78 return TEGRA_SMCCC_MINOR_REV(revision);
79 #endif
80 return (tegra_read_chipid() >> 16) & 0xf;
81
82 }
83
tegra_get_platform(void)84 u8 tegra_get_platform(void)
85 {
86 #if IS_ENABLED(CONFIG_HAVE_ARM_SMCCC_DISCOVERY)
87 s32 revision = arm_smccc_get_soc_id_revision();
88
89 if (revision >= 0)
90 return TEGRA_SMCCC_PLATFORM(revision);
91 #endif
92 return (tegra_read_chipid() >> 20) & 0xf;
93 }
94
tegra_is_silicon(void)95 bool tegra_is_silicon(void)
96 {
97 switch (tegra_get_chip_id()) {
98 case TEGRA194:
99 case TEGRA234:
100 case TEGRA241:
101 case TEGRA264:
102 if (tegra_get_platform() == 0)
103 return true;
104
105 return false;
106 }
107
108 /*
109 * Chips prior to Tegra194 have a different way of determining whether
110 * they are silicon or not. Since we never supported simulation on the
111 * older Tegra chips, don't bother extracting the information and just
112 * report that we're running on silicon.
113 */
114 return true;
115 }
116
tegra_read_straps(void)117 u32 tegra_read_straps(void)
118 {
119 WARN(!apbmisc_base, "Tegra ABP MISC not yet available\n");
120
121 return strapping;
122 }
123
tegra_read_ram_code(void)124 u32 tegra_read_ram_code(void)
125 {
126 u32 straps = tegra_read_straps();
127
128 if (long_ram_code)
129 straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
130 else
131 straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
132
133 return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
134 }
135 EXPORT_SYMBOL_GPL(tegra_read_ram_code);
136
137 /*
138 * The function sets ERD(Error Response Disable) bit.
139 * This allows to mask inband errors and always send an
140 * OKAY response from CBB to the master which caused error.
141 */
tegra194_miscreg_mask_serror(void)142 int tegra194_miscreg_mask_serror(void)
143 {
144 if (!apbmisc_base)
145 return -EPROBE_DEFER;
146
147 if (!of_machine_is_compatible("nvidia,tegra194")) {
148 WARN(1, "Only supported for Tegra194 devices!\n");
149 return -EOPNOTSUPP;
150 }
151
152 writel_relaxed(ERD_MASK_INBAND_ERR,
153 apbmisc_base + ERD_ERR_CONFIG);
154
155 return 0;
156 }
157 EXPORT_SYMBOL(tegra194_miscreg_mask_serror);
158
159 static const struct of_device_id apbmisc_match[] __initconst = {
160 { .compatible = "nvidia,tegra20-apbmisc", },
161 { .compatible = "nvidia,tegra186-misc", },
162 { .compatible = "nvidia,tegra194-misc", },
163 { .compatible = "nvidia,tegra234-misc", },
164 { .compatible = "nvidia,tegra264-misc", },
165 {},
166 };
167
tegra_init_revision(void)168 void __init tegra_init_revision(void)
169 {
170 u8 chip_id, minor_rev;
171
172 chip_id = tegra_get_chip_id();
173 minor_rev = tegra_get_minor_rev();
174
175 switch (minor_rev) {
176 case 1:
177 tegra_sku_info.revision = TEGRA_REVISION_A01;
178 break;
179 case 2:
180 tegra_sku_info.revision = TEGRA_REVISION_A02;
181 break;
182 case 3:
183 if (chip_id == TEGRA20 && (tegra_fuse_read_spare(18) ||
184 tegra_fuse_read_spare(19)))
185 tegra_sku_info.revision = TEGRA_REVISION_A03p;
186 else
187 tegra_sku_info.revision = TEGRA_REVISION_A03;
188 break;
189 case 4:
190 tegra_sku_info.revision = TEGRA_REVISION_A04;
191 break;
192 default:
193 tegra_sku_info.revision = TEGRA_REVISION_UNKNOWN;
194 }
195
196 tegra_sku_info.sku_id = tegra_fuse_read_early(FUSE_SKU_INFO);
197 tegra_sku_info.platform = tegra_get_platform();
198 }
199
tegra_init_apbmisc_resources(struct resource * apbmisc,struct resource * straps)200 static void tegra_init_apbmisc_resources(struct resource *apbmisc,
201 struct resource *straps)
202 {
203 void __iomem *strapping_base;
204
205 apbmisc_base = ioremap(apbmisc->start, resource_size(apbmisc));
206 if (!apbmisc_base)
207 pr_err("failed to map APBMISC registers\n");
208
209 strapping_base = ioremap(straps->start, resource_size(straps));
210 if (strapping_base) {
211 strapping = readl_relaxed(strapping_base);
212 iounmap(strapping_base);
213 } else {
214 pr_err("failed to map strapping options registers\n");
215 }
216 }
217
218 /**
219 * tegra_init_apbmisc - Initializes Tegra APBMISC and Strapping registers.
220 *
221 * This is called during early init as some of the old 32-bit ARM code needs
222 * information from the APBMISC registers very early during boot.
223 */
tegra_init_apbmisc(void)224 void __init tegra_init_apbmisc(void)
225 {
226 struct resource apbmisc, straps;
227 struct device_node *np;
228
229 np = of_find_matching_node(NULL, apbmisc_match);
230 if (!np) {
231 /*
232 * Fall back to legacy initialization for 32-bit ARM only. All
233 * 64-bit ARM device tree files for Tegra are required to have
234 * an APBMISC node.
235 *
236 * This is for backwards-compatibility with old device trees
237 * that didn't contain an APBMISC node.
238 */
239 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
240 /* APBMISC registers (chip revision, ...) */
241 apbmisc.start = 0x70000800;
242 apbmisc.end = 0x70000863;
243 apbmisc.flags = IORESOURCE_MEM;
244
245 /* strapping options */
246 if (of_machine_is_compatible("nvidia,tegra124")) {
247 straps.start = 0x7000e864;
248 straps.end = 0x7000e867;
249 } else {
250 straps.start = 0x70000008;
251 straps.end = 0x7000000b;
252 }
253
254 straps.flags = IORESOURCE_MEM;
255
256 pr_warn("Using APBMISC region %pR\n", &apbmisc);
257 pr_warn("Using strapping options registers %pR\n",
258 &straps);
259 } else {
260 /*
261 * At this point we're not running on Tegra, so play
262 * nice with multi-platform kernels.
263 */
264 return;
265 }
266 } else {
267 /*
268 * Extract information from the device tree if we've found a
269 * matching node.
270 */
271 if (of_address_to_resource(np, 0, &apbmisc) < 0) {
272 pr_err("failed to get APBMISC registers\n");
273 goto put;
274 }
275
276 if (of_address_to_resource(np, 1, &straps) < 0) {
277 pr_err("failed to get strapping options registers\n");
278 goto put;
279 }
280 }
281
282 tegra_init_apbmisc_resources(&apbmisc, &straps);
283 long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
284
285 put:
286 of_node_put(np);
287 }
288
289 #ifdef CONFIG_ACPI
290 static const struct acpi_device_id apbmisc_acpi_match[] = {
291 { "NVDA2010" },
292 { /* sentinel */ }
293 };
294
tegra_acpi_init_apbmisc(void)295 void tegra_acpi_init_apbmisc(void)
296 {
297 struct resource *resources[2] = { NULL };
298 struct resource_entry *rentry;
299 struct acpi_device *adev = NULL;
300 struct list_head resource_list;
301 int rcount = 0;
302 int ret;
303
304 adev = acpi_dev_get_first_match_dev(apbmisc_acpi_match[0].id, NULL, -1);
305 if (!adev)
306 return;
307
308 INIT_LIST_HEAD(&resource_list);
309
310 ret = acpi_dev_get_memory_resources(adev, &resource_list);
311 if (ret < 0) {
312 pr_err("failed to get APBMISC memory resources");
313 goto out_put_acpi_dev;
314 }
315
316 /*
317 * Get required memory resources.
318 *
319 * resources[0]: apbmisc.
320 * resources[1]: straps.
321 */
322 resource_list_for_each_entry(rentry, &resource_list) {
323 if (rcount >= ARRAY_SIZE(resources))
324 break;
325
326 resources[rcount++] = rentry->res;
327 }
328
329 if (!resources[0]) {
330 pr_err("failed to get APBMISC registers\n");
331 goto out_free_resource_list;
332 }
333
334 if (!resources[1]) {
335 pr_err("failed to get strapping options registers\n");
336 goto out_free_resource_list;
337 }
338
339 tegra_init_apbmisc_resources(resources[0], resources[1]);
340
341 out_free_resource_list:
342 acpi_dev_free_resource_list(&resource_list);
343
344 out_put_acpi_dev:
345 acpi_dev_put(adev);
346 }
347 #else
tegra_acpi_init_apbmisc(void)348 void tegra_acpi_init_apbmisc(void)
349 {
350 }
351 #endif
352