1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2013-2023, NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/acpi.h>
7 #include <linux/clk.h>
8 #include <linux/device.h>
9 #include <linux/kobject.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/nvmem-consumer.h>
13 #include <linux/nvmem-provider.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/reset.h>
19 #include <linux/slab.h>
20 #include <linux/sys_soc.h>
21
22 #include <soc/tegra/common.h>
23 #include <soc/tegra/fuse.h>
24
25 #include "fuse.h"
26
27 struct tegra_sku_info tegra_sku_info;
28 EXPORT_SYMBOL(tegra_sku_info);
29
30 static const char *tegra_revision_name[TEGRA_REVISION_MAX] = {
31 [TEGRA_REVISION_UNKNOWN] = "unknown",
32 [TEGRA_REVISION_A01] = "A01",
33 [TEGRA_REVISION_A02] = "A02",
34 [TEGRA_REVISION_A03] = "A03",
35 [TEGRA_REVISION_A03p] = "A03 prime",
36 [TEGRA_REVISION_A04] = "A04",
37 };
38
39 static const char *tegra_platform_name[TEGRA_PLATFORM_MAX] = {
40 [TEGRA_PLATFORM_SILICON] = "Silicon",
41 [TEGRA_PLATFORM_QT] = "QT",
42 [TEGRA_PLATFORM_SYSTEM_FPGA] = "System FPGA",
43 [TEGRA_PLATFORM_UNIT_FPGA] = "Unit FPGA",
44 [TEGRA_PLATFORM_ASIM_QT] = "Asim QT",
45 [TEGRA_PLATFORM_ASIM_LINSIM] = "Asim Linsim",
46 [TEGRA_PLATFORM_DSIM_ASIM_LINSIM] = "Dsim Asim Linsim",
47 [TEGRA_PLATFORM_VERIFICATION_SIMULATION] = "Verification Simulation",
48 [TEGRA_PLATFORM_VDK] = "VDK",
49 [TEGRA_PLATFORM_VSP] = "VSP",
50 };
51
52 static const struct of_device_id car_match[] __initconst = {
53 { .compatible = "nvidia,tegra20-car", },
54 { .compatible = "nvidia,tegra30-car", },
55 { .compatible = "nvidia,tegra114-car", },
56 { .compatible = "nvidia,tegra124-car", },
57 { .compatible = "nvidia,tegra132-car", },
58 { .compatible = "nvidia,tegra210-car", },
59 {},
60 };
61
62 static struct tegra_fuse *fuse = &(struct tegra_fuse) {
63 .base = NULL,
64 .soc = NULL,
65 };
66
67 static const struct of_device_id tegra_fuse_match[] = {
68 #ifdef CONFIG_ARCH_TEGRA_234_SOC
69 { .compatible = "nvidia,tegra234-efuse", .data = &tegra234_fuse_soc },
70 #endif
71 #ifdef CONFIG_ARCH_TEGRA_194_SOC
72 { .compatible = "nvidia,tegra194-efuse", .data = &tegra194_fuse_soc },
73 #endif
74 #ifdef CONFIG_ARCH_TEGRA_186_SOC
75 { .compatible = "nvidia,tegra186-efuse", .data = &tegra186_fuse_soc },
76 #endif
77 #ifdef CONFIG_ARCH_TEGRA_210_SOC
78 { .compatible = "nvidia,tegra210-efuse", .data = &tegra210_fuse_soc },
79 #endif
80 #ifdef CONFIG_ARCH_TEGRA_132_SOC
81 { .compatible = "nvidia,tegra132-efuse", .data = &tegra124_fuse_soc },
82 #endif
83 #ifdef CONFIG_ARCH_TEGRA_124_SOC
84 { .compatible = "nvidia,tegra124-efuse", .data = &tegra124_fuse_soc },
85 #endif
86 #ifdef CONFIG_ARCH_TEGRA_114_SOC
87 { .compatible = "nvidia,tegra114-efuse", .data = &tegra114_fuse_soc },
88 #endif
89 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
90 { .compatible = "nvidia,tegra30-efuse", .data = &tegra30_fuse_soc },
91 #endif
92 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
93 { .compatible = "nvidia,tegra20-efuse", .data = &tegra20_fuse_soc },
94 #endif
95 { /* sentinel */ }
96 };
97
tegra_fuse_read(void * priv,unsigned int offset,void * value,size_t bytes)98 static int tegra_fuse_read(void *priv, unsigned int offset, void *value,
99 size_t bytes)
100 {
101 unsigned int count = bytes / 4, i;
102 struct tegra_fuse *fuse = priv;
103 u32 *buffer = value;
104
105 for (i = 0; i < count; i++)
106 buffer[i] = fuse->read(fuse, offset + i * 4);
107
108 return 0;
109 }
110
tegra_fuse_restore(void * base)111 static void tegra_fuse_restore(void *base)
112 {
113 fuse->base = (void __iomem *)base;
114 fuse->clk = NULL;
115 }
116
tegra_fuse_print_sku_info(struct tegra_sku_info * tegra_sku_info)117 static void tegra_fuse_print_sku_info(struct tegra_sku_info *tegra_sku_info)
118 {
119 pr_info("Tegra Revision: %s SKU: %d CPU Process: %d SoC Process: %d\n",
120 tegra_revision_name[tegra_sku_info->revision],
121 tegra_sku_info->sku_id, tegra_sku_info->cpu_process_id,
122 tegra_sku_info->soc_process_id);
123 pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
124 tegra_sku_info->cpu_speedo_id, tegra_sku_info->soc_speedo_id);
125 }
126
tegra_fuse_add_lookups(struct tegra_fuse * fuse)127 static int tegra_fuse_add_lookups(struct tegra_fuse *fuse)
128 {
129 fuse->lookups = kmemdup_array(fuse->soc->lookups, fuse->soc->num_lookups,
130 sizeof(*fuse->lookups), GFP_KERNEL);
131 if (!fuse->lookups)
132 return -ENOMEM;
133
134 nvmem_add_cell_lookups(fuse->lookups, fuse->soc->num_lookups);
135
136 return 0;
137 }
138
tegra_fuse_probe(struct platform_device * pdev)139 static int tegra_fuse_probe(struct platform_device *pdev)
140 {
141 void __iomem *base = fuse->base;
142 struct nvmem_config nvmem;
143 struct resource *res;
144 int err;
145
146 err = devm_add_action(&pdev->dev, tegra_fuse_restore, (void __force *)base);
147 if (err)
148 return err;
149
150 /* take over the memory region from the early initialization */
151 fuse->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
152 if (IS_ERR(fuse->base))
153 return PTR_ERR(fuse->base);
154 fuse->phys = res->start;
155
156 /* Initialize the soc data and lookups if using ACPI boot. */
157 if (is_acpi_node(dev_fwnode(&pdev->dev)) && !fuse->soc) {
158 u8 chip;
159
160 tegra_acpi_init_apbmisc();
161
162 chip = tegra_get_chip_id();
163 switch (chip) {
164 #if defined(CONFIG_ARCH_TEGRA_194_SOC)
165 case TEGRA194:
166 fuse->soc = &tegra194_fuse_soc;
167 break;
168 #endif
169 #if defined(CONFIG_ARCH_TEGRA_234_SOC)
170 case TEGRA234:
171 fuse->soc = &tegra234_fuse_soc;
172 break;
173 #endif
174 #if defined(CONFIG_ARCH_TEGRA_241_SOC)
175 case TEGRA241:
176 fuse->soc = &tegra241_fuse_soc;
177 break;
178 #endif
179 default:
180 return dev_err_probe(&pdev->dev, -EINVAL, "Unsupported SoC: %02x\n", chip);
181 }
182
183 fuse->soc->init(fuse);
184 }
185
186 fuse->clk = devm_clk_get_optional(&pdev->dev, "fuse");
187 if (IS_ERR(fuse->clk))
188 return dev_err_probe(&pdev->dev, PTR_ERR(fuse->clk), "failed to get FUSE clock\n");
189
190 platform_set_drvdata(pdev, fuse);
191 fuse->dev = &pdev->dev;
192
193 err = devm_pm_runtime_enable(&pdev->dev);
194 if (err)
195 return err;
196
197 if (fuse->soc->probe) {
198 err = fuse->soc->probe(fuse);
199 if (err < 0)
200 return err;
201 }
202
203 memset(&nvmem, 0, sizeof(nvmem));
204 nvmem.dev = &pdev->dev;
205 nvmem.name = "fuse";
206 nvmem.id = -1;
207 nvmem.owner = THIS_MODULE;
208 nvmem.cells = fuse->soc->cells;
209 nvmem.ncells = fuse->soc->num_cells;
210 nvmem.keepout = fuse->soc->keepouts;
211 nvmem.nkeepout = fuse->soc->num_keepouts;
212 nvmem.type = NVMEM_TYPE_OTP;
213 nvmem.read_only = true;
214 nvmem.root_only = false;
215 nvmem.reg_read = tegra_fuse_read;
216 nvmem.size = fuse->soc->info->size;
217 nvmem.word_size = 4;
218 nvmem.stride = 4;
219 nvmem.priv = fuse;
220
221 fuse->nvmem = devm_nvmem_register(&pdev->dev, &nvmem);
222 if (IS_ERR(fuse->nvmem)) {
223 err = PTR_ERR(fuse->nvmem);
224 dev_err(&pdev->dev, "failed to register NVMEM device: %d\n",
225 err);
226 return err;
227 }
228
229 err = tegra_fuse_add_lookups(fuse);
230 if (err)
231 return dev_err_probe(&pdev->dev, err, "failed to add FUSE lookups\n");
232
233 fuse->rst = devm_reset_control_get_optional(&pdev->dev, "fuse");
234 if (IS_ERR(fuse->rst))
235 return dev_err_probe(&pdev->dev, PTR_ERR(fuse->rst), "failed to get FUSE reset\n");
236
237 /*
238 * FUSE clock is enabled at a boot time, hence this resume/suspend
239 * disables the clock besides the h/w resetting.
240 */
241 err = pm_runtime_resume_and_get(&pdev->dev);
242 if (err)
243 return err;
244
245 err = reset_control_reset(fuse->rst);
246 pm_runtime_put(&pdev->dev);
247
248 if (err < 0) {
249 dev_err(&pdev->dev, "failed to reset FUSE: %d\n", err);
250 return err;
251 }
252
253 /* release the early I/O memory mapping */
254 iounmap(base);
255
256 return 0;
257 }
258
tegra_fuse_runtime_resume(struct device * dev)259 static int __maybe_unused tegra_fuse_runtime_resume(struct device *dev)
260 {
261 struct tegra_fuse *fuse = dev_get_drvdata(dev);
262 int err;
263
264 err = clk_prepare_enable(fuse->clk);
265 if (err < 0) {
266 dev_err(dev, "failed to enable FUSE clock: %d\n", err);
267 return err;
268 }
269
270 return 0;
271 }
272
tegra_fuse_runtime_suspend(struct device * dev)273 static int __maybe_unused tegra_fuse_runtime_suspend(struct device *dev)
274 {
275 struct tegra_fuse *fuse = dev_get_drvdata(dev);
276
277 clk_disable_unprepare(fuse->clk);
278
279 return 0;
280 }
281
tegra_fuse_suspend(struct device * dev)282 static int __maybe_unused tegra_fuse_suspend(struct device *dev)
283 {
284 struct tegra_fuse *fuse = dev_get_drvdata(dev);
285 int ret;
286
287 /*
288 * Critical for RAM re-repair operation, which must occur on resume
289 * from LP1 system suspend and as part of CCPLEX cluster switching.
290 */
291 if (fuse->soc->clk_suspend_on)
292 ret = pm_runtime_resume_and_get(dev);
293 else
294 ret = pm_runtime_force_suspend(dev);
295
296 return ret;
297 }
298
tegra_fuse_resume(struct device * dev)299 static int __maybe_unused tegra_fuse_resume(struct device *dev)
300 {
301 struct tegra_fuse *fuse = dev_get_drvdata(dev);
302 int ret = 0;
303
304 if (fuse->soc->clk_suspend_on)
305 pm_runtime_put(dev);
306 else
307 ret = pm_runtime_force_resume(dev);
308
309 return ret;
310 }
311
312 static const struct dev_pm_ops tegra_fuse_pm = {
313 SET_RUNTIME_PM_OPS(tegra_fuse_runtime_suspend, tegra_fuse_runtime_resume,
314 NULL)
315 SET_SYSTEM_SLEEP_PM_OPS(tegra_fuse_suspend, tegra_fuse_resume)
316 };
317
318 static const struct acpi_device_id tegra_fuse_acpi_match[] = {
319 { "NVDA200F" },
320 { /* sentinel */ }
321 };
322 MODULE_DEVICE_TABLE(acpi, tegra_fuse_acpi_match);
323
324 static struct platform_driver tegra_fuse_driver = {
325 .driver = {
326 .name = "tegra-fuse",
327 .of_match_table = tegra_fuse_match,
328 .acpi_match_table = tegra_fuse_acpi_match,
329 .pm = &tegra_fuse_pm,
330 .suppress_bind_attrs = true,
331 },
332 .probe = tegra_fuse_probe,
333 };
334 builtin_platform_driver(tegra_fuse_driver);
335
tegra_fuse_read_spare(unsigned int spare)336 u32 __init tegra_fuse_read_spare(unsigned int spare)
337 {
338 unsigned int offset = fuse->soc->info->spare + spare * 4;
339
340 return fuse->read_early(fuse, offset) & 1;
341 }
342
tegra_fuse_read_early(unsigned int offset)343 u32 __init tegra_fuse_read_early(unsigned int offset)
344 {
345 return fuse->read_early(fuse, offset);
346 }
347
tegra_fuse_readl(unsigned long offset,u32 * value)348 int tegra_fuse_readl(unsigned long offset, u32 *value)
349 {
350 if (!fuse->dev)
351 return -EPROBE_DEFER;
352
353 /*
354 * Wait for fuse->clk to be initialized if device-tree boot is used.
355 */
356 if (is_of_node(dev_fwnode(fuse->dev)) && !fuse->clk)
357 return -EPROBE_DEFER;
358
359 if (!fuse->read)
360 return -EPROBE_DEFER;
361
362 if (IS_ERR(fuse->clk))
363 return PTR_ERR(fuse->clk);
364
365 *value = fuse->read(fuse, offset);
366
367 return 0;
368 }
369 EXPORT_SYMBOL(tegra_fuse_readl);
370
tegra_enable_fuse_clk(void __iomem * base)371 static void tegra_enable_fuse_clk(void __iomem *base)
372 {
373 u32 reg;
374
375 reg = readl_relaxed(base + 0x48);
376 reg |= 1 << 28;
377 writel(reg, base + 0x48);
378
379 /*
380 * Enable FUSE clock. This needs to be hardcoded because the clock
381 * subsystem is not active during early boot.
382 */
383 reg = readl(base + 0x14);
384 reg |= 1 << 7;
385 writel(reg, base + 0x14);
386 }
387
major_show(struct device * dev,struct device_attribute * attr,char * buf)388 static ssize_t major_show(struct device *dev, struct device_attribute *attr,
389 char *buf)
390 {
391 return sprintf(buf, "%d\n", tegra_get_major_rev());
392 }
393
394 static DEVICE_ATTR_RO(major);
395
minor_show(struct device * dev,struct device_attribute * attr,char * buf)396 static ssize_t minor_show(struct device *dev, struct device_attribute *attr,
397 char *buf)
398 {
399 return sprintf(buf, "%d\n", tegra_get_minor_rev());
400 }
401
402 static DEVICE_ATTR_RO(minor);
403
404 static struct attribute *tegra_soc_attr[] = {
405 &dev_attr_major.attr,
406 &dev_attr_minor.attr,
407 NULL,
408 };
409
410 const struct attribute_group tegra_soc_attr_group = {
411 .attrs = tegra_soc_attr,
412 };
413
414 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
415 IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \
416 IS_ENABLED(CONFIG_ARCH_TEGRA_241_SOC)
platform_show(struct device * dev,struct device_attribute * attr,char * buf)417 static ssize_t platform_show(struct device *dev, struct device_attribute *attr,
418 char *buf)
419 {
420 /*
421 * Displays the value in the 'pre_si_platform' field of the HIDREV
422 * register for Tegra194 devices. A value of 0 indicates that the
423 * platform type is silicon and all other non-zero values indicate
424 * the type of simulation platform is being used.
425 */
426 return sprintf(buf, "%d\n", tegra_get_platform());
427 }
428
429 static DEVICE_ATTR_RO(platform);
430
431 static struct attribute *tegra194_soc_attr[] = {
432 &dev_attr_major.attr,
433 &dev_attr_minor.attr,
434 &dev_attr_platform.attr,
435 NULL,
436 };
437
438 const struct attribute_group tegra194_soc_attr_group = {
439 .attrs = tegra194_soc_attr,
440 };
441 #endif
442
tegra_soc_device_register(void)443 struct device *tegra_soc_device_register(void)
444 {
445 struct soc_device_attribute *attr;
446 struct soc_device *dev;
447
448 attr = kzalloc_obj(*attr);
449 if (!attr)
450 return NULL;
451
452 attr->family = kasprintf(GFP_KERNEL, "Tegra");
453 if (tegra_is_silicon())
454 attr->revision = kasprintf(GFP_KERNEL, "%s %s",
455 tegra_platform_name[tegra_sku_info.platform],
456 tegra_revision_name[tegra_sku_info.revision]);
457 else
458 attr->revision = kasprintf(GFP_KERNEL, "%s",
459 tegra_platform_name[tegra_sku_info.platform]);
460 attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id());
461 attr->custom_attr_group = fuse->soc->soc_attr_group;
462
463 dev = soc_device_register(attr);
464 if (IS_ERR(dev)) {
465 kfree(attr->soc_id);
466 kfree(attr->revision);
467 kfree(attr->family);
468 kfree(attr);
469 return ERR_CAST(dev);
470 }
471
472 return soc_device_to_device(dev);
473 }
474
tegra_init_fuse(void)475 static int __init tegra_init_fuse(void)
476 {
477 const struct of_device_id *match;
478 struct device_node *np;
479 struct resource regs;
480 int err = 0;
481
482 tegra_init_apbmisc();
483
484 np = of_find_matching_node_and_match(NULL, tegra_fuse_match, &match);
485 if (!np) {
486 /*
487 * Fall back to legacy initialization for 32-bit ARM only. All
488 * 64-bit ARM device tree files for Tegra are required to have
489 * a FUSE node.
490 *
491 * This is for backwards-compatibility with old device trees
492 * that didn't contain a FUSE node.
493 */
494 if (IS_ENABLED(CONFIG_ARM) && soc_is_tegra()) {
495 u8 chip = tegra_get_chip_id();
496
497 regs.start = 0x7000f800;
498 regs.end = 0x7000fbff;
499 regs.flags = IORESOURCE_MEM;
500
501 switch (chip) {
502 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
503 case TEGRA20:
504 fuse->soc = &tegra20_fuse_soc;
505 break;
506 #endif
507
508 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
509 case TEGRA30:
510 fuse->soc = &tegra30_fuse_soc;
511 break;
512 #endif
513
514 #ifdef CONFIG_ARCH_TEGRA_114_SOC
515 case TEGRA114:
516 fuse->soc = &tegra114_fuse_soc;
517 break;
518 #endif
519
520 #ifdef CONFIG_ARCH_TEGRA_124_SOC
521 case TEGRA124:
522 fuse->soc = &tegra124_fuse_soc;
523 break;
524 #endif
525
526 default:
527 pr_warn("Unsupported SoC: %02x\n", chip);
528 break;
529 }
530 } else {
531 /*
532 * At this point we're not running on Tegra, so play
533 * nice with multi-platform kernels.
534 */
535 return 0;
536 }
537 } else {
538 /*
539 * Extract information from the device tree if we've found a
540 * matching node.
541 */
542 if (of_address_to_resource(np, 0, ®s) < 0) {
543 pr_err("failed to get FUSE register\n");
544 return -ENXIO;
545 }
546
547 fuse->soc = match->data;
548 }
549
550 np = of_find_matching_node(NULL, car_match);
551 if (np) {
552 void __iomem *base = of_iomap(np, 0);
553 of_node_put(np);
554 if (base) {
555 tegra_enable_fuse_clk(base);
556 iounmap(base);
557 } else {
558 pr_err("failed to map clock registers\n");
559 return -ENXIO;
560 }
561 }
562
563 fuse->base = ioremap(regs.start, resource_size(®s));
564 if (!fuse->base) {
565 pr_err("failed to map FUSE registers\n");
566 return -ENXIO;
567 }
568
569 fuse->soc->init(fuse);
570
571 tegra_fuse_print_sku_info(&tegra_sku_info);
572
573 return err;
574 }
575 early_initcall(tegra_init_fuse);
576
577 #ifdef CONFIG_ARM64
tegra_init_soc(void)578 static int __init tegra_init_soc(void)
579 {
580 struct device_node *np;
581 struct device *soc;
582
583 /* make sure we're running on Tegra */
584 np = of_find_matching_node(NULL, tegra_fuse_match);
585 if (!np)
586 return 0;
587
588 of_node_put(np);
589
590 soc = tegra_soc_device_register();
591 if (IS_ERR(soc)) {
592 pr_err("failed to register SoC device: %ld\n", PTR_ERR(soc));
593 return PTR_ERR(soc);
594 }
595
596 return 0;
597 }
598 device_initcall(tegra_init_soc);
599 #endif
600