1 /* SPDX-License-Identifier: GPL-2.0-only 2 * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. 3 * All rights reserved. 4 * 5 * tegra210_i2s.h - Definitions for Tegra210 I2S driver 6 * 7 */ 8 9 #ifndef __TEGRA210_I2S_H__ 10 #define __TEGRA210_I2S_H__ 11 12 /* Register offsets from I2S*_BASE */ 13 #define TEGRA210_I2S_RX_ENABLE 0x0 14 #define TEGRA210_I2S_RX_SOFT_RESET 0x4 15 #define TEGRA210_I2S_RX_STATUS 0x0c 16 #define TEGRA210_I2S_RX_INT_STATUS 0x10 17 #define TEGRA210_I2S_RX_INT_MASK 0x14 18 #define TEGRA210_I2S_RX_INT_SET 0x18 19 #define TEGRA210_I2S_RX_INT_CLEAR 0x1c 20 #define TEGRA210_I2S_RX_CIF_CTRL 0x20 21 #define TEGRA210_I2S_RX_CTRL 0x24 22 #define TEGRA210_I2S_RX_SLOT_CTRL 0x28 23 #define TEGRA210_I2S_RX_CLK_TRIM 0x2c 24 #define TEGRA210_I2S_RX_CYA 0x30 25 #define TEGRA210_I2S_RX_CIF_FIFO_STATUS 0x34 26 #define TEGRA210_I2S_TX_ENABLE 0x40 27 #define TEGRA210_I2S_TX_SOFT_RESET 0x44 28 #define TEGRA210_I2S_TX_STATUS 0x4c 29 #define TEGRA210_I2S_TX_INT_STATUS 0x50 30 #define TEGRA210_I2S_TX_INT_MASK 0x54 31 #define TEGRA210_I2S_TX_INT_SET 0x58 32 #define TEGRA210_I2S_TX_INT_CLEAR 0x5c 33 #define TEGRA210_I2S_TX_CIF_CTRL 0x60 34 #define TEGRA210_I2S_TX_CTRL 0x64 35 #define TEGRA210_I2S_TX_SLOT_CTRL 0x68 36 #define TEGRA210_I2S_TX_CLK_TRIM 0x6c 37 #define TEGRA210_I2S_TX_CYA 0x70 38 #define TEGRA210_I2S_TX_CIF_FIFO_STATUS 0x74 39 #define TEGRA210_I2S_ENABLE 0x80 40 #define TEGRA210_I2S_SOFT_RESET 0x84 41 #define TEGRA210_I2S_CG 0x88 42 #define TEGRA210_I2S_STATUS 0x8c 43 #define TEGRA210_I2S_INT_STATUS 0x90 44 #define TEGRA210_I2S_CTRL 0xa0 45 #define TEGRA210_I2S_TIMING 0xa4 46 #define TEGRA210_I2S_SLOT_CTRL 0xa8 47 #define TEGRA210_I2S_CLK_TRIM 0xac 48 #define TEGRA210_I2S_CYA 0xb0 49 50 /* T264 specific registers */ 51 #define TEGRA264_I2S_RX_FIFO_WR_ACCESS_MODE 0x30 52 #define TEGRA264_I2S_RX_CYA 0x3c 53 #define TEGRA264_I2S_RX_CIF_FIFO_STATUS 0x40 54 #define TEGRA264_I2S_TX_ENABLE 0x80 55 #define TEGRA264_I2S_TX_SOFT_RESET 0x84 56 #define TEGRA264_I2S_TX_STATUS 0x8c 57 #define TEGRA264_I2S_TX_INT_STATUS 0x90 58 #define TEGRA264_I2S_TX_INT_MASK 0x94 59 #define TEGRA264_I2S_TX_CIF_CTRL 0xa0 60 #define TEGRA264_I2S_TX_FIFO_RD_ACCESS_MODE 0xb0 61 #define TEGRA264_I2S_TX_FIFO_RD_DATA 0xb4 62 #define TEGRA264_I2S_TX_FIFO_THRESHOLD 0xb8 63 #define TEGRA264_I2S_TX_CYA 0xbc 64 #define TEGRA264_I2S_TX_CIF_FIFO_STATUS 0xc0 65 #define TEGRA264_I2S_ENABLE 0x100 66 #define TEGRA264_I2S_CG 0x108 67 #define TEGRA264_I2S_STATUS 0x10c 68 #define TEGRA264_I2S_INT_STATUS 0x110 69 #define TEGRA264_I2S_INT_SET 0x114 70 #define TEGRA264_I2S_INT_MASK 0x11c 71 #define TEGRA264_I2S_CTRL 0x12c 72 #define TEGRA264_I2S_TIMING 0x130 73 #define TEGRA264_I2S_CYA 0x13c 74 #define TEGRA264_I2S_PIO_MODE_ENABLE 0x140 75 #define TEGRA264_I2S_PAD_MACRO_STATUS 0x144 76 77 /* Bit fields, shifts and masks */ 78 #define I2S_DATA_SHIFT 8 79 #define I2S_CTRL_DATA_OFFSET_MASK (0x7ff << I2S_DATA_SHIFT) 80 #define TEGRA264_I2S_FSYNC_WIDTH_SHIFT 23 81 #define TEGRA264_I2S_CTRL_FSYNC_WIDTH_MASK (0x1ff << TEGRA264_I2S_FSYNC_WIDTH_SHIFT) 82 83 #define I2S_EN_SHIFT 0 84 #define I2S_EN_MASK BIT(I2S_EN_SHIFT) 85 #define I2S_EN BIT(I2S_EN_SHIFT) 86 87 #define I2S_FSYNC_WIDTH_SHIFT 24 88 #define I2S_CTRL_FSYNC_WIDTH_MASK (0xff << I2S_FSYNC_WIDTH_SHIFT) 89 90 #define I2S_POS_EDGE 0 91 #define I2S_NEG_EDGE 1 92 #define I2S_EDGE_SHIFT 20 93 #define I2S_CTRL_EDGE_CTRL_MASK BIT(I2S_EDGE_SHIFT) 94 #define I2S_CTRL_EDGE_CTRL_POS_EDGE (I2S_POS_EDGE << I2S_EDGE_SHIFT) 95 #define I2S_CTRL_EDGE_CTRL_NEG_EDGE (I2S_NEG_EDGE << I2S_EDGE_SHIFT) 96 97 #define I2S_FMT_LRCK 0 98 #define I2S_FMT_FSYNC 1 99 #define I2S_FMT_SHIFT 12 100 #define I2S_CTRL_FRAME_FMT_MASK (7 << I2S_FMT_SHIFT) 101 #define I2S_CTRL_FRAME_FMT_LRCK_MODE (I2S_FMT_LRCK << I2S_FMT_SHIFT) 102 #define I2S_CTRL_FRAME_FMT_FSYNC_MODE (I2S_FMT_FSYNC << I2S_FMT_SHIFT) 103 104 #define I2S_CTRL_MASTER_EN_SHIFT 10 105 #define I2S_CTRL_MASTER_EN_MASK BIT(I2S_CTRL_MASTER_EN_SHIFT) 106 #define I2S_CTRL_MASTER_EN BIT(I2S_CTRL_MASTER_EN_SHIFT) 107 108 #define I2S_CTRL_LRCK_POL_SHIFT 9 109 #define I2S_CTRL_LRCK_POL_MASK BIT(I2S_CTRL_LRCK_POL_SHIFT) 110 #define I2S_CTRL_LRCK_POL_LOW (0 << I2S_CTRL_LRCK_POL_SHIFT) 111 #define I2S_CTRL_LRCK_POL_HIGH BIT(I2S_CTRL_LRCK_POL_SHIFT) 112 113 #define I2S_CTRL_LPBK_SHIFT 8 114 #define I2S_CTRL_LPBK_MASK BIT(I2S_CTRL_LPBK_SHIFT) 115 #define I2S_CTRL_LPBK_EN BIT(I2S_CTRL_LPBK_SHIFT) 116 117 #define I2S_BITS_8 1 118 #define I2S_BITS_16 3 119 #define I2S_BITS_24 5 120 #define I2S_BITS_32 7 121 #define I2S_CTRL_BIT_SIZE_MASK 0x7 122 123 #define I2S_TIMING_CH_BIT_CNT_MASK 0x7ff 124 #define I2S_TIMING_CH_BIT_CNT_SHIFT 0 125 126 #define I2S_SOFT_RESET_SHIFT 0 127 #define I2S_SOFT_RESET_MASK BIT(I2S_SOFT_RESET_SHIFT) 128 #define I2S_SOFT_RESET_EN BIT(I2S_SOFT_RESET_SHIFT) 129 130 #define I2S_RX_FIFO_DEPTH 64 131 #define DEFAULT_I2S_RX_FIFO_THRESHOLD 3 132 133 #define DEFAULT_I2S_SLOT_MASK 0xffff 134 #define TEGRA210_I2S_TX_OFFSET 0 135 #define TEGRA210_I2S_CTRL_OFFSET 0 136 #define TEGRA210_I2S_MAX_CHANNEL 16 137 138 #define TEGRA264_DEFAULT_I2S_SLOT_MASK 0xffffffff 139 #define TEGRA264_I2S_TX_OFFSET 0x40 140 #define TEGRA264_I2S_CTRL_OFFSET 0x8c 141 #define TEGRA264_I2S_MAX_CHANNEL 32 142 143 enum tegra210_i2s_path { 144 I2S_RX_PATH, 145 I2S_TX_PATH, 146 I2S_PATHS, 147 }; 148 149 struct tegra_i2s_soc_data { 150 const struct regmap_config *regmap_conf; 151 const struct snd_soc_component_driver *i2s_cmpnt; 152 unsigned int max_ch; 153 unsigned int tx_offset; 154 unsigned int i2s_ctrl_offset; 155 unsigned int fsync_width_mask; 156 unsigned int fsync_width_shift; 157 unsigned int slot_mask; 158 }; 159 160 struct tegra210_i2s { 161 const struct tegra_i2s_soc_data *soc_data; 162 struct clk *clk_i2s; 163 struct clk *clk_sync_input; 164 struct regmap *regmap; 165 int client_sample_format; 166 unsigned int client_channels; 167 unsigned int stereo_to_mono[I2S_PATHS]; 168 unsigned int mono_to_stereo[I2S_PATHS]; 169 unsigned int dai_fmt; 170 unsigned int fsync_width; 171 unsigned int bclk_ratio; 172 unsigned int tx_mask; 173 unsigned int rx_mask; 174 unsigned int rx_fifo_th; 175 bool loopback; 176 }; 177 178 #endif 179