1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // tegra210_ahub.c - Tegra210 AHUB driver 4 // 5 // Copyright (c) 2020-2025, NVIDIA CORPORATION. All rights reserved. 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/module.h> 10 #include <linux/of_platform.h> 11 #include <linux/platform_device.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/regmap.h> 14 #include <sound/soc.h> 15 #include "tegra210_ahub.h" 16 17 static int tegra_ahub_get_value_enum(struct snd_kcontrol *kctl, 18 struct snd_ctl_elem_value *uctl) 19 { 20 struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_to_component(kctl); 21 struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt); 22 struct soc_enum *e = (struct soc_enum *)kctl->private_value; 23 int val_bytes = snd_soc_component_regmap_val_bytes(cmpnt); 24 unsigned int reg, i, bit_pos = 0; 25 26 /* 27 * Find the bit position of current MUX input. 28 * If nothing is set, position would be 0 and it corresponds to 'None'. 29 */ 30 for (i = 0; i < ahub->soc_data->reg_count; i++) { 31 unsigned int reg_val; 32 33 reg = e->reg + (ahub->soc_data->xbar_part_size * i); 34 reg_val = snd_soc_component_read(cmpnt, reg); 35 reg_val &= ahub->soc_data->mask[i]; 36 37 if (reg_val) { 38 bit_pos = ffs(reg_val) + 39 (8 * val_bytes * i); 40 break; 41 } 42 } 43 44 /* Find index related to the item in array *_ahub_mux_texts[] */ 45 for (i = 0; i < e->items; i++) { 46 if (bit_pos == e->values[i]) { 47 uctl->value.enumerated.item[0] = i; 48 break; 49 } 50 } 51 52 return 0; 53 } 54 55 static int tegra_ahub_put_value_enum(struct snd_kcontrol *kctl, 56 struct snd_ctl_elem_value *uctl) 57 { 58 struct snd_soc_component *cmpnt = snd_soc_dapm_kcontrol_to_component(kctl); 59 struct tegra_ahub *ahub = snd_soc_component_get_drvdata(cmpnt); 60 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_to_dapm(kctl); 61 struct soc_enum *e = (struct soc_enum *)kctl->private_value; 62 struct snd_soc_dapm_update update[TEGRA_XBAR_UPDATE_MAX_REG] = { }; 63 int val_bytes = snd_soc_component_regmap_val_bytes(cmpnt); 64 unsigned int *item = uctl->value.enumerated.item; 65 unsigned int value = e->values[item[0]]; 66 unsigned int i, bit_pos, reg_idx = 0, reg_val = 0; 67 int change = 0; 68 69 if (item[0] >= e->items) 70 return -EINVAL; 71 72 if (value) { 73 /* Get the register index and value to set */ 74 reg_idx = (value - 1) / (8 * val_bytes); 75 bit_pos = (value - 1) % (8 * val_bytes); 76 reg_val = BIT(bit_pos); 77 } 78 79 /* 80 * Run through all parts of a MUX register to find the state changes. 81 * There will be an additional update if new MUX input value is from 82 * different part of the MUX register. 83 */ 84 for (i = 0; i < ahub->soc_data->reg_count; i++) { 85 update[i].reg = e->reg + (ahub->soc_data->xbar_part_size * i); 86 update[i].val = (i == reg_idx) ? reg_val : 0; 87 update[i].mask = ahub->soc_data->mask[i]; 88 update[i].kcontrol = kctl; 89 90 /* Update widget power if state has changed */ 91 if (snd_soc_component_test_bits(cmpnt, update[i].reg, 92 update[i].mask, 93 update[i].val)) 94 change |= snd_soc_dapm_mux_update_power(dapm, kctl, 95 item[0], e, 96 &update[i]); 97 } 98 99 return change; 100 } 101 102 static struct snd_soc_dai_driver tegra210_ahub_dais[] = { 103 DAI(ADMAIF1), 104 DAI(ADMAIF2), 105 DAI(ADMAIF3), 106 DAI(ADMAIF4), 107 DAI(ADMAIF5), 108 DAI(ADMAIF6), 109 DAI(ADMAIF7), 110 DAI(ADMAIF8), 111 DAI(ADMAIF9), 112 DAI(ADMAIF10), 113 /* XBAR <-> I2S <-> Codec */ 114 DAI(I2S1), 115 DAI(I2S2), 116 DAI(I2S3), 117 DAI(I2S4), 118 DAI(I2S5), 119 /* XBAR <- DMIC <- Codec */ 120 DAI(DMIC1), 121 DAI(DMIC2), 122 DAI(DMIC3), 123 /* XBAR -> SFC -> XBAR */ 124 DAI(SFC1 RX), 125 DAI(SFC1 TX), 126 DAI(SFC2 RX), 127 DAI(SFC2 TX), 128 DAI(SFC3 RX), 129 DAI(SFC3 TX), 130 DAI(SFC4 RX), 131 DAI(SFC4 TX), 132 /* XBAR -> MVC -> XBAR */ 133 DAI(MVC1 RX), 134 DAI(MVC1 TX), 135 DAI(MVC2 RX), 136 DAI(MVC2 TX), 137 /* XBAR -> AMX(4:1) -> XBAR */ 138 DAI(AMX1 RX1), 139 DAI(AMX1 RX2), 140 DAI(AMX1 RX3), 141 DAI(AMX1 RX4), 142 DAI(AMX1), 143 DAI(AMX2 RX1), 144 DAI(AMX2 RX2), 145 DAI(AMX2 RX3), 146 DAI(AMX2 RX4), 147 DAI(AMX2), 148 /* XBAR -> ADX(1:4) -> XBAR */ 149 DAI(ADX1), 150 DAI(ADX1 TX1), 151 DAI(ADX1 TX2), 152 DAI(ADX1 TX3), 153 DAI(ADX1 TX4), 154 DAI(ADX2), 155 DAI(ADX2 TX1), 156 DAI(ADX2 TX2), 157 DAI(ADX2 TX3), 158 DAI(ADX2 TX4), 159 /* XBAR -> MIXER(10:5) -> XBAR */ 160 DAI(MIXER1 RX1), 161 DAI(MIXER1 RX2), 162 DAI(MIXER1 RX3), 163 DAI(MIXER1 RX4), 164 DAI(MIXER1 RX5), 165 DAI(MIXER1 RX6), 166 DAI(MIXER1 RX7), 167 DAI(MIXER1 RX8), 168 DAI(MIXER1 RX9), 169 DAI(MIXER1 RX10), 170 DAI(MIXER1 TX1), 171 DAI(MIXER1 TX2), 172 DAI(MIXER1 TX3), 173 DAI(MIXER1 TX4), 174 DAI(MIXER1 TX5), 175 /* XBAR -> OPE -> XBAR */ 176 DAI(OPE1 RX), 177 DAI(OPE1 TX), 178 DAI(OPE2 RX), 179 DAI(OPE2 TX), 180 }; 181 182 static struct snd_soc_dai_driver tegra186_ahub_dais[] = { 183 DAI(ADMAIF1), 184 DAI(ADMAIF2), 185 DAI(ADMAIF3), 186 DAI(ADMAIF4), 187 DAI(ADMAIF5), 188 DAI(ADMAIF6), 189 DAI(ADMAIF7), 190 DAI(ADMAIF8), 191 DAI(ADMAIF9), 192 DAI(ADMAIF10), 193 DAI(ADMAIF11), 194 DAI(ADMAIF12), 195 DAI(ADMAIF13), 196 DAI(ADMAIF14), 197 DAI(ADMAIF15), 198 DAI(ADMAIF16), 199 DAI(ADMAIF17), 200 DAI(ADMAIF18), 201 DAI(ADMAIF19), 202 DAI(ADMAIF20), 203 /* XBAR <-> I2S <-> Codec */ 204 DAI(I2S1), 205 DAI(I2S2), 206 DAI(I2S3), 207 DAI(I2S4), 208 DAI(I2S5), 209 DAI(I2S6), 210 /* XBAR <- DMIC <- Codec */ 211 DAI(DMIC1), 212 DAI(DMIC2), 213 DAI(DMIC3), 214 DAI(DMIC4), 215 /* XBAR -> DSPK -> Codec */ 216 DAI(DSPK1), 217 DAI(DSPK2), 218 /* XBAR -> SFC -> XBAR */ 219 DAI(SFC1 RX), 220 DAI(SFC1 TX), 221 DAI(SFC2 RX), 222 DAI(SFC2 TX), 223 DAI(SFC3 RX), 224 DAI(SFC3 TX), 225 DAI(SFC4 RX), 226 DAI(SFC4 TX), 227 /* XBAR -> MVC -> XBAR */ 228 DAI(MVC1 RX), 229 DAI(MVC1 TX), 230 DAI(MVC2 RX), 231 DAI(MVC2 TX), 232 /* XBAR -> AMX(4:1) -> XBAR */ 233 DAI(AMX1 RX1), 234 DAI(AMX1 RX2), 235 DAI(AMX1 RX3), 236 DAI(AMX1 RX4), 237 DAI(AMX1), 238 DAI(AMX2 RX1), 239 DAI(AMX2 RX2), 240 DAI(AMX2 RX3), 241 DAI(AMX2 RX4), 242 DAI(AMX2), 243 DAI(AMX3 RX1), 244 DAI(AMX3 RX2), 245 DAI(AMX3 RX3), 246 DAI(AMX3 RX4), 247 DAI(AMX3), 248 DAI(AMX4 RX1), 249 DAI(AMX4 RX2), 250 DAI(AMX4 RX3), 251 DAI(AMX4 RX4), 252 DAI(AMX4), 253 /* XBAR -> ADX(1:4) -> XBAR */ 254 DAI(ADX1), 255 DAI(ADX1 TX1), 256 DAI(ADX1 TX2), 257 DAI(ADX1 TX3), 258 DAI(ADX1 TX4), 259 DAI(ADX2), 260 DAI(ADX2 TX1), 261 DAI(ADX2 TX2), 262 DAI(ADX2 TX3), 263 DAI(ADX2 TX4), 264 DAI(ADX3), 265 DAI(ADX3 TX1), 266 DAI(ADX3 TX2), 267 DAI(ADX3 TX3), 268 DAI(ADX3 TX4), 269 DAI(ADX4), 270 DAI(ADX4 TX1), 271 DAI(ADX4 TX2), 272 DAI(ADX4 TX3), 273 DAI(ADX4 TX4), 274 /* XBAR -> MIXER1(10:5) -> XBAR */ 275 DAI(MIXER1 RX1), 276 DAI(MIXER1 RX2), 277 DAI(MIXER1 RX3), 278 DAI(MIXER1 RX4), 279 DAI(MIXER1 RX5), 280 DAI(MIXER1 RX6), 281 DAI(MIXER1 RX7), 282 DAI(MIXER1 RX8), 283 DAI(MIXER1 RX9), 284 DAI(MIXER1 RX10), 285 DAI(MIXER1 TX1), 286 DAI(MIXER1 TX2), 287 DAI(MIXER1 TX3), 288 DAI(MIXER1 TX4), 289 DAI(MIXER1 TX5), 290 /* XBAR -> ASRC -> XBAR */ 291 DAI(ASRC1 RX1), 292 DAI(ASRC1 TX1), 293 DAI(ASRC1 RX2), 294 DAI(ASRC1 TX2), 295 DAI(ASRC1 RX3), 296 DAI(ASRC1 TX3), 297 DAI(ASRC1 RX4), 298 DAI(ASRC1 TX4), 299 DAI(ASRC1 RX5), 300 DAI(ASRC1 TX5), 301 DAI(ASRC1 RX6), 302 DAI(ASRC1 TX6), 303 DAI(ASRC1 RX7), 304 /* XBAR -> OPE -> XBAR */ 305 DAI(OPE1 RX), 306 DAI(OPE1 TX), 307 }; 308 309 static struct snd_soc_dai_driver tegra264_ahub_dais[] = { 310 DAI(ADMAIF1), 311 DAI(ADMAIF2), 312 DAI(ADMAIF3), 313 DAI(ADMAIF4), 314 DAI(ADMAIF5), 315 DAI(ADMAIF6), 316 DAI(ADMAIF7), 317 DAI(ADMAIF8), 318 DAI(ADMAIF9), 319 DAI(ADMAIF10), 320 DAI(ADMAIF11), 321 DAI(ADMAIF12), 322 DAI(ADMAIF13), 323 DAI(ADMAIF14), 324 DAI(ADMAIF15), 325 DAI(ADMAIF16), 326 DAI(ADMAIF17), 327 DAI(ADMAIF18), 328 DAI(ADMAIF19), 329 DAI(ADMAIF20), 330 DAI(ADMAIF21), 331 DAI(ADMAIF22), 332 DAI(ADMAIF23), 333 DAI(ADMAIF24), 334 DAI(ADMAIF25), 335 DAI(ADMAIF26), 336 DAI(ADMAIF27), 337 DAI(ADMAIF28), 338 DAI(ADMAIF29), 339 DAI(ADMAIF30), 340 DAI(ADMAIF31), 341 DAI(ADMAIF32), 342 /* XBAR <-> I2S <-> Codec */ 343 DAI(I2S1), 344 DAI(I2S2), 345 DAI(I2S3), 346 DAI(I2S4), 347 DAI(I2S5), 348 DAI(I2S6), 349 DAI(I2S7), 350 DAI(I2S8), 351 /* XBAR <-> DMIC <-> Codec */ 352 DAI(DMIC1), 353 DAI(DMIC2), 354 /* XBAR <-> DSPK <-> Codec */ 355 DAI(DSPK1), 356 /* XBAR -> SFC -> XBAR */ 357 DAI(SFC1 RX), 358 DAI(SFC1 TX), 359 DAI(SFC2 RX), 360 DAI(SFC2 TX), 361 DAI(SFC3 RX), 362 DAI(SFC3 TX), 363 DAI(SFC4 RX), 364 DAI(SFC4 TX), 365 /* XBAR -> MVC -> XBAR */ 366 DAI(MVC1 RX), 367 DAI(MVC1 TX), 368 DAI(MVC2 RX), 369 DAI(MVC2 TX), 370 /* XBAR -> AMX(4:1) -> XBAR */ 371 DAI(AMX1 RX1), 372 DAI(AMX1 RX2), 373 DAI(AMX1 RX3), 374 DAI(AMX1 RX4), 375 DAI(AMX1), 376 DAI(AMX2 RX1), 377 DAI(AMX2 RX2), 378 DAI(AMX2 RX3), 379 DAI(AMX2 RX4), 380 DAI(AMX2), 381 DAI(AMX3 RX1), 382 DAI(AMX3 RX2), 383 DAI(AMX3 RX3), 384 DAI(AMX3 RX4), 385 DAI(AMX3), 386 DAI(AMX4 RX1), 387 DAI(AMX4 RX2), 388 DAI(AMX4 RX3), 389 DAI(AMX4 RX4), 390 DAI(AMX4), 391 DAI(AMX5 RX1), 392 DAI(AMX5 RX2), 393 DAI(AMX5 RX3), 394 DAI(AMX5 RX4), 395 DAI(AMX5), 396 DAI(AMX6 RX1), 397 DAI(AMX6 RX2), 398 DAI(AMX6 RX3), 399 DAI(AMX6 RX4), 400 DAI(AMX6), 401 /* XBAR -> ADX(1:4) -> XBAR */ 402 DAI(ADX1), 403 DAI(ADX1 TX1), 404 DAI(ADX1 TX2), 405 DAI(ADX1 TX3), 406 DAI(ADX1 TX4), 407 DAI(ADX2), 408 DAI(ADX2 TX1), 409 DAI(ADX2 TX2), 410 DAI(ADX2 TX3), 411 DAI(ADX2 TX4), 412 DAI(ADX3), 413 DAI(ADX3 TX1), 414 DAI(ADX3 TX2), 415 DAI(ADX3 TX3), 416 DAI(ADX3 TX4), 417 DAI(ADX4), 418 DAI(ADX4 TX1), 419 DAI(ADX4 TX2), 420 DAI(ADX4 TX3), 421 DAI(ADX4 TX4), 422 DAI(ADX5), 423 DAI(ADX5 TX1), 424 DAI(ADX5 TX2), 425 DAI(ADX5 TX3), 426 DAI(ADX5 TX4), 427 DAI(ADX6), 428 DAI(ADX6 TX1), 429 DAI(ADX6 TX2), 430 DAI(ADX6 TX3), 431 DAI(ADX6 TX4), 432 /* XBAR -> MIXER1(10:5) -> XBAR */ 433 DAI(MIXER1 RX1), 434 DAI(MIXER1 RX2), 435 DAI(MIXER1 RX3), 436 DAI(MIXER1 RX4), 437 DAI(MIXER1 RX5), 438 DAI(MIXER1 RX6), 439 DAI(MIXER1 RX7), 440 DAI(MIXER1 RX8), 441 DAI(MIXER1 RX9), 442 DAI(MIXER1 RX10), 443 DAI(MIXER1 TX1), 444 DAI(MIXER1 TX2), 445 DAI(MIXER1 TX3), 446 DAI(MIXER1 TX4), 447 DAI(MIXER1 TX5), 448 /* XBAR -> ASRC -> XBAR */ 449 DAI(ASRC1 RX1), 450 DAI(ASRC1 TX1), 451 DAI(ASRC1 RX2), 452 DAI(ASRC1 TX2), 453 DAI(ASRC1 RX3), 454 DAI(ASRC1 TX3), 455 DAI(ASRC1 RX4), 456 DAI(ASRC1 TX4), 457 DAI(ASRC1 RX5), 458 DAI(ASRC1 TX5), 459 DAI(ASRC1 RX6), 460 DAI(ASRC1 TX6), 461 DAI(ASRC1 RX7), 462 /* XBAR -> OPE -> XBAR */ 463 DAI(OPE1 RX), 464 DAI(OPE1 TX), 465 }; 466 467 static const char * const tegra210_ahub_mux_texts[] = { 468 "None", 469 "ADMAIF1", 470 "ADMAIF2", 471 "ADMAIF3", 472 "ADMAIF4", 473 "ADMAIF5", 474 "ADMAIF6", 475 "ADMAIF7", 476 "ADMAIF8", 477 "ADMAIF9", 478 "ADMAIF10", 479 "I2S1", 480 "I2S2", 481 "I2S3", 482 "I2S4", 483 "I2S5", 484 "DMIC1", 485 "DMIC2", 486 "DMIC3", 487 "SFC1", 488 "SFC2", 489 "SFC3", 490 "SFC4", 491 "MVC1", 492 "MVC2", 493 "AMX1", 494 "AMX2", 495 "ADX1 TX1", 496 "ADX1 TX2", 497 "ADX1 TX3", 498 "ADX1 TX4", 499 "ADX2 TX1", 500 "ADX2 TX2", 501 "ADX2 TX3", 502 "ADX2 TX4", 503 "MIXER1 TX1", 504 "MIXER1 TX2", 505 "MIXER1 TX3", 506 "MIXER1 TX4", 507 "MIXER1 TX5", 508 "OPE1", 509 "OPE2", 510 }; 511 512 static const char * const tegra186_ahub_mux_texts[] = { 513 "None", 514 "ADMAIF1", 515 "ADMAIF2", 516 "ADMAIF3", 517 "ADMAIF4", 518 "ADMAIF5", 519 "ADMAIF6", 520 "ADMAIF7", 521 "ADMAIF8", 522 "ADMAIF9", 523 "ADMAIF10", 524 "ADMAIF11", 525 "ADMAIF12", 526 "ADMAIF13", 527 "ADMAIF14", 528 "ADMAIF15", 529 "ADMAIF16", 530 "I2S1", 531 "I2S2", 532 "I2S3", 533 "I2S4", 534 "I2S5", 535 "I2S6", 536 "ADMAIF17", 537 "ADMAIF18", 538 "ADMAIF19", 539 "ADMAIF20", 540 "DMIC1", 541 "DMIC2", 542 "DMIC3", 543 "DMIC4", 544 "SFC1", 545 "SFC2", 546 "SFC3", 547 "SFC4", 548 "MVC1", 549 "MVC2", 550 "AMX1", 551 "AMX2", 552 "AMX3", 553 "AMX4", 554 "ADX1 TX1", 555 "ADX1 TX2", 556 "ADX1 TX3", 557 "ADX1 TX4", 558 "ADX2 TX1", 559 "ADX2 TX2", 560 "ADX2 TX3", 561 "ADX2 TX4", 562 "ADX3 TX1", 563 "ADX3 TX2", 564 "ADX3 TX3", 565 "ADX3 TX4", 566 "ADX4 TX1", 567 "ADX4 TX2", 568 "ADX4 TX3", 569 "ADX4 TX4", 570 "MIXER1 TX1", 571 "MIXER1 TX2", 572 "MIXER1 TX3", 573 "MIXER1 TX4", 574 "MIXER1 TX5", 575 "ASRC1 TX1", 576 "ASRC1 TX2", 577 "ASRC1 TX3", 578 "ASRC1 TX4", 579 "ASRC1 TX5", 580 "ASRC1 TX6", 581 "OPE1", 582 }; 583 584 static const char * const tegra264_ahub_mux_texts[] = { 585 "None", 586 "ADMAIF1", 587 "ADMAIF2", 588 "ADMAIF3", 589 "ADMAIF4", 590 "ADMAIF5", 591 "ADMAIF6", 592 "ADMAIF7", 593 "ADMAIF8", 594 "ADMAIF9", 595 "ADMAIF10", 596 "ADMAIF11", 597 "ADMAIF12", 598 "ADMAIF13", 599 "ADMAIF14", 600 "ADMAIF15", 601 "ADMAIF16", 602 "I2S1", 603 "I2S2", 604 "I2S3", 605 "I2S4", 606 "I2S5", 607 "I2S6", 608 "I2S7", 609 "I2S8", 610 "SFC1", 611 "SFC2", 612 "SFC3", 613 "SFC4", 614 "MIXER1 TX1", 615 "MIXER1 TX2", 616 "MIXER1 TX3", 617 "MIXER1 TX4", 618 "MIXER1 TX5", 619 "AMX1", 620 "AMX2", 621 "AMX3", 622 "AMX4", 623 "AMX5", 624 "AMX6", 625 "OPE1", 626 "MVC1", 627 "MVC2", 628 "DMIC1", 629 "DMIC2", 630 "ADX1 TX1", 631 "ADX1 TX2", 632 "ADX1 TX3", 633 "ADX1 TX4", 634 "ADX2 TX1", 635 "ADX2 TX2", 636 "ADX2 TX3", 637 "ADX2 TX4", 638 "ADX3 TX1", 639 "ADX3 TX2", 640 "ADX3 TX3", 641 "ADX3 TX4", 642 "ADX4 TX1", 643 "ADX4 TX2", 644 "ADX4 TX3", 645 "ADX4 TX4", 646 "ADX5 TX1", 647 "ADX5 TX2", 648 "ADX5 TX3", 649 "ADX5 TX4", 650 "ADX6 TX1", 651 "ADX6 TX2", 652 "ADX6 TX3", 653 "ADX6 TX4", 654 "ASRC1 TX1", 655 "ASRC1 TX2", 656 "ASRC1 TX3", 657 "ASRC1 TX4", 658 "ASRC1 TX5", 659 "ASRC1 TX6", 660 "ADMAIF17", 661 "ADMAIF18", 662 "ADMAIF19", 663 "ADMAIF20", 664 "ADMAIF21", 665 "ADMAIF22", 666 "ADMAIF23", 667 "ADMAIF24", 668 "ADMAIF25", 669 "ADMAIF26", 670 "ADMAIF27", 671 "ADMAIF28", 672 "ADMAIF29", 673 "ADMAIF30", 674 "ADMAIF31", 675 "ADMAIF32", 676 }; 677 678 static const unsigned int tegra210_ahub_mux_values[] = { 679 0, 680 /* ADMAIF */ 681 MUX_VALUE(0, 0), 682 MUX_VALUE(0, 1), 683 MUX_VALUE(0, 2), 684 MUX_VALUE(0, 3), 685 MUX_VALUE(0, 4), 686 MUX_VALUE(0, 5), 687 MUX_VALUE(0, 6), 688 MUX_VALUE(0, 7), 689 MUX_VALUE(0, 8), 690 MUX_VALUE(0, 9), 691 /* I2S */ 692 MUX_VALUE(0, 16), 693 MUX_VALUE(0, 17), 694 MUX_VALUE(0, 18), 695 MUX_VALUE(0, 19), 696 MUX_VALUE(0, 20), 697 /* DMIC */ 698 MUX_VALUE(2, 18), 699 MUX_VALUE(2, 19), 700 MUX_VALUE(2, 20), 701 /* SFC */ 702 MUX_VALUE(0, 24), 703 MUX_VALUE(0, 25), 704 MUX_VALUE(0, 26), 705 MUX_VALUE(0, 27), 706 /* MVC */ 707 MUX_VALUE(2, 8), 708 MUX_VALUE(2, 9), 709 /* AMX */ 710 MUX_VALUE(1, 8), 711 MUX_VALUE(1, 9), 712 /* ADX */ 713 MUX_VALUE(2, 24), 714 MUX_VALUE(2, 25), 715 MUX_VALUE(2, 26), 716 MUX_VALUE(2, 27), 717 MUX_VALUE(2, 28), 718 MUX_VALUE(2, 29), 719 MUX_VALUE(2, 30), 720 MUX_VALUE(2, 31), 721 /* MIXER */ 722 MUX_VALUE(1, 0), 723 MUX_VALUE(1, 1), 724 MUX_VALUE(1, 2), 725 MUX_VALUE(1, 3), 726 MUX_VALUE(1, 4), 727 /* OPE */ 728 MUX_VALUE(2, 0), 729 MUX_VALUE(2, 1), 730 }; 731 732 static const unsigned int tegra186_ahub_mux_values[] = { 733 0, 734 /* ADMAIF */ 735 MUX_VALUE(0, 0), 736 MUX_VALUE(0, 1), 737 MUX_VALUE(0, 2), 738 MUX_VALUE(0, 3), 739 MUX_VALUE(0, 4), 740 MUX_VALUE(0, 5), 741 MUX_VALUE(0, 6), 742 MUX_VALUE(0, 7), 743 MUX_VALUE(0, 8), 744 MUX_VALUE(0, 9), 745 MUX_VALUE(0, 10), 746 MUX_VALUE(0, 11), 747 MUX_VALUE(0, 12), 748 MUX_VALUE(0, 13), 749 MUX_VALUE(0, 14), 750 MUX_VALUE(0, 15), 751 /* I2S */ 752 MUX_VALUE(0, 16), 753 MUX_VALUE(0, 17), 754 MUX_VALUE(0, 18), 755 MUX_VALUE(0, 19), 756 MUX_VALUE(0, 20), 757 MUX_VALUE(0, 21), 758 /* ADMAIF */ 759 MUX_VALUE(3, 16), 760 MUX_VALUE(3, 17), 761 MUX_VALUE(3, 18), 762 MUX_VALUE(3, 19), 763 /* DMIC */ 764 MUX_VALUE(2, 18), 765 MUX_VALUE(2, 19), 766 MUX_VALUE(2, 20), 767 MUX_VALUE(2, 21), 768 /* SFC */ 769 MUX_VALUE(0, 24), 770 MUX_VALUE(0, 25), 771 MUX_VALUE(0, 26), 772 MUX_VALUE(0, 27), 773 /* MVC */ 774 MUX_VALUE(2, 8), 775 MUX_VALUE(2, 9), 776 /* AMX */ 777 MUX_VALUE(1, 8), 778 MUX_VALUE(1, 9), 779 MUX_VALUE(1, 10), 780 MUX_VALUE(1, 11), 781 /* ADX */ 782 MUX_VALUE(2, 24), 783 MUX_VALUE(2, 25), 784 MUX_VALUE(2, 26), 785 MUX_VALUE(2, 27), 786 MUX_VALUE(2, 28), 787 MUX_VALUE(2, 29), 788 MUX_VALUE(2, 30), 789 MUX_VALUE(2, 31), 790 MUX_VALUE(3, 0), 791 MUX_VALUE(3, 1), 792 MUX_VALUE(3, 2), 793 MUX_VALUE(3, 3), 794 MUX_VALUE(3, 4), 795 MUX_VALUE(3, 5), 796 MUX_VALUE(3, 6), 797 MUX_VALUE(3, 7), 798 /* MIXER */ 799 MUX_VALUE(1, 0), 800 MUX_VALUE(1, 1), 801 MUX_VALUE(1, 2), 802 MUX_VALUE(1, 3), 803 MUX_VALUE(1, 4), 804 /* ASRC */ 805 MUX_VALUE(3, 24), 806 MUX_VALUE(3, 25), 807 MUX_VALUE(3, 26), 808 MUX_VALUE(3, 27), 809 MUX_VALUE(3, 28), 810 MUX_VALUE(3, 29), 811 /* OPE */ 812 MUX_VALUE(2, 0), 813 }; 814 815 static const unsigned int tegra264_ahub_mux_values[] = { 816 0, 817 /* ADMAIF */ 818 MUX_VALUE(0, 0), 819 MUX_VALUE(0, 1), 820 MUX_VALUE(0, 2), 821 MUX_VALUE(0, 3), 822 MUX_VALUE(0, 4), 823 MUX_VALUE(0, 5), 824 MUX_VALUE(0, 6), 825 MUX_VALUE(0, 7), 826 MUX_VALUE(0, 8), 827 MUX_VALUE(0, 9), 828 MUX_VALUE(0, 10), 829 MUX_VALUE(0, 11), 830 MUX_VALUE(0, 12), 831 MUX_VALUE(0, 13), 832 MUX_VALUE(0, 14), 833 MUX_VALUE(0, 15), 834 /* I2S */ 835 MUX_VALUE(0, 16), 836 MUX_VALUE(0, 17), 837 MUX_VALUE(0, 18), 838 MUX_VALUE(0, 19), 839 MUX_VALUE(0, 20), 840 MUX_VALUE(0, 21), 841 MUX_VALUE(0, 22), 842 MUX_VALUE(0, 23), 843 /* SFC */ 844 MUX_VALUE(0, 24), 845 MUX_VALUE(0, 25), 846 MUX_VALUE(0, 26), 847 MUX_VALUE(0, 27), 848 /* MIXER */ 849 MUX_VALUE(1, 0), 850 MUX_VALUE(1, 1), 851 MUX_VALUE(1, 2), 852 MUX_VALUE(1, 3), 853 MUX_VALUE(1, 4), 854 /* AMX */ 855 MUX_VALUE(1, 8), 856 MUX_VALUE(1, 9), 857 MUX_VALUE(1, 10), 858 MUX_VALUE(1, 11), 859 MUX_VALUE(1, 12), 860 MUX_VALUE(1, 13), 861 /* OPE */ 862 MUX_VALUE(2, 0), 863 /* MVC */ 864 MUX_VALUE(2, 8), 865 MUX_VALUE(2, 9), 866 /* DMIC */ 867 MUX_VALUE(2, 18), 868 MUX_VALUE(2, 19), 869 /* ADX */ 870 MUX_VALUE(2, 24), 871 MUX_VALUE(2, 25), 872 MUX_VALUE(2, 26), 873 MUX_VALUE(2, 27), 874 MUX_VALUE(2, 28), 875 MUX_VALUE(2, 29), 876 MUX_VALUE(2, 30), 877 MUX_VALUE(2, 31), 878 MUX_VALUE(3, 0), 879 MUX_VALUE(3, 1), 880 MUX_VALUE(3, 2), 881 MUX_VALUE(3, 3), 882 MUX_VALUE(3, 4), 883 MUX_VALUE(3, 5), 884 MUX_VALUE(3, 6), 885 MUX_VALUE(3, 7), 886 MUX_VALUE(3, 8), 887 MUX_VALUE(3, 9), 888 MUX_VALUE(3, 10), 889 MUX_VALUE(3, 11), 890 MUX_VALUE(3, 12), 891 MUX_VALUE(3, 13), 892 MUX_VALUE(3, 14), 893 MUX_VALUE(3, 15), 894 /* ASRC */ 895 MUX_VALUE(3, 24), 896 MUX_VALUE(3, 25), 897 MUX_VALUE(3, 26), 898 MUX_VALUE(3, 27), 899 MUX_VALUE(3, 28), 900 MUX_VALUE(3, 29), 901 /* ADMAIF */ 902 MUX_VALUE(4, 7), 903 MUX_VALUE(4, 8), 904 MUX_VALUE(4, 9), 905 MUX_VALUE(4, 10), 906 MUX_VALUE(4, 11), 907 MUX_VALUE(4, 12), 908 MUX_VALUE(4, 13), 909 MUX_VALUE(4, 14), 910 MUX_VALUE(4, 15), 911 MUX_VALUE(4, 16), 912 MUX_VALUE(4, 17), 913 MUX_VALUE(4, 18), 914 MUX_VALUE(4, 19), 915 MUX_VALUE(4, 20), 916 MUX_VALUE(4, 21), 917 MUX_VALUE(4, 22), 918 }; 919 920 /* Controls for t210 */ 921 MUX_ENUM_CTRL_DECL(t210_admaif1_tx, 0x00); 922 MUX_ENUM_CTRL_DECL(t210_admaif2_tx, 0x01); 923 MUX_ENUM_CTRL_DECL(t210_admaif3_tx, 0x02); 924 MUX_ENUM_CTRL_DECL(t210_admaif4_tx, 0x03); 925 MUX_ENUM_CTRL_DECL(t210_admaif5_tx, 0x04); 926 MUX_ENUM_CTRL_DECL(t210_admaif6_tx, 0x05); 927 MUX_ENUM_CTRL_DECL(t210_admaif7_tx, 0x06); 928 MUX_ENUM_CTRL_DECL(t210_admaif8_tx, 0x07); 929 MUX_ENUM_CTRL_DECL(t210_admaif9_tx, 0x08); 930 MUX_ENUM_CTRL_DECL(t210_admaif10_tx, 0x09); 931 MUX_ENUM_CTRL_DECL(t210_i2s1_tx, 0x10); 932 MUX_ENUM_CTRL_DECL(t210_i2s2_tx, 0x11); 933 MUX_ENUM_CTRL_DECL(t210_i2s3_tx, 0x12); 934 MUX_ENUM_CTRL_DECL(t210_i2s4_tx, 0x13); 935 MUX_ENUM_CTRL_DECL(t210_i2s5_tx, 0x14); 936 MUX_ENUM_CTRL_DECL(t210_sfc1_tx, 0x18); 937 MUX_ENUM_CTRL_DECL(t210_sfc2_tx, 0x19); 938 MUX_ENUM_CTRL_DECL(t210_sfc3_tx, 0x1a); 939 MUX_ENUM_CTRL_DECL(t210_sfc4_tx, 0x1b); 940 MUX_ENUM_CTRL_DECL(t210_mvc1_tx, 0x48); 941 MUX_ENUM_CTRL_DECL(t210_mvc2_tx, 0x49); 942 MUX_ENUM_CTRL_DECL(t210_amx11_tx, 0x50); 943 MUX_ENUM_CTRL_DECL(t210_amx12_tx, 0x51); 944 MUX_ENUM_CTRL_DECL(t210_amx13_tx, 0x52); 945 MUX_ENUM_CTRL_DECL(t210_amx14_tx, 0x53); 946 MUX_ENUM_CTRL_DECL(t210_amx21_tx, 0x54); 947 MUX_ENUM_CTRL_DECL(t210_amx22_tx, 0x55); 948 MUX_ENUM_CTRL_DECL(t210_amx23_tx, 0x56); 949 MUX_ENUM_CTRL_DECL(t210_amx24_tx, 0x57); 950 MUX_ENUM_CTRL_DECL(t210_adx1_tx, 0x58); 951 MUX_ENUM_CTRL_DECL(t210_adx2_tx, 0x59); 952 MUX_ENUM_CTRL_DECL(t210_mixer11_tx, 0x20); 953 MUX_ENUM_CTRL_DECL(t210_mixer12_tx, 0x21); 954 MUX_ENUM_CTRL_DECL(t210_mixer13_tx, 0x22); 955 MUX_ENUM_CTRL_DECL(t210_mixer14_tx, 0x23); 956 MUX_ENUM_CTRL_DECL(t210_mixer15_tx, 0x24); 957 MUX_ENUM_CTRL_DECL(t210_mixer16_tx, 0x25); 958 MUX_ENUM_CTRL_DECL(t210_mixer17_tx, 0x26); 959 MUX_ENUM_CTRL_DECL(t210_mixer18_tx, 0x27); 960 MUX_ENUM_CTRL_DECL(t210_mixer19_tx, 0x28); 961 MUX_ENUM_CTRL_DECL(t210_mixer110_tx, 0x29); 962 MUX_ENUM_CTRL_DECL(t210_ope1_tx, 0x40); 963 MUX_ENUM_CTRL_DECL(t210_ope2_tx, 0x41); 964 965 /* Controls for t186 */ 966 MUX_ENUM_CTRL_DECL_186(t186_admaif1_tx, 0x00); 967 MUX_ENUM_CTRL_DECL_186(t186_admaif2_tx, 0x01); 968 MUX_ENUM_CTRL_DECL_186(t186_admaif3_tx, 0x02); 969 MUX_ENUM_CTRL_DECL_186(t186_admaif4_tx, 0x03); 970 MUX_ENUM_CTRL_DECL_186(t186_admaif5_tx, 0x04); 971 MUX_ENUM_CTRL_DECL_186(t186_admaif6_tx, 0x05); 972 MUX_ENUM_CTRL_DECL_186(t186_admaif7_tx, 0x06); 973 MUX_ENUM_CTRL_DECL_186(t186_admaif8_tx, 0x07); 974 MUX_ENUM_CTRL_DECL_186(t186_admaif9_tx, 0x08); 975 MUX_ENUM_CTRL_DECL_186(t186_admaif10_tx, 0x09); 976 MUX_ENUM_CTRL_DECL_186(t186_i2s1_tx, 0x10); 977 MUX_ENUM_CTRL_DECL_186(t186_i2s2_tx, 0x11); 978 MUX_ENUM_CTRL_DECL_186(t186_i2s3_tx, 0x12); 979 MUX_ENUM_CTRL_DECL_186(t186_i2s4_tx, 0x13); 980 MUX_ENUM_CTRL_DECL_186(t186_i2s5_tx, 0x14); 981 MUX_ENUM_CTRL_DECL_186(t186_admaif11_tx, 0x0a); 982 MUX_ENUM_CTRL_DECL_186(t186_admaif12_tx, 0x0b); 983 MUX_ENUM_CTRL_DECL_186(t186_admaif13_tx, 0x0c); 984 MUX_ENUM_CTRL_DECL_186(t186_admaif14_tx, 0x0d); 985 MUX_ENUM_CTRL_DECL_186(t186_admaif15_tx, 0x0e); 986 MUX_ENUM_CTRL_DECL_186(t186_admaif16_tx, 0x0f); 987 MUX_ENUM_CTRL_DECL_186(t186_i2s6_tx, 0x15); 988 MUX_ENUM_CTRL_DECL_186(t186_dspk1_tx, 0x30); 989 MUX_ENUM_CTRL_DECL_186(t186_dspk2_tx, 0x31); 990 MUX_ENUM_CTRL_DECL_186(t186_admaif17_tx, 0x68); 991 MUX_ENUM_CTRL_DECL_186(t186_admaif18_tx, 0x69); 992 MUX_ENUM_CTRL_DECL_186(t186_admaif19_tx, 0x6a); 993 MUX_ENUM_CTRL_DECL_186(t186_admaif20_tx, 0x6b); 994 MUX_ENUM_CTRL_DECL_186(t186_sfc1_tx, 0x18); 995 MUX_ENUM_CTRL_DECL_186(t186_sfc2_tx, 0x19); 996 MUX_ENUM_CTRL_DECL_186(t186_sfc3_tx, 0x1a); 997 MUX_ENUM_CTRL_DECL_186(t186_sfc4_tx, 0x1b); 998 MUX_ENUM_CTRL_DECL_186(t186_mvc1_tx, 0x48); 999 MUX_ENUM_CTRL_DECL_186(t186_mvc2_tx, 0x49); 1000 MUX_ENUM_CTRL_DECL_186(t186_amx11_tx, 0x50); 1001 MUX_ENUM_CTRL_DECL_186(t186_amx12_tx, 0x51); 1002 MUX_ENUM_CTRL_DECL_186(t186_amx13_tx, 0x52); 1003 MUX_ENUM_CTRL_DECL_186(t186_amx14_tx, 0x53); 1004 MUX_ENUM_CTRL_DECL_186(t186_amx21_tx, 0x54); 1005 MUX_ENUM_CTRL_DECL_186(t186_amx22_tx, 0x55); 1006 MUX_ENUM_CTRL_DECL_186(t186_amx23_tx, 0x56); 1007 MUX_ENUM_CTRL_DECL_186(t186_amx24_tx, 0x57); 1008 MUX_ENUM_CTRL_DECL_186(t186_amx31_tx, 0x58); 1009 MUX_ENUM_CTRL_DECL_186(t186_amx32_tx, 0x59); 1010 MUX_ENUM_CTRL_DECL_186(t186_amx33_tx, 0x5a); 1011 MUX_ENUM_CTRL_DECL_186(t186_amx34_tx, 0x5b); 1012 MUX_ENUM_CTRL_DECL_186(t186_amx41_tx, 0x64); 1013 MUX_ENUM_CTRL_DECL_186(t186_amx42_tx, 0x65); 1014 MUX_ENUM_CTRL_DECL_186(t186_amx43_tx, 0x66); 1015 MUX_ENUM_CTRL_DECL_186(t186_amx44_tx, 0x67); 1016 MUX_ENUM_CTRL_DECL_186(t186_adx1_tx, 0x60); 1017 MUX_ENUM_CTRL_DECL_186(t186_adx2_tx, 0x61); 1018 MUX_ENUM_CTRL_DECL_186(t186_adx3_tx, 0x62); 1019 MUX_ENUM_CTRL_DECL_186(t186_adx4_tx, 0x63); 1020 MUX_ENUM_CTRL_DECL_186(t186_mixer11_tx, 0x20); 1021 MUX_ENUM_CTRL_DECL_186(t186_mixer12_tx, 0x21); 1022 MUX_ENUM_CTRL_DECL_186(t186_mixer13_tx, 0x22); 1023 MUX_ENUM_CTRL_DECL_186(t186_mixer14_tx, 0x23); 1024 MUX_ENUM_CTRL_DECL_186(t186_mixer15_tx, 0x24); 1025 MUX_ENUM_CTRL_DECL_186(t186_mixer16_tx, 0x25); 1026 MUX_ENUM_CTRL_DECL_186(t186_mixer17_tx, 0x26); 1027 MUX_ENUM_CTRL_DECL_186(t186_mixer18_tx, 0x27); 1028 MUX_ENUM_CTRL_DECL_186(t186_mixer19_tx, 0x28); 1029 MUX_ENUM_CTRL_DECL_186(t186_mixer110_tx, 0x29); 1030 MUX_ENUM_CTRL_DECL_186(t186_asrc11_tx, 0x6c); 1031 MUX_ENUM_CTRL_DECL_186(t186_asrc12_tx, 0x6d); 1032 MUX_ENUM_CTRL_DECL_186(t186_asrc13_tx, 0x6e); 1033 MUX_ENUM_CTRL_DECL_186(t186_asrc14_tx, 0x6f); 1034 MUX_ENUM_CTRL_DECL_186(t186_asrc15_tx, 0x70); 1035 MUX_ENUM_CTRL_DECL_186(t186_asrc16_tx, 0x71); 1036 MUX_ENUM_CTRL_DECL_186(t186_asrc17_tx, 0x72); 1037 MUX_ENUM_CTRL_DECL_186(t186_ope1_tx, 0x40); 1038 1039 /* Controls for t234 */ 1040 MUX_ENUM_CTRL_DECL_234(t234_mvc1_tx, 0x44); 1041 MUX_ENUM_CTRL_DECL_234(t234_mvc2_tx, 0x45); 1042 MUX_ENUM_CTRL_DECL_234(t234_amx11_tx, 0x48); 1043 MUX_ENUM_CTRL_DECL_234(t234_amx12_tx, 0x49); 1044 MUX_ENUM_CTRL_DECL_234(t234_amx13_tx, 0x4a); 1045 MUX_ENUM_CTRL_DECL_234(t234_amx14_tx, 0x4b); 1046 MUX_ENUM_CTRL_DECL_234(t234_amx21_tx, 0x4c); 1047 MUX_ENUM_CTRL_DECL_234(t234_amx22_tx, 0x4d); 1048 MUX_ENUM_CTRL_DECL_234(t234_amx23_tx, 0x4e); 1049 MUX_ENUM_CTRL_DECL_234(t234_amx24_tx, 0x4f); 1050 MUX_ENUM_CTRL_DECL_234(t234_amx31_tx, 0x50); 1051 MUX_ENUM_CTRL_DECL_234(t234_amx32_tx, 0x51); 1052 MUX_ENUM_CTRL_DECL_234(t234_amx33_tx, 0x52); 1053 MUX_ENUM_CTRL_DECL_234(t234_amx34_tx, 0x53); 1054 MUX_ENUM_CTRL_DECL_234(t234_adx1_tx, 0x58); 1055 MUX_ENUM_CTRL_DECL_234(t234_adx2_tx, 0x59); 1056 MUX_ENUM_CTRL_DECL_234(t234_adx3_tx, 0x5a); 1057 MUX_ENUM_CTRL_DECL_234(t234_adx4_tx, 0x5b); 1058 MUX_ENUM_CTRL_DECL_234(t234_amx41_tx, 0x5c); 1059 MUX_ENUM_CTRL_DECL_234(t234_amx42_tx, 0x5d); 1060 MUX_ENUM_CTRL_DECL_234(t234_amx43_tx, 0x5e); 1061 MUX_ENUM_CTRL_DECL_234(t234_amx44_tx, 0x5f); 1062 MUX_ENUM_CTRL_DECL_234(t234_admaif17_tx, 0x60); 1063 MUX_ENUM_CTRL_DECL_234(t234_admaif18_tx, 0x61); 1064 MUX_ENUM_CTRL_DECL_234(t234_admaif19_tx, 0x62); 1065 MUX_ENUM_CTRL_DECL_234(t234_admaif20_tx, 0x63); 1066 MUX_ENUM_CTRL_DECL_234(t234_asrc11_tx, 0x64); 1067 MUX_ENUM_CTRL_DECL_234(t234_asrc12_tx, 0x65); 1068 MUX_ENUM_CTRL_DECL_234(t234_asrc13_tx, 0x66); 1069 MUX_ENUM_CTRL_DECL_234(t234_asrc14_tx, 0x67); 1070 MUX_ENUM_CTRL_DECL_234(t234_asrc15_tx, 0x68); 1071 MUX_ENUM_CTRL_DECL_234(t234_asrc16_tx, 0x69); 1072 MUX_ENUM_CTRL_DECL_234(t234_asrc17_tx, 0x6a); 1073 1074 /* Controls for t264 */ 1075 MUX_ENUM_CTRL_DECL_264(t264_admaif1_tx, 0x00); 1076 MUX_ENUM_CTRL_DECL_264(t264_admaif2_tx, 0x01); 1077 MUX_ENUM_CTRL_DECL_264(t264_admaif3_tx, 0x02); 1078 MUX_ENUM_CTRL_DECL_264(t264_admaif4_tx, 0x03); 1079 MUX_ENUM_CTRL_DECL_264(t264_admaif5_tx, 0x04); 1080 MUX_ENUM_CTRL_DECL_264(t264_admaif6_tx, 0x05); 1081 MUX_ENUM_CTRL_DECL_264(t264_admaif7_tx, 0x06); 1082 MUX_ENUM_CTRL_DECL_264(t264_admaif8_tx, 0x07); 1083 MUX_ENUM_CTRL_DECL_264(t264_admaif9_tx, 0x08); 1084 MUX_ENUM_CTRL_DECL_264(t264_admaif10_tx, 0x09); 1085 MUX_ENUM_CTRL_DECL_264(t264_admaif11_tx, 0x0a); 1086 MUX_ENUM_CTRL_DECL_264(t264_admaif12_tx, 0x0b); 1087 MUX_ENUM_CTRL_DECL_264(t264_admaif13_tx, 0x0c); 1088 MUX_ENUM_CTRL_DECL_264(t264_admaif14_tx, 0x0d); 1089 MUX_ENUM_CTRL_DECL_264(t264_admaif15_tx, 0x0e); 1090 MUX_ENUM_CTRL_DECL_264(t264_admaif16_tx, 0x0f); 1091 MUX_ENUM_CTRL_DECL_264(t264_i2s1_tx, 0x10); 1092 MUX_ENUM_CTRL_DECL_264(t264_i2s2_tx, 0x11); 1093 MUX_ENUM_CTRL_DECL_264(t264_i2s3_tx, 0x12); 1094 MUX_ENUM_CTRL_DECL_264(t264_i2s4_tx, 0x13); 1095 MUX_ENUM_CTRL_DECL_264(t264_i2s5_tx, 0x14); 1096 MUX_ENUM_CTRL_DECL_264(t264_i2s6_tx, 0x15); 1097 MUX_ENUM_CTRL_DECL_264(t264_i2s7_tx, 0x16); 1098 MUX_ENUM_CTRL_DECL_264(t264_i2s8_tx, 0x17); 1099 MUX_ENUM_CTRL_DECL_264(t264_sfc1_tx, 0x18); 1100 MUX_ENUM_CTRL_DECL_264(t264_sfc2_tx, 0x19); 1101 MUX_ENUM_CTRL_DECL_264(t264_sfc3_tx, 0x1a); 1102 MUX_ENUM_CTRL_DECL_264(t264_sfc4_tx, 0x1b); 1103 MUX_ENUM_CTRL_DECL_264(t264_mixer11_tx, 0x20); 1104 MUX_ENUM_CTRL_DECL_264(t264_mixer12_tx, 0x21); 1105 MUX_ENUM_CTRL_DECL_264(t264_mixer13_tx, 0x22); 1106 MUX_ENUM_CTRL_DECL_264(t264_mixer14_tx, 0x23); 1107 MUX_ENUM_CTRL_DECL_264(t264_mixer15_tx, 0x24); 1108 MUX_ENUM_CTRL_DECL_264(t264_mixer16_tx, 0x25); 1109 MUX_ENUM_CTRL_DECL_264(t264_mixer17_tx, 0x26); 1110 MUX_ENUM_CTRL_DECL_264(t264_mixer18_tx, 0x27); 1111 MUX_ENUM_CTRL_DECL_264(t264_mixer19_tx, 0x28); 1112 MUX_ENUM_CTRL_DECL_264(t264_mixer110_tx, 0x29); 1113 MUX_ENUM_CTRL_DECL_264(t264_dspk1_tx, 0x30); 1114 MUX_ENUM_CTRL_DECL_264(t264_ope1_tx, 0x40); 1115 MUX_ENUM_CTRL_DECL_264(t264_mvc1_tx, 0x44); 1116 MUX_ENUM_CTRL_DECL_264(t264_mvc2_tx, 0x45); 1117 MUX_ENUM_CTRL_DECL_264(t264_amx11_tx, 0x48); 1118 MUX_ENUM_CTRL_DECL_264(t264_amx12_tx, 0x49); 1119 MUX_ENUM_CTRL_DECL_264(t264_amx13_tx, 0x4a); 1120 MUX_ENUM_CTRL_DECL_264(t264_amx14_tx, 0x4b); 1121 MUX_ENUM_CTRL_DECL_264(t264_amx21_tx, 0x4c); 1122 MUX_ENUM_CTRL_DECL_264(t264_amx22_tx, 0x4d); 1123 MUX_ENUM_CTRL_DECL_264(t264_amx23_tx, 0x4e); 1124 MUX_ENUM_CTRL_DECL_264(t264_amx24_tx, 0x4f); 1125 MUX_ENUM_CTRL_DECL_264(t264_amx31_tx, 0x50); 1126 MUX_ENUM_CTRL_DECL_264(t264_amx32_tx, 0x51); 1127 MUX_ENUM_CTRL_DECL_264(t264_amx33_tx, 0x52); 1128 MUX_ENUM_CTRL_DECL_264(t264_amx34_tx, 0x53); 1129 MUX_ENUM_CTRL_DECL_264(t264_adx1_tx, 0x58); 1130 MUX_ENUM_CTRL_DECL_264(t264_adx2_tx, 0x59); 1131 MUX_ENUM_CTRL_DECL_264(t264_adx3_tx, 0x5a); 1132 MUX_ENUM_CTRL_DECL_264(t264_adx4_tx, 0x5b); 1133 MUX_ENUM_CTRL_DECL_264(t264_amx41_tx, 0x5c); 1134 MUX_ENUM_CTRL_DECL_264(t264_amx42_tx, 0x5d); 1135 MUX_ENUM_CTRL_DECL_264(t264_amx43_tx, 0x5e); 1136 MUX_ENUM_CTRL_DECL_264(t264_amx44_tx, 0x5f); 1137 MUX_ENUM_CTRL_DECL_264(t264_admaif17_tx, 0x60); 1138 MUX_ENUM_CTRL_DECL_264(t264_admaif18_tx, 0x61); 1139 MUX_ENUM_CTRL_DECL_264(t264_admaif19_tx, 0x62); 1140 MUX_ENUM_CTRL_DECL_264(t264_admaif20_tx, 0x63); 1141 MUX_ENUM_CTRL_DECL_264(t264_asrc11_tx, 0x64); 1142 MUX_ENUM_CTRL_DECL_264(t264_asrc12_tx, 0x65); 1143 MUX_ENUM_CTRL_DECL_264(t264_asrc13_tx, 0x66); 1144 MUX_ENUM_CTRL_DECL_264(t264_asrc14_tx, 0x67); 1145 MUX_ENUM_CTRL_DECL_264(t264_asrc15_tx, 0x68); 1146 MUX_ENUM_CTRL_DECL_264(t264_asrc16_tx, 0x69); 1147 MUX_ENUM_CTRL_DECL_264(t264_asrc17_tx, 0x6a); 1148 MUX_ENUM_CTRL_DECL_264(t264_admaif21_tx, 0x74); 1149 MUX_ENUM_CTRL_DECL_264(t264_admaif22_tx, 0x75); 1150 MUX_ENUM_CTRL_DECL_264(t264_admaif23_tx, 0x76); 1151 MUX_ENUM_CTRL_DECL_264(t264_admaif24_tx, 0x77); 1152 MUX_ENUM_CTRL_DECL_264(t264_admaif25_tx, 0x78); 1153 MUX_ENUM_CTRL_DECL_264(t264_admaif26_tx, 0x79); 1154 MUX_ENUM_CTRL_DECL_264(t264_admaif27_tx, 0x7a); 1155 MUX_ENUM_CTRL_DECL_264(t264_admaif28_tx, 0x7b); 1156 MUX_ENUM_CTRL_DECL_264(t264_admaif29_tx, 0x7c); 1157 MUX_ENUM_CTRL_DECL_264(t264_admaif30_tx, 0x7d); 1158 MUX_ENUM_CTRL_DECL_264(t264_admaif31_tx, 0x7e); 1159 MUX_ENUM_CTRL_DECL_264(t264_admaif32_tx, 0x7f); 1160 MUX_ENUM_CTRL_DECL_264(t264_amx51_tx, 0x80); 1161 MUX_ENUM_CTRL_DECL_264(t264_amx52_tx, 0x81); 1162 MUX_ENUM_CTRL_DECL_264(t264_amx53_tx, 0x82); 1163 MUX_ENUM_CTRL_DECL_264(t264_amx54_tx, 0x83); 1164 MUX_ENUM_CTRL_DECL_264(t264_amx61_tx, 0x84); 1165 MUX_ENUM_CTRL_DECL_264(t264_amx62_tx, 0x85); 1166 MUX_ENUM_CTRL_DECL_264(t264_amx63_tx, 0x86); 1167 MUX_ENUM_CTRL_DECL_264(t264_amx64_tx, 0x87); 1168 MUX_ENUM_CTRL_DECL_264(t264_adx5_tx, 0x88); 1169 MUX_ENUM_CTRL_DECL_264(t264_adx6_tx, 0x89); 1170 1171 static const struct snd_soc_dapm_widget tegra210_ahub_widgets[] = { 1172 WIDGETS("ADMAIF1", t210_admaif1_tx), 1173 WIDGETS("ADMAIF2", t210_admaif2_tx), 1174 WIDGETS("ADMAIF3", t210_admaif3_tx), 1175 WIDGETS("ADMAIF4", t210_admaif4_tx), 1176 WIDGETS("ADMAIF5", t210_admaif5_tx), 1177 WIDGETS("ADMAIF6", t210_admaif6_tx), 1178 WIDGETS("ADMAIF7", t210_admaif7_tx), 1179 WIDGETS("ADMAIF8", t210_admaif8_tx), 1180 WIDGETS("ADMAIF9", t210_admaif9_tx), 1181 WIDGETS("ADMAIF10", t210_admaif10_tx), 1182 WIDGETS("I2S1", t210_i2s1_tx), 1183 WIDGETS("I2S2", t210_i2s2_tx), 1184 WIDGETS("I2S3", t210_i2s3_tx), 1185 WIDGETS("I2S4", t210_i2s4_tx), 1186 WIDGETS("I2S5", t210_i2s5_tx), 1187 TX_WIDGETS("DMIC1"), 1188 TX_WIDGETS("DMIC2"), 1189 TX_WIDGETS("DMIC3"), 1190 WIDGETS("SFC1", t210_sfc1_tx), 1191 WIDGETS("SFC2", t210_sfc2_tx), 1192 WIDGETS("SFC3", t210_sfc3_tx), 1193 WIDGETS("SFC4", t210_sfc4_tx), 1194 WIDGETS("MVC1", t210_mvc1_tx), 1195 WIDGETS("MVC2", t210_mvc2_tx), 1196 WIDGETS("AMX1 RX1", t210_amx11_tx), 1197 WIDGETS("AMX1 RX2", t210_amx12_tx), 1198 WIDGETS("AMX1 RX3", t210_amx13_tx), 1199 WIDGETS("AMX1 RX4", t210_amx14_tx), 1200 WIDGETS("AMX2 RX1", t210_amx21_tx), 1201 WIDGETS("AMX2 RX2", t210_amx22_tx), 1202 WIDGETS("AMX2 RX3", t210_amx23_tx), 1203 WIDGETS("AMX2 RX4", t210_amx24_tx), 1204 TX_WIDGETS("AMX1"), 1205 TX_WIDGETS("AMX2"), 1206 WIDGETS("ADX1", t210_adx1_tx), 1207 WIDGETS("ADX2", t210_adx2_tx), 1208 TX_WIDGETS("ADX1 TX1"), 1209 TX_WIDGETS("ADX1 TX2"), 1210 TX_WIDGETS("ADX1 TX3"), 1211 TX_WIDGETS("ADX1 TX4"), 1212 TX_WIDGETS("ADX2 TX1"), 1213 TX_WIDGETS("ADX2 TX2"), 1214 TX_WIDGETS("ADX2 TX3"), 1215 TX_WIDGETS("ADX2 TX4"), 1216 WIDGETS("MIXER1 RX1", t210_mixer11_tx), 1217 WIDGETS("MIXER1 RX2", t210_mixer12_tx), 1218 WIDGETS("MIXER1 RX3", t210_mixer13_tx), 1219 WIDGETS("MIXER1 RX4", t210_mixer14_tx), 1220 WIDGETS("MIXER1 RX5", t210_mixer15_tx), 1221 WIDGETS("MIXER1 RX6", t210_mixer16_tx), 1222 WIDGETS("MIXER1 RX7", t210_mixer17_tx), 1223 WIDGETS("MIXER1 RX8", t210_mixer18_tx), 1224 WIDGETS("MIXER1 RX9", t210_mixer19_tx), 1225 WIDGETS("MIXER1 RX10", t210_mixer110_tx), 1226 TX_WIDGETS("MIXER1 TX1"), 1227 TX_WIDGETS("MIXER1 TX2"), 1228 TX_WIDGETS("MIXER1 TX3"), 1229 TX_WIDGETS("MIXER1 TX4"), 1230 TX_WIDGETS("MIXER1 TX5"), 1231 WIDGETS("OPE1", t210_ope1_tx), 1232 WIDGETS("OPE2", t210_ope2_tx), 1233 }; 1234 1235 static const struct snd_soc_dapm_widget tegra186_ahub_widgets[] = { 1236 WIDGETS("ADMAIF1", t186_admaif1_tx), 1237 WIDGETS("ADMAIF2", t186_admaif2_tx), 1238 WIDGETS("ADMAIF3", t186_admaif3_tx), 1239 WIDGETS("ADMAIF4", t186_admaif4_tx), 1240 WIDGETS("ADMAIF5", t186_admaif5_tx), 1241 WIDGETS("ADMAIF6", t186_admaif6_tx), 1242 WIDGETS("ADMAIF7", t186_admaif7_tx), 1243 WIDGETS("ADMAIF8", t186_admaif8_tx), 1244 WIDGETS("ADMAIF9", t186_admaif9_tx), 1245 WIDGETS("ADMAIF10", t186_admaif10_tx), 1246 WIDGETS("ADMAIF11", t186_admaif11_tx), 1247 WIDGETS("ADMAIF12", t186_admaif12_tx), 1248 WIDGETS("ADMAIF13", t186_admaif13_tx), 1249 WIDGETS("ADMAIF14", t186_admaif14_tx), 1250 WIDGETS("ADMAIF15", t186_admaif15_tx), 1251 WIDGETS("ADMAIF16", t186_admaif16_tx), 1252 WIDGETS("ADMAIF17", t186_admaif17_tx), 1253 WIDGETS("ADMAIF18", t186_admaif18_tx), 1254 WIDGETS("ADMAIF19", t186_admaif19_tx), 1255 WIDGETS("ADMAIF20", t186_admaif20_tx), 1256 WIDGETS("I2S1", t186_i2s1_tx), 1257 WIDGETS("I2S2", t186_i2s2_tx), 1258 WIDGETS("I2S3", t186_i2s3_tx), 1259 WIDGETS("I2S4", t186_i2s4_tx), 1260 WIDGETS("I2S5", t186_i2s5_tx), 1261 WIDGETS("I2S6", t186_i2s6_tx), 1262 TX_WIDGETS("DMIC1"), 1263 TX_WIDGETS("DMIC2"), 1264 TX_WIDGETS("DMIC3"), 1265 TX_WIDGETS("DMIC4"), 1266 WIDGETS("DSPK1", t186_dspk1_tx), 1267 WIDGETS("DSPK2", t186_dspk2_tx), 1268 WIDGETS("SFC1", t186_sfc1_tx), 1269 WIDGETS("SFC2", t186_sfc2_tx), 1270 WIDGETS("SFC3", t186_sfc3_tx), 1271 WIDGETS("SFC4", t186_sfc4_tx), 1272 WIDGETS("MVC1", t186_mvc1_tx), 1273 WIDGETS("MVC2", t186_mvc2_tx), 1274 WIDGETS("AMX1 RX1", t186_amx11_tx), 1275 WIDGETS("AMX1 RX2", t186_amx12_tx), 1276 WIDGETS("AMX1 RX3", t186_amx13_tx), 1277 WIDGETS("AMX1 RX4", t186_amx14_tx), 1278 WIDGETS("AMX2 RX1", t186_amx21_tx), 1279 WIDGETS("AMX2 RX2", t186_amx22_tx), 1280 WIDGETS("AMX2 RX3", t186_amx23_tx), 1281 WIDGETS("AMX2 RX4", t186_amx24_tx), 1282 WIDGETS("AMX3 RX1", t186_amx31_tx), 1283 WIDGETS("AMX3 RX2", t186_amx32_tx), 1284 WIDGETS("AMX3 RX3", t186_amx33_tx), 1285 WIDGETS("AMX3 RX4", t186_amx34_tx), 1286 WIDGETS("AMX4 RX1", t186_amx41_tx), 1287 WIDGETS("AMX4 RX2", t186_amx42_tx), 1288 WIDGETS("AMX4 RX3", t186_amx43_tx), 1289 WIDGETS("AMX4 RX4", t186_amx44_tx), 1290 TX_WIDGETS("AMX1"), 1291 TX_WIDGETS("AMX2"), 1292 TX_WIDGETS("AMX3"), 1293 TX_WIDGETS("AMX4"), 1294 WIDGETS("ADX1", t186_adx1_tx), 1295 WIDGETS("ADX2", t186_adx2_tx), 1296 WIDGETS("ADX3", t186_adx3_tx), 1297 WIDGETS("ADX4", t186_adx4_tx), 1298 TX_WIDGETS("ADX1 TX1"), 1299 TX_WIDGETS("ADX1 TX2"), 1300 TX_WIDGETS("ADX1 TX3"), 1301 TX_WIDGETS("ADX1 TX4"), 1302 TX_WIDGETS("ADX2 TX1"), 1303 TX_WIDGETS("ADX2 TX2"), 1304 TX_WIDGETS("ADX2 TX3"), 1305 TX_WIDGETS("ADX2 TX4"), 1306 TX_WIDGETS("ADX3 TX1"), 1307 TX_WIDGETS("ADX3 TX2"), 1308 TX_WIDGETS("ADX3 TX3"), 1309 TX_WIDGETS("ADX3 TX4"), 1310 TX_WIDGETS("ADX4 TX1"), 1311 TX_WIDGETS("ADX4 TX2"), 1312 TX_WIDGETS("ADX4 TX3"), 1313 TX_WIDGETS("ADX4 TX4"), 1314 WIDGETS("MIXER1 RX1", t186_mixer11_tx), 1315 WIDGETS("MIXER1 RX2", t186_mixer12_tx), 1316 WIDGETS("MIXER1 RX3", t186_mixer13_tx), 1317 WIDGETS("MIXER1 RX4", t186_mixer14_tx), 1318 WIDGETS("MIXER1 RX5", t186_mixer15_tx), 1319 WIDGETS("MIXER1 RX6", t186_mixer16_tx), 1320 WIDGETS("MIXER1 RX7", t186_mixer17_tx), 1321 WIDGETS("MIXER1 RX8", t186_mixer18_tx), 1322 WIDGETS("MIXER1 RX9", t186_mixer19_tx), 1323 WIDGETS("MIXER1 RX10", t186_mixer110_tx), 1324 TX_WIDGETS("MIXER1 TX1"), 1325 TX_WIDGETS("MIXER1 TX2"), 1326 TX_WIDGETS("MIXER1 TX3"), 1327 TX_WIDGETS("MIXER1 TX4"), 1328 TX_WIDGETS("MIXER1 TX5"), 1329 WIDGETS("ASRC1 RX1", t186_asrc11_tx), 1330 WIDGETS("ASRC1 RX2", t186_asrc12_tx), 1331 WIDGETS("ASRC1 RX3", t186_asrc13_tx), 1332 WIDGETS("ASRC1 RX4", t186_asrc14_tx), 1333 WIDGETS("ASRC1 RX5", t186_asrc15_tx), 1334 WIDGETS("ASRC1 RX6", t186_asrc16_tx), 1335 WIDGETS("ASRC1 RX7", t186_asrc17_tx), 1336 TX_WIDGETS("ASRC1 TX1"), 1337 TX_WIDGETS("ASRC1 TX2"), 1338 TX_WIDGETS("ASRC1 TX3"), 1339 TX_WIDGETS("ASRC1 TX4"), 1340 TX_WIDGETS("ASRC1 TX5"), 1341 TX_WIDGETS("ASRC1 TX6"), 1342 WIDGETS("OPE1", t186_ope1_tx), 1343 }; 1344 1345 static const struct snd_soc_dapm_widget tegra234_ahub_widgets[] = { 1346 WIDGETS("ADMAIF1", t186_admaif1_tx), 1347 WIDGETS("ADMAIF2", t186_admaif2_tx), 1348 WIDGETS("ADMAIF3", t186_admaif3_tx), 1349 WIDGETS("ADMAIF4", t186_admaif4_tx), 1350 WIDGETS("ADMAIF5", t186_admaif5_tx), 1351 WIDGETS("ADMAIF6", t186_admaif6_tx), 1352 WIDGETS("ADMAIF7", t186_admaif7_tx), 1353 WIDGETS("ADMAIF8", t186_admaif8_tx), 1354 WIDGETS("ADMAIF9", t186_admaif9_tx), 1355 WIDGETS("ADMAIF10", t186_admaif10_tx), 1356 WIDGETS("ADMAIF11", t186_admaif11_tx), 1357 WIDGETS("ADMAIF12", t186_admaif12_tx), 1358 WIDGETS("ADMAIF13", t186_admaif13_tx), 1359 WIDGETS("ADMAIF14", t186_admaif14_tx), 1360 WIDGETS("ADMAIF15", t186_admaif15_tx), 1361 WIDGETS("ADMAIF16", t186_admaif16_tx), 1362 WIDGETS("ADMAIF17", t234_admaif17_tx), 1363 WIDGETS("ADMAIF18", t234_admaif18_tx), 1364 WIDGETS("ADMAIF19", t234_admaif19_tx), 1365 WIDGETS("ADMAIF20", t234_admaif20_tx), 1366 WIDGETS("I2S1", t186_i2s1_tx), 1367 WIDGETS("I2S2", t186_i2s2_tx), 1368 WIDGETS("I2S3", t186_i2s3_tx), 1369 WIDGETS("I2S4", t186_i2s4_tx), 1370 WIDGETS("I2S5", t186_i2s5_tx), 1371 WIDGETS("I2S6", t186_i2s6_tx), 1372 TX_WIDGETS("DMIC1"), 1373 TX_WIDGETS("DMIC2"), 1374 TX_WIDGETS("DMIC3"), 1375 TX_WIDGETS("DMIC4"), 1376 WIDGETS("DSPK1", t186_dspk1_tx), 1377 WIDGETS("DSPK2", t186_dspk2_tx), 1378 WIDGETS("SFC1", t186_sfc1_tx), 1379 WIDGETS("SFC2", t186_sfc2_tx), 1380 WIDGETS("SFC3", t186_sfc3_tx), 1381 WIDGETS("SFC4", t186_sfc4_tx), 1382 WIDGETS("MVC1", t234_mvc1_tx), 1383 WIDGETS("MVC2", t234_mvc2_tx), 1384 WIDGETS("AMX1 RX1", t234_amx11_tx), 1385 WIDGETS("AMX1 RX2", t234_amx12_tx), 1386 WIDGETS("AMX1 RX3", t234_amx13_tx), 1387 WIDGETS("AMX1 RX4", t234_amx14_tx), 1388 WIDGETS("AMX2 RX1", t234_amx21_tx), 1389 WIDGETS("AMX2 RX2", t234_amx22_tx), 1390 WIDGETS("AMX2 RX3", t234_amx23_tx), 1391 WIDGETS("AMX2 RX4", t234_amx24_tx), 1392 WIDGETS("AMX3 RX1", t234_amx31_tx), 1393 WIDGETS("AMX3 RX2", t234_amx32_tx), 1394 WIDGETS("AMX3 RX3", t234_amx33_tx), 1395 WIDGETS("AMX3 RX4", t234_amx34_tx), 1396 WIDGETS("AMX4 RX1", t234_amx41_tx), 1397 WIDGETS("AMX4 RX2", t234_amx42_tx), 1398 WIDGETS("AMX4 RX3", t234_amx43_tx), 1399 WIDGETS("AMX4 RX4", t234_amx44_tx), 1400 TX_WIDGETS("AMX1"), 1401 TX_WIDGETS("AMX2"), 1402 TX_WIDGETS("AMX3"), 1403 TX_WIDGETS("AMX4"), 1404 WIDGETS("ADX1", t234_adx1_tx), 1405 WIDGETS("ADX2", t234_adx2_tx), 1406 WIDGETS("ADX3", t234_adx3_tx), 1407 WIDGETS("ADX4", t234_adx4_tx), 1408 TX_WIDGETS("ADX1 TX1"), 1409 TX_WIDGETS("ADX1 TX2"), 1410 TX_WIDGETS("ADX1 TX3"), 1411 TX_WIDGETS("ADX1 TX4"), 1412 TX_WIDGETS("ADX2 TX1"), 1413 TX_WIDGETS("ADX2 TX2"), 1414 TX_WIDGETS("ADX2 TX3"), 1415 TX_WIDGETS("ADX2 TX4"), 1416 TX_WIDGETS("ADX3 TX1"), 1417 TX_WIDGETS("ADX3 TX2"), 1418 TX_WIDGETS("ADX3 TX3"), 1419 TX_WIDGETS("ADX3 TX4"), 1420 TX_WIDGETS("ADX4 TX1"), 1421 TX_WIDGETS("ADX4 TX2"), 1422 TX_WIDGETS("ADX4 TX3"), 1423 TX_WIDGETS("ADX4 TX4"), 1424 WIDGETS("MIXER1 RX1", t186_mixer11_tx), 1425 WIDGETS("MIXER1 RX2", t186_mixer12_tx), 1426 WIDGETS("MIXER1 RX3", t186_mixer13_tx), 1427 WIDGETS("MIXER1 RX4", t186_mixer14_tx), 1428 WIDGETS("MIXER1 RX5", t186_mixer15_tx), 1429 WIDGETS("MIXER1 RX6", t186_mixer16_tx), 1430 WIDGETS("MIXER1 RX7", t186_mixer17_tx), 1431 WIDGETS("MIXER1 RX8", t186_mixer18_tx), 1432 WIDGETS("MIXER1 RX9", t186_mixer19_tx), 1433 WIDGETS("MIXER1 RX10", t186_mixer110_tx), 1434 TX_WIDGETS("MIXER1 TX1"), 1435 TX_WIDGETS("MIXER1 TX2"), 1436 TX_WIDGETS("MIXER1 TX3"), 1437 TX_WIDGETS("MIXER1 TX4"), 1438 TX_WIDGETS("MIXER1 TX5"), 1439 WIDGETS("ASRC1 RX1", t234_asrc11_tx), 1440 WIDGETS("ASRC1 RX2", t234_asrc12_tx), 1441 WIDGETS("ASRC1 RX3", t234_asrc13_tx), 1442 WIDGETS("ASRC1 RX4", t234_asrc14_tx), 1443 WIDGETS("ASRC1 RX5", t234_asrc15_tx), 1444 WIDGETS("ASRC1 RX6", t234_asrc16_tx), 1445 WIDGETS("ASRC1 RX7", t234_asrc17_tx), 1446 TX_WIDGETS("ASRC1 TX1"), 1447 TX_WIDGETS("ASRC1 TX2"), 1448 TX_WIDGETS("ASRC1 TX3"), 1449 TX_WIDGETS("ASRC1 TX4"), 1450 TX_WIDGETS("ASRC1 TX5"), 1451 TX_WIDGETS("ASRC1 TX6"), 1452 WIDGETS("OPE1", t186_ope1_tx), 1453 }; 1454 1455 static const struct snd_soc_dapm_widget tegra264_ahub_widgets[] = { 1456 WIDGETS("ADMAIF1", t264_admaif1_tx), 1457 WIDGETS("ADMAIF2", t264_admaif2_tx), 1458 WIDGETS("ADMAIF3", t264_admaif3_tx), 1459 WIDGETS("ADMAIF4", t264_admaif4_tx), 1460 WIDGETS("ADMAIF5", t264_admaif5_tx), 1461 WIDGETS("ADMAIF6", t264_admaif6_tx), 1462 WIDGETS("ADMAIF7", t264_admaif7_tx), 1463 WIDGETS("ADMAIF8", t264_admaif8_tx), 1464 WIDGETS("ADMAIF9", t264_admaif9_tx), 1465 WIDGETS("ADMAIF10", t264_admaif10_tx), 1466 WIDGETS("ADMAIF11", t264_admaif11_tx), 1467 WIDGETS("ADMAIF12", t264_admaif12_tx), 1468 WIDGETS("ADMAIF13", t264_admaif13_tx), 1469 WIDGETS("ADMAIF14", t264_admaif14_tx), 1470 WIDGETS("ADMAIF15", t264_admaif15_tx), 1471 WIDGETS("ADMAIF16", t264_admaif16_tx), 1472 WIDGETS("ADMAIF17", t264_admaif17_tx), 1473 WIDGETS("ADMAIF18", t264_admaif18_tx), 1474 WIDGETS("ADMAIF19", t264_admaif19_tx), 1475 WIDGETS("ADMAIF20", t264_admaif20_tx), 1476 WIDGETS("ADMAIF21", t264_admaif21_tx), 1477 WIDGETS("ADMAIF22", t264_admaif22_tx), 1478 WIDGETS("ADMAIF23", t264_admaif23_tx), 1479 WIDGETS("ADMAIF24", t264_admaif24_tx), 1480 WIDGETS("ADMAIF25", t264_admaif25_tx), 1481 WIDGETS("ADMAIF26", t264_admaif26_tx), 1482 WIDGETS("ADMAIF27", t264_admaif27_tx), 1483 WIDGETS("ADMAIF28", t264_admaif28_tx), 1484 WIDGETS("ADMAIF29", t264_admaif29_tx), 1485 WIDGETS("ADMAIF30", t264_admaif30_tx), 1486 WIDGETS("ADMAIF31", t264_admaif31_tx), 1487 WIDGETS("ADMAIF32", t264_admaif32_tx), 1488 WIDGETS("I2S1", t264_i2s1_tx), 1489 WIDGETS("I2S2", t264_i2s2_tx), 1490 WIDGETS("I2S3", t264_i2s3_tx), 1491 WIDGETS("I2S4", t264_i2s4_tx), 1492 WIDGETS("I2S5", t264_i2s5_tx), 1493 WIDGETS("I2S6", t264_i2s6_tx), 1494 WIDGETS("I2S7", t264_i2s7_tx), 1495 WIDGETS("I2S8", t264_i2s8_tx), 1496 TX_WIDGETS("DMIC1"), 1497 TX_WIDGETS("DMIC2"), 1498 WIDGETS("DSPK1", t264_dspk1_tx), 1499 WIDGETS("SFC1", t264_sfc1_tx), 1500 WIDGETS("SFC2", t264_sfc2_tx), 1501 WIDGETS("SFC3", t264_sfc3_tx), 1502 WIDGETS("SFC4", t264_sfc4_tx), 1503 WIDGETS("MVC1", t264_mvc1_tx), 1504 WIDGETS("MVC2", t264_mvc2_tx), 1505 WIDGETS("AMX1 RX1", t264_amx11_tx), 1506 WIDGETS("AMX1 RX2", t264_amx12_tx), 1507 WIDGETS("AMX1 RX3", t264_amx13_tx), 1508 WIDGETS("AMX1 RX4", t264_amx14_tx), 1509 WIDGETS("AMX2 RX1", t264_amx21_tx), 1510 WIDGETS("AMX2 RX2", t264_amx22_tx), 1511 WIDGETS("AMX2 RX3", t264_amx23_tx), 1512 WIDGETS("AMX2 RX4", t264_amx24_tx), 1513 WIDGETS("AMX3 RX1", t264_amx31_tx), 1514 WIDGETS("AMX3 RX2", t264_amx32_tx), 1515 WIDGETS("AMX3 RX3", t264_amx33_tx), 1516 WIDGETS("AMX3 RX4", t264_amx34_tx), 1517 WIDGETS("AMX4 RX1", t264_amx41_tx), 1518 WIDGETS("AMX4 RX2", t264_amx42_tx), 1519 WIDGETS("AMX4 RX3", t264_amx43_tx), 1520 WIDGETS("AMX4 RX4", t264_amx44_tx), 1521 WIDGETS("AMX5 RX1", t264_amx51_tx), 1522 WIDGETS("AMX5 RX2", t264_amx52_tx), 1523 WIDGETS("AMX5 RX3", t264_amx53_tx), 1524 WIDGETS("AMX5 RX4", t264_amx54_tx), 1525 WIDGETS("AMX6 RX1", t264_amx61_tx), 1526 WIDGETS("AMX6 RX2", t264_amx62_tx), 1527 WIDGETS("AMX6 RX3", t264_amx63_tx), 1528 WIDGETS("AMX6 RX4", t264_amx64_tx), 1529 TX_WIDGETS("AMX1"), 1530 TX_WIDGETS("AMX2"), 1531 TX_WIDGETS("AMX3"), 1532 TX_WIDGETS("AMX4"), 1533 TX_WIDGETS("AMX5"), 1534 TX_WIDGETS("AMX6"), 1535 WIDGETS("ADX1", t264_adx1_tx), 1536 WIDGETS("ADX2", t264_adx2_tx), 1537 WIDGETS("ADX3", t264_adx3_tx), 1538 WIDGETS("ADX4", t264_adx4_tx), 1539 WIDGETS("ADX5", t264_adx5_tx), 1540 WIDGETS("ADX6", t264_adx6_tx), 1541 TX_WIDGETS("ADX1 TX1"), 1542 TX_WIDGETS("ADX1 TX2"), 1543 TX_WIDGETS("ADX1 TX3"), 1544 TX_WIDGETS("ADX1 TX4"), 1545 TX_WIDGETS("ADX2 TX1"), 1546 TX_WIDGETS("ADX2 TX2"), 1547 TX_WIDGETS("ADX2 TX3"), 1548 TX_WIDGETS("ADX2 TX4"), 1549 TX_WIDGETS("ADX3 TX1"), 1550 TX_WIDGETS("ADX3 TX2"), 1551 TX_WIDGETS("ADX3 TX3"), 1552 TX_WIDGETS("ADX3 TX4"), 1553 TX_WIDGETS("ADX4 TX1"), 1554 TX_WIDGETS("ADX4 TX2"), 1555 TX_WIDGETS("ADX4 TX3"), 1556 TX_WIDGETS("ADX4 TX4"), 1557 TX_WIDGETS("ADX5 TX1"), 1558 TX_WIDGETS("ADX5 TX2"), 1559 TX_WIDGETS("ADX5 TX3"), 1560 TX_WIDGETS("ADX5 TX4"), 1561 TX_WIDGETS("ADX6 TX1"), 1562 TX_WIDGETS("ADX6 TX2"), 1563 TX_WIDGETS("ADX6 TX3"), 1564 TX_WIDGETS("ADX6 TX4"), 1565 WIDGETS("MIXER1 RX1", t264_mixer11_tx), 1566 WIDGETS("MIXER1 RX2", t264_mixer12_tx), 1567 WIDGETS("MIXER1 RX3", t264_mixer13_tx), 1568 WIDGETS("MIXER1 RX4", t264_mixer14_tx), 1569 WIDGETS("MIXER1 RX5", t264_mixer15_tx), 1570 WIDGETS("MIXER1 RX6", t264_mixer16_tx), 1571 WIDGETS("MIXER1 RX7", t264_mixer17_tx), 1572 WIDGETS("MIXER1 RX8", t264_mixer18_tx), 1573 WIDGETS("MIXER1 RX9", t264_mixer19_tx), 1574 WIDGETS("MIXER1 RX10", t264_mixer110_tx), 1575 TX_WIDGETS("MIXER1 TX1"), 1576 TX_WIDGETS("MIXER1 TX2"), 1577 TX_WIDGETS("MIXER1 TX3"), 1578 TX_WIDGETS("MIXER1 TX4"), 1579 TX_WIDGETS("MIXER1 TX5"), 1580 WIDGETS("ASRC1 RX1", t264_asrc11_tx), 1581 WIDGETS("ASRC1 RX2", t264_asrc12_tx), 1582 WIDGETS("ASRC1 RX3", t264_asrc13_tx), 1583 WIDGETS("ASRC1 RX4", t264_asrc14_tx), 1584 WIDGETS("ASRC1 RX5", t264_asrc15_tx), 1585 WIDGETS("ASRC1 RX6", t264_asrc16_tx), 1586 WIDGETS("ASRC1 RX7", t264_asrc17_tx), 1587 TX_WIDGETS("ASRC1 TX1"), 1588 TX_WIDGETS("ASRC1 TX2"), 1589 TX_WIDGETS("ASRC1 TX3"), 1590 TX_WIDGETS("ASRC1 TX4"), 1591 TX_WIDGETS("ASRC1 TX5"), 1592 TX_WIDGETS("ASRC1 TX6"), 1593 WIDGETS("OPE1", t264_ope1_tx), 1594 }; 1595 1596 #define TEGRA_COMMON_MUX_ROUTES(name) \ 1597 { name " XBAR-TX", NULL, name " Mux" }, \ 1598 { name " Mux", "ADMAIF1", "ADMAIF1 XBAR-RX" }, \ 1599 { name " Mux", "ADMAIF2", "ADMAIF2 XBAR-RX" }, \ 1600 { name " Mux", "ADMAIF3", "ADMAIF3 XBAR-RX" }, \ 1601 { name " Mux", "ADMAIF4", "ADMAIF4 XBAR-RX" }, \ 1602 { name " Mux", "ADMAIF5", "ADMAIF5 XBAR-RX" }, \ 1603 { name " Mux", "ADMAIF6", "ADMAIF6 XBAR-RX" }, \ 1604 { name " Mux", "ADMAIF7", "ADMAIF7 XBAR-RX" }, \ 1605 { name " Mux", "ADMAIF8", "ADMAIF8 XBAR-RX" }, \ 1606 { name " Mux", "ADMAIF9", "ADMAIF9 XBAR-RX" }, \ 1607 { name " Mux", "ADMAIF10", "ADMAIF10 XBAR-RX" }, \ 1608 { name " Mux", "I2S1", "I2S1 XBAR-RX" }, \ 1609 { name " Mux", "I2S2", "I2S2 XBAR-RX" }, \ 1610 { name " Mux", "I2S3", "I2S3 XBAR-RX" }, \ 1611 { name " Mux", "I2S4", "I2S4 XBAR-RX" }, \ 1612 { name " Mux", "I2S5", "I2S5 XBAR-RX" }, \ 1613 { name " Mux", "DMIC1", "DMIC1 XBAR-RX" }, \ 1614 { name " Mux", "DMIC2", "DMIC2 XBAR-RX" }, \ 1615 { name " Mux", "SFC1", "SFC1 XBAR-RX" }, \ 1616 { name " Mux", "SFC2", "SFC2 XBAR-RX" }, \ 1617 { name " Mux", "SFC3", "SFC3 XBAR-RX" }, \ 1618 { name " Mux", "SFC4", "SFC4 XBAR-RX" }, \ 1619 { name " Mux", "MVC1", "MVC1 XBAR-RX" }, \ 1620 { name " Mux", "MVC2", "MVC2 XBAR-RX" }, \ 1621 { name " Mux", "AMX1", "AMX1 XBAR-RX" }, \ 1622 { name " Mux", "AMX2", "AMX2 XBAR-RX" }, \ 1623 { name " Mux", "ADX1 TX1", "ADX1 TX1 XBAR-RX" }, \ 1624 { name " Mux", "ADX1 TX2", "ADX1 TX2 XBAR-RX" }, \ 1625 { name " Mux", "ADX1 TX3", "ADX1 TX3 XBAR-RX" }, \ 1626 { name " Mux", "ADX1 TX4", "ADX1 TX4 XBAR-RX" }, \ 1627 { name " Mux", "ADX2 TX1", "ADX2 TX1 XBAR-RX" }, \ 1628 { name " Mux", "ADX2 TX2", "ADX2 TX2 XBAR-RX" }, \ 1629 { name " Mux", "ADX2 TX3", "ADX2 TX3 XBAR-RX" }, \ 1630 { name " Mux", "ADX2 TX4", "ADX2 TX4 XBAR-RX" }, \ 1631 { name " Mux", "MIXER1 TX1", "MIXER1 TX1 XBAR-RX" }, \ 1632 { name " Mux", "MIXER1 TX2", "MIXER1 TX2 XBAR-RX" }, \ 1633 { name " Mux", "MIXER1 TX3", "MIXER1 TX3 XBAR-RX" }, \ 1634 { name " Mux", "MIXER1 TX4", "MIXER1 TX4 XBAR-RX" }, \ 1635 { name " Mux", "MIXER1 TX5", "MIXER1 TX5 XBAR-RX" }, \ 1636 { name " Mux", "OPE1", "OPE1 XBAR-RX" }, 1637 1638 #define TEGRA210_ONLY_MUX_ROUTES(name) \ 1639 { name " Mux", "DMIC3", "DMIC3 XBAR-RX" }, \ 1640 { name " Mux", "OPE2", "OPE2 XBAR-RX" }, 1641 1642 #define TEGRA186_ONLY_MUX_ROUTES(name) \ 1643 { name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \ 1644 { name " Mux", "ADMAIF12", "ADMAIF12 XBAR-RX" }, \ 1645 { name " Mux", "ADMAIF13", "ADMAIF13 XBAR-RX" }, \ 1646 { name " Mux", "ADMAIF14", "ADMAIF14 XBAR-RX" }, \ 1647 { name " Mux", "ADMAIF15", "ADMAIF15 XBAR-RX" }, \ 1648 { name " Mux", "ADMAIF16", "ADMAIF16 XBAR-RX" }, \ 1649 { name " Mux", "ADMAIF17", "ADMAIF17 XBAR-RX" }, \ 1650 { name " Mux", "ADMAIF18", "ADMAIF18 XBAR-RX" }, \ 1651 { name " Mux", "ADMAIF19", "ADMAIF19 XBAR-RX" }, \ 1652 { name " Mux", "ADMAIF20", "ADMAIF20 XBAR-RX" }, \ 1653 { name " Mux", "I2S6", "I2S6 XBAR-RX" }, \ 1654 { name " Mux", "DMIC3", "DMIC3 XBAR-RX" }, \ 1655 { name " Mux", "DMIC4", "DMIC4 XBAR-RX" }, \ 1656 { name " Mux", "AMX3", "AMX3 XBAR-RX" }, \ 1657 { name " Mux", "AMX4", "AMX4 XBAR-RX" }, \ 1658 { name " Mux", "ADX3 TX1", "ADX3 TX1 XBAR-RX" }, \ 1659 { name " Mux", "ADX3 TX2", "ADX3 TX2 XBAR-RX" }, \ 1660 { name " Mux", "ADX3 TX3", "ADX3 TX3 XBAR-RX" }, \ 1661 { name " Mux", "ADX3 TX4", "ADX3 TX4 XBAR-RX" }, \ 1662 { name " Mux", "ADX4 TX1", "ADX4 TX1 XBAR-RX" }, \ 1663 { name " Mux", "ADX4 TX2", "ADX4 TX2 XBAR-RX" }, \ 1664 { name " Mux", "ADX4 TX3", "ADX4 TX3 XBAR-RX" }, \ 1665 { name " Mux", "ADX4 TX4", "ADX4 TX4 XBAR-RX" }, \ 1666 { name " Mux", "ASRC1 TX1", "ASRC1 TX1 XBAR-RX" }, \ 1667 { name " Mux", "ASRC1 TX2", "ASRC1 TX2 XBAR-RX" }, \ 1668 { name " Mux", "ASRC1 TX3", "ASRC1 TX3 XBAR-RX" }, \ 1669 { name " Mux", "ASRC1 TX4", "ASRC1 TX4 XBAR-RX" }, \ 1670 { name " Mux", "ASRC1 TX5", "ASRC1 TX5 XBAR-RX" }, \ 1671 { name " Mux", "ASRC1 TX6", "ASRC1 TX6 XBAR-RX" }, 1672 1673 #define TEGRA264_ONLY_MUX_ROUTES(name) \ 1674 { name " Mux", "ADMAIF11", "ADMAIF11 XBAR-RX" }, \ 1675 { name " Mux", "ADMAIF12", "ADMAIF12 XBAR-RX" }, \ 1676 { name " Mux", "ADMAIF13", "ADMAIF13 XBAR-RX" }, \ 1677 { name " Mux", "ADMAIF14", "ADMAIF14 XBAR-RX" }, \ 1678 { name " Mux", "ADMAIF15", "ADMAIF15 XBAR-RX" }, \ 1679 { name " Mux", "ADMAIF16", "ADMAIF16 XBAR-RX" }, \ 1680 { name " Mux", "ADMAIF17", "ADMAIF17 XBAR-RX" }, \ 1681 { name " Mux", "ADMAIF18", "ADMAIF18 XBAR-RX" }, \ 1682 { name " Mux", "ADMAIF19", "ADMAIF19 XBAR-RX" }, \ 1683 { name " Mux", "ADMAIF20", "ADMAIF20 XBAR-RX" }, \ 1684 { name " Mux", "ADMAIF21", "ADMAIF21 XBAR-RX" }, \ 1685 { name " Mux", "ADMAIF22", "ADMAIF22 XBAR-RX" }, \ 1686 { name " Mux", "ADMAIF23", "ADMAIF23 XBAR-RX" }, \ 1687 { name " Mux", "ADMAIF24", "ADMAIF24 XBAR-RX" }, \ 1688 { name " Mux", "ADMAIF25", "ADMAIF25 XBAR-RX" }, \ 1689 { name " Mux", "ADMAIF26", "ADMAIF26 XBAR-RX" }, \ 1690 { name " Mux", "ADMAIF27", "ADMAIF27 XBAR-RX" }, \ 1691 { name " Mux", "ADMAIF28", "ADMAIF28 XBAR-RX" }, \ 1692 { name " Mux", "ADMAIF29", "ADMAIF29 XBAR-RX" }, \ 1693 { name " Mux", "ADMAIF30", "ADMAIF30 XBAR-RX" }, \ 1694 { name " Mux", "ADMAIF31", "ADMAIF31 XBAR-RX" }, \ 1695 { name " Mux", "ADMAIF32", "ADMAIF32 XBAR-RX" }, \ 1696 { name " Mux", "I2S6", "I2S6 XBAR-RX" }, \ 1697 { name " Mux", "I2S7", "I2S7 XBAR-RX" }, \ 1698 { name " Mux", "I2S8", "I2S8 XBAR-RX" }, \ 1699 { name " Mux", "AMX3", "AMX3 XBAR-RX" }, \ 1700 { name " Mux", "AMX4", "AMX4 XBAR-RX" }, \ 1701 { name " Mux", "AMX5", "AMX5 XBAR-RX" }, \ 1702 { name " Mux", "AMX6", "AMX6 XBAR-RX" }, \ 1703 { name " Mux", "ADX3 TX1", "ADX3 TX1 XBAR-RX" }, \ 1704 { name " Mux", "ADX3 TX2", "ADX3 TX2 XBAR-RX" }, \ 1705 { name " Mux", "ADX3 TX3", "ADX3 TX3 XBAR-RX" }, \ 1706 { name " Mux", "ADX3 TX4", "ADX3 TX4 XBAR-RX" }, \ 1707 { name " Mux", "ADX4 TX1", "ADX4 TX1 XBAR-RX" }, \ 1708 { name " Mux", "ADX4 TX2", "ADX4 TX2 XBAR-RX" }, \ 1709 { name " Mux", "ADX4 TX3", "ADX4 TX3 XBAR-RX" }, \ 1710 { name " Mux", "ADX4 TX4", "ADX4 TX4 XBAR-RX" }, \ 1711 { name " Mux", "ADX5 TX1", "ADX5 TX1 XBAR-RX" }, \ 1712 { name " Mux", "ADX5 TX2", "ADX5 TX2 XBAR-RX" }, \ 1713 { name " Mux", "ADX5 TX3", "ADX5 TX3 XBAR-RX" }, \ 1714 { name " Mux", "ADX5 TX4", "ADX5 TX4 XBAR-RX" }, \ 1715 { name " Mux", "ADX6 TX1", "ADX6 TX1 XBAR-RX" }, \ 1716 { name " Mux", "ADX6 TX2", "ADX6 TX2 XBAR-RX" }, \ 1717 { name " Mux", "ADX6 TX3", "ADX6 TX3 XBAR-RX" }, \ 1718 { name " Mux", "ADX6 TX4", "ADX6 TX4 XBAR-RX" }, \ 1719 { name " Mux", "ASRC1 TX1", "ASRC1 TX1 XBAR-RX" }, \ 1720 { name " Mux", "ASRC1 TX2", "ASRC1 TX2 XBAR-RX" }, \ 1721 { name " Mux", "ASRC1 TX3", "ASRC1 TX3 XBAR-RX" }, \ 1722 { name " Mux", "ASRC1 TX4", "ASRC1 TX4 XBAR-RX" }, \ 1723 { name " Mux", "ASRC1 TX5", "ASRC1 TX5 XBAR-RX" }, \ 1724 { name " Mux", "ASRC1 TX6", "ASRC1 TX6 XBAR-RX" }, 1725 1726 #define TEGRA210_MUX_ROUTES(name) \ 1727 TEGRA_COMMON_MUX_ROUTES(name) \ 1728 TEGRA210_ONLY_MUX_ROUTES(name) 1729 1730 #define TEGRA186_MUX_ROUTES(name) \ 1731 TEGRA_COMMON_MUX_ROUTES(name) \ 1732 TEGRA186_ONLY_MUX_ROUTES(name) 1733 1734 #define TEGRA264_MUX_ROUTES(name) \ 1735 TEGRA_COMMON_MUX_ROUTES(name) \ 1736 TEGRA264_ONLY_MUX_ROUTES(name) 1737 1738 /* Connect FEs with XBAR */ 1739 #define TEGRA_FE_ROUTES(name) \ 1740 { name " XBAR-Playback", NULL, name " Playback" }, \ 1741 { name " XBAR-RX", NULL, name " XBAR-Playback"}, \ 1742 { name " XBAR-Capture", NULL, name " XBAR-TX" }, \ 1743 { name " Capture", NULL, name " XBAR-Capture" }, 1744 1745 static const struct snd_soc_dapm_route tegra210_ahub_routes[] = { 1746 TEGRA_FE_ROUTES("ADMAIF1") 1747 TEGRA_FE_ROUTES("ADMAIF2") 1748 TEGRA_FE_ROUTES("ADMAIF3") 1749 TEGRA_FE_ROUTES("ADMAIF4") 1750 TEGRA_FE_ROUTES("ADMAIF5") 1751 TEGRA_FE_ROUTES("ADMAIF6") 1752 TEGRA_FE_ROUTES("ADMAIF7") 1753 TEGRA_FE_ROUTES("ADMAIF8") 1754 TEGRA_FE_ROUTES("ADMAIF9") 1755 TEGRA_FE_ROUTES("ADMAIF10") 1756 TEGRA210_MUX_ROUTES("ADMAIF1") 1757 TEGRA210_MUX_ROUTES("ADMAIF2") 1758 TEGRA210_MUX_ROUTES("ADMAIF3") 1759 TEGRA210_MUX_ROUTES("ADMAIF4") 1760 TEGRA210_MUX_ROUTES("ADMAIF5") 1761 TEGRA210_MUX_ROUTES("ADMAIF6") 1762 TEGRA210_MUX_ROUTES("ADMAIF7") 1763 TEGRA210_MUX_ROUTES("ADMAIF8") 1764 TEGRA210_MUX_ROUTES("ADMAIF9") 1765 TEGRA210_MUX_ROUTES("ADMAIF10") 1766 TEGRA210_MUX_ROUTES("I2S1") 1767 TEGRA210_MUX_ROUTES("I2S2") 1768 TEGRA210_MUX_ROUTES("I2S3") 1769 TEGRA210_MUX_ROUTES("I2S4") 1770 TEGRA210_MUX_ROUTES("I2S5") 1771 TEGRA210_MUX_ROUTES("SFC1") 1772 TEGRA210_MUX_ROUTES("SFC2") 1773 TEGRA210_MUX_ROUTES("SFC3") 1774 TEGRA210_MUX_ROUTES("SFC4") 1775 TEGRA210_MUX_ROUTES("MVC1") 1776 TEGRA210_MUX_ROUTES("MVC2") 1777 TEGRA210_MUX_ROUTES("AMX1 RX1") 1778 TEGRA210_MUX_ROUTES("AMX1 RX2") 1779 TEGRA210_MUX_ROUTES("AMX1 RX3") 1780 TEGRA210_MUX_ROUTES("AMX1 RX4") 1781 TEGRA210_MUX_ROUTES("AMX2 RX1") 1782 TEGRA210_MUX_ROUTES("AMX2 RX2") 1783 TEGRA210_MUX_ROUTES("AMX2 RX3") 1784 TEGRA210_MUX_ROUTES("AMX2 RX4") 1785 TEGRA210_MUX_ROUTES("ADX1") 1786 TEGRA210_MUX_ROUTES("ADX2") 1787 TEGRA210_MUX_ROUTES("MIXER1 RX1") 1788 TEGRA210_MUX_ROUTES("MIXER1 RX2") 1789 TEGRA210_MUX_ROUTES("MIXER1 RX3") 1790 TEGRA210_MUX_ROUTES("MIXER1 RX4") 1791 TEGRA210_MUX_ROUTES("MIXER1 RX5") 1792 TEGRA210_MUX_ROUTES("MIXER1 RX6") 1793 TEGRA210_MUX_ROUTES("MIXER1 RX7") 1794 TEGRA210_MUX_ROUTES("MIXER1 RX8") 1795 TEGRA210_MUX_ROUTES("MIXER1 RX9") 1796 TEGRA210_MUX_ROUTES("MIXER1 RX10") 1797 TEGRA210_MUX_ROUTES("OPE1") 1798 TEGRA210_MUX_ROUTES("OPE2") 1799 }; 1800 1801 static const struct snd_soc_dapm_route tegra186_ahub_routes[] = { 1802 TEGRA_FE_ROUTES("ADMAIF1") 1803 TEGRA_FE_ROUTES("ADMAIF2") 1804 TEGRA_FE_ROUTES("ADMAIF3") 1805 TEGRA_FE_ROUTES("ADMAIF4") 1806 TEGRA_FE_ROUTES("ADMAIF5") 1807 TEGRA_FE_ROUTES("ADMAIF6") 1808 TEGRA_FE_ROUTES("ADMAIF7") 1809 TEGRA_FE_ROUTES("ADMAIF8") 1810 TEGRA_FE_ROUTES("ADMAIF9") 1811 TEGRA_FE_ROUTES("ADMAIF10") 1812 TEGRA_FE_ROUTES("ADMAIF11") 1813 TEGRA_FE_ROUTES("ADMAIF12") 1814 TEGRA_FE_ROUTES("ADMAIF13") 1815 TEGRA_FE_ROUTES("ADMAIF14") 1816 TEGRA_FE_ROUTES("ADMAIF15") 1817 TEGRA_FE_ROUTES("ADMAIF16") 1818 TEGRA_FE_ROUTES("ADMAIF17") 1819 TEGRA_FE_ROUTES("ADMAIF18") 1820 TEGRA_FE_ROUTES("ADMAIF19") 1821 TEGRA_FE_ROUTES("ADMAIF20") 1822 TEGRA186_MUX_ROUTES("ADMAIF1") 1823 TEGRA186_MUX_ROUTES("ADMAIF2") 1824 TEGRA186_MUX_ROUTES("ADMAIF3") 1825 TEGRA186_MUX_ROUTES("ADMAIF4") 1826 TEGRA186_MUX_ROUTES("ADMAIF5") 1827 TEGRA186_MUX_ROUTES("ADMAIF6") 1828 TEGRA186_MUX_ROUTES("ADMAIF7") 1829 TEGRA186_MUX_ROUTES("ADMAIF8") 1830 TEGRA186_MUX_ROUTES("ADMAIF9") 1831 TEGRA186_MUX_ROUTES("ADMAIF10") 1832 TEGRA186_MUX_ROUTES("ADMAIF11") 1833 TEGRA186_MUX_ROUTES("ADMAIF12") 1834 TEGRA186_MUX_ROUTES("ADMAIF13") 1835 TEGRA186_MUX_ROUTES("ADMAIF14") 1836 TEGRA186_MUX_ROUTES("ADMAIF15") 1837 TEGRA186_MUX_ROUTES("ADMAIF16") 1838 TEGRA186_MUX_ROUTES("ADMAIF17") 1839 TEGRA186_MUX_ROUTES("ADMAIF18") 1840 TEGRA186_MUX_ROUTES("ADMAIF19") 1841 TEGRA186_MUX_ROUTES("ADMAIF20") 1842 TEGRA186_MUX_ROUTES("I2S1") 1843 TEGRA186_MUX_ROUTES("I2S2") 1844 TEGRA186_MUX_ROUTES("I2S3") 1845 TEGRA186_MUX_ROUTES("I2S4") 1846 TEGRA186_MUX_ROUTES("I2S5") 1847 TEGRA186_MUX_ROUTES("I2S6") 1848 TEGRA186_MUX_ROUTES("DSPK1") 1849 TEGRA186_MUX_ROUTES("DSPK2") 1850 TEGRA186_MUX_ROUTES("SFC1") 1851 TEGRA186_MUX_ROUTES("SFC2") 1852 TEGRA186_MUX_ROUTES("SFC3") 1853 TEGRA186_MUX_ROUTES("SFC4") 1854 TEGRA186_MUX_ROUTES("MVC1") 1855 TEGRA186_MUX_ROUTES("MVC2") 1856 TEGRA186_MUX_ROUTES("AMX1 RX1") 1857 TEGRA186_MUX_ROUTES("AMX1 RX2") 1858 TEGRA186_MUX_ROUTES("AMX1 RX3") 1859 TEGRA186_MUX_ROUTES("AMX1 RX4") 1860 TEGRA186_MUX_ROUTES("AMX2 RX1") 1861 TEGRA186_MUX_ROUTES("AMX2 RX2") 1862 TEGRA186_MUX_ROUTES("AMX2 RX3") 1863 TEGRA186_MUX_ROUTES("AMX2 RX4") 1864 TEGRA186_MUX_ROUTES("AMX3 RX1") 1865 TEGRA186_MUX_ROUTES("AMX3 RX2") 1866 TEGRA186_MUX_ROUTES("AMX3 RX3") 1867 TEGRA186_MUX_ROUTES("AMX3 RX4") 1868 TEGRA186_MUX_ROUTES("AMX4 RX1") 1869 TEGRA186_MUX_ROUTES("AMX4 RX2") 1870 TEGRA186_MUX_ROUTES("AMX4 RX3") 1871 TEGRA186_MUX_ROUTES("AMX4 RX4") 1872 TEGRA186_MUX_ROUTES("ADX1") 1873 TEGRA186_MUX_ROUTES("ADX2") 1874 TEGRA186_MUX_ROUTES("ADX3") 1875 TEGRA186_MUX_ROUTES("ADX4") 1876 TEGRA186_MUX_ROUTES("MIXER1 RX1") 1877 TEGRA186_MUX_ROUTES("MIXER1 RX2") 1878 TEGRA186_MUX_ROUTES("MIXER1 RX3") 1879 TEGRA186_MUX_ROUTES("MIXER1 RX4") 1880 TEGRA186_MUX_ROUTES("MIXER1 RX5") 1881 TEGRA186_MUX_ROUTES("MIXER1 RX6") 1882 TEGRA186_MUX_ROUTES("MIXER1 RX7") 1883 TEGRA186_MUX_ROUTES("MIXER1 RX8") 1884 TEGRA186_MUX_ROUTES("MIXER1 RX9") 1885 TEGRA186_MUX_ROUTES("MIXER1 RX10") 1886 TEGRA186_MUX_ROUTES("ASRC1 RX1") 1887 TEGRA186_MUX_ROUTES("ASRC1 RX2") 1888 TEGRA186_MUX_ROUTES("ASRC1 RX3") 1889 TEGRA186_MUX_ROUTES("ASRC1 RX4") 1890 TEGRA186_MUX_ROUTES("ASRC1 RX5") 1891 TEGRA186_MUX_ROUTES("ASRC1 RX6") 1892 TEGRA186_MUX_ROUTES("ASRC1 RX7") 1893 TEGRA186_MUX_ROUTES("OPE1") 1894 }; 1895 1896 static const struct snd_soc_dapm_route tegra264_ahub_routes[] = { 1897 TEGRA_FE_ROUTES("ADMAIF1") 1898 TEGRA_FE_ROUTES("ADMAIF2") 1899 TEGRA_FE_ROUTES("ADMAIF3") 1900 TEGRA_FE_ROUTES("ADMAIF4") 1901 TEGRA_FE_ROUTES("ADMAIF5") 1902 TEGRA_FE_ROUTES("ADMAIF6") 1903 TEGRA_FE_ROUTES("ADMAIF7") 1904 TEGRA_FE_ROUTES("ADMAIF8") 1905 TEGRA_FE_ROUTES("ADMAIF9") 1906 TEGRA_FE_ROUTES("ADMAIF10") 1907 TEGRA_FE_ROUTES("ADMAIF11") 1908 TEGRA_FE_ROUTES("ADMAIF12") 1909 TEGRA_FE_ROUTES("ADMAIF13") 1910 TEGRA_FE_ROUTES("ADMAIF14") 1911 TEGRA_FE_ROUTES("ADMAIF15") 1912 TEGRA_FE_ROUTES("ADMAIF16") 1913 TEGRA_FE_ROUTES("ADMAIF17") 1914 TEGRA_FE_ROUTES("ADMAIF18") 1915 TEGRA_FE_ROUTES("ADMAIF19") 1916 TEGRA_FE_ROUTES("ADMAIF20") 1917 TEGRA_FE_ROUTES("ADMAIF21") 1918 TEGRA_FE_ROUTES("ADMAIF22") 1919 TEGRA_FE_ROUTES("ADMAIF23") 1920 TEGRA_FE_ROUTES("ADMAIF24") 1921 TEGRA_FE_ROUTES("ADMAIF25") 1922 TEGRA_FE_ROUTES("ADMAIF26") 1923 TEGRA_FE_ROUTES("ADMAIF27") 1924 TEGRA_FE_ROUTES("ADMAIF28") 1925 TEGRA_FE_ROUTES("ADMAIF29") 1926 TEGRA_FE_ROUTES("ADMAIF30") 1927 TEGRA_FE_ROUTES("ADMAIF31") 1928 TEGRA_FE_ROUTES("ADMAIF32") 1929 TEGRA264_MUX_ROUTES("ADMAIF1") 1930 TEGRA264_MUX_ROUTES("ADMAIF2") 1931 TEGRA264_MUX_ROUTES("ADMAIF3") 1932 TEGRA264_MUX_ROUTES("ADMAIF4") 1933 TEGRA264_MUX_ROUTES("ADMAIF5") 1934 TEGRA264_MUX_ROUTES("ADMAIF6") 1935 TEGRA264_MUX_ROUTES("ADMAIF7") 1936 TEGRA264_MUX_ROUTES("ADMAIF8") 1937 TEGRA264_MUX_ROUTES("ADMAIF9") 1938 TEGRA264_MUX_ROUTES("ADMAIF10") 1939 TEGRA264_MUX_ROUTES("ADMAIF11") 1940 TEGRA264_MUX_ROUTES("ADMAIF12") 1941 TEGRA264_MUX_ROUTES("ADMAIF13") 1942 TEGRA264_MUX_ROUTES("ADMAIF14") 1943 TEGRA264_MUX_ROUTES("ADMAIF15") 1944 TEGRA264_MUX_ROUTES("ADMAIF16") 1945 TEGRA264_MUX_ROUTES("ADMAIF17") 1946 TEGRA264_MUX_ROUTES("ADMAIF18") 1947 TEGRA264_MUX_ROUTES("ADMAIF19") 1948 TEGRA264_MUX_ROUTES("ADMAIF20") 1949 TEGRA264_MUX_ROUTES("ADMAIF21") 1950 TEGRA264_MUX_ROUTES("ADMAIF22") 1951 TEGRA264_MUX_ROUTES("ADMAIF23") 1952 TEGRA264_MUX_ROUTES("ADMAIF24") 1953 TEGRA264_MUX_ROUTES("ADMAIF25") 1954 TEGRA264_MUX_ROUTES("ADMAIF26") 1955 TEGRA264_MUX_ROUTES("ADMAIF27") 1956 TEGRA264_MUX_ROUTES("ADMAIF28") 1957 TEGRA264_MUX_ROUTES("ADMAIF29") 1958 TEGRA264_MUX_ROUTES("ADMAIF30") 1959 TEGRA264_MUX_ROUTES("ADMAIF31") 1960 TEGRA264_MUX_ROUTES("ADMAIF32") 1961 TEGRA264_MUX_ROUTES("I2S1") 1962 TEGRA264_MUX_ROUTES("I2S2") 1963 TEGRA264_MUX_ROUTES("I2S3") 1964 TEGRA264_MUX_ROUTES("I2S4") 1965 TEGRA264_MUX_ROUTES("I2S5") 1966 TEGRA264_MUX_ROUTES("I2S6") 1967 TEGRA264_MUX_ROUTES("I2S7") 1968 TEGRA264_MUX_ROUTES("I2S8") 1969 TEGRA264_MUX_ROUTES("DSPK1") 1970 TEGRA264_MUX_ROUTES("SFC1") 1971 TEGRA264_MUX_ROUTES("SFC2") 1972 TEGRA264_MUX_ROUTES("SFC3") 1973 TEGRA264_MUX_ROUTES("SFC4") 1974 TEGRA264_MUX_ROUTES("MVC1") 1975 TEGRA264_MUX_ROUTES("MVC2") 1976 TEGRA264_MUX_ROUTES("AMX1 RX1") 1977 TEGRA264_MUX_ROUTES("AMX1 RX2") 1978 TEGRA264_MUX_ROUTES("AMX1 RX3") 1979 TEGRA264_MUX_ROUTES("AMX1 RX4") 1980 TEGRA264_MUX_ROUTES("AMX2 RX1") 1981 TEGRA264_MUX_ROUTES("AMX2 RX2") 1982 TEGRA264_MUX_ROUTES("AMX2 RX3") 1983 TEGRA264_MUX_ROUTES("AMX2 RX4") 1984 TEGRA264_MUX_ROUTES("AMX3 RX1") 1985 TEGRA264_MUX_ROUTES("AMX3 RX2") 1986 TEGRA264_MUX_ROUTES("AMX3 RX3") 1987 TEGRA264_MUX_ROUTES("AMX3 RX4") 1988 TEGRA264_MUX_ROUTES("AMX4 RX1") 1989 TEGRA264_MUX_ROUTES("AMX4 RX2") 1990 TEGRA264_MUX_ROUTES("AMX4 RX3") 1991 TEGRA264_MUX_ROUTES("AMX4 RX4") 1992 TEGRA264_MUX_ROUTES("AMX5 RX1") 1993 TEGRA264_MUX_ROUTES("AMX5 RX2") 1994 TEGRA264_MUX_ROUTES("AMX5 RX3") 1995 TEGRA264_MUX_ROUTES("AMX5 RX4") 1996 TEGRA264_MUX_ROUTES("AMX6 RX1") 1997 TEGRA264_MUX_ROUTES("AMX6 RX2") 1998 TEGRA264_MUX_ROUTES("AMX6 RX3") 1999 TEGRA264_MUX_ROUTES("AMX6 RX4") 2000 TEGRA264_MUX_ROUTES("ADX1") 2001 TEGRA264_MUX_ROUTES("ADX2") 2002 TEGRA264_MUX_ROUTES("ADX3") 2003 TEGRA264_MUX_ROUTES("ADX4") 2004 TEGRA264_MUX_ROUTES("ADX5") 2005 TEGRA264_MUX_ROUTES("ADX6") 2006 TEGRA264_MUX_ROUTES("MIXER1 RX1") 2007 TEGRA264_MUX_ROUTES("MIXER1 RX2") 2008 TEGRA264_MUX_ROUTES("MIXER1 RX3") 2009 TEGRA264_MUX_ROUTES("MIXER1 RX4") 2010 TEGRA264_MUX_ROUTES("MIXER1 RX5") 2011 TEGRA264_MUX_ROUTES("MIXER1 RX6") 2012 TEGRA264_MUX_ROUTES("MIXER1 RX7") 2013 TEGRA264_MUX_ROUTES("MIXER1 RX8") 2014 TEGRA264_MUX_ROUTES("MIXER1 RX9") 2015 TEGRA264_MUX_ROUTES("MIXER1 RX10") 2016 TEGRA264_MUX_ROUTES("ASRC1 RX1") 2017 TEGRA264_MUX_ROUTES("ASRC1 RX2") 2018 TEGRA264_MUX_ROUTES("ASRC1 RX3") 2019 TEGRA264_MUX_ROUTES("ASRC1 RX4") 2020 TEGRA264_MUX_ROUTES("ASRC1 RX5") 2021 TEGRA264_MUX_ROUTES("ASRC1 RX6") 2022 TEGRA264_MUX_ROUTES("ASRC1 RX7") 2023 TEGRA264_MUX_ROUTES("OPE1") 2024 }; 2025 2026 static const struct snd_soc_component_driver tegra210_ahub_component = { 2027 .dapm_widgets = tegra210_ahub_widgets, 2028 .num_dapm_widgets = ARRAY_SIZE(tegra210_ahub_widgets), 2029 .dapm_routes = tegra210_ahub_routes, 2030 .num_dapm_routes = ARRAY_SIZE(tegra210_ahub_routes), 2031 }; 2032 2033 static const struct snd_soc_component_driver tegra186_ahub_component = { 2034 .dapm_widgets = tegra186_ahub_widgets, 2035 .num_dapm_widgets = ARRAY_SIZE(tegra186_ahub_widgets), 2036 .dapm_routes = tegra186_ahub_routes, 2037 .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes), 2038 }; 2039 2040 static const struct snd_soc_component_driver tegra234_ahub_component = { 2041 .dapm_widgets = tegra234_ahub_widgets, 2042 .num_dapm_widgets = ARRAY_SIZE(tegra234_ahub_widgets), 2043 .dapm_routes = tegra186_ahub_routes, 2044 .num_dapm_routes = ARRAY_SIZE(tegra186_ahub_routes), 2045 }; 2046 2047 static const struct snd_soc_component_driver tegra264_ahub_component = { 2048 .dapm_widgets = tegra264_ahub_widgets, 2049 .num_dapm_widgets = ARRAY_SIZE(tegra264_ahub_widgets), 2050 .dapm_routes = tegra264_ahub_routes, 2051 .num_dapm_routes = ARRAY_SIZE(tegra264_ahub_routes), 2052 }; 2053 2054 static bool tegra210_ahub_wr_reg(struct device *dev, unsigned int reg) 2055 { 2056 int part; 2057 2058 if (reg % TEGRA210_XBAR_RX_STRIDE) 2059 return false; 2060 2061 for (part = 0; part < TEGRA210_XBAR_UPDATE_MAX_REG; part++) { 2062 switch (reg & ~(part * TEGRA210_XBAR_PART1_RX)) { 2063 case TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 ... TEGRA210_AXBAR_PART_0_ADMAIF_RX10_0: 2064 case TEGRA210_AXBAR_PART_0_I2S1_RX1_0 ... TEGRA210_AXBAR_PART_0_I2S5_RX1_0: 2065 case TEGRA210_AXBAR_PART_0_SFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_SFC4_RX1_0: 2066 case TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 ... TEGRA210_AXBAR_PART_0_MIXER1_RX10_0: 2067 case TEGRA210_AXBAR_PART_0_SPDIF1_RX1_0 ... TEGRA210_AXBAR_PART_0_SPDIF1_RX2_0: 2068 case TEGRA210_AXBAR_PART_0_AFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_AFC6_RX1_0: 2069 case TEGRA210_AXBAR_PART_0_OPE1_RX1_0 ... TEGRA210_AXBAR_PART_0_OPE2_RX1_0: 2070 case TEGRA210_AXBAR_PART_0_SPKPROT1_RX1_0: 2071 case TEGRA210_AXBAR_PART_0_MVC1_RX1_0 ... TEGRA210_AXBAR_PART_0_MVC2_RX1_0: 2072 case TEGRA210_AXBAR_PART_0_AMX1_RX1_0 ... TEGRA210_AXBAR_PART_0_ADX2_RX1_0: 2073 return true; 2074 default: 2075 break; 2076 } 2077 } 2078 2079 return false; 2080 } 2081 2082 static bool tegra186_ahub_wr_reg(struct device *dev, unsigned int reg) 2083 { 2084 int part; 2085 2086 if (reg % TEGRA210_XBAR_RX_STRIDE) 2087 return false; 2088 2089 for (part = 0; part < TEGRA186_XBAR_UPDATE_MAX_REG; part++) { 2090 switch (reg & ~(part * TEGRA210_XBAR_PART1_RX)) { 2091 case TEGRA210_AXBAR_PART_0_ADMAIF_RX1_0 ... TEGRA186_AXBAR_PART_0_I2S6_RX1_0: 2092 case TEGRA210_AXBAR_PART_0_SFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_SFC4_RX1_0: 2093 case TEGRA210_AXBAR_PART_0_MIXER1_RX1_0 ... TEGRA210_AXBAR_PART_0_MIXER1_RX10_0: 2094 case TEGRA186_AXBAR_PART_0_DSPK1_RX1_0 ... TEGRA186_AXBAR_PART_0_DSPK2_RX1_0: 2095 case TEGRA210_AXBAR_PART_0_AFC1_RX1_0 ... TEGRA210_AXBAR_PART_0_AFC6_RX1_0: 2096 case TEGRA210_AXBAR_PART_0_OPE1_RX1_0: 2097 case TEGRA186_AXBAR_PART_0_MVC1_RX1_0 ... TEGRA186_AXBAR_PART_0_MVC2_RX1_0: 2098 case TEGRA186_AXBAR_PART_0_AMX1_RX1_0 ... TEGRA186_AXBAR_PART_0_AMX3_RX4_0: 2099 case TEGRA210_AXBAR_PART_0_ADX1_RX1_0 ... TEGRA186_AXBAR_PART_0_ASRC1_RX7_0: 2100 return true; 2101 default: 2102 break; 2103 } 2104 } 2105 2106 return false; 2107 } 2108 2109 static bool tegra264_ahub_wr_reg(struct device *dev, unsigned int reg) 2110 { 2111 int part; 2112 2113 for (part = 0; part < TEGRA264_XBAR_UPDATE_MAX_REG; part++) { 2114 switch (reg & ~(part << 12)) { 2115 case TEGRA264_AXBAR_ADMAIF_RX1 ... TEGRA264_AXBAR_SFC4_RX1: 2116 case TEGRA264_AXBAR_MIXER1_RX1 ... TEGRA264_AXBAR_MIXER1_RX10: 2117 case TEGRA264_AXBAR_DSPK1_RX1: 2118 case TEGRA264_AXBAR_OPE1_RX1: 2119 case TEGRA264_AXBAR_MVC1_RX1 ... TEGRA264_AXBAR_MVC2_RX1: 2120 case TEGRA264_AXBAR_AMX1_RX1 ... TEGRA264_AXBAR_AMX3_RX4: 2121 case TEGRA264_AXBAR_ADX1_RX1 ... TEGRA264_AXBAR_ASRC1_RX7: 2122 case TEGRA264_AXBAR_ADMAIF_RX21 ... TEGRA264_AXBAR_ADX6_RX1: 2123 return true; 2124 default: 2125 break; 2126 } 2127 } 2128 2129 return false; 2130 } 2131 2132 static const struct regmap_config tegra210_ahub_regmap_config = { 2133 .reg_bits = 32, 2134 .val_bits = 32, 2135 .reg_stride = 4, 2136 .writeable_reg = tegra210_ahub_wr_reg, 2137 .max_register = TEGRA210_MAX_REGISTER_ADDR, 2138 .reg_default_cb = regmap_default_zero_cb, 2139 .cache_type = REGCACHE_FLAT, 2140 }; 2141 2142 static const struct regmap_config tegra186_ahub_regmap_config = { 2143 .reg_bits = 32, 2144 .val_bits = 32, 2145 .reg_stride = 4, 2146 .writeable_reg = tegra186_ahub_wr_reg, 2147 .max_register = TEGRA186_MAX_REGISTER_ADDR, 2148 .reg_default_cb = regmap_default_zero_cb, 2149 .cache_type = REGCACHE_FLAT, 2150 }; 2151 2152 static const struct regmap_config tegra264_ahub_regmap_config = { 2153 .reg_bits = 32, 2154 .val_bits = 32, 2155 .reg_stride = 4, 2156 .writeable_reg = tegra264_ahub_wr_reg, 2157 .max_register = TEGRA264_MAX_REGISTER_ADDR, 2158 .reg_default_cb = regmap_default_zero_cb, 2159 .cache_type = REGCACHE_FLAT, 2160 }; 2161 2162 static const struct tegra_ahub_soc_data soc_data_tegra210 = { 2163 .cmpnt_drv = &tegra210_ahub_component, 2164 .dai_drv = tegra210_ahub_dais, 2165 .num_dais = ARRAY_SIZE(tegra210_ahub_dais), 2166 .regmap_config = &tegra210_ahub_regmap_config, 2167 .mask[0] = TEGRA210_XBAR_REG_MASK_0, 2168 .mask[1] = TEGRA210_XBAR_REG_MASK_1, 2169 .mask[2] = TEGRA210_XBAR_REG_MASK_2, 2170 .mask[3] = TEGRA210_XBAR_REG_MASK_3, 2171 .reg_count = TEGRA210_XBAR_UPDATE_MAX_REG, 2172 .xbar_part_size = TEGRA210_XBAR_PART1_RX, 2173 }; 2174 2175 static const struct tegra_ahub_soc_data soc_data_tegra186 = { 2176 .cmpnt_drv = &tegra186_ahub_component, 2177 .dai_drv = tegra186_ahub_dais, 2178 .num_dais = ARRAY_SIZE(tegra186_ahub_dais), 2179 .regmap_config = &tegra186_ahub_regmap_config, 2180 .mask[0] = TEGRA186_XBAR_REG_MASK_0, 2181 .mask[1] = TEGRA186_XBAR_REG_MASK_1, 2182 .mask[2] = TEGRA186_XBAR_REG_MASK_2, 2183 .mask[3] = TEGRA186_XBAR_REG_MASK_3, 2184 .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG, 2185 .xbar_part_size = TEGRA210_XBAR_PART1_RX, 2186 }; 2187 2188 static const struct tegra_ahub_soc_data soc_data_tegra234 = { 2189 .cmpnt_drv = &tegra234_ahub_component, 2190 .dai_drv = tegra186_ahub_dais, 2191 .num_dais = ARRAY_SIZE(tegra186_ahub_dais), 2192 .regmap_config = &tegra186_ahub_regmap_config, 2193 .mask[0] = TEGRA186_XBAR_REG_MASK_0, 2194 .mask[1] = TEGRA186_XBAR_REG_MASK_1, 2195 .mask[2] = TEGRA186_XBAR_REG_MASK_2, 2196 .mask[3] = TEGRA186_XBAR_REG_MASK_3, 2197 .reg_count = TEGRA186_XBAR_UPDATE_MAX_REG, 2198 .xbar_part_size = TEGRA210_XBAR_PART1_RX, 2199 }; 2200 2201 static const struct tegra_ahub_soc_data soc_data_tegra264 = { 2202 .cmpnt_drv = &tegra264_ahub_component, 2203 .dai_drv = tegra264_ahub_dais, 2204 .num_dais = ARRAY_SIZE(tegra264_ahub_dais), 2205 .regmap_config = &tegra264_ahub_regmap_config, 2206 .mask[0] = TEGRA264_XBAR_REG_MASK_0, 2207 .mask[1] = TEGRA264_XBAR_REG_MASK_1, 2208 .mask[2] = TEGRA264_XBAR_REG_MASK_2, 2209 .mask[3] = TEGRA264_XBAR_REG_MASK_3, 2210 .mask[4] = TEGRA264_XBAR_REG_MASK_4, 2211 .reg_count = TEGRA264_XBAR_UPDATE_MAX_REG, 2212 .xbar_part_size = TEGRA264_XBAR_PART1_RX, 2213 }; 2214 2215 static const struct of_device_id tegra_ahub_of_match[] = { 2216 { .compatible = "nvidia,tegra210-ahub", .data = &soc_data_tegra210 }, 2217 { .compatible = "nvidia,tegra186-ahub", .data = &soc_data_tegra186 }, 2218 { .compatible = "nvidia,tegra234-ahub", .data = &soc_data_tegra234 }, 2219 { .compatible = "nvidia,tegra264-ahub", .data = &soc_data_tegra264 }, 2220 {}, 2221 }; 2222 MODULE_DEVICE_TABLE(of, tegra_ahub_of_match); 2223 2224 static int tegra_ahub_runtime_suspend(struct device *dev) 2225 { 2226 struct tegra_ahub *ahub = dev_get_drvdata(dev); 2227 2228 regcache_cache_only(ahub->regmap, true); 2229 regcache_mark_dirty(ahub->regmap); 2230 2231 clk_disable_unprepare(ahub->clk); 2232 2233 return 0; 2234 } 2235 2236 static int tegra_ahub_runtime_resume(struct device *dev) 2237 { 2238 struct tegra_ahub *ahub = dev_get_drvdata(dev); 2239 int err; 2240 2241 err = clk_prepare_enable(ahub->clk); 2242 if (err) { 2243 dev_err(dev, "failed to enable AHUB clock, err: %d\n", err); 2244 return err; 2245 } 2246 2247 regcache_cache_only(ahub->regmap, false); 2248 regcache_sync(ahub->regmap); 2249 2250 return 0; 2251 } 2252 2253 static int tegra_ahub_probe(struct platform_device *pdev) 2254 { 2255 struct tegra_ahub *ahub; 2256 void __iomem *regs; 2257 int err; 2258 2259 ahub = devm_kzalloc(&pdev->dev, sizeof(*ahub), GFP_KERNEL); 2260 if (!ahub) 2261 return -ENOMEM; 2262 2263 ahub->soc_data = of_device_get_match_data(&pdev->dev); 2264 if (!ahub->soc_data) 2265 return -ENODEV; 2266 2267 platform_set_drvdata(pdev, ahub); 2268 2269 ahub->clk = devm_clk_get(&pdev->dev, "ahub"); 2270 if (IS_ERR(ahub->clk)) 2271 return dev_err_probe(&pdev->dev, PTR_ERR(ahub->clk), 2272 "can't retrieve AHUB clock\n"); 2273 2274 regs = devm_platform_ioremap_resource(pdev, 0); 2275 if (IS_ERR(regs)) 2276 return PTR_ERR(regs); 2277 2278 ahub->regmap = devm_regmap_init_mmio(&pdev->dev, regs, 2279 ahub->soc_data->regmap_config); 2280 if (IS_ERR(ahub->regmap)) 2281 return dev_err_probe(&pdev->dev, PTR_ERR(ahub->regmap), 2282 "regmap init failed\n"); 2283 2284 regcache_cache_only(ahub->regmap, true); 2285 2286 err = devm_snd_soc_register_component(&pdev->dev, 2287 ahub->soc_data->cmpnt_drv, 2288 ahub->soc_data->dai_drv, 2289 ahub->soc_data->num_dais); 2290 if (err) 2291 return dev_err_probe(&pdev->dev, err, 2292 "can't register AHUB component\n"); 2293 2294 pm_runtime_enable(&pdev->dev); 2295 2296 err = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev); 2297 if (err) { 2298 pm_runtime_disable(&pdev->dev); 2299 return dev_err_probe(&pdev->dev, err, 2300 "failed to populate child nodes\n"); 2301 } 2302 2303 return 0; 2304 } 2305 2306 static void tegra_ahub_remove(struct platform_device *pdev) 2307 { 2308 pm_runtime_disable(&pdev->dev); 2309 } 2310 2311 static const struct dev_pm_ops tegra_ahub_pm_ops = { 2312 RUNTIME_PM_OPS(tegra_ahub_runtime_suspend, 2313 tegra_ahub_runtime_resume, NULL) 2314 SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 2315 }; 2316 2317 static struct platform_driver tegra_ahub_driver = { 2318 .probe = tegra_ahub_probe, 2319 .remove = tegra_ahub_remove, 2320 .driver = { 2321 .name = "tegra210-ahub", 2322 .of_match_table = tegra_ahub_of_match, 2323 .pm = pm_ptr(&tegra_ahub_pm_ops), 2324 }, 2325 }; 2326 module_platform_driver(tegra_ahub_driver); 2327 2328 MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); 2329 MODULE_AUTHOR("Mohan Kumar <mkumard@nvidia.com>"); 2330 MODULE_DESCRIPTION("Tegra210 ASoC AHUB driver"); 2331 MODULE_LICENSE("GPL v2"); 2332