xref: /linux/drivers/phy/tegra/xusb-tegra186.c (revision 5b35eb8435fd33f357918f2aefa50357695522e3)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
4  */
5 
6 #include <linux/delay.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/phy/phy.h>
11 #include <linux/regulator/consumer.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/slab.h>
15 
16 #include <soc/tegra/fuse.h>
17 
18 #include "xusb.h"
19 
20 /* FUSE USB_CALIB registers */
21 #define HS_CURR_LEVEL_PADX_SHIFT(x)	((x) ? (11 + (x - 1) * 6) : 0)
22 #define HS_CURR_LEVEL_PAD_MASK		0x3f
23 #define HS_TERM_RANGE_ADJ_SHIFT		7
24 #define HS_TERM_RANGE_ADJ_MASK		0xf
25 #define HS_SQUELCH_SHIFT		29
26 #define HS_SQUELCH_MASK			0x7
27 
28 #define RPD_CTRL_SHIFT			0
29 #define RPD_CTRL_MASK			0x1f
30 
31 /* XUSB PADCTL registers */
32 #define XUSB_PADCTL_USB2_PAD_MUX	0x4
33 #define  USB2_PORT_SHIFT(x)		((x) * 2)
34 #define  USB2_PORT_MASK			0x3
35 #define   PORT_XUSB			1
36 #define  HSIC_PORT_SHIFT(x)		((x) + 20)
37 #define  HSIC_PORT_MASK			0x1
38 #define   PORT_HSIC			0
39 
40 #define XUSB_PADCTL_USB2_PORT_CAP	0x8
41 #define XUSB_PADCTL_SS_PORT_CAP		0xc
42 #define  PORTX_CAP_SHIFT(x)		((x) * 4)
43 #define  PORT_CAP_MASK			0x3
44 #define   PORT_CAP_DISABLED		0x0
45 #define   PORT_CAP_HOST			0x1
46 #define   PORT_CAP_DEVICE		0x2
47 #define   PORT_CAP_OTG			0x3
48 
49 #define XUSB_PADCTL_ELPG_PROGRAM		0x20
50 #define  USB2_PORT_WAKE_INTERRUPT_ENABLE(x)		BIT(x)
51 #define  USB2_PORT_WAKEUP_EVENT(x)			BIT((x) +  7)
52 #define  SS_PORT_WAKE_INTERRUPT_ENABLE(x)		BIT((x) + 14)
53 #define  SS_PORT_WAKEUP_EVENT(x)			BIT((x) + 21)
54 #define  USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x)	BIT((x) + 28)
55 #define  USB2_HSIC_PORT_WAKEUP_EVENT(x)			BIT((x) + 30)
56 #define  ALL_WAKE_EVENTS						\
57 	(USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) |	\
58 	USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) |		\
59 	SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) |		\
60 	USB2_HSIC_PORT_WAKEUP_EVENT(0))
61 
62 #define XUSB_PADCTL_ELPG_PROGRAM_1		0x24
63 #define  SSPX_ELPG_CLAMP_EN(x)			BIT(0 + (x) * 3)
64 #define  SSPX_ELPG_CLAMP_EN_EARLY(x)		BIT(1 + (x) * 3)
65 #define  SSPX_ELPG_VCORE_DOWN(x)		BIT(2 + (x) * 3)
66 #define XUSB_PADCTL_SS_PORT_CFG			0x2c
67 #define   PORTX_SPEED_SUPPORT_SHIFT(x)		((x) * 4)
68 #define   PORTX_SPEED_SUPPORT_MASK		(0x3)
69 #define     PORT_SPEED_SUPPORT_GEN1		(0x0)
70 
71 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x)	(0x88 + (x) * 0x40)
72 #define  HS_CURR_LEVEL(x)			((x) & 0x3f)
73 #define  TERM_SEL				BIT(25)
74 #define  USB2_OTG_PD				BIT(26)
75 #define  USB2_OTG_PD2				BIT(27)
76 #define  USB2_OTG_PD2_OVRD_EN			BIT(28)
77 #define  USB2_OTG_PD_ZI				BIT(29)
78 
79 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x)	(0x8c + (x) * 0x40)
80 #define  USB2_OTG_PD_DR				BIT(2)
81 #define  TERM_RANGE_ADJ(x)			(((x) & 0xf) << 3)
82 #define  RPD_CTRL(x)				(((x) & 0x1f) << 26)
83 
84 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0		0x284
85 #define  BIAS_PAD_PD				BIT(11)
86 #define  HS_SQUELCH_LEVEL(x)			(((x) & 0x7) << 0)
87 
88 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1		0x288
89 #define  USB2_TRK_START_TIMER(x)		(((x) & 0x7f) << 12)
90 #define  USB2_TRK_DONE_RESET_TIMER(x)		(((x) & 0x7f) << 19)
91 #define  USB2_PD_TRK				BIT(26)
92 #define  USB2_TRK_COMPLETED			BIT(31)
93 
94 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL2		0x28c
95 #define  USB2_TRK_HW_MODE			BIT(0)
96 #define  CYA_TRK_CODE_UPDATE_ON_IDLE		BIT(31)
97 
98 #define XUSB_PADCTL_HSIC_PADX_CTL0(x)		(0x300 + (x) * 0x20)
99 #define  HSIC_PD_TX_DATA0			BIT(1)
100 #define  HSIC_PD_TX_STROBE			BIT(3)
101 #define  HSIC_PD_RX_DATA0			BIT(4)
102 #define  HSIC_PD_RX_STROBE			BIT(6)
103 #define  HSIC_PD_ZI_DATA0			BIT(7)
104 #define  HSIC_PD_ZI_STROBE			BIT(9)
105 #define  HSIC_RPD_DATA0				BIT(13)
106 #define  HSIC_RPD_STROBE			BIT(15)
107 #define  HSIC_RPU_DATA0				BIT(16)
108 #define  HSIC_RPU_STROBE			BIT(18)
109 
110 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL0		0x340
111 #define  HSIC_TRK_START_TIMER(x)		(((x) & 0x7f) << 5)
112 #define  HSIC_TRK_DONE_RESET_TIMER(x)		(((x) & 0x7f) << 12)
113 #define  HSIC_PD_TRK				BIT(19)
114 
115 #define USB2_VBUS_ID				0x360
116 #define  VBUS_OVERRIDE				BIT(14)
117 #define  ID_OVERRIDE(x)				(((x) & 0xf) << 18)
118 #define  ID_OVERRIDE_FLOATING			ID_OVERRIDE(8)
119 #define  ID_OVERRIDE_GROUNDED			ID_OVERRIDE(0)
120 
121 /* XUSB AO registers */
122 #define XUSB_AO_USB_DEBOUNCE_DEL		(0x4)
123 #define   UHSIC_LINE_DEB_CNT(x)			(((x) & 0xf) << 4)
124 #define   UTMIP_LINE_DEB_CNT(x)			((x) & 0xf)
125 
126 #define XUSB_AO_UTMIP_TRIGGERS(x)		(0x40 + (x) * 4)
127 #define   CLR_WALK_PTR				BIT(0)
128 #define   CAP_CFG				BIT(1)
129 #define   CLR_WAKE_ALARM			BIT(3)
130 
131 #define XUSB_AO_UHSIC_TRIGGERS(x)		(0x60 + (x) * 4)
132 #define   HSIC_CLR_WALK_PTR			BIT(0)
133 #define   HSIC_CLR_WAKE_ALARM			BIT(3)
134 #define   HSIC_CAP_CFG				BIT(4)
135 
136 #define XUSB_AO_UTMIP_SAVED_STATE(x)		(0x70 + (x) * 4)
137 #define   SPEED(x)				((x) & 0x3)
138 #define     UTMI_HS				SPEED(0)
139 #define     UTMI_FS				SPEED(1)
140 #define     UTMI_LS				SPEED(2)
141 #define     UTMI_RST				SPEED(3)
142 
143 #define XUSB_AO_UHSIC_SAVED_STATE(x)		(0x90 + (x) * 4)
144 #define   MODE(x)				((x) & 0x1)
145 #define   MODE_HS				MODE(0)
146 #define   MODE_RST				MODE(1)
147 
148 #define XUSB_AO_UTMIP_SLEEPWALK_STATUS(x)	(0xa0 + (x) * 4)
149 
150 #define XUSB_AO_UTMIP_SLEEPWALK_CFG(x)		(0xd0 + (x) * 4)
151 #define XUSB_AO_UHSIC_SLEEPWALK_CFG(x)		(0xf0 + (x) * 4)
152 #define   FAKE_USBOP_VAL			BIT(0)
153 #define   FAKE_USBON_VAL			BIT(1)
154 #define   FAKE_USBOP_EN				BIT(2)
155 #define   FAKE_USBON_EN				BIT(3)
156 #define   FAKE_STROBE_VAL			BIT(0)
157 #define   FAKE_DATA_VAL				BIT(1)
158 #define   FAKE_STROBE_EN			BIT(2)
159 #define   FAKE_DATA_EN				BIT(3)
160 #define   WAKE_WALK_EN				BIT(14)
161 #define   MASTER_ENABLE				BIT(15)
162 #define   LINEVAL_WALK_EN			BIT(16)
163 #define   WAKE_VAL(x)				(((x) & 0xf) << 17)
164 #define     WAKE_VAL_NONE			WAKE_VAL(12)
165 #define     WAKE_VAL_ANY			WAKE_VAL(15)
166 #define     WAKE_VAL_DS10			WAKE_VAL(2)
167 #define   LINE_WAKEUP_EN			BIT(21)
168 #define   MASTER_CFG_SEL			BIT(22)
169 
170 #define XUSB_AO_UTMIP_SLEEPWALK(x)		(0x100 + (x) * 4)
171 /* phase A */
172 #define   USBOP_RPD_A				BIT(0)
173 #define   USBON_RPD_A				BIT(1)
174 #define   AP_A					BIT(4)
175 #define   AN_A					BIT(5)
176 #define   HIGHZ_A				BIT(6)
177 #define   MASTER_ENABLE_A			BIT(7)
178 /* phase B */
179 #define   USBOP_RPD_B				BIT(8)
180 #define   USBON_RPD_B				BIT(9)
181 #define   AP_B					BIT(12)
182 #define   AN_B					BIT(13)
183 #define   HIGHZ_B				BIT(14)
184 #define   MASTER_ENABLE_B			BIT(15)
185 /* phase C */
186 #define   USBOP_RPD_C				BIT(16)
187 #define   USBON_RPD_C				BIT(17)
188 #define   AP_C					BIT(20)
189 #define   AN_C					BIT(21)
190 #define   HIGHZ_C				BIT(22)
191 #define   MASTER_ENABLE_C			BIT(23)
192 /* phase D */
193 #define   USBOP_RPD_D				BIT(24)
194 #define   USBON_RPD_D				BIT(25)
195 #define   AP_D					BIT(28)
196 #define   AN_D					BIT(29)
197 #define   HIGHZ_D				BIT(30)
198 #define   MASTER_ENABLE_D			BIT(31)
199 #define   MASTER_ENABLE_B_C_D					\
200 	 (MASTER_ENABLE_B | MASTER_ENABLE_C | MASTER_ENABLE_D)
201 
202 #define XUSB_AO_UHSIC_SLEEPWALK(x)		(0x120 + (x) * 4)
203 /* phase A */
204 #define   RPD_STROBE_A				BIT(0)
205 #define   RPD_DATA0_A				BIT(1)
206 #define   RPU_STROBE_A				BIT(2)
207 #define   RPU_DATA0_A				BIT(3)
208 /* phase B */
209 #define   RPD_STROBE_B				BIT(8)
210 #define   RPD_DATA0_B				BIT(9)
211 #define   RPU_STROBE_B				BIT(10)
212 #define   RPU_DATA0_B				BIT(11)
213 /* phase C */
214 #define   RPD_STROBE_C				BIT(16)
215 #define   RPD_DATA0_C				BIT(17)
216 #define   RPU_STROBE_C				BIT(18)
217 #define   RPU_DATA0_C				BIT(19)
218 /* phase D */
219 #define   RPD_STROBE_D				BIT(24)
220 #define   RPD_DATA0_D				BIT(25)
221 #define   RPU_STROBE_D				BIT(26)
222 #define   RPU_DATA0_D				BIT(27)
223 
224 #define XUSB_AO_UTMIP_PAD_CFG(x)		(0x130 + (x) * 4)
225 #define   FSLS_USE_XUSB_AO			BIT(3)
226 #define   TRK_CTRL_USE_XUSB_AO			BIT(4)
227 #define   RPD_CTRL_USE_XUSB_AO			BIT(5)
228 #define   RPU_USE_XUSB_AO			BIT(6)
229 #define   VREG_USE_XUSB_AO			BIT(7)
230 #define   USBOP_VAL_PD				BIT(8)
231 #define   USBON_VAL_PD				BIT(9)
232 #define   E_DPD_OVRD_EN				BIT(10)
233 #define   E_DPD_OVRD_VAL			BIT(11)
234 
235 #define XUSB_AO_UHSIC_PAD_CFG(x)		(0x150 + (x) * 4)
236 #define   STROBE_VAL_PD				BIT(0)
237 #define   DATA0_VAL_PD				BIT(1)
238 #define   USE_XUSB_AO				BIT(4)
239 
240 #define TEGRA_UTMI_PAD_MAX 4
241 
242 #define TEGRA186_LANE(_name, _offset, _shift, _mask, _type)		\
243 	{								\
244 		.name = _name,						\
245 		.offset = _offset,					\
246 		.shift = _shift,					\
247 		.mask = _mask,						\
248 		.num_funcs = ARRAY_SIZE(tegra186_##_type##_functions),	\
249 		.funcs = tegra186_##_type##_functions,			\
250 	}
251 
252 struct tegra_xusb_fuse_calibration {
253 	u32 *hs_curr_level;
254 	u32 hs_squelch;
255 	u32 hs_term_range_adj;
256 	u32 rpd_ctrl;
257 };
258 
259 struct tegra186_xusb_padctl_context {
260 	u32 vbus_id;
261 	u32 usb2_pad_mux;
262 	u32 usb2_port_cap;
263 	u32 ss_port_cap;
264 };
265 
266 struct tegra186_xusb_padctl {
267 	struct tegra_xusb_padctl base;
268 	void __iomem *ao_regs;
269 
270 	struct tegra_xusb_fuse_calibration calib;
271 
272 	/* UTMI bias and tracking */
273 	struct clk *usb2_trk_clk;
274 	DECLARE_BITMAP(utmi_pad_enabled, TEGRA_UTMI_PAD_MAX);
275 
276 	/* padctl context */
277 	struct tegra186_xusb_padctl_context context;
278 };
279 
280 static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset)
281 {
282 	writel(value, priv->ao_regs + offset);
283 }
284 
285 static inline u32 ao_readl(struct tegra186_xusb_padctl *priv, unsigned int offset)
286 {
287 	return readl(priv->ao_regs + offset);
288 }
289 
290 static inline struct tegra186_xusb_padctl *
291 to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
292 {
293 	return container_of(padctl, struct tegra186_xusb_padctl, base);
294 }
295 
296 /* USB 2.0 UTMI PHY support */
297 static struct tegra_xusb_lane *
298 tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
299 			 unsigned int index)
300 {
301 	struct tegra_xusb_usb2_lane *usb2;
302 	int err;
303 
304 	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
305 	if (!usb2)
306 		return ERR_PTR(-ENOMEM);
307 
308 	INIT_LIST_HEAD(&usb2->base.list);
309 	usb2->base.soc = &pad->soc->lanes[index];
310 	usb2->base.index = index;
311 	usb2->base.pad = pad;
312 	usb2->base.np = np;
313 
314 	err = tegra_xusb_lane_parse_dt(&usb2->base, np);
315 	if (err < 0) {
316 		kfree(usb2);
317 		return ERR_PTR(err);
318 	}
319 
320 	return &usb2->base;
321 }
322 
323 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane)
324 {
325 	struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
326 
327 	kfree(usb2);
328 }
329 
330 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
331 					      enum usb_device_speed speed)
332 {
333 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
334 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
335 	unsigned int index = lane->index;
336 	u32 value;
337 
338 	mutex_lock(&padctl->lock);
339 
340 	/* ensure sleepwalk logic is disabled */
341 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
342 	value &= ~MASTER_ENABLE;
343 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
344 
345 	/* ensure sleepwalk logics are in low power mode */
346 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
347 	value |= MASTER_CFG_SEL;
348 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
349 
350 	/* set debounce time */
351 	value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL);
352 	value &= ~UTMIP_LINE_DEB_CNT(~0);
353 	value |= UTMIP_LINE_DEB_CNT(1);
354 	ao_writel(priv, value, XUSB_AO_USB_DEBOUNCE_DEL);
355 
356 	/* ensure fake events of sleepwalk logic are desiabled */
357 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
358 	value &= ~(FAKE_USBOP_VAL | FAKE_USBON_VAL |
359 		FAKE_USBOP_EN | FAKE_USBON_EN);
360 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
361 
362 	/* ensure wake events of sleepwalk logic are not latched */
363 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
364 	value &= ~LINE_WAKEUP_EN;
365 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
366 
367 	/* disable wake event triggers of sleepwalk logic */
368 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
369 	value &= ~WAKE_VAL(~0);
370 	value |= WAKE_VAL_NONE;
371 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
372 
373 	/* power down the line state detectors of the pad */
374 	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
375 	value |= (USBOP_VAL_PD | USBON_VAL_PD);
376 	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
377 
378 	/* save state per speed */
379 	value = ao_readl(priv, XUSB_AO_UTMIP_SAVED_STATE(index));
380 	value &= ~SPEED(~0);
381 
382 	switch (speed) {
383 	case USB_SPEED_HIGH:
384 		value |= UTMI_HS;
385 		break;
386 
387 	case USB_SPEED_FULL:
388 		value |= UTMI_FS;
389 		break;
390 
391 	case USB_SPEED_LOW:
392 		value |= UTMI_LS;
393 		break;
394 
395 	default:
396 		value |= UTMI_RST;
397 		break;
398 	}
399 
400 	ao_writel(priv, value, XUSB_AO_UTMIP_SAVED_STATE(index));
401 
402 	/* enable the trigger of the sleepwalk logic */
403 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
404 	value |= LINEVAL_WALK_EN;
405 	value &= ~WAKE_WALK_EN;
406 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
407 
408 	/* reset the walk pointer and clear the alarm of the sleepwalk logic,
409 	 * as well as capture the configuration of the USB2.0 pad
410 	 */
411 	value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
412 	value |= (CLR_WALK_PTR | CLR_WAKE_ALARM | CAP_CFG);
413 	ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
414 
415 	/* setup the pull-ups and pull-downs of the signals during the four
416 	 * stages of sleepwalk.
417 	 * if device is connected, program sleepwalk logic to maintain a J and
418 	 * keep driving K upon seeing remote wake.
419 	 */
420 	value = USBOP_RPD_A | USBOP_RPD_B | USBOP_RPD_C | USBOP_RPD_D;
421 	value |= USBON_RPD_A | USBON_RPD_B | USBON_RPD_C | USBON_RPD_D;
422 
423 	switch (speed) {
424 	case USB_SPEED_HIGH:
425 	case USB_SPEED_FULL:
426 		/* J state: D+/D- = high/low, K state: D+/D- = low/high */
427 		value |= HIGHZ_A;
428 		value |= AP_A;
429 		value |= AN_B | AN_C | AN_D;
430 		if (padctl->soc->supports_lp_cfg_en)
431 			value |= MASTER_ENABLE_B_C_D;
432 		break;
433 
434 	case USB_SPEED_LOW:
435 		/* J state: D+/D- = low/high, K state: D+/D- = high/low */
436 		value |= HIGHZ_A;
437 		value |= AN_A;
438 		value |= AP_B | AP_C | AP_D;
439 		if (padctl->soc->supports_lp_cfg_en)
440 			value |= MASTER_ENABLE_B_C_D;
441 		break;
442 
443 	default:
444 		value |= HIGHZ_A | HIGHZ_B | HIGHZ_C | HIGHZ_D;
445 		break;
446 	}
447 
448 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
449 
450 	/* power up the line state detectors of the pad */
451 	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
452 	value &= ~(USBOP_VAL_PD | USBON_VAL_PD);
453 	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
454 
455 	usleep_range(150, 200);
456 
457 	/* switch the electric control of the USB2.0 pad to XUSB_AO */
458 	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
459 	value |= FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
460 		 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO;
461 	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
462 
463 	/* set the wake signaling trigger events */
464 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
465 	value &= ~WAKE_VAL(~0);
466 	value |= WAKE_VAL_ANY;
467 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
468 
469 	/* enable the wake detection */
470 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
471 	value |= MASTER_ENABLE | LINE_WAKEUP_EN;
472 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
473 
474 	mutex_unlock(&padctl->lock);
475 
476 	return 0;
477 }
478 
479 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
480 {
481 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
482 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
483 	unsigned int index = lane->index;
484 	u32 value;
485 
486 	mutex_lock(&padctl->lock);
487 
488 	/* disable the wake detection */
489 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
490 	value &= ~(MASTER_ENABLE | LINE_WAKEUP_EN);
491 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
492 
493 	/* switch the electric control of the USB2.0 pad to XUSB vcore logic */
494 	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
495 	value &= ~(FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
496 		   RPU_USE_XUSB_AO | VREG_USE_XUSB_AO);
497 	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
498 
499 	/* disable wake event triggers of sleepwalk logic */
500 	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
501 	value &= ~WAKE_VAL(~0);
502 	value |= WAKE_VAL_NONE;
503 	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
504 
505 	if (padctl->soc->supports_lp_cfg_en) {
506 		/* disable the four stages of sleepwalk */
507 		value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK(index));
508 		value &= ~(MASTER_ENABLE_A | MASTER_ENABLE_B_C_D);
509 		ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
510 	}
511 
512 	/* power down the line state detectors of the port */
513 	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
514 	value |= USBOP_VAL_PD | USBON_VAL_PD;
515 	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
516 
517 	/* clear alarm of the sleepwalk logic */
518 	value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
519 	value |= CLR_WAKE_ALARM;
520 	ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
521 
522 	mutex_unlock(&padctl->lock);
523 
524 	return 0;
525 }
526 
527 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane)
528 {
529 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
530 	unsigned int index = lane->index;
531 	u32 value;
532 
533 	mutex_lock(&padctl->lock);
534 
535 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
536 	value &= ~ALL_WAKE_EVENTS;
537 	value |= USB2_PORT_WAKEUP_EVENT(index);
538 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
539 
540 	usleep_range(10, 20);
541 
542 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
543 	value &= ~ALL_WAKE_EVENTS;
544 	value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
545 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
546 
547 	mutex_unlock(&padctl->lock);
548 
549 	return 0;
550 }
551 
552 static int tegra186_utmi_disable_phy_wake(struct tegra_xusb_lane *lane)
553 {
554 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
555 	unsigned int index = lane->index;
556 	u32 value;
557 
558 	mutex_lock(&padctl->lock);
559 
560 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
561 	value &= ~ALL_WAKE_EVENTS;
562 	value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
563 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
564 
565 	usleep_range(10, 20);
566 
567 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
568 	value &= ~ALL_WAKE_EVENTS;
569 	value |= USB2_PORT_WAKEUP_EVENT(index);
570 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
571 
572 	mutex_unlock(&padctl->lock);
573 
574 	return 0;
575 }
576 
577 static bool tegra186_utmi_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
578 {
579 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
580 	unsigned int index = lane->index;
581 	u32 value;
582 
583 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
584 	if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) &&
585 	    (value & USB2_PORT_WAKEUP_EVENT(index)))
586 		return true;
587 
588 	return false;
589 }
590 
591 static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = {
592 	.probe = tegra186_usb2_lane_probe,
593 	.remove = tegra186_usb2_lane_remove,
594 	.enable_phy_sleepwalk = tegra186_utmi_enable_phy_sleepwalk,
595 	.disable_phy_sleepwalk = tegra186_utmi_disable_phy_sleepwalk,
596 	.enable_phy_wake = tegra186_utmi_enable_phy_wake,
597 	.disable_phy_wake = tegra186_utmi_disable_phy_wake,
598 	.remote_wake_detected = tegra186_utmi_phy_remote_wake_detected,
599 };
600 
601 static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
602 {
603 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
604 	struct device *dev = padctl->dev;
605 	u32 value;
606 	int err;
607 
608 	if (!bitmap_empty(priv->utmi_pad_enabled, TEGRA_UTMI_PAD_MAX))
609 		return;
610 
611 	err = clk_prepare_enable(priv->usb2_trk_clk);
612 	if (err < 0)
613 		dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);
614 
615 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
616 	value &= ~USB2_TRK_START_TIMER(~0);
617 	value |= USB2_TRK_START_TIMER(0x1e);
618 	value &= ~USB2_TRK_DONE_RESET_TIMER(~0);
619 	value |= USB2_TRK_DONE_RESET_TIMER(0xa);
620 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
621 
622 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
623 	value &= ~BIAS_PAD_PD;
624 	value &= ~HS_SQUELCH_LEVEL(~0);
625 	value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);
626 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
627 
628 	udelay(1);
629 
630 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
631 	value &= ~USB2_PD_TRK;
632 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
633 
634 	if (padctl->soc->poll_trk_completed) {
635 		err = padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1,
636 					USB2_TRK_COMPLETED, USB2_TRK_COMPLETED, 100);
637 		if (err) {
638 			/* The failure with polling on trk complete will not
639 			 * cause the failure of powering on the bias pad.
640 			 */
641 			dev_warn(dev, "failed to poll USB2 trk completed: %d\n", err);
642 		}
643 
644 		value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
645 		value |= USB2_TRK_COMPLETED;
646 		padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
647 	} else {
648 		udelay(100);
649 	}
650 
651 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
652 	if (padctl->soc->trk_update_on_idle)
653 		value &= ~CYA_TRK_CODE_UPDATE_ON_IDLE;
654 	if (padctl->soc->trk_hw_mode)
655 		value |= USB2_TRK_HW_MODE;
656 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
657 
658 	if (!padctl->soc->trk_hw_mode)
659 		clk_disable_unprepare(priv->usb2_trk_clk);
660 }
661 
662 static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
663 {
664 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
665 	u32 value;
666 
667 	if (!bitmap_empty(priv->utmi_pad_enabled, TEGRA_UTMI_PAD_MAX))
668 		return;
669 
670 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
671 	value |= USB2_PD_TRK;
672 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
673 
674 	if (padctl->soc->trk_hw_mode) {
675 		value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
676 		value &= ~USB2_TRK_HW_MODE;
677 		padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
678 		clk_disable_unprepare(priv->usb2_trk_clk);
679 	}
680 
681 }
682 
683 static void tegra186_utmi_pad_power_on(struct phy *phy)
684 {
685 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
686 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
687 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
688 	struct tegra_xusb_usb2_port *port;
689 	struct device *dev = padctl->dev;
690 	unsigned int index = lane->index;
691 	u32 value;
692 
693 	if (!phy)
694 		return;
695 
696 	mutex_lock(&padctl->lock);
697 	if (test_bit(index, priv->utmi_pad_enabled)) {
698 		mutex_unlock(&padctl->lock);
699 		return;
700 	}
701 
702 	port = tegra_xusb_find_usb2_port(padctl, index);
703 	if (!port) {
704 		dev_err(dev, "no port found for USB2 lane %u\n", index);
705 		mutex_unlock(&padctl->lock);
706 		return;
707 	}
708 
709 	dev_dbg(dev, "power on UTMI pad %u\n", index);
710 
711 	tegra186_utmi_bias_pad_power_on(padctl);
712 
713 	udelay(2);
714 
715 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
716 	value &= ~USB2_OTG_PD;
717 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
718 
719 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
720 	value &= ~USB2_OTG_PD_DR;
721 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
722 
723 	set_bit(index, priv->utmi_pad_enabled);
724 	mutex_unlock(&padctl->lock);
725 }
726 
727 static void tegra186_utmi_pad_power_down(struct phy *phy)
728 {
729 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
730 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
731 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
732 	unsigned int index = lane->index;
733 	u32 value;
734 
735 	if (!phy)
736 		return;
737 
738 	mutex_lock(&padctl->lock);
739 	if (!test_bit(index, priv->utmi_pad_enabled)) {
740 		mutex_unlock(&padctl->lock);
741 		return;
742 	}
743 
744 	dev_dbg(padctl->dev, "power down UTMI pad %u\n", index);
745 
746 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
747 	value |= USB2_OTG_PD;
748 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
749 
750 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
751 	value |= USB2_OTG_PD_DR;
752 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
753 
754 	udelay(2);
755 
756 	clear_bit(index, priv->utmi_pad_enabled);
757 
758 	tegra186_utmi_bias_pad_power_off(padctl);
759 
760 	mutex_unlock(&padctl->lock);
761 }
762 
763 static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
764 					       bool status)
765 {
766 	u32 value;
767 
768 	dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
769 
770 	value = padctl_readl(padctl, USB2_VBUS_ID);
771 
772 	if (status) {
773 		value |= VBUS_OVERRIDE;
774 		value &= ~ID_OVERRIDE(~0);
775 		value |= ID_OVERRIDE_FLOATING;
776 	} else {
777 		value &= ~VBUS_OVERRIDE;
778 	}
779 
780 	padctl_writel(padctl, value, USB2_VBUS_ID);
781 
782 	return 0;
783 }
784 
785 static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
786 					    struct tegra_xusb_usb2_port *port, bool status)
787 {
788 	u32 value, id_override;
789 	int err = 0;
790 
791 	dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
792 
793 	value = padctl_readl(padctl, USB2_VBUS_ID);
794 	id_override = value & ID_OVERRIDE(~0);
795 
796 	if (status) {
797 		if (value & VBUS_OVERRIDE) {
798 			value &= ~VBUS_OVERRIDE;
799 			padctl_writel(padctl, value, USB2_VBUS_ID);
800 			usleep_range(1000, 2000);
801 
802 			value = padctl_readl(padctl, USB2_VBUS_ID);
803 		}
804 
805 		if (id_override != ID_OVERRIDE_GROUNDED) {
806 			value &= ~ID_OVERRIDE(~0);
807 			value |= ID_OVERRIDE_GROUNDED;
808 			padctl_writel(padctl, value, USB2_VBUS_ID);
809 
810 			err = regulator_enable(port->supply);
811 			if (err) {
812 				dev_err(padctl->dev, "Failed to enable regulator: %d\n", err);
813 				return err;
814 			}
815 		}
816 	} else {
817 		if (id_override == ID_OVERRIDE_GROUNDED) {
818 			/*
819 			 * The regulator is disabled only when the role transitions
820 			 * from USB_ROLE_HOST to USB_ROLE_NONE.
821 			 */
822 			err = regulator_disable(port->supply);
823 			if (err) {
824 				dev_err(padctl->dev, "Failed to disable regulator: %d\n", err);
825 				return err;
826 			}
827 
828 			value &= ~ID_OVERRIDE(~0);
829 			value |= ID_OVERRIDE_FLOATING;
830 			padctl_writel(padctl, value, USB2_VBUS_ID);
831 		}
832 	}
833 
834 	return 0;
835 }
836 
837 static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode,
838 				      int submode)
839 {
840 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
841 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
842 	struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
843 								lane->index);
844 	int err = 0;
845 
846 	mutex_lock(&padctl->lock);
847 
848 	dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
849 
850 	if (mode == PHY_MODE_USB_OTG) {
851 		if (submode == USB_ROLE_HOST) {
852 			err = tegra186_xusb_padctl_id_override(padctl, port, true);
853 			if (err)
854 				goto out;
855 		} else if (submode == USB_ROLE_DEVICE) {
856 			tegra186_xusb_padctl_vbus_override(padctl, true);
857 		} else if (submode == USB_ROLE_NONE) {
858 			err = tegra186_xusb_padctl_id_override(padctl, port, false);
859 			if (err)
860 				goto out;
861 			tegra186_xusb_padctl_vbus_override(padctl, false);
862 		}
863 	}
864 out:
865 	mutex_unlock(&padctl->lock);
866 	return err;
867 }
868 
869 static int tegra186_utmi_phy_power_on(struct phy *phy)
870 {
871 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
872 	struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
873 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
874 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
875 	struct tegra_xusb_usb2_port *port;
876 	unsigned int index = lane->index;
877 	struct device *dev = padctl->dev;
878 	u32 value;
879 
880 	port = tegra_xusb_find_usb2_port(padctl, index);
881 	if (!port) {
882 		dev_err(dev, "no port found for USB2 lane %u\n", index);
883 		return -ENODEV;
884 	}
885 
886 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
887 	value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
888 	value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
889 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
890 
891 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
892 	value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
893 
894 	if (port->mode == USB_DR_MODE_UNKNOWN)
895 		value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
896 	else if (port->mode == USB_DR_MODE_PERIPHERAL)
897 		value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
898 	else if (port->mode == USB_DR_MODE_HOST)
899 		value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
900 	else if (port->mode == USB_DR_MODE_OTG)
901 		value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
902 
903 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
904 
905 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
906 	value &= ~USB2_OTG_PD_ZI;
907 	value |= TERM_SEL;
908 	value &= ~HS_CURR_LEVEL(~0);
909 
910 	if (usb2->hs_curr_level_offset) {
911 		int hs_current_level;
912 
913 		hs_current_level = (int)priv->calib.hs_curr_level[index] +
914 						usb2->hs_curr_level_offset;
915 
916 		if (hs_current_level < 0)
917 			hs_current_level = 0;
918 		if (hs_current_level > 0x3f)
919 			hs_current_level = 0x3f;
920 
921 		value |= HS_CURR_LEVEL(hs_current_level);
922 	} else {
923 		value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);
924 	}
925 
926 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
927 
928 	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
929 	value &= ~TERM_RANGE_ADJ(~0);
930 	value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
931 	value &= ~RPD_CTRL(~0);
932 	value |= RPD_CTRL(priv->calib.rpd_ctrl);
933 	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
934 
935 	tegra186_utmi_pad_power_on(phy);
936 
937 	return 0;
938 }
939 
940 static int tegra186_utmi_phy_power_off(struct phy *phy)
941 {
942 	tegra186_utmi_pad_power_down(phy);
943 
944 	return 0;
945 }
946 
947 static int tegra186_utmi_phy_init(struct phy *phy)
948 {
949 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
950 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
951 	struct tegra_xusb_usb2_port *port;
952 	unsigned int index = lane->index;
953 	struct device *dev = padctl->dev;
954 	int err;
955 	u32 reg;
956 
957 	port = tegra_xusb_find_usb2_port(padctl, index);
958 	if (!port) {
959 		dev_err(dev, "no port found for USB2 lane %u\n", index);
960 		return -ENODEV;
961 	}
962 
963 	if (port->mode == USB_DR_MODE_OTG ||
964 	    port->mode == USB_DR_MODE_PERIPHERAL) {
965 		/* reset VBUS&ID OVERRIDE */
966 		reg = padctl_readl(padctl, USB2_VBUS_ID);
967 		reg &= ~VBUS_OVERRIDE;
968 		reg &= ~ID_OVERRIDE(~0);
969 		reg |= ID_OVERRIDE_FLOATING;
970 		padctl_writel(padctl, reg, USB2_VBUS_ID);
971 	}
972 
973 	if (port->supply && port->mode == USB_DR_MODE_HOST) {
974 		err = regulator_enable(port->supply);
975 		if (err) {
976 			dev_err(dev, "failed to enable port %u VBUS: %d\n",
977 				index, err);
978 			return err;
979 		}
980 	}
981 
982 	return 0;
983 }
984 
985 static int tegra186_utmi_phy_exit(struct phy *phy)
986 {
987 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
988 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
989 	struct tegra_xusb_usb2_port *port;
990 	unsigned int index = lane->index;
991 	struct device *dev = padctl->dev;
992 	int err;
993 
994 	port = tegra_xusb_find_usb2_port(padctl, index);
995 	if (!port) {
996 		dev_err(dev, "no port found for USB2 lane %u\n", index);
997 		return -ENODEV;
998 	}
999 
1000 	if (port->supply && port->mode == USB_DR_MODE_HOST) {
1001 		err = regulator_disable(port->supply);
1002 		if (err) {
1003 			dev_err(dev, "failed to disable port %u VBUS: %d\n",
1004 				index, err);
1005 			return err;
1006 		}
1007 	}
1008 
1009 	return 0;
1010 }
1011 
1012 static const struct phy_ops utmi_phy_ops = {
1013 	.init = tegra186_utmi_phy_init,
1014 	.exit = tegra186_utmi_phy_exit,
1015 	.power_on = tegra186_utmi_phy_power_on,
1016 	.power_off = tegra186_utmi_phy_power_off,
1017 	.set_mode = tegra186_utmi_phy_set_mode,
1018 	.owner = THIS_MODULE,
1019 };
1020 
1021 static struct tegra_xusb_pad *
1022 tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
1023 			const struct tegra_xusb_pad_soc *soc,
1024 			struct device_node *np)
1025 {
1026 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1027 	struct tegra_xusb_usb2_pad *usb2;
1028 	struct tegra_xusb_pad *pad;
1029 	int err;
1030 
1031 	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
1032 	if (!usb2)
1033 		return ERR_PTR(-ENOMEM);
1034 
1035 	pad = &usb2->base;
1036 	pad->ops = &tegra186_usb2_lane_ops;
1037 	pad->soc = soc;
1038 
1039 	err = tegra_xusb_pad_init(pad, padctl, np);
1040 	if (err < 0) {
1041 		kfree(usb2);
1042 		goto out;
1043 	}
1044 
1045 	priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
1046 	if (IS_ERR(priv->usb2_trk_clk)) {
1047 		err = PTR_ERR(priv->usb2_trk_clk);
1048 		dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
1049 		goto unregister;
1050 	}
1051 
1052 	err = tegra_xusb_pad_register(pad, &utmi_phy_ops);
1053 	if (err < 0)
1054 		goto unregister;
1055 
1056 	dev_set_drvdata(&pad->dev, pad);
1057 
1058 	return pad;
1059 
1060 unregister:
1061 	device_unregister(&pad->dev);
1062 out:
1063 	return ERR_PTR(err);
1064 }
1065 
1066 static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad)
1067 {
1068 	struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1069 
1070 	kfree(usb2);
1071 }
1072 
1073 static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = {
1074 	.probe = tegra186_usb2_pad_probe,
1075 	.remove = tegra186_usb2_pad_remove,
1076 };
1077 
1078 static const char * const tegra186_usb2_functions[] = {
1079 	"xusb",
1080 };
1081 
1082 static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
1083 {
1084 	return 0;
1085 }
1086 
1087 static void tegra186_usb2_port_disable(struct tegra_xusb_port *port)
1088 {
1089 }
1090 
1091 static struct tegra_xusb_lane *
1092 tegra186_usb2_port_map(struct tegra_xusb_port *port)
1093 {
1094 	return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1095 }
1096 
1097 static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = {
1098 	.release = tegra_xusb_usb2_port_release,
1099 	.remove = tegra_xusb_usb2_port_remove,
1100 	.enable = tegra186_usb2_port_enable,
1101 	.disable = tegra186_usb2_port_disable,
1102 	.map = tegra186_usb2_port_map,
1103 };
1104 
1105 /* SuperSpeed PHY support */
1106 static struct tegra_xusb_lane *
1107 tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1108 			 unsigned int index)
1109 {
1110 	struct tegra_xusb_usb3_lane *usb3;
1111 	int err;
1112 
1113 	usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
1114 	if (!usb3)
1115 		return ERR_PTR(-ENOMEM);
1116 
1117 	INIT_LIST_HEAD(&usb3->base.list);
1118 	usb3->base.soc = &pad->soc->lanes[index];
1119 	usb3->base.index = index;
1120 	usb3->base.pad = pad;
1121 	usb3->base.np = np;
1122 
1123 	err = tegra_xusb_lane_parse_dt(&usb3->base, np);
1124 	if (err < 0) {
1125 		kfree(usb3);
1126 		return ERR_PTR(err);
1127 	}
1128 
1129 	return &usb3->base;
1130 }
1131 
1132 static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane)
1133 {
1134 	struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);
1135 
1136 	kfree(usb3);
1137 }
1138 
1139 static int tegra186_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
1140 					      enum usb_device_speed speed)
1141 {
1142 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1143 	unsigned int index = lane->index;
1144 	u32 value;
1145 
1146 	mutex_lock(&padctl->lock);
1147 
1148 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1149 	value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1150 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1151 
1152 	usleep_range(100, 200);
1153 
1154 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1155 	value |= SSPX_ELPG_CLAMP_EN(index);
1156 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1157 
1158 	usleep_range(250, 350);
1159 
1160 	mutex_unlock(&padctl->lock);
1161 
1162 	return 0;
1163 }
1164 
1165 static int tegra186_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
1166 {
1167 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1168 	unsigned int index = lane->index;
1169 	u32 value;
1170 
1171 	mutex_lock(&padctl->lock);
1172 
1173 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1174 	value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1175 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1176 
1177 	usleep_range(100, 200);
1178 
1179 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1180 	value &= ~SSPX_ELPG_CLAMP_EN(index);
1181 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1182 
1183 	mutex_unlock(&padctl->lock);
1184 
1185 	return 0;
1186 }
1187 
1188 static int tegra186_usb3_enable_phy_wake(struct tegra_xusb_lane *lane)
1189 {
1190 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1191 	unsigned int index = lane->index;
1192 	u32 value;
1193 
1194 	mutex_lock(&padctl->lock);
1195 
1196 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1197 	value &= ~ALL_WAKE_EVENTS;
1198 	value |= SS_PORT_WAKEUP_EVENT(index);
1199 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1200 
1201 	usleep_range(10, 20);
1202 
1203 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1204 	value &= ~ALL_WAKE_EVENTS;
1205 	value |= SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1206 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1207 
1208 	mutex_unlock(&padctl->lock);
1209 
1210 	return 0;
1211 }
1212 
1213 static int tegra186_usb3_disable_phy_wake(struct tegra_xusb_lane *lane)
1214 {
1215 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1216 	unsigned int index = lane->index;
1217 	u32 value;
1218 
1219 	mutex_lock(&padctl->lock);
1220 
1221 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1222 	value &= ~ALL_WAKE_EVENTS;
1223 	value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1224 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1225 
1226 	usleep_range(10, 20);
1227 
1228 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1229 	value &= ~ALL_WAKE_EVENTS;
1230 	value |= SS_PORT_WAKEUP_EVENT(index);
1231 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1232 
1233 	mutex_unlock(&padctl->lock);
1234 
1235 	return 0;
1236 }
1237 
1238 static bool tegra186_usb3_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
1239 {
1240 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1241 	unsigned int index = lane->index;
1242 	u32 value;
1243 
1244 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1245 	if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index)))
1246 		return true;
1247 
1248 	return false;
1249 }
1250 
1251 static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = {
1252 	.probe = tegra186_usb3_lane_probe,
1253 	.remove = tegra186_usb3_lane_remove,
1254 	.enable_phy_sleepwalk = tegra186_usb3_enable_phy_sleepwalk,
1255 	.disable_phy_sleepwalk = tegra186_usb3_disable_phy_sleepwalk,
1256 	.enable_phy_wake = tegra186_usb3_enable_phy_wake,
1257 	.disable_phy_wake = tegra186_usb3_disable_phy_wake,
1258 	.remote_wake_detected = tegra186_usb3_phy_remote_wake_detected,
1259 };
1260 
1261 static int tegra186_usb3_port_enable(struct tegra_xusb_port *port)
1262 {
1263 	return 0;
1264 }
1265 
1266 static void tegra186_usb3_port_disable(struct tegra_xusb_port *port)
1267 {
1268 }
1269 
1270 static struct tegra_xusb_lane *
1271 tegra186_usb3_port_map(struct tegra_xusb_port *port)
1272 {
1273 	return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
1274 }
1275 
1276 static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = {
1277 	.release = tegra_xusb_usb3_port_release,
1278 	.enable = tegra186_usb3_port_enable,
1279 	.disable = tegra186_usb3_port_disable,
1280 	.map = tegra186_usb3_port_map,
1281 };
1282 
1283 static int tegra186_usb3_phy_power_on(struct phy *phy)
1284 {
1285 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1286 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1287 	struct tegra_xusb_usb3_port *port;
1288 	struct tegra_xusb_usb2_port *usb2;
1289 	unsigned int index = lane->index;
1290 	struct device *dev = padctl->dev;
1291 	u32 value;
1292 
1293 	port = tegra_xusb_find_usb3_port(padctl, index);
1294 	if (!port) {
1295 		dev_err(dev, "no port found for USB3 lane %u\n", index);
1296 		return -ENODEV;
1297 	}
1298 
1299 	usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
1300 	if (!usb2) {
1301 		dev_err(dev, "no companion port found for USB3 lane %u\n",
1302 			index);
1303 		return -ENODEV;
1304 	}
1305 
1306 	mutex_lock(&padctl->lock);
1307 
1308 	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1309 	value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
1310 
1311 	if (usb2->mode == USB_DR_MODE_UNKNOWN)
1312 		value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
1313 	else if (usb2->mode == USB_DR_MODE_PERIPHERAL)
1314 		value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
1315 	else if (usb2->mode == USB_DR_MODE_HOST)
1316 		value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
1317 	else if (usb2->mode == USB_DR_MODE_OTG)
1318 		value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
1319 
1320 	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
1321 
1322 	if (padctl->soc->supports_gen2 && port->disable_gen2) {
1323 		value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
1324 		value &= ~(PORTX_SPEED_SUPPORT_MASK <<
1325 			PORTX_SPEED_SUPPORT_SHIFT(index));
1326 		value |= (PORT_SPEED_SUPPORT_GEN1 <<
1327 			PORTX_SPEED_SUPPORT_SHIFT(index));
1328 		padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
1329 	}
1330 
1331 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1332 	value &= ~SSPX_ELPG_VCORE_DOWN(index);
1333 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1334 
1335 	usleep_range(100, 200);
1336 
1337 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1338 	value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1339 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1340 
1341 	usleep_range(100, 200);
1342 
1343 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1344 	value &= ~SSPX_ELPG_CLAMP_EN(index);
1345 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1346 
1347 	mutex_unlock(&padctl->lock);
1348 
1349 	return 0;
1350 }
1351 
1352 static int tegra186_usb3_phy_power_off(struct phy *phy)
1353 {
1354 	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1355 	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1356 	struct tegra_xusb_usb3_port *port;
1357 	unsigned int index = lane->index;
1358 	struct device *dev = padctl->dev;
1359 	u32 value;
1360 
1361 	port = tegra_xusb_find_usb3_port(padctl, index);
1362 	if (!port) {
1363 		dev_err(dev, "no port found for USB3 lane %u\n", index);
1364 		return -ENODEV;
1365 	}
1366 
1367 	mutex_lock(&padctl->lock);
1368 
1369 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1370 	value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1371 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1372 
1373 	usleep_range(100, 200);
1374 
1375 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1376 	value |= SSPX_ELPG_CLAMP_EN(index);
1377 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1378 
1379 	usleep_range(250, 350);
1380 
1381 	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1382 	value |= SSPX_ELPG_VCORE_DOWN(index);
1383 	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1384 
1385 	mutex_unlock(&padctl->lock);
1386 
1387 	return 0;
1388 }
1389 
1390 static int tegra186_usb3_phy_init(struct phy *phy)
1391 {
1392 	return 0;
1393 }
1394 
1395 static int tegra186_usb3_phy_exit(struct phy *phy)
1396 {
1397 	return 0;
1398 }
1399 
1400 static const struct phy_ops usb3_phy_ops = {
1401 	.init = tegra186_usb3_phy_init,
1402 	.exit = tegra186_usb3_phy_exit,
1403 	.power_on = tegra186_usb3_phy_power_on,
1404 	.power_off = tegra186_usb3_phy_power_off,
1405 	.owner = THIS_MODULE,
1406 };
1407 
1408 static struct tegra_xusb_pad *
1409 tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
1410 			const struct tegra_xusb_pad_soc *soc,
1411 			struct device_node *np)
1412 {
1413 	struct tegra_xusb_usb3_pad *usb3;
1414 	struct tegra_xusb_pad *pad;
1415 	int err;
1416 
1417 	usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
1418 	if (!usb3)
1419 		return ERR_PTR(-ENOMEM);
1420 
1421 	pad = &usb3->base;
1422 	pad->ops = &tegra186_usb3_lane_ops;
1423 	pad->soc = soc;
1424 
1425 	err = tegra_xusb_pad_init(pad, padctl, np);
1426 	if (err < 0) {
1427 		kfree(usb3);
1428 		goto out;
1429 	}
1430 
1431 	err = tegra_xusb_pad_register(pad, &usb3_phy_ops);
1432 	if (err < 0)
1433 		goto unregister;
1434 
1435 	dev_set_drvdata(&pad->dev, pad);
1436 
1437 	return pad;
1438 
1439 unregister:
1440 	device_unregister(&pad->dev);
1441 out:
1442 	return ERR_PTR(err);
1443 }
1444 
1445 static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad)
1446 {
1447 	struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1448 
1449 	kfree(usb2);
1450 }
1451 
1452 static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = {
1453 	.probe = tegra186_usb3_pad_probe,
1454 	.remove = tegra186_usb3_pad_remove,
1455 };
1456 
1457 static const char * const tegra186_usb3_functions[] = {
1458 	"xusb",
1459 };
1460 
1461 static int
1462 tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
1463 {
1464 	struct device *dev = padctl->base.dev;
1465 	unsigned int i, count;
1466 	u32 value, *level;
1467 	int err;
1468 
1469 	count = padctl->base.soc->ports.usb2.count;
1470 
1471 	level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
1472 	if (!level)
1473 		return -ENOMEM;
1474 
1475 	err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
1476 	if (err)
1477 		return dev_err_probe(dev, err,
1478 				     "failed to read calibration fuse\n");
1479 
1480 	dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value);
1481 
1482 	for (i = 0; i < count; i++)
1483 		level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) &
1484 				HS_CURR_LEVEL_PAD_MASK;
1485 
1486 	padctl->calib.hs_curr_level = level;
1487 
1488 	padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
1489 					HS_SQUELCH_MASK;
1490 	padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
1491 						HS_TERM_RANGE_ADJ_MASK;
1492 
1493 	err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
1494 	if (err) {
1495 		dev_err(dev, "failed to read calibration fuse: %d\n", err);
1496 		return err;
1497 	}
1498 
1499 	dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value);
1500 
1501 	padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
1502 
1503 	return 0;
1504 }
1505 
1506 static struct tegra_xusb_padctl *
1507 tegra186_xusb_padctl_probe(struct device *dev,
1508 			   const struct tegra_xusb_padctl_soc *soc)
1509 {
1510 	struct platform_device *pdev = to_platform_device(dev);
1511 	struct tegra186_xusb_padctl *priv;
1512 	struct resource *res;
1513 	int err;
1514 
1515 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1516 	if (!priv)
1517 		return ERR_PTR(-ENOMEM);
1518 
1519 	priv->base.dev = dev;
1520 	priv->base.soc = soc;
1521 
1522 	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao");
1523 	priv->ao_regs = devm_ioremap_resource(dev, res);
1524 	if (IS_ERR(priv->ao_regs))
1525 		return ERR_CAST(priv->ao_regs);
1526 
1527 	err = tegra186_xusb_read_fuse_calibration(priv);
1528 	if (err < 0)
1529 		return ERR_PTR(err);
1530 
1531 	return &priv->base;
1532 }
1533 
1534 static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
1535 {
1536 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1537 
1538 	priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);
1539 	priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1540 	priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
1541 	priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1542 }
1543 
1544 static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
1545 {
1546 	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1547 
1548 	padctl_writel(padctl, priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX);
1549 	padctl_writel(padctl, priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP);
1550 	padctl_writel(padctl, priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP);
1551 	padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID);
1552 }
1553 
1554 static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
1555 {
1556 	tegra186_xusb_padctl_save(padctl);
1557 
1558 	return 0;
1559 }
1560 
1561 static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
1562 {
1563 	tegra186_xusb_padctl_restore(padctl);
1564 
1565 	return 0;
1566 }
1567 
1568 static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
1569 {
1570 }
1571 
1572 static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
1573 	.probe = tegra186_xusb_padctl_probe,
1574 	.remove = tegra186_xusb_padctl_remove,
1575 	.suspend_noirq = tegra186_xusb_padctl_suspend_noirq,
1576 	.resume_noirq = tegra186_xusb_padctl_resume_noirq,
1577 	.vbus_override = tegra186_xusb_padctl_vbus_override,
1578 	.utmi_pad_power_on = tegra186_utmi_pad_power_on,
1579 	.utmi_pad_power_down = tegra186_utmi_pad_power_down,
1580 };
1581 
1582 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
1583 static const char * const tegra186_xusb_padctl_supply_names[] = {
1584 	"avdd-pll-erefeut",
1585 	"avdd-usb",
1586 	"vclamp-usb",
1587 	"vddio-hsic",
1588 };
1589 
1590 static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
1591 	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
1592 	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
1593 	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
1594 };
1595 
1596 static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
1597 	.name = "usb2",
1598 	.num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
1599 	.lanes = tegra186_usb2_lanes,
1600 	.ops = &tegra186_usb2_pad_ops,
1601 };
1602 
1603 static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
1604 	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
1605 	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
1606 	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
1607 };
1608 
1609 static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
1610 	.name = "usb3",
1611 	.num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
1612 	.lanes = tegra186_usb3_lanes,
1613 	.ops = &tegra186_usb3_pad_ops,
1614 };
1615 
1616 static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
1617 	&tegra186_usb2_pad,
1618 	&tegra186_usb3_pad,
1619 #if 0 /* TODO implement */
1620 	&tegra186_hsic_pad,
1621 #endif
1622 };
1623 
1624 const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
1625 	.num_pads = ARRAY_SIZE(tegra186_pads),
1626 	.pads = tegra186_pads,
1627 	.ports = {
1628 		.usb2 = {
1629 			.ops = &tegra186_usb2_port_ops,
1630 			.count = 3,
1631 		},
1632 #if 0 /* TODO implement */
1633 		.hsic = {
1634 			.ops = &tegra186_hsic_port_ops,
1635 			.count = 1,
1636 		},
1637 #endif
1638 		.usb3 = {
1639 			.ops = &tegra186_usb3_port_ops,
1640 			.count = 3,
1641 		},
1642 	},
1643 	.ops = &tegra186_xusb_padctl_ops,
1644 	.supply_names = tegra186_xusb_padctl_supply_names,
1645 	.num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
1646 };
1647 EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
1648 #endif
1649 
1650 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
1651 	IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
1652 static const char * const tegra194_xusb_padctl_supply_names[] = {
1653 	"avdd-usb",
1654 	"vclamp-usb",
1655 };
1656 
1657 static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
1658 	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
1659 	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
1660 	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
1661 	TEGRA186_LANE("usb2-3", 0,  0, 0, usb2),
1662 };
1663 
1664 static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
1665 	.name = "usb2",
1666 	.num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
1667 	.lanes = tegra194_usb2_lanes,
1668 	.ops = &tegra186_usb2_pad_ops,
1669 };
1670 
1671 static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
1672 	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
1673 	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
1674 	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
1675 	TEGRA186_LANE("usb3-3", 0,  0, 0, usb3),
1676 };
1677 
1678 static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
1679 	.name = "usb3",
1680 	.num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
1681 	.lanes = tegra194_usb3_lanes,
1682 	.ops = &tegra186_usb3_pad_ops,
1683 };
1684 
1685 static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
1686 	&tegra194_usb2_pad,
1687 	&tegra194_usb3_pad,
1688 };
1689 
1690 const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
1691 	.num_pads = ARRAY_SIZE(tegra194_pads),
1692 	.pads = tegra194_pads,
1693 	.ports = {
1694 		.usb2 = {
1695 			.ops = &tegra186_usb2_port_ops,
1696 			.count = 4,
1697 		},
1698 		.usb3 = {
1699 			.ops = &tegra186_usb3_port_ops,
1700 			.count = 4,
1701 		},
1702 	},
1703 	.ops = &tegra186_xusb_padctl_ops,
1704 	.supply_names = tegra194_xusb_padctl_supply_names,
1705 	.num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1706 	.supports_gen2 = true,
1707 	.poll_trk_completed = true,
1708 };
1709 EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
1710 
1711 const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = {
1712 	.num_pads = ARRAY_SIZE(tegra194_pads),
1713 	.pads = tegra194_pads,
1714 	.ports = {
1715 		.usb2 = {
1716 			.ops = &tegra186_usb2_port_ops,
1717 			.count = 4,
1718 		},
1719 		.usb3 = {
1720 			.ops = &tegra186_usb3_port_ops,
1721 			.count = 4,
1722 		},
1723 	},
1724 	.ops = &tegra186_xusb_padctl_ops,
1725 	.supply_names = tegra194_xusb_padctl_supply_names,
1726 	.num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1727 	.supports_gen2 = true,
1728 	.poll_trk_completed = true,
1729 	.trk_hw_mode = false,
1730 	.trk_update_on_idle = true,
1731 	.supports_lp_cfg_en = true,
1732 };
1733 EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc);
1734 #endif
1735 
1736 MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
1737 MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
1738 MODULE_LICENSE("GPL v2");
1739