1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2017-2025 NVIDIA CORPORATION. All rights reserved.
4 */
5
6 #include <linux/io.h>
7 #include <linux/iommu.h>
8 #include <linux/module.h>
9 #include <linux/mod_devicetable.h>
10 #include <linux/of.h>
11 #include <linux/of_platform.h>
12 #include <linux/platform_device.h>
13
14 #include <soc/tegra/mc.h>
15
16 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
17 #include <dt-bindings/memory/tegra186-mc.h>
18 #endif
19
20 #include "mc.h"
21
22 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
23 #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
24 #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
25
tegra186_mc_probe(struct tegra_mc * mc)26 static int tegra186_mc_probe(struct tegra_mc *mc)
27 {
28 struct platform_device *pdev = to_platform_device(mc->dev);
29 struct resource *res;
30 unsigned int i;
31 char name[8];
32 int err;
33
34 /*
35 * From Tegra264, the SID region is not present in MC node and BROADCAST is first.
36 * The common function 'tegra_mc_probe()' already maps first region entry from DT.
37 * Check if the SID region is present in DT then map BROADCAST. Otherwise, consider
38 * the first entry mapped in mc probe as the BROADCAST region. This is done to avoid
39 * mapping the region twice when SID is not present and keep backward compatibility.
40 */
41 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sid");
42 if (res)
43 mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
44 else
45 mc->bcast_ch_regs = mc->regs;
46
47 if (IS_ERR(mc->bcast_ch_regs)) {
48 if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) {
49 dev_warn(&pdev->dev,
50 "Broadcast channel is missing, please update your device-tree\n");
51 mc->bcast_ch_regs = NULL;
52 goto populate;
53 }
54
55 return PTR_ERR(mc->bcast_ch_regs);
56 }
57
58 mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs),
59 GFP_KERNEL);
60 if (!mc->ch_regs)
61 return -ENOMEM;
62
63 for (i = 0; i < mc->soc->num_channels; i++) {
64 snprintf(name, sizeof(name), "ch%u", i);
65
66 mc->ch_regs[i] = devm_platform_ioremap_resource_byname(pdev, name);
67 if (IS_ERR(mc->ch_regs[i]))
68 return PTR_ERR(mc->ch_regs[i]);
69 }
70
71 populate:
72 err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
73 if (err < 0)
74 return err;
75
76 return 0;
77 }
78
tegra186_mc_remove(struct tegra_mc * mc)79 static void tegra186_mc_remove(struct tegra_mc *mc)
80 {
81 of_platform_depopulate(mc->dev);
82 }
83
84 #if IS_ENABLED(CONFIG_IOMMU_API)
tegra186_mc_client_sid_override(struct tegra_mc * mc,const struct tegra_mc_client * client,unsigned int sid)85 static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
86 const struct tegra_mc_client *client,
87 unsigned int sid)
88 {
89 u32 value, old;
90
91 if (client->regs.sid.security == 0 && client->regs.sid.override == 0)
92 return;
93
94 value = readl(mc->regs + client->regs.sid.security);
95 if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
96 /*
97 * If the secure firmware has locked this down the override
98 * for this memory client, there's nothing we can do here.
99 */
100 if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
101 return;
102
103 /*
104 * Otherwise, try to set the override itself. Typically the
105 * secure firmware will never have set this configuration.
106 * Instead, it will either have disabled write access to
107 * this field, or it will already have set an explicit
108 * override itself.
109 */
110 WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
111
112 value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
113 writel(value, mc->regs + client->regs.sid.security);
114 }
115
116 value = readl(mc->regs + client->regs.sid.override);
117 old = value & MC_SID_STREAMID_OVERRIDE_MASK;
118
119 if (old != sid) {
120 dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
121 client->name, sid);
122 writel(sid, mc->regs + client->regs.sid.override);
123 }
124 }
125 #endif
126
tegra186_mc_probe_device(struct tegra_mc * mc,struct device * dev)127 static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
128 {
129 #if IS_ENABLED(CONFIG_IOMMU_API)
130 struct of_phandle_args args;
131 unsigned int i, index = 0;
132 u32 sid;
133
134 if (!tegra_dev_iommu_get_stream_id(dev, &sid))
135 return 0;
136
137 while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
138 index, &args)) {
139 if (args.np == mc->dev->of_node && args.args_count != 0) {
140 for (i = 0; i < mc->soc->num_clients; i++) {
141 const struct tegra_mc_client *client = &mc->soc->clients[i];
142
143 if (client->id == args.args[0])
144 tegra186_mc_client_sid_override(
145 mc, client,
146 sid & MC_SID_STREAMID_OVERRIDE_MASK);
147 }
148 }
149
150 index++;
151 }
152 #endif
153
154 return 0;
155 }
156
tegra186_mc_resume(struct tegra_mc * mc)157 static int tegra186_mc_resume(struct tegra_mc *mc)
158 {
159 #if IS_ENABLED(CONFIG_IOMMU_API)
160 unsigned int i;
161
162 for (i = 0; i < mc->soc->num_clients; i++) {
163 const struct tegra_mc_client *client = &mc->soc->clients[i];
164
165 tegra186_mc_client_sid_override(mc, client, client->sid);
166 }
167 #endif
168
169 return 0;
170 }
171
172 const struct tegra_mc_ops tegra186_mc_ops = {
173 .probe = tegra186_mc_probe,
174 .remove = tegra186_mc_remove,
175 .resume = tegra186_mc_resume,
176 .probe_device = tegra186_mc_probe_device,
177 .handle_irq = tegra30_mc_handle_irq,
178 };
179
180 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
181 static const struct tegra_mc_client tegra186_mc_clients[] = {
182 {
183 .id = TEGRA186_MEMORY_CLIENT_PTCR,
184 .name = "ptcr",
185 .sid = TEGRA186_SID_PASSTHROUGH,
186 .regs = {
187 .sid = {
188 .override = 0x000,
189 .security = 0x004,
190 },
191 },
192 }, {
193 .id = TEGRA186_MEMORY_CLIENT_AFIR,
194 .name = "afir",
195 .sid = TEGRA186_SID_AFI,
196 .regs = {
197 .sid = {
198 .override = 0x070,
199 .security = 0x074,
200 },
201 },
202 }, {
203 .id = TEGRA186_MEMORY_CLIENT_HDAR,
204 .name = "hdar",
205 .sid = TEGRA186_SID_HDA,
206 .regs = {
207 .sid = {
208 .override = 0x0a8,
209 .security = 0x0ac,
210 },
211 },
212 }, {
213 .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
214 .name = "host1xdmar",
215 .sid = TEGRA186_SID_HOST1X,
216 .regs = {
217 .sid = {
218 .override = 0x0b0,
219 .security = 0x0b4,
220 },
221 },
222 }, {
223 .id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
224 .name = "nvencsrd",
225 .sid = TEGRA186_SID_NVENC,
226 .regs = {
227 .sid = {
228 .override = 0x0e0,
229 .security = 0x0e4,
230 },
231 },
232 }, {
233 .id = TEGRA186_MEMORY_CLIENT_SATAR,
234 .name = "satar",
235 .sid = TEGRA186_SID_SATA,
236 .regs = {
237 .sid = {
238 .override = 0x0f8,
239 .security = 0x0fc,
240 },
241 },
242 }, {
243 .id = TEGRA186_MEMORY_CLIENT_MPCORER,
244 .name = "mpcorer",
245 .sid = TEGRA186_SID_PASSTHROUGH,
246 .regs = {
247 .sid = {
248 .override = 0x138,
249 .security = 0x13c,
250 },
251 },
252 }, {
253 .id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
254 .name = "nvencswr",
255 .sid = TEGRA186_SID_NVENC,
256 .regs = {
257 .sid = {
258 .override = 0x158,
259 .security = 0x15c,
260 },
261 },
262 }, {
263 .id = TEGRA186_MEMORY_CLIENT_AFIW,
264 .name = "afiw",
265 .sid = TEGRA186_SID_AFI,
266 .regs = {
267 .sid = {
268 .override = 0x188,
269 .security = 0x18c,
270 },
271 },
272 }, {
273 .id = TEGRA186_MEMORY_CLIENT_HDAW,
274 .name = "hdaw",
275 .sid = TEGRA186_SID_HDA,
276 .regs = {
277 .sid = {
278 .override = 0x1a8,
279 .security = 0x1ac,
280 },
281 },
282 }, {
283 .id = TEGRA186_MEMORY_CLIENT_MPCOREW,
284 .name = "mpcorew",
285 .sid = TEGRA186_SID_PASSTHROUGH,
286 .regs = {
287 .sid = {
288 .override = 0x1c8,
289 .security = 0x1cc,
290 },
291 },
292 }, {
293 .id = TEGRA186_MEMORY_CLIENT_SATAW,
294 .name = "sataw",
295 .sid = TEGRA186_SID_SATA,
296 .regs = {
297 .sid = {
298 .override = 0x1e8,
299 .security = 0x1ec,
300 },
301 },
302 }, {
303 .id = TEGRA186_MEMORY_CLIENT_ISPRA,
304 .name = "ispra",
305 .sid = TEGRA186_SID_ISP,
306 .regs = {
307 .sid = {
308 .override = 0x220,
309 .security = 0x224,
310 },
311 },
312 }, {
313 .id = TEGRA186_MEMORY_CLIENT_ISPWA,
314 .name = "ispwa",
315 .sid = TEGRA186_SID_ISP,
316 .regs = {
317 .sid = {
318 .override = 0x230,
319 .security = 0x234,
320 },
321 },
322 }, {
323 .id = TEGRA186_MEMORY_CLIENT_ISPWB,
324 .name = "ispwb",
325 .sid = TEGRA186_SID_ISP,
326 .regs = {
327 .sid = {
328 .override = 0x238,
329 .security = 0x23c,
330 },
331 },
332 }, {
333 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR,
334 .name = "xusb_hostr",
335 .sid = TEGRA186_SID_XUSB_HOST,
336 .regs = {
337 .sid = {
338 .override = 0x250,
339 .security = 0x254,
340 },
341 },
342 }, {
343 .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW,
344 .name = "xusb_hostw",
345 .sid = TEGRA186_SID_XUSB_HOST,
346 .regs = {
347 .sid = {
348 .override = 0x258,
349 .security = 0x25c,
350 },
351 },
352 }, {
353 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR,
354 .name = "xusb_devr",
355 .sid = TEGRA186_SID_XUSB_DEV,
356 .regs = {
357 .sid = {
358 .override = 0x260,
359 .security = 0x264,
360 },
361 },
362 }, {
363 .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW,
364 .name = "xusb_devw",
365 .sid = TEGRA186_SID_XUSB_DEV,
366 .regs = {
367 .sid = {
368 .override = 0x268,
369 .security = 0x26c,
370 },
371 },
372 }, {
373 .id = TEGRA186_MEMORY_CLIENT_TSECSRD,
374 .name = "tsecsrd",
375 .sid = TEGRA186_SID_TSEC,
376 .regs = {
377 .sid = {
378 .override = 0x2a0,
379 .security = 0x2a4,
380 },
381 },
382 }, {
383 .id = TEGRA186_MEMORY_CLIENT_TSECSWR,
384 .name = "tsecswr",
385 .sid = TEGRA186_SID_TSEC,
386 .regs = {
387 .sid = {
388 .override = 0x2a8,
389 .security = 0x2ac,
390 },
391 },
392 }, {
393 .id = TEGRA186_MEMORY_CLIENT_GPUSRD,
394 .name = "gpusrd",
395 .sid = TEGRA186_SID_GPU,
396 .regs = {
397 .sid = {
398 .override = 0x2c0,
399 .security = 0x2c4,
400 },
401 },
402 }, {
403 .id = TEGRA186_MEMORY_CLIENT_GPUSWR,
404 .name = "gpuswr",
405 .sid = TEGRA186_SID_GPU,
406 .regs = {
407 .sid = {
408 .override = 0x2c8,
409 .security = 0x2cc,
410 },
411 },
412 }, {
413 .id = TEGRA186_MEMORY_CLIENT_SDMMCRA,
414 .name = "sdmmcra",
415 .sid = TEGRA186_SID_SDMMC1,
416 .regs = {
417 .sid = {
418 .override = 0x300,
419 .security = 0x304,
420 },
421 },
422 }, {
423 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA,
424 .name = "sdmmcraa",
425 .sid = TEGRA186_SID_SDMMC2,
426 .regs = {
427 .sid = {
428 .override = 0x308,
429 .security = 0x30c,
430 },
431 },
432 }, {
433 .id = TEGRA186_MEMORY_CLIENT_SDMMCR,
434 .name = "sdmmcr",
435 .sid = TEGRA186_SID_SDMMC3,
436 .regs = {
437 .sid = {
438 .override = 0x310,
439 .security = 0x314,
440 },
441 },
442 }, {
443 .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB,
444 .name = "sdmmcrab",
445 .sid = TEGRA186_SID_SDMMC4,
446 .regs = {
447 .sid = {
448 .override = 0x318,
449 .security = 0x31c,
450 },
451 },
452 }, {
453 .id = TEGRA186_MEMORY_CLIENT_SDMMCWA,
454 .name = "sdmmcwa",
455 .sid = TEGRA186_SID_SDMMC1,
456 .regs = {
457 .sid = {
458 .override = 0x320,
459 .security = 0x324,
460 },
461 },
462 }, {
463 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA,
464 .name = "sdmmcwaa",
465 .sid = TEGRA186_SID_SDMMC2,
466 .regs = {
467 .sid = {
468 .override = 0x328,
469 .security = 0x32c,
470 },
471 },
472 }, {
473 .id = TEGRA186_MEMORY_CLIENT_SDMMCW,
474 .name = "sdmmcw",
475 .sid = TEGRA186_SID_SDMMC3,
476 .regs = {
477 .sid = {
478 .override = 0x330,
479 .security = 0x334,
480 },
481 },
482 }, {
483 .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB,
484 .name = "sdmmcwab",
485 .sid = TEGRA186_SID_SDMMC4,
486 .regs = {
487 .sid = {
488 .override = 0x338,
489 .security = 0x33c,
490 },
491 },
492 }, {
493 .id = TEGRA186_MEMORY_CLIENT_VICSRD,
494 .name = "vicsrd",
495 .sid = TEGRA186_SID_VIC,
496 .regs = {
497 .sid = {
498 .override = 0x360,
499 .security = 0x364,
500 },
501 },
502 }, {
503 .id = TEGRA186_MEMORY_CLIENT_VICSWR,
504 .name = "vicswr",
505 .sid = TEGRA186_SID_VIC,
506 .regs = {
507 .sid = {
508 .override = 0x368,
509 .security = 0x36c,
510 },
511 },
512 }, {
513 .id = TEGRA186_MEMORY_CLIENT_VIW,
514 .name = "viw",
515 .sid = TEGRA186_SID_VI,
516 .regs = {
517 .sid = {
518 .override = 0x390,
519 .security = 0x394,
520 },
521 },
522 }, {
523 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD,
524 .name = "nvdecsrd",
525 .sid = TEGRA186_SID_NVDEC,
526 .regs = {
527 .sid = {
528 .override = 0x3c0,
529 .security = 0x3c4,
530 },
531 },
532 }, {
533 .id = TEGRA186_MEMORY_CLIENT_NVDECSWR,
534 .name = "nvdecswr",
535 .sid = TEGRA186_SID_NVDEC,
536 .regs = {
537 .sid = {
538 .override = 0x3c8,
539 .security = 0x3cc,
540 },
541 },
542 }, {
543 .id = TEGRA186_MEMORY_CLIENT_APER,
544 .name = "aper",
545 .sid = TEGRA186_SID_APE,
546 .regs = {
547 .sid = {
548 .override = 0x3d0,
549 .security = 0x3d4,
550 },
551 },
552 }, {
553 .id = TEGRA186_MEMORY_CLIENT_APEW,
554 .name = "apew",
555 .sid = TEGRA186_SID_APE,
556 .regs = {
557 .sid = {
558 .override = 0x3d8,
559 .security = 0x3dc,
560 },
561 },
562 }, {
563 .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD,
564 .name = "nvjpgsrd",
565 .sid = TEGRA186_SID_NVJPG,
566 .regs = {
567 .sid = {
568 .override = 0x3f0,
569 .security = 0x3f4,
570 },
571 },
572 }, {
573 .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR,
574 .name = "nvjpgswr",
575 .sid = TEGRA186_SID_NVJPG,
576 .regs = {
577 .sid = {
578 .override = 0x3f8,
579 .security = 0x3fc,
580 },
581 },
582 }, {
583 .id = TEGRA186_MEMORY_CLIENT_SESRD,
584 .name = "sesrd",
585 .sid = TEGRA186_SID_SE,
586 .regs = {
587 .sid = {
588 .override = 0x400,
589 .security = 0x404,
590 },
591 },
592 }, {
593 .id = TEGRA186_MEMORY_CLIENT_SESWR,
594 .name = "seswr",
595 .sid = TEGRA186_SID_SE,
596 .regs = {
597 .sid = {
598 .override = 0x408,
599 .security = 0x40c,
600 },
601 },
602 }, {
603 .id = TEGRA186_MEMORY_CLIENT_ETRR,
604 .name = "etrr",
605 .sid = TEGRA186_SID_ETR,
606 .regs = {
607 .sid = {
608 .override = 0x420,
609 .security = 0x424,
610 },
611 },
612 }, {
613 .id = TEGRA186_MEMORY_CLIENT_ETRW,
614 .name = "etrw",
615 .sid = TEGRA186_SID_ETR,
616 .regs = {
617 .sid = {
618 .override = 0x428,
619 .security = 0x42c,
620 },
621 },
622 }, {
623 .id = TEGRA186_MEMORY_CLIENT_TSECSRDB,
624 .name = "tsecsrdb",
625 .sid = TEGRA186_SID_TSECB,
626 .regs = {
627 .sid = {
628 .override = 0x430,
629 .security = 0x434,
630 },
631 },
632 }, {
633 .id = TEGRA186_MEMORY_CLIENT_TSECSWRB,
634 .name = "tsecswrb",
635 .sid = TEGRA186_SID_TSECB,
636 .regs = {
637 .sid = {
638 .override = 0x438,
639 .security = 0x43c,
640 },
641 },
642 }, {
643 .id = TEGRA186_MEMORY_CLIENT_GPUSRD2,
644 .name = "gpusrd2",
645 .sid = TEGRA186_SID_GPU,
646 .regs = {
647 .sid = {
648 .override = 0x440,
649 .security = 0x444,
650 },
651 },
652 }, {
653 .id = TEGRA186_MEMORY_CLIENT_GPUSWR2,
654 .name = "gpuswr2",
655 .sid = TEGRA186_SID_GPU,
656 .regs = {
657 .sid = {
658 .override = 0x448,
659 .security = 0x44c,
660 },
661 },
662 }, {
663 .id = TEGRA186_MEMORY_CLIENT_AXISR,
664 .name = "axisr",
665 .sid = TEGRA186_SID_GPCDMA_0,
666 .regs = {
667 .sid = {
668 .override = 0x460,
669 .security = 0x464,
670 },
671 },
672 }, {
673 .id = TEGRA186_MEMORY_CLIENT_AXISW,
674 .name = "axisw",
675 .sid = TEGRA186_SID_GPCDMA_0,
676 .regs = {
677 .sid = {
678 .override = 0x468,
679 .security = 0x46c,
680 },
681 },
682 }, {
683 .id = TEGRA186_MEMORY_CLIENT_EQOSR,
684 .name = "eqosr",
685 .sid = TEGRA186_SID_EQOS,
686 .regs = {
687 .sid = {
688 .override = 0x470,
689 .security = 0x474,
690 },
691 },
692 }, {
693 .id = TEGRA186_MEMORY_CLIENT_EQOSW,
694 .name = "eqosw",
695 .sid = TEGRA186_SID_EQOS,
696 .regs = {
697 .sid = {
698 .override = 0x478,
699 .security = 0x47c,
700 },
701 },
702 }, {
703 .id = TEGRA186_MEMORY_CLIENT_UFSHCR,
704 .name = "ufshcr",
705 .sid = TEGRA186_SID_UFSHC,
706 .regs = {
707 .sid = {
708 .override = 0x480,
709 .security = 0x484,
710 },
711 },
712 }, {
713 .id = TEGRA186_MEMORY_CLIENT_UFSHCW,
714 .name = "ufshcw",
715 .sid = TEGRA186_SID_UFSHC,
716 .regs = {
717 .sid = {
718 .override = 0x488,
719 .security = 0x48c,
720 },
721 },
722 }, {
723 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR,
724 .name = "nvdisplayr",
725 .sid = TEGRA186_SID_NVDISPLAY,
726 .regs = {
727 .sid = {
728 .override = 0x490,
729 .security = 0x494,
730 },
731 },
732 }, {
733 .id = TEGRA186_MEMORY_CLIENT_BPMPR,
734 .name = "bpmpr",
735 .sid = TEGRA186_SID_BPMP,
736 .regs = {
737 .sid = {
738 .override = 0x498,
739 .security = 0x49c,
740 },
741 },
742 }, {
743 .id = TEGRA186_MEMORY_CLIENT_BPMPW,
744 .name = "bpmpw",
745 .sid = TEGRA186_SID_BPMP,
746 .regs = {
747 .sid = {
748 .override = 0x4a0,
749 .security = 0x4a4,
750 },
751 },
752 }, {
753 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR,
754 .name = "bpmpdmar",
755 .sid = TEGRA186_SID_BPMP,
756 .regs = {
757 .sid = {
758 .override = 0x4a8,
759 .security = 0x4ac,
760 },
761 },
762 }, {
763 .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW,
764 .name = "bpmpdmaw",
765 .sid = TEGRA186_SID_BPMP,
766 .regs = {
767 .sid = {
768 .override = 0x4b0,
769 .security = 0x4b4,
770 },
771 },
772 }, {
773 .id = TEGRA186_MEMORY_CLIENT_AONR,
774 .name = "aonr",
775 .sid = TEGRA186_SID_AON,
776 .regs = {
777 .sid = {
778 .override = 0x4b8,
779 .security = 0x4bc,
780 },
781 },
782 }, {
783 .id = TEGRA186_MEMORY_CLIENT_AONW,
784 .name = "aonw",
785 .sid = TEGRA186_SID_AON,
786 .regs = {
787 .sid = {
788 .override = 0x4c0,
789 .security = 0x4c4,
790 },
791 },
792 }, {
793 .id = TEGRA186_MEMORY_CLIENT_AONDMAR,
794 .name = "aondmar",
795 .sid = TEGRA186_SID_AON,
796 .regs = {
797 .sid = {
798 .override = 0x4c8,
799 .security = 0x4cc,
800 },
801 },
802 }, {
803 .id = TEGRA186_MEMORY_CLIENT_AONDMAW,
804 .name = "aondmaw",
805 .sid = TEGRA186_SID_AON,
806 .regs = {
807 .sid = {
808 .override = 0x4d0,
809 .security = 0x4d4,
810 },
811 },
812 }, {
813 .id = TEGRA186_MEMORY_CLIENT_SCER,
814 .name = "scer",
815 .sid = TEGRA186_SID_SCE,
816 .regs = {
817 .sid = {
818 .override = 0x4d8,
819 .security = 0x4dc,
820 },
821 },
822 }, {
823 .id = TEGRA186_MEMORY_CLIENT_SCEW,
824 .name = "scew",
825 .sid = TEGRA186_SID_SCE,
826 .regs = {
827 .sid = {
828 .override = 0x4e0,
829 .security = 0x4e4,
830 },
831 },
832 }, {
833 .id = TEGRA186_MEMORY_CLIENT_SCEDMAR,
834 .name = "scedmar",
835 .sid = TEGRA186_SID_SCE,
836 .regs = {
837 .sid = {
838 .override = 0x4e8,
839 .security = 0x4ec,
840 },
841 },
842 }, {
843 .id = TEGRA186_MEMORY_CLIENT_SCEDMAW,
844 .name = "scedmaw",
845 .sid = TEGRA186_SID_SCE,
846 .regs = {
847 .sid = {
848 .override = 0x4f0,
849 .security = 0x4f4,
850 },
851 },
852 }, {
853 .id = TEGRA186_MEMORY_CLIENT_APEDMAR,
854 .name = "apedmar",
855 .sid = TEGRA186_SID_APE,
856 .regs = {
857 .sid = {
858 .override = 0x4f8,
859 .security = 0x4fc,
860 },
861 },
862 }, {
863 .id = TEGRA186_MEMORY_CLIENT_APEDMAW,
864 .name = "apedmaw",
865 .sid = TEGRA186_SID_APE,
866 .regs = {
867 .sid = {
868 .override = 0x500,
869 .security = 0x504,
870 },
871 },
872 }, {
873 .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1,
874 .name = "nvdisplayr1",
875 .sid = TEGRA186_SID_NVDISPLAY,
876 .regs = {
877 .sid = {
878 .override = 0x508,
879 .security = 0x50c,
880 },
881 },
882 }, {
883 .id = TEGRA186_MEMORY_CLIENT_VICSRD1,
884 .name = "vicsrd1",
885 .sid = TEGRA186_SID_VIC,
886 .regs = {
887 .sid = {
888 .override = 0x510,
889 .security = 0x514,
890 },
891 },
892 }, {
893 .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1,
894 .name = "nvdecsrd1",
895 .sid = TEGRA186_SID_NVDEC,
896 .regs = {
897 .sid = {
898 .override = 0x518,
899 .security = 0x51c,
900 },
901 },
902 },
903 };
904
905 const struct tegra_mc_soc tegra186_mc_soc = {
906 .num_clients = ARRAY_SIZE(tegra186_mc_clients),
907 .clients = tegra186_mc_clients,
908 .num_address_bits = 40,
909 .num_channels = 4,
910 .client_id_mask = 0xff,
911 .intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
912 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
913 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
914 .ops = &tegra186_mc_ops,
915 .ch_intmask = 0x0000000f,
916 .global_intstatus_channel_shift = 0,
917 };
918 #endif
919