1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) ST-Ericsson SA 2010
4 *
5 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com> for ST-Ericsson
6 * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson
7 */
8
9 #include <linux/init.h>
10 #include <linux/platform_device.h>
11 #include <linux/slab.h>
12 #include <linux/gpio/driver.h>
13 #include <linux/of.h>
14 #include <linux/interrupt.h>
15 #include <linux/mfd/tc3589x.h>
16 #include <linux/bitops.h>
17
18 /*
19 * These registers are modified under the irq bus lock and cached to avoid
20 * unnecessary writes in bus_sync_unlock.
21 */
22 enum { REG_IBE, REG_IEV, REG_IS, REG_IE, REG_DIRECT };
23
24 #define CACHE_NR_REGS 5
25 #define CACHE_NR_BANKS 3
26
27 struct tc3589x_gpio {
28 struct gpio_chip chip;
29 struct tc3589x *tc3589x;
30 struct device *dev;
31 struct mutex irq_lock;
32 /* Caches of interrupt control registers for bus_lock */
33 u8 regs[CACHE_NR_REGS][CACHE_NR_BANKS];
34 u8 oldregs[CACHE_NR_REGS][CACHE_NR_BANKS];
35 };
36
tc3589x_gpio_get(struct gpio_chip * chip,unsigned int offset)37 static int tc3589x_gpio_get(struct gpio_chip *chip, unsigned int offset)
38 {
39 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
40 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
41 u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
42 u8 mask = BIT(offset % 8);
43 int ret;
44
45 ret = tc3589x_reg_read(tc3589x, reg);
46 if (ret < 0)
47 return ret;
48
49 return !!(ret & mask);
50 }
51
tc3589x_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)52 static int tc3589x_gpio_set(struct gpio_chip *chip, unsigned int offset, int val)
53 {
54 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
55 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
56 u8 reg = TC3589x_GPIODATA0 + (offset / 8) * 2;
57 unsigned int pos = offset % 8;
58 u8 data[] = {val ? BIT(pos) : 0, BIT(pos)};
59
60 return tc3589x_block_write(tc3589x, reg, ARRAY_SIZE(data), data);
61 }
62
tc3589x_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int val)63 static int tc3589x_gpio_direction_output(struct gpio_chip *chip,
64 unsigned int offset, int val)
65 {
66 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
67 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
68 u8 reg = TC3589x_GPIODIR0 + offset / 8;
69 unsigned int pos = offset % 8;
70 int ret;
71
72 ret = tc3589x_gpio_set(chip, offset, val);
73 if (ret)
74 return ret;
75
76 return tc3589x_set_bits(tc3589x, reg, BIT(pos), BIT(pos));
77 }
78
tc3589x_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)79 static int tc3589x_gpio_direction_input(struct gpio_chip *chip,
80 unsigned int offset)
81 {
82 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
83 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
84 u8 reg = TC3589x_GPIODIR0 + offset / 8;
85 unsigned int pos = offset % 8;
86
87 return tc3589x_set_bits(tc3589x, reg, BIT(pos), 0);
88 }
89
tc3589x_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)90 static int tc3589x_gpio_get_direction(struct gpio_chip *chip,
91 unsigned int offset)
92 {
93 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
94 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
95 u8 reg = TC3589x_GPIODIR0 + offset / 8;
96 unsigned int pos = offset % 8;
97 int ret;
98
99 ret = tc3589x_reg_read(tc3589x, reg);
100 if (ret < 0)
101 return ret;
102
103 if (ret & BIT(pos))
104 return GPIO_LINE_DIRECTION_OUT;
105
106 return GPIO_LINE_DIRECTION_IN;
107 }
108
tc3589x_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)109 static int tc3589x_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
110 unsigned long config)
111 {
112 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(chip);
113 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
114 /*
115 * These registers are alterated at each second address
116 * ODM bit 0 = drive to GND or Hi-Z (open drain)
117 * ODM bit 1 = drive to VDD or Hi-Z (open source)
118 */
119 u8 odmreg = TC3589x_GPIOODM0 + (offset / 8) * 2;
120 u8 odereg = TC3589x_GPIOODE0 + (offset / 8) * 2;
121 unsigned int pos = offset % 8;
122 int ret;
123
124 switch (pinconf_to_config_param(config)) {
125 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
126 /* Set open drain mode */
127 ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), 0);
128 if (ret)
129 return ret;
130 /* Enable open drain/source mode */
131 return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
132 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
133 /* Set open source mode */
134 ret = tc3589x_set_bits(tc3589x, odmreg, BIT(pos), BIT(pos));
135 if (ret)
136 return ret;
137 /* Enable open drain/source mode */
138 return tc3589x_set_bits(tc3589x, odereg, BIT(pos), BIT(pos));
139 case PIN_CONFIG_DRIVE_PUSH_PULL:
140 /* Disable open drain/source mode */
141 return tc3589x_set_bits(tc3589x, odereg, BIT(pos), 0);
142 default:
143 break;
144 }
145 return -ENOTSUPP;
146 }
147
148 static const struct gpio_chip template_chip = {
149 .label = "tc3589x",
150 .owner = THIS_MODULE,
151 .get = tc3589x_gpio_get,
152 .set = tc3589x_gpio_set,
153 .direction_output = tc3589x_gpio_direction_output,
154 .direction_input = tc3589x_gpio_direction_input,
155 .get_direction = tc3589x_gpio_get_direction,
156 .set_config = tc3589x_gpio_set_config,
157 .can_sleep = true,
158 };
159
tc3589x_gpio_irq_set_type(struct irq_data * d,unsigned int type)160 static int tc3589x_gpio_irq_set_type(struct irq_data *d, unsigned int type)
161 {
162 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
163 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
164 int offset = d->hwirq;
165 int regoffset = offset / 8;
166 int mask = BIT(offset % 8);
167
168 if (type == IRQ_TYPE_EDGE_BOTH) {
169 tc3589x_gpio->regs[REG_IBE][regoffset] |= mask;
170 return 0;
171 }
172
173 tc3589x_gpio->regs[REG_IBE][regoffset] &= ~mask;
174
175 if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
176 tc3589x_gpio->regs[REG_IS][regoffset] |= mask;
177 else
178 tc3589x_gpio->regs[REG_IS][regoffset] &= ~mask;
179
180 if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
181 tc3589x_gpio->regs[REG_IEV][regoffset] |= mask;
182 else
183 tc3589x_gpio->regs[REG_IEV][regoffset] &= ~mask;
184
185 return 0;
186 }
187
tc3589x_gpio_irq_lock(struct irq_data * d)188 static void tc3589x_gpio_irq_lock(struct irq_data *d)
189 {
190 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
191 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
192
193 mutex_lock(&tc3589x_gpio->irq_lock);
194 }
195
tc3589x_gpio_irq_sync_unlock(struct irq_data * d)196 static void tc3589x_gpio_irq_sync_unlock(struct irq_data *d)
197 {
198 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
199 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
200 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
201 static const u8 regmap[] = {
202 [REG_IBE] = TC3589x_GPIOIBE0,
203 [REG_IEV] = TC3589x_GPIOIEV0,
204 [REG_IS] = TC3589x_GPIOIS0,
205 [REG_IE] = TC3589x_GPIOIE0,
206 [REG_DIRECT] = TC3589x_DIRECT0,
207 };
208 int i, j;
209
210 for (i = 0; i < CACHE_NR_REGS; i++) {
211 for (j = 0; j < CACHE_NR_BANKS; j++) {
212 u8 old = tc3589x_gpio->oldregs[i][j];
213 u8 new = tc3589x_gpio->regs[i][j];
214
215 if (new == old)
216 continue;
217
218 tc3589x_gpio->oldregs[i][j] = new;
219 tc3589x_reg_write(tc3589x, regmap[i] + j, new);
220 }
221 }
222
223 mutex_unlock(&tc3589x_gpio->irq_lock);
224 }
225
tc3589x_gpio_irq_mask(struct irq_data * d)226 static void tc3589x_gpio_irq_mask(struct irq_data *d)
227 {
228 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
229 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
230 int offset = d->hwirq;
231 int regoffset = offset / 8;
232 int mask = BIT(offset % 8);
233
234 tc3589x_gpio->regs[REG_IE][regoffset] &= ~mask;
235 tc3589x_gpio->regs[REG_DIRECT][regoffset] |= mask;
236 gpiochip_disable_irq(gc, offset);
237 }
238
tc3589x_gpio_irq_unmask(struct irq_data * d)239 static void tc3589x_gpio_irq_unmask(struct irq_data *d)
240 {
241 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
242 struct tc3589x_gpio *tc3589x_gpio = gpiochip_get_data(gc);
243 int offset = d->hwirq;
244 int regoffset = offset / 8;
245 int mask = BIT(offset % 8);
246
247 gpiochip_enable_irq(gc, offset);
248 tc3589x_gpio->regs[REG_IE][regoffset] |= mask;
249 tc3589x_gpio->regs[REG_DIRECT][regoffset] &= ~mask;
250 }
251
252 static const struct irq_chip tc3589x_gpio_irq_chip = {
253 .name = "tc3589x-gpio",
254 .irq_bus_lock = tc3589x_gpio_irq_lock,
255 .irq_bus_sync_unlock = tc3589x_gpio_irq_sync_unlock,
256 .irq_mask = tc3589x_gpio_irq_mask,
257 .irq_unmask = tc3589x_gpio_irq_unmask,
258 .irq_set_type = tc3589x_gpio_irq_set_type,
259 .flags = IRQCHIP_IMMUTABLE,
260 GPIOCHIP_IRQ_RESOURCE_HELPERS,
261 };
262
tc3589x_gpio_irq(int irq,void * dev)263 static irqreturn_t tc3589x_gpio_irq(int irq, void *dev)
264 {
265 struct tc3589x_gpio *tc3589x_gpio = dev;
266 struct tc3589x *tc3589x = tc3589x_gpio->tc3589x;
267 u8 status[CACHE_NR_BANKS];
268 int ret;
269 int i;
270
271 ret = tc3589x_block_read(tc3589x, TC3589x_GPIOMIS0,
272 ARRAY_SIZE(status), status);
273 if (ret < 0)
274 return IRQ_NONE;
275
276 for (i = 0; i < ARRAY_SIZE(status); i++) {
277 unsigned int stat = status[i];
278 if (!stat)
279 continue;
280
281 while (stat) {
282 int bit = __ffs(stat);
283 int line = i * 8 + bit;
284 int irq = irq_find_mapping(tc3589x_gpio->chip.irq.domain,
285 line);
286
287 handle_nested_irq(irq);
288 stat &= ~(1 << bit);
289 }
290
291 tc3589x_reg_write(tc3589x, TC3589x_GPIOIC0 + i, status[i]);
292 }
293
294 return IRQ_HANDLED;
295 }
296
tc3589x_gpio_probe(struct platform_device * pdev)297 static int tc3589x_gpio_probe(struct platform_device *pdev)
298 {
299 struct tc3589x *tc3589x = dev_get_drvdata(pdev->dev.parent);
300 struct device_node *np = pdev->dev.of_node;
301 struct tc3589x_gpio *tc3589x_gpio;
302 struct gpio_irq_chip *girq;
303 int ret;
304 int irq;
305
306 if (!np) {
307 dev_err(&pdev->dev, "No Device Tree node found\n");
308 return -EINVAL;
309 }
310
311 irq = platform_get_irq(pdev, 0);
312 if (irq < 0)
313 return irq;
314
315 tc3589x_gpio = devm_kzalloc(&pdev->dev, sizeof(struct tc3589x_gpio),
316 GFP_KERNEL);
317 if (!tc3589x_gpio)
318 return -ENOMEM;
319
320 mutex_init(&tc3589x_gpio->irq_lock);
321
322 tc3589x_gpio->dev = &pdev->dev;
323 tc3589x_gpio->tc3589x = tc3589x;
324
325 tc3589x_gpio->chip = template_chip;
326 tc3589x_gpio->chip.ngpio = tc3589x->num_gpio;
327 tc3589x_gpio->chip.parent = &pdev->dev;
328 tc3589x_gpio->chip.base = -1;
329
330 girq = &tc3589x_gpio->chip.irq;
331 gpio_irq_chip_set_chip(girq, &tc3589x_gpio_irq_chip);
332 /* This will let us handle the parent IRQ in the driver */
333 girq->parent_handler = NULL;
334 girq->num_parents = 0;
335 girq->parents = NULL;
336 girq->default_type = IRQ_TYPE_NONE;
337 girq->handler = handle_simple_irq;
338 girq->threaded = true;
339
340 /* Bring the GPIO module out of reset */
341 ret = tc3589x_set_bits(tc3589x, TC3589x_RSTCTRL,
342 TC3589x_RSTCTRL_GPIRST, 0);
343 if (ret < 0)
344 return ret;
345
346 /* For tc35894, have to disable Direct KBD interrupts,
347 * else IRQST will always be 0x20, IRQN low level, can't
348 * clear the irq status.
349 * TODO: need more test on other tc3589x chip.
350 *
351 */
352 ret = tc3589x_reg_write(tc3589x, TC3589x_DKBDMSK,
353 TC3589x_DKBDMSK_ELINT | TC3589x_DKBDMSK_EINT);
354 if (ret < 0)
355 return ret;
356
357 ret = devm_request_threaded_irq(&pdev->dev,
358 irq, NULL, tc3589x_gpio_irq,
359 IRQF_ONESHOT, "tc3589x-gpio",
360 tc3589x_gpio);
361 if (ret) {
362 dev_err(&pdev->dev, "unable to get irq: %d\n", ret);
363 return ret;
364 }
365
366 return devm_gpiochip_add_data(&pdev->dev, &tc3589x_gpio->chip, tc3589x_gpio);
367 }
368
369 static struct platform_driver tc3589x_gpio_driver = {
370 .driver.name = "tc3589x-gpio",
371 .probe = tc3589x_gpio_probe,
372 };
373
tc3589x_gpio_init(void)374 static int __init tc3589x_gpio_init(void)
375 {
376 return platform_driver_register(&tc3589x_gpio_driver);
377 }
378 subsys_initcall(tc3589x_gpio_init);
379