1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/delay.h>
36 #include <linux/string_choices.h>
37 #include "cxgb4.h"
38 #include "t4_regs.h"
39 #include "t4_values.h"
40 #include "t4fw_api.h"
41 #include "t4fw_version.h"
42
43 /**
44 * t4_wait_op_done_val - wait until an operation is completed
45 * @adapter: the adapter performing the operation
46 * @reg: the register to check for completion
47 * @mask: a single-bit field within @reg that indicates completion
48 * @polarity: the value of the field when the operation is completed
49 * @attempts: number of check iterations
50 * @delay: delay in usecs between iterations
51 * @valp: where to store the value of the register at completion time
52 *
53 * Wait until an operation is completed by checking a bit in a register
54 * up to @attempts times. If @valp is not NULL the value of the register
55 * at the time it indicated completion is stored there. Returns 0 if the
56 * operation completes and -EAGAIN otherwise.
57 */
t4_wait_op_done_val(struct adapter * adapter,int reg,u32 mask,int polarity,int attempts,int delay,u32 * valp)58 static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
59 int polarity, int attempts, int delay, u32 *valp)
60 {
61 while (1) {
62 u32 val = t4_read_reg(adapter, reg);
63
64 if (!!(val & mask) == polarity) {
65 if (valp)
66 *valp = val;
67 return 0;
68 }
69 if (--attempts == 0)
70 return -EAGAIN;
71 if (delay)
72 udelay(delay);
73 }
74 }
75
t4_wait_op_done(struct adapter * adapter,int reg,u32 mask,int polarity,int attempts,int delay)76 static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
77 int polarity, int attempts, int delay)
78 {
79 return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
80 delay, NULL);
81 }
82
83 /**
84 * t4_set_reg_field - set a register field to a value
85 * @adapter: the adapter to program
86 * @addr: the register address
87 * @mask: specifies the portion of the register to modify
88 * @val: the new value for the register field
89 *
90 * Sets a register field specified by the supplied mask to the
91 * given value.
92 */
t4_set_reg_field(struct adapter * adapter,unsigned int addr,u32 mask,u32 val)93 void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
94 u32 val)
95 {
96 u32 v = t4_read_reg(adapter, addr) & ~mask;
97
98 t4_write_reg(adapter, addr, v | val);
99 (void) t4_read_reg(adapter, addr); /* flush */
100 }
101
102 /**
103 * t4_read_indirect - read indirectly addressed registers
104 * @adap: the adapter
105 * @addr_reg: register holding the indirect address
106 * @data_reg: register holding the value of the indirect register
107 * @vals: where the read register values are stored
108 * @nregs: how many indirect registers to read
109 * @start_idx: index of first indirect register to read
110 *
111 * Reads registers that are accessed indirectly through an address/data
112 * register pair.
113 */
t4_read_indirect(struct adapter * adap,unsigned int addr_reg,unsigned int data_reg,u32 * vals,unsigned int nregs,unsigned int start_idx)114 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
115 unsigned int data_reg, u32 *vals,
116 unsigned int nregs, unsigned int start_idx)
117 {
118 while (nregs--) {
119 t4_write_reg(adap, addr_reg, start_idx);
120 *vals++ = t4_read_reg(adap, data_reg);
121 start_idx++;
122 }
123 }
124
125 /**
126 * t4_write_indirect - write indirectly addressed registers
127 * @adap: the adapter
128 * @addr_reg: register holding the indirect addresses
129 * @data_reg: register holding the value for the indirect registers
130 * @vals: values to write
131 * @nregs: how many indirect registers to write
132 * @start_idx: address of first indirect register to write
133 *
134 * Writes a sequential block of registers that are accessed indirectly
135 * through an address/data register pair.
136 */
t4_write_indirect(struct adapter * adap,unsigned int addr_reg,unsigned int data_reg,const u32 * vals,unsigned int nregs,unsigned int start_idx)137 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
138 unsigned int data_reg, const u32 *vals,
139 unsigned int nregs, unsigned int start_idx)
140 {
141 while (nregs--) {
142 t4_write_reg(adap, addr_reg, start_idx++);
143 t4_write_reg(adap, data_reg, *vals++);
144 }
145 }
146
147 /*
148 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
149 * mechanism. This guarantees that we get the real value even if we're
150 * operating within a Virtual Machine and the Hypervisor is trapping our
151 * Configuration Space accesses.
152 */
t4_hw_pci_read_cfg4(struct adapter * adap,int reg,u32 * val)153 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
154 {
155 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
156
157 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
158 req |= ENABLE_F;
159 else
160 req |= T6_ENABLE_F;
161
162 if (is_t4(adap->params.chip))
163 req |= LOCALCFG_F;
164
165 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
166 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
167
168 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
169 * Configuration Space read. (None of the other fields matter when
170 * ENABLE is 0 so a simple register write is easier than a
171 * read-modify-write via t4_set_reg_field().)
172 */
173 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
174 }
175
176 /*
177 * t4_report_fw_error - report firmware error
178 * @adap: the adapter
179 *
180 * The adapter firmware can indicate error conditions to the host.
181 * If the firmware has indicated an error, print out the reason for
182 * the firmware error.
183 */
t4_report_fw_error(struct adapter * adap)184 static void t4_report_fw_error(struct adapter *adap)
185 {
186 static const char *const reason[] = {
187 "Crash", /* PCIE_FW_EVAL_CRASH */
188 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
189 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
190 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
191 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
192 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
193 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
194 "Reserved", /* reserved */
195 };
196 u32 pcie_fw;
197
198 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
199 if (pcie_fw & PCIE_FW_ERR_F) {
200 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
201 reason[PCIE_FW_EVAL_G(pcie_fw)]);
202 adap->flags &= ~CXGB4_FW_OK;
203 }
204 }
205
206 /*
207 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
208 */
get_mbox_rpl(struct adapter * adap,__be64 * rpl,int nflit,u32 mbox_addr)209 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
210 u32 mbox_addr)
211 {
212 for ( ; nflit; nflit--, mbox_addr += 8)
213 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
214 }
215
216 /*
217 * Handle a FW assertion reported in a mailbox.
218 */
fw_asrt(struct adapter * adap,u32 mbox_addr)219 static void fw_asrt(struct adapter *adap, u32 mbox_addr)
220 {
221 struct fw_debug_cmd asrt;
222
223 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
224 dev_alert(adap->pdev_dev,
225 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
226 asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
227 be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
228 }
229
230 /**
231 * t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
232 * @adapter: the adapter
233 * @cmd: the Firmware Mailbox Command or Reply
234 * @size: command length in bytes
235 * @access: the time (ms) needed to access the Firmware Mailbox
236 * @execute: the time (ms) the command spent being executed
237 */
t4_record_mbox(struct adapter * adapter,const __be64 * cmd,unsigned int size,int access,int execute)238 static void t4_record_mbox(struct adapter *adapter,
239 const __be64 *cmd, unsigned int size,
240 int access, int execute)
241 {
242 struct mbox_cmd_log *log = adapter->mbox_log;
243 struct mbox_cmd *entry;
244 int i;
245
246 entry = mbox_cmd_log_entry(log, log->cursor++);
247 if (log->cursor == log->size)
248 log->cursor = 0;
249
250 for (i = 0; i < size / 8; i++)
251 entry->cmd[i] = be64_to_cpu(cmd[i]);
252 while (i < MBOX_LEN / 8)
253 entry->cmd[i++] = 0;
254 entry->timestamp = jiffies;
255 entry->seqno = log->seqno++;
256 entry->access = access;
257 entry->execute = execute;
258 }
259
260 /**
261 * t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
262 * @adap: the adapter
263 * @mbox: index of the mailbox to use
264 * @cmd: the command to write
265 * @size: command length in bytes
266 * @rpl: where to optionally store the reply
267 * @sleep_ok: if true we may sleep while awaiting command completion
268 * @timeout: time to wait for command to finish before timing out
269 *
270 * Sends the given command to FW through the selected mailbox and waits
271 * for the FW to execute the command. If @rpl is not %NULL it is used to
272 * store the FW's reply to the command. The command and its optional
273 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
274 * to respond. @sleep_ok determines whether we may sleep while awaiting
275 * the response. If sleeping is allowed we use progressive backoff
276 * otherwise we spin.
277 *
278 * The return value is 0 on success or a negative errno on failure. A
279 * failure can happen either because we are not able to execute the
280 * command or FW executes it but signals an error. In the latter case
281 * the return value is the error code indicated by FW (negated).
282 */
t4_wr_mbox_meat_timeout(struct adapter * adap,int mbox,const void * cmd,int size,void * rpl,bool sleep_ok,int timeout)283 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
284 int size, void *rpl, bool sleep_ok, int timeout)
285 {
286 static const int delay[] = {
287 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
288 };
289
290 struct mbox_list entry;
291 u16 access = 0;
292 u16 execute = 0;
293 u32 v;
294 u64 res;
295 int i, ms, delay_idx, ret;
296 const __be64 *p = cmd;
297 u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
298 u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
299 __be64 cmd_rpl[MBOX_LEN / 8];
300 u32 pcie_fw;
301
302 if ((size & 15) || size > MBOX_LEN)
303 return -EINVAL;
304
305 /*
306 * If the device is off-line, as in EEH, commands will time out.
307 * Fail them early so we don't waste time waiting.
308 */
309 if (adap->pdev->error_state != pci_channel_io_normal)
310 return -EIO;
311
312 /* If we have a negative timeout, that implies that we can't sleep. */
313 if (timeout < 0) {
314 sleep_ok = false;
315 timeout = -timeout;
316 }
317
318 /* Queue ourselves onto the mailbox access list. When our entry is at
319 * the front of the list, we have rights to access the mailbox. So we
320 * wait [for a while] till we're at the front [or bail out with an
321 * EBUSY] ...
322 */
323 spin_lock_bh(&adap->mbox_lock);
324 list_add_tail(&entry.list, &adap->mlist.list);
325 spin_unlock_bh(&adap->mbox_lock);
326
327 delay_idx = 0;
328 ms = delay[0];
329
330 for (i = 0; ; i += ms) {
331 /* If we've waited too long, return a busy indication. This
332 * really ought to be based on our initial position in the
333 * mailbox access list but this is a start. We very rarely
334 * contend on access to the mailbox ...
335 */
336 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
337 if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
338 spin_lock_bh(&adap->mbox_lock);
339 list_del(&entry.list);
340 spin_unlock_bh(&adap->mbox_lock);
341 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
342 t4_record_mbox(adap, cmd, size, access, ret);
343 return ret;
344 }
345
346 /* If we're at the head, break out and start the mailbox
347 * protocol.
348 */
349 if (list_first_entry(&adap->mlist.list, struct mbox_list,
350 list) == &entry)
351 break;
352
353 /* Delay for a bit before checking again ... */
354 if (sleep_ok) {
355 ms = delay[delay_idx]; /* last element may repeat */
356 if (delay_idx < ARRAY_SIZE(delay) - 1)
357 delay_idx++;
358 msleep(ms);
359 } else {
360 mdelay(ms);
361 }
362 }
363
364 /* Loop trying to get ownership of the mailbox. Return an error
365 * if we can't gain ownership.
366 */
367 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
368 for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
369 v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
370 if (v != MBOX_OWNER_DRV) {
371 spin_lock_bh(&adap->mbox_lock);
372 list_del(&entry.list);
373 spin_unlock_bh(&adap->mbox_lock);
374 ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
375 t4_record_mbox(adap, cmd, size, access, ret);
376 return ret;
377 }
378
379 /* Copy in the new mailbox command and send it on its way ... */
380 t4_record_mbox(adap, cmd, size, access, 0);
381 for (i = 0; i < size; i += 8)
382 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
383
384 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
385 t4_read_reg(adap, ctl_reg); /* flush write */
386
387 delay_idx = 0;
388 ms = delay[0];
389
390 for (i = 0;
391 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
392 i < timeout;
393 i += ms) {
394 if (sleep_ok) {
395 ms = delay[delay_idx]; /* last element may repeat */
396 if (delay_idx < ARRAY_SIZE(delay) - 1)
397 delay_idx++;
398 msleep(ms);
399 } else
400 mdelay(ms);
401
402 v = t4_read_reg(adap, ctl_reg);
403 if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
404 if (!(v & MBMSGVALID_F)) {
405 t4_write_reg(adap, ctl_reg, 0);
406 continue;
407 }
408
409 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
410 res = be64_to_cpu(cmd_rpl[0]);
411
412 if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
413 fw_asrt(adap, data_reg);
414 res = FW_CMD_RETVAL_V(EIO);
415 } else if (rpl) {
416 memcpy(rpl, cmd_rpl, size);
417 }
418
419 t4_write_reg(adap, ctl_reg, 0);
420
421 execute = i + ms;
422 t4_record_mbox(adap, cmd_rpl,
423 MBOX_LEN, access, execute);
424 spin_lock_bh(&adap->mbox_lock);
425 list_del(&entry.list);
426 spin_unlock_bh(&adap->mbox_lock);
427 return -FW_CMD_RETVAL_G((int)res);
428 }
429 }
430
431 ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
432 t4_record_mbox(adap, cmd, size, access, ret);
433 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
434 *(const u8 *)cmd, mbox);
435 t4_report_fw_error(adap);
436 spin_lock_bh(&adap->mbox_lock);
437 list_del(&entry.list);
438 spin_unlock_bh(&adap->mbox_lock);
439 t4_fatal_err(adap);
440 return ret;
441 }
442
t4_wr_mbox_meat(struct adapter * adap,int mbox,const void * cmd,int size,void * rpl,bool sleep_ok)443 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
444 void *rpl, bool sleep_ok)
445 {
446 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
447 FW_CMD_MAX_TIMEOUT);
448 }
449
t4_edc_err_read(struct adapter * adap,int idx)450 static int t4_edc_err_read(struct adapter *adap, int idx)
451 {
452 u32 edc_ecc_err_addr_reg;
453 u32 rdata_reg;
454
455 if (is_t4(adap->params.chip)) {
456 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
457 return 0;
458 }
459 if (idx != 0 && idx != 1) {
460 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
461 return 0;
462 }
463
464 edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
465 rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
466
467 CH_WARN(adap,
468 "edc%d err addr 0x%x: 0x%x.\n",
469 idx, edc_ecc_err_addr_reg,
470 t4_read_reg(adap, edc_ecc_err_addr_reg));
471 CH_WARN(adap,
472 "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
473 rdata_reg,
474 (unsigned long long)t4_read_reg64(adap, rdata_reg),
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
480 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
481 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
482 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
483
484 return 0;
485 }
486
487 /**
488 * t4_memory_rw_init - Get memory window relative offset, base, and size.
489 * @adap: the adapter
490 * @win: PCI-E Memory Window to use
491 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
492 * @mem_off: memory relative offset with respect to @mtype.
493 * @mem_base: configured memory base address.
494 * @mem_aperture: configured memory window aperture.
495 *
496 * Get the configured memory window's relative offset, base, and size.
497 */
t4_memory_rw_init(struct adapter * adap,int win,int mtype,u32 * mem_off,u32 * mem_base,u32 * mem_aperture)498 int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
499 u32 *mem_base, u32 *mem_aperture)
500 {
501 u32 edc_size, mc_size, mem_reg;
502
503 /* Offset into the region of memory which is being accessed
504 * MEM_EDC0 = 0
505 * MEM_EDC1 = 1
506 * MEM_MC = 2 -- MEM_MC for chips with only 1 memory controller
507 * MEM_MC1 = 3 -- for chips with 2 memory controllers (e.g. T5)
508 * MEM_HMA = 4
509 */
510 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
511 if (mtype == MEM_HMA) {
512 *mem_off = 2 * (edc_size * 1024 * 1024);
513 } else if (mtype != MEM_MC1) {
514 *mem_off = (mtype * (edc_size * 1024 * 1024));
515 } else {
516 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
517 MA_EXT_MEMORY0_BAR_A));
518 *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
519 }
520
521 /* Each PCI-E Memory Window is programmed with a window size -- or
522 * "aperture" -- which controls the granularity of its mapping onto
523 * adapter memory. We need to grab that aperture in order to know
524 * how to use the specified window. The window is also programmed
525 * with the base address of the Memory Window in BAR0's address
526 * space. For T4 this is an absolute PCI-E Bus Address. For T5
527 * the address is relative to BAR0.
528 */
529 mem_reg = t4_read_reg(adap,
530 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
531 win));
532 /* a dead adapter will return 0xffffffff for PIO reads */
533 if (mem_reg == 0xffffffff)
534 return -ENXIO;
535
536 *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
537 *mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
538 if (is_t4(adap->params.chip))
539 *mem_base -= adap->t4_bar0;
540
541 return 0;
542 }
543
544 /**
545 * t4_memory_update_win - Move memory window to specified address.
546 * @adap: the adapter
547 * @win: PCI-E Memory Window to use
548 * @addr: location to move.
549 *
550 * Move memory window to specified address.
551 */
t4_memory_update_win(struct adapter * adap,int win,u32 addr)552 void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
553 {
554 t4_write_reg(adap,
555 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
556 addr);
557 /* Read it back to ensure that changes propagate before we
558 * attempt to use the new value.
559 */
560 t4_read_reg(adap,
561 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
562 }
563
564 /**
565 * t4_memory_rw_residual - Read/Write residual data.
566 * @adap: the adapter
567 * @off: relative offset within residual to start read/write.
568 * @addr: address within indicated memory type.
569 * @buf: host memory buffer
570 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
571 *
572 * Read/Write residual data less than 32-bits.
573 */
t4_memory_rw_residual(struct adapter * adap,u32 off,u32 addr,u8 * buf,int dir)574 void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
575 int dir)
576 {
577 union {
578 u32 word;
579 char byte[4];
580 } last;
581 unsigned char *bp;
582 int i;
583
584 if (dir == T4_MEMORY_READ) {
585 last.word = le32_to_cpu((__force __le32)
586 t4_read_reg(adap, addr));
587 for (bp = (unsigned char *)buf, i = off; i < 4; i++)
588 bp[i] = last.byte[i];
589 } else {
590 last.word = *buf;
591 for (i = off; i < 4; i++)
592 last.byte[i] = 0;
593 t4_write_reg(adap, addr,
594 (__force u32)cpu_to_le32(last.word));
595 }
596 }
597
598 /**
599 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
600 * @adap: the adapter
601 * @win: PCI-E Memory Window to use
602 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
603 * @addr: address within indicated memory type
604 * @len: amount of memory to transfer
605 * @hbuf: host memory buffer
606 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
607 *
608 * Reads/writes an [almost] arbitrary memory region in the firmware: the
609 * firmware memory address and host buffer must be aligned on 32-bit
610 * boundaries; the length may be arbitrary. The memory is transferred as
611 * a raw byte sequence from/to the firmware's memory. If this memory
612 * contains data structures which contain multi-byte integers, it's the
613 * caller's responsibility to perform appropriate byte order conversions.
614 */
t4_memory_rw(struct adapter * adap,int win,int mtype,u32 addr,u32 len,void * hbuf,int dir)615 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
616 u32 len, void *hbuf, int dir)
617 {
618 u32 pos, offset, resid, memoffset;
619 u32 win_pf, mem_aperture, mem_base;
620 u32 *buf;
621 int ret;
622
623 /* Argument sanity checks ...
624 */
625 if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
626 return -EINVAL;
627 buf = (u32 *)hbuf;
628
629 /* It's convenient to be able to handle lengths which aren't a
630 * multiple of 32-bits because we often end up transferring files to
631 * the firmware. So we'll handle that by normalizing the length here
632 * and then handling any residual transfer at the end.
633 */
634 resid = len & 0x3;
635 len -= resid;
636
637 ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
638 &mem_aperture);
639 if (ret)
640 return ret;
641
642 /* Determine the PCIE_MEM_ACCESS_OFFSET */
643 addr = addr + memoffset;
644
645 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
646
647 /* Calculate our initial PCI-E Memory Window Position and Offset into
648 * that Window.
649 */
650 pos = addr & ~(mem_aperture - 1);
651 offset = addr - pos;
652
653 /* Set up initial PCI-E Memory Window to cover the start of our
654 * transfer.
655 */
656 t4_memory_update_win(adap, win, pos | win_pf);
657
658 /* Transfer data to/from the adapter as long as there's an integral
659 * number of 32-bit transfers to complete.
660 *
661 * A note on Endianness issues:
662 *
663 * The "register" reads and writes below from/to the PCI-E Memory
664 * Window invoke the standard adapter Big-Endian to PCI-E Link
665 * Little-Endian "swizzel." As a result, if we have the following
666 * data in adapter memory:
667 *
668 * Memory: ... | b0 | b1 | b2 | b3 | ...
669 * Address: i+0 i+1 i+2 i+3
670 *
671 * Then a read of the adapter memory via the PCI-E Memory Window
672 * will yield:
673 *
674 * x = readl(i)
675 * 31 0
676 * [ b3 | b2 | b1 | b0 ]
677 *
678 * If this value is stored into local memory on a Little-Endian system
679 * it will show up correctly in local memory as:
680 *
681 * ( ..., b0, b1, b2, b3, ... )
682 *
683 * But on a Big-Endian system, the store will show up in memory
684 * incorrectly swizzled as:
685 *
686 * ( ..., b3, b2, b1, b0, ... )
687 *
688 * So we need to account for this in the reads and writes to the
689 * PCI-E Memory Window below by undoing the register read/write
690 * swizzels.
691 */
692 while (len > 0) {
693 if (dir == T4_MEMORY_READ)
694 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
695 mem_base + offset));
696 else
697 t4_write_reg(adap, mem_base + offset,
698 (__force u32)cpu_to_le32(*buf++));
699 offset += sizeof(__be32);
700 len -= sizeof(__be32);
701
702 /* If we've reached the end of our current window aperture,
703 * move the PCI-E Memory Window on to the next. Note that
704 * doing this here after "len" may be 0 allows us to set up
705 * the PCI-E Memory Window for a possible final residual
706 * transfer below ...
707 */
708 if (offset == mem_aperture) {
709 pos += mem_aperture;
710 offset = 0;
711 t4_memory_update_win(adap, win, pos | win_pf);
712 }
713 }
714
715 /* If the original transfer had a length which wasn't a multiple of
716 * 32-bits, now's where we need to finish off the transfer of the
717 * residual amount. The PCI-E Memory Window has already been moved
718 * above (if necessary) to cover this final transfer.
719 */
720 if (resid)
721 t4_memory_rw_residual(adap, resid, mem_base + offset,
722 (u8 *)buf, dir);
723
724 return 0;
725 }
726
727 /* Return the specified PCI-E Configuration Space register from our Physical
728 * Function. We try first via a Firmware LDST Command since we prefer to let
729 * the firmware own all of these registers, but if that fails we go for it
730 * directly ourselves.
731 */
t4_read_pcie_cfg4(struct adapter * adap,int reg)732 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
733 {
734 u32 val, ldst_addrspace;
735
736 /* If fw_attach != 0, construct and send the Firmware LDST Command to
737 * retrieve the specified PCI-E Configuration Space register.
738 */
739 struct fw_ldst_cmd ldst_cmd;
740 int ret;
741
742 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
743 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
744 ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
745 FW_CMD_REQUEST_F |
746 FW_CMD_READ_F |
747 ldst_addrspace);
748 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
749 ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
750 ldst_cmd.u.pcie.ctrl_to_fn =
751 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
752 ldst_cmd.u.pcie.r = reg;
753
754 /* If the LDST Command succeeds, return the result, otherwise
755 * fall through to reading it directly ourselves ...
756 */
757 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
758 &ldst_cmd);
759 if (ret == 0)
760 val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
761 else
762 /* Read the desired Configuration Space register via the PCI-E
763 * Backdoor mechanism.
764 */
765 t4_hw_pci_read_cfg4(adap, reg, &val);
766 return val;
767 }
768
769 /* Get the window based on base passed to it.
770 * Window aperture is currently unhandled, but there is no use case for it
771 * right now
772 */
t4_get_window(struct adapter * adap,u32 pci_base,u64 pci_mask,u32 memwin_base)773 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
774 u32 memwin_base)
775 {
776 u32 ret;
777
778 if (is_t4(adap->params.chip)) {
779 u32 bar0;
780
781 /* Truncation intentional: we only read the bottom 32-bits of
782 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
783 * mechanism to read BAR0 instead of using
784 * pci_resource_start() because we could be operating from
785 * within a Virtual Machine which is trapping our accesses to
786 * our Configuration Space and we need to set up the PCI-E
787 * Memory Window decoders with the actual addresses which will
788 * be coming across the PCI-E link.
789 */
790 bar0 = t4_read_pcie_cfg4(adap, pci_base);
791 bar0 &= pci_mask;
792 adap->t4_bar0 = bar0;
793
794 ret = bar0 + memwin_base;
795 } else {
796 /* For T5, only relative offset inside the PCIe BAR is passed */
797 ret = memwin_base;
798 }
799 return ret;
800 }
801
802 /* Get the default utility window (win0) used by everyone */
t4_get_util_window(struct adapter * adap)803 u32 t4_get_util_window(struct adapter *adap)
804 {
805 return t4_get_window(adap, PCI_BASE_ADDRESS_0,
806 PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
807 }
808
809 /* Set up memory window for accessing adapter memory ranges. (Read
810 * back MA register to ensure that changes propagate before we attempt
811 * to use the new values.)
812 */
t4_setup_memwin(struct adapter * adap,u32 memwin_base,u32 window)813 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
814 {
815 t4_write_reg(adap,
816 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
817 memwin_base | BIR_V(0) |
818 WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
819 t4_read_reg(adap,
820 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
821 }
822
823 /**
824 * t4_get_regs_len - return the size of the chips register set
825 * @adapter: the adapter
826 *
827 * Returns the size of the chip's BAR0 register space.
828 */
t4_get_regs_len(struct adapter * adapter)829 unsigned int t4_get_regs_len(struct adapter *adapter)
830 {
831 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
832
833 switch (chip_version) {
834 case CHELSIO_T4:
835 return T4_REGMAP_SIZE;
836
837 case CHELSIO_T5:
838 case CHELSIO_T6:
839 return T5_REGMAP_SIZE;
840 }
841
842 dev_err(adapter->pdev_dev,
843 "Unsupported chip version %d\n", chip_version);
844 return 0;
845 }
846
847 /**
848 * t4_get_regs - read chip registers into provided buffer
849 * @adap: the adapter
850 * @buf: register buffer
851 * @buf_size: size (in bytes) of register buffer
852 *
853 * If the provided register buffer isn't large enough for the chip's
854 * full register range, the register dump will be truncated to the
855 * register buffer's size.
856 */
t4_get_regs(struct adapter * adap,void * buf,size_t buf_size)857 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
858 {
859 static const unsigned int t4_reg_ranges[] = {
860 0x1008, 0x1108,
861 0x1180, 0x1184,
862 0x1190, 0x1194,
863 0x11a0, 0x11a4,
864 0x11b0, 0x11b4,
865 0x11fc, 0x123c,
866 0x1300, 0x173c,
867 0x1800, 0x18fc,
868 0x3000, 0x30d8,
869 0x30e0, 0x30e4,
870 0x30ec, 0x5910,
871 0x5920, 0x5924,
872 0x5960, 0x5960,
873 0x5968, 0x5968,
874 0x5970, 0x5970,
875 0x5978, 0x5978,
876 0x5980, 0x5980,
877 0x5988, 0x5988,
878 0x5990, 0x5990,
879 0x5998, 0x5998,
880 0x59a0, 0x59d4,
881 0x5a00, 0x5ae0,
882 0x5ae8, 0x5ae8,
883 0x5af0, 0x5af0,
884 0x5af8, 0x5af8,
885 0x6000, 0x6098,
886 0x6100, 0x6150,
887 0x6200, 0x6208,
888 0x6240, 0x6248,
889 0x6280, 0x62b0,
890 0x62c0, 0x6338,
891 0x6370, 0x638c,
892 0x6400, 0x643c,
893 0x6500, 0x6524,
894 0x6a00, 0x6a04,
895 0x6a14, 0x6a38,
896 0x6a60, 0x6a70,
897 0x6a78, 0x6a78,
898 0x6b00, 0x6b0c,
899 0x6b1c, 0x6b84,
900 0x6bf0, 0x6bf8,
901 0x6c00, 0x6c0c,
902 0x6c1c, 0x6c84,
903 0x6cf0, 0x6cf8,
904 0x6d00, 0x6d0c,
905 0x6d1c, 0x6d84,
906 0x6df0, 0x6df8,
907 0x6e00, 0x6e0c,
908 0x6e1c, 0x6e84,
909 0x6ef0, 0x6ef8,
910 0x6f00, 0x6f0c,
911 0x6f1c, 0x6f84,
912 0x6ff0, 0x6ff8,
913 0x7000, 0x700c,
914 0x701c, 0x7084,
915 0x70f0, 0x70f8,
916 0x7100, 0x710c,
917 0x711c, 0x7184,
918 0x71f0, 0x71f8,
919 0x7200, 0x720c,
920 0x721c, 0x7284,
921 0x72f0, 0x72f8,
922 0x7300, 0x730c,
923 0x731c, 0x7384,
924 0x73f0, 0x73f8,
925 0x7400, 0x7450,
926 0x7500, 0x7530,
927 0x7600, 0x760c,
928 0x7614, 0x761c,
929 0x7680, 0x76cc,
930 0x7700, 0x7798,
931 0x77c0, 0x77fc,
932 0x7900, 0x79fc,
933 0x7b00, 0x7b58,
934 0x7b60, 0x7b84,
935 0x7b8c, 0x7c38,
936 0x7d00, 0x7d38,
937 0x7d40, 0x7d80,
938 0x7d8c, 0x7ddc,
939 0x7de4, 0x7e04,
940 0x7e10, 0x7e1c,
941 0x7e24, 0x7e38,
942 0x7e40, 0x7e44,
943 0x7e4c, 0x7e78,
944 0x7e80, 0x7ea4,
945 0x7eac, 0x7edc,
946 0x7ee8, 0x7efc,
947 0x8dc0, 0x8e04,
948 0x8e10, 0x8e1c,
949 0x8e30, 0x8e78,
950 0x8ea0, 0x8eb8,
951 0x8ec0, 0x8f6c,
952 0x8fc0, 0x9008,
953 0x9010, 0x9058,
954 0x9060, 0x9060,
955 0x9068, 0x9074,
956 0x90fc, 0x90fc,
957 0x9400, 0x9408,
958 0x9410, 0x9458,
959 0x9600, 0x9600,
960 0x9608, 0x9638,
961 0x9640, 0x96bc,
962 0x9800, 0x9808,
963 0x9820, 0x983c,
964 0x9850, 0x9864,
965 0x9c00, 0x9c6c,
966 0x9c80, 0x9cec,
967 0x9d00, 0x9d6c,
968 0x9d80, 0x9dec,
969 0x9e00, 0x9e6c,
970 0x9e80, 0x9eec,
971 0x9f00, 0x9f6c,
972 0x9f80, 0x9fec,
973 0xd004, 0xd004,
974 0xd010, 0xd03c,
975 0xdfc0, 0xdfe0,
976 0xe000, 0xea7c,
977 0xf000, 0x11110,
978 0x11118, 0x11190,
979 0x19040, 0x1906c,
980 0x19078, 0x19080,
981 0x1908c, 0x190e4,
982 0x190f0, 0x190f8,
983 0x19100, 0x19110,
984 0x19120, 0x19124,
985 0x19150, 0x19194,
986 0x1919c, 0x191b0,
987 0x191d0, 0x191e8,
988 0x19238, 0x1924c,
989 0x193f8, 0x1943c,
990 0x1944c, 0x19474,
991 0x19490, 0x194e0,
992 0x194f0, 0x194f8,
993 0x19800, 0x19c08,
994 0x19c10, 0x19c90,
995 0x19ca0, 0x19ce4,
996 0x19cf0, 0x19d40,
997 0x19d50, 0x19d94,
998 0x19da0, 0x19de8,
999 0x19df0, 0x19e40,
1000 0x19e50, 0x19e90,
1001 0x19ea0, 0x19f4c,
1002 0x1a000, 0x1a004,
1003 0x1a010, 0x1a06c,
1004 0x1a0b0, 0x1a0e4,
1005 0x1a0ec, 0x1a0f4,
1006 0x1a100, 0x1a108,
1007 0x1a114, 0x1a120,
1008 0x1a128, 0x1a130,
1009 0x1a138, 0x1a138,
1010 0x1a190, 0x1a1c4,
1011 0x1a1fc, 0x1a1fc,
1012 0x1e040, 0x1e04c,
1013 0x1e284, 0x1e28c,
1014 0x1e2c0, 0x1e2c0,
1015 0x1e2e0, 0x1e2e0,
1016 0x1e300, 0x1e384,
1017 0x1e3c0, 0x1e3c8,
1018 0x1e440, 0x1e44c,
1019 0x1e684, 0x1e68c,
1020 0x1e6c0, 0x1e6c0,
1021 0x1e6e0, 0x1e6e0,
1022 0x1e700, 0x1e784,
1023 0x1e7c0, 0x1e7c8,
1024 0x1e840, 0x1e84c,
1025 0x1ea84, 0x1ea8c,
1026 0x1eac0, 0x1eac0,
1027 0x1eae0, 0x1eae0,
1028 0x1eb00, 0x1eb84,
1029 0x1ebc0, 0x1ebc8,
1030 0x1ec40, 0x1ec4c,
1031 0x1ee84, 0x1ee8c,
1032 0x1eec0, 0x1eec0,
1033 0x1eee0, 0x1eee0,
1034 0x1ef00, 0x1ef84,
1035 0x1efc0, 0x1efc8,
1036 0x1f040, 0x1f04c,
1037 0x1f284, 0x1f28c,
1038 0x1f2c0, 0x1f2c0,
1039 0x1f2e0, 0x1f2e0,
1040 0x1f300, 0x1f384,
1041 0x1f3c0, 0x1f3c8,
1042 0x1f440, 0x1f44c,
1043 0x1f684, 0x1f68c,
1044 0x1f6c0, 0x1f6c0,
1045 0x1f6e0, 0x1f6e0,
1046 0x1f700, 0x1f784,
1047 0x1f7c0, 0x1f7c8,
1048 0x1f840, 0x1f84c,
1049 0x1fa84, 0x1fa8c,
1050 0x1fac0, 0x1fac0,
1051 0x1fae0, 0x1fae0,
1052 0x1fb00, 0x1fb84,
1053 0x1fbc0, 0x1fbc8,
1054 0x1fc40, 0x1fc4c,
1055 0x1fe84, 0x1fe8c,
1056 0x1fec0, 0x1fec0,
1057 0x1fee0, 0x1fee0,
1058 0x1ff00, 0x1ff84,
1059 0x1ffc0, 0x1ffc8,
1060 0x20000, 0x2002c,
1061 0x20100, 0x2013c,
1062 0x20190, 0x201a0,
1063 0x201a8, 0x201b8,
1064 0x201c4, 0x201c8,
1065 0x20200, 0x20318,
1066 0x20400, 0x204b4,
1067 0x204c0, 0x20528,
1068 0x20540, 0x20614,
1069 0x21000, 0x21040,
1070 0x2104c, 0x21060,
1071 0x210c0, 0x210ec,
1072 0x21200, 0x21268,
1073 0x21270, 0x21284,
1074 0x212fc, 0x21388,
1075 0x21400, 0x21404,
1076 0x21500, 0x21500,
1077 0x21510, 0x21518,
1078 0x2152c, 0x21530,
1079 0x2153c, 0x2153c,
1080 0x21550, 0x21554,
1081 0x21600, 0x21600,
1082 0x21608, 0x2161c,
1083 0x21624, 0x21628,
1084 0x21630, 0x21634,
1085 0x2163c, 0x2163c,
1086 0x21700, 0x2171c,
1087 0x21780, 0x2178c,
1088 0x21800, 0x21818,
1089 0x21820, 0x21828,
1090 0x21830, 0x21848,
1091 0x21850, 0x21854,
1092 0x21860, 0x21868,
1093 0x21870, 0x21870,
1094 0x21878, 0x21898,
1095 0x218a0, 0x218a8,
1096 0x218b0, 0x218c8,
1097 0x218d0, 0x218d4,
1098 0x218e0, 0x218e8,
1099 0x218f0, 0x218f0,
1100 0x218f8, 0x21a18,
1101 0x21a20, 0x21a28,
1102 0x21a30, 0x21a48,
1103 0x21a50, 0x21a54,
1104 0x21a60, 0x21a68,
1105 0x21a70, 0x21a70,
1106 0x21a78, 0x21a98,
1107 0x21aa0, 0x21aa8,
1108 0x21ab0, 0x21ac8,
1109 0x21ad0, 0x21ad4,
1110 0x21ae0, 0x21ae8,
1111 0x21af0, 0x21af0,
1112 0x21af8, 0x21c18,
1113 0x21c20, 0x21c20,
1114 0x21c28, 0x21c30,
1115 0x21c38, 0x21c38,
1116 0x21c80, 0x21c98,
1117 0x21ca0, 0x21ca8,
1118 0x21cb0, 0x21cc8,
1119 0x21cd0, 0x21cd4,
1120 0x21ce0, 0x21ce8,
1121 0x21cf0, 0x21cf0,
1122 0x21cf8, 0x21d7c,
1123 0x21e00, 0x21e04,
1124 0x22000, 0x2202c,
1125 0x22100, 0x2213c,
1126 0x22190, 0x221a0,
1127 0x221a8, 0x221b8,
1128 0x221c4, 0x221c8,
1129 0x22200, 0x22318,
1130 0x22400, 0x224b4,
1131 0x224c0, 0x22528,
1132 0x22540, 0x22614,
1133 0x23000, 0x23040,
1134 0x2304c, 0x23060,
1135 0x230c0, 0x230ec,
1136 0x23200, 0x23268,
1137 0x23270, 0x23284,
1138 0x232fc, 0x23388,
1139 0x23400, 0x23404,
1140 0x23500, 0x23500,
1141 0x23510, 0x23518,
1142 0x2352c, 0x23530,
1143 0x2353c, 0x2353c,
1144 0x23550, 0x23554,
1145 0x23600, 0x23600,
1146 0x23608, 0x2361c,
1147 0x23624, 0x23628,
1148 0x23630, 0x23634,
1149 0x2363c, 0x2363c,
1150 0x23700, 0x2371c,
1151 0x23780, 0x2378c,
1152 0x23800, 0x23818,
1153 0x23820, 0x23828,
1154 0x23830, 0x23848,
1155 0x23850, 0x23854,
1156 0x23860, 0x23868,
1157 0x23870, 0x23870,
1158 0x23878, 0x23898,
1159 0x238a0, 0x238a8,
1160 0x238b0, 0x238c8,
1161 0x238d0, 0x238d4,
1162 0x238e0, 0x238e8,
1163 0x238f0, 0x238f0,
1164 0x238f8, 0x23a18,
1165 0x23a20, 0x23a28,
1166 0x23a30, 0x23a48,
1167 0x23a50, 0x23a54,
1168 0x23a60, 0x23a68,
1169 0x23a70, 0x23a70,
1170 0x23a78, 0x23a98,
1171 0x23aa0, 0x23aa8,
1172 0x23ab0, 0x23ac8,
1173 0x23ad0, 0x23ad4,
1174 0x23ae0, 0x23ae8,
1175 0x23af0, 0x23af0,
1176 0x23af8, 0x23c18,
1177 0x23c20, 0x23c20,
1178 0x23c28, 0x23c30,
1179 0x23c38, 0x23c38,
1180 0x23c80, 0x23c98,
1181 0x23ca0, 0x23ca8,
1182 0x23cb0, 0x23cc8,
1183 0x23cd0, 0x23cd4,
1184 0x23ce0, 0x23ce8,
1185 0x23cf0, 0x23cf0,
1186 0x23cf8, 0x23d7c,
1187 0x23e00, 0x23e04,
1188 0x24000, 0x2402c,
1189 0x24100, 0x2413c,
1190 0x24190, 0x241a0,
1191 0x241a8, 0x241b8,
1192 0x241c4, 0x241c8,
1193 0x24200, 0x24318,
1194 0x24400, 0x244b4,
1195 0x244c0, 0x24528,
1196 0x24540, 0x24614,
1197 0x25000, 0x25040,
1198 0x2504c, 0x25060,
1199 0x250c0, 0x250ec,
1200 0x25200, 0x25268,
1201 0x25270, 0x25284,
1202 0x252fc, 0x25388,
1203 0x25400, 0x25404,
1204 0x25500, 0x25500,
1205 0x25510, 0x25518,
1206 0x2552c, 0x25530,
1207 0x2553c, 0x2553c,
1208 0x25550, 0x25554,
1209 0x25600, 0x25600,
1210 0x25608, 0x2561c,
1211 0x25624, 0x25628,
1212 0x25630, 0x25634,
1213 0x2563c, 0x2563c,
1214 0x25700, 0x2571c,
1215 0x25780, 0x2578c,
1216 0x25800, 0x25818,
1217 0x25820, 0x25828,
1218 0x25830, 0x25848,
1219 0x25850, 0x25854,
1220 0x25860, 0x25868,
1221 0x25870, 0x25870,
1222 0x25878, 0x25898,
1223 0x258a0, 0x258a8,
1224 0x258b0, 0x258c8,
1225 0x258d0, 0x258d4,
1226 0x258e0, 0x258e8,
1227 0x258f0, 0x258f0,
1228 0x258f8, 0x25a18,
1229 0x25a20, 0x25a28,
1230 0x25a30, 0x25a48,
1231 0x25a50, 0x25a54,
1232 0x25a60, 0x25a68,
1233 0x25a70, 0x25a70,
1234 0x25a78, 0x25a98,
1235 0x25aa0, 0x25aa8,
1236 0x25ab0, 0x25ac8,
1237 0x25ad0, 0x25ad4,
1238 0x25ae0, 0x25ae8,
1239 0x25af0, 0x25af0,
1240 0x25af8, 0x25c18,
1241 0x25c20, 0x25c20,
1242 0x25c28, 0x25c30,
1243 0x25c38, 0x25c38,
1244 0x25c80, 0x25c98,
1245 0x25ca0, 0x25ca8,
1246 0x25cb0, 0x25cc8,
1247 0x25cd0, 0x25cd4,
1248 0x25ce0, 0x25ce8,
1249 0x25cf0, 0x25cf0,
1250 0x25cf8, 0x25d7c,
1251 0x25e00, 0x25e04,
1252 0x26000, 0x2602c,
1253 0x26100, 0x2613c,
1254 0x26190, 0x261a0,
1255 0x261a8, 0x261b8,
1256 0x261c4, 0x261c8,
1257 0x26200, 0x26318,
1258 0x26400, 0x264b4,
1259 0x264c0, 0x26528,
1260 0x26540, 0x26614,
1261 0x27000, 0x27040,
1262 0x2704c, 0x27060,
1263 0x270c0, 0x270ec,
1264 0x27200, 0x27268,
1265 0x27270, 0x27284,
1266 0x272fc, 0x27388,
1267 0x27400, 0x27404,
1268 0x27500, 0x27500,
1269 0x27510, 0x27518,
1270 0x2752c, 0x27530,
1271 0x2753c, 0x2753c,
1272 0x27550, 0x27554,
1273 0x27600, 0x27600,
1274 0x27608, 0x2761c,
1275 0x27624, 0x27628,
1276 0x27630, 0x27634,
1277 0x2763c, 0x2763c,
1278 0x27700, 0x2771c,
1279 0x27780, 0x2778c,
1280 0x27800, 0x27818,
1281 0x27820, 0x27828,
1282 0x27830, 0x27848,
1283 0x27850, 0x27854,
1284 0x27860, 0x27868,
1285 0x27870, 0x27870,
1286 0x27878, 0x27898,
1287 0x278a0, 0x278a8,
1288 0x278b0, 0x278c8,
1289 0x278d0, 0x278d4,
1290 0x278e0, 0x278e8,
1291 0x278f0, 0x278f0,
1292 0x278f8, 0x27a18,
1293 0x27a20, 0x27a28,
1294 0x27a30, 0x27a48,
1295 0x27a50, 0x27a54,
1296 0x27a60, 0x27a68,
1297 0x27a70, 0x27a70,
1298 0x27a78, 0x27a98,
1299 0x27aa0, 0x27aa8,
1300 0x27ab0, 0x27ac8,
1301 0x27ad0, 0x27ad4,
1302 0x27ae0, 0x27ae8,
1303 0x27af0, 0x27af0,
1304 0x27af8, 0x27c18,
1305 0x27c20, 0x27c20,
1306 0x27c28, 0x27c30,
1307 0x27c38, 0x27c38,
1308 0x27c80, 0x27c98,
1309 0x27ca0, 0x27ca8,
1310 0x27cb0, 0x27cc8,
1311 0x27cd0, 0x27cd4,
1312 0x27ce0, 0x27ce8,
1313 0x27cf0, 0x27cf0,
1314 0x27cf8, 0x27d7c,
1315 0x27e00, 0x27e04,
1316 };
1317
1318 static const unsigned int t5_reg_ranges[] = {
1319 0x1008, 0x10c0,
1320 0x10cc, 0x10f8,
1321 0x1100, 0x1100,
1322 0x110c, 0x1148,
1323 0x1180, 0x1184,
1324 0x1190, 0x1194,
1325 0x11a0, 0x11a4,
1326 0x11b0, 0x11b4,
1327 0x11fc, 0x123c,
1328 0x1280, 0x173c,
1329 0x1800, 0x18fc,
1330 0x3000, 0x3028,
1331 0x3060, 0x30b0,
1332 0x30b8, 0x30d8,
1333 0x30e0, 0x30fc,
1334 0x3140, 0x357c,
1335 0x35a8, 0x35cc,
1336 0x35ec, 0x35ec,
1337 0x3600, 0x5624,
1338 0x56cc, 0x56ec,
1339 0x56f4, 0x5720,
1340 0x5728, 0x575c,
1341 0x580c, 0x5814,
1342 0x5890, 0x589c,
1343 0x58a4, 0x58ac,
1344 0x58b8, 0x58bc,
1345 0x5940, 0x59c8,
1346 0x59d0, 0x59dc,
1347 0x59fc, 0x5a18,
1348 0x5a60, 0x5a70,
1349 0x5a80, 0x5a9c,
1350 0x5b94, 0x5bfc,
1351 0x6000, 0x6020,
1352 0x6028, 0x6040,
1353 0x6058, 0x609c,
1354 0x60a8, 0x614c,
1355 0x7700, 0x7798,
1356 0x77c0, 0x78fc,
1357 0x7b00, 0x7b58,
1358 0x7b60, 0x7b84,
1359 0x7b8c, 0x7c54,
1360 0x7d00, 0x7d38,
1361 0x7d40, 0x7d80,
1362 0x7d8c, 0x7ddc,
1363 0x7de4, 0x7e04,
1364 0x7e10, 0x7e1c,
1365 0x7e24, 0x7e38,
1366 0x7e40, 0x7e44,
1367 0x7e4c, 0x7e78,
1368 0x7e80, 0x7edc,
1369 0x7ee8, 0x7efc,
1370 0x8dc0, 0x8de0,
1371 0x8df8, 0x8e04,
1372 0x8e10, 0x8e84,
1373 0x8ea0, 0x8f84,
1374 0x8fc0, 0x9058,
1375 0x9060, 0x9060,
1376 0x9068, 0x90f8,
1377 0x9400, 0x9408,
1378 0x9410, 0x9470,
1379 0x9600, 0x9600,
1380 0x9608, 0x9638,
1381 0x9640, 0x96f4,
1382 0x9800, 0x9808,
1383 0x9810, 0x9864,
1384 0x9c00, 0x9c6c,
1385 0x9c80, 0x9cec,
1386 0x9d00, 0x9d6c,
1387 0x9d80, 0x9dec,
1388 0x9e00, 0x9e6c,
1389 0x9e80, 0x9eec,
1390 0x9f00, 0x9f6c,
1391 0x9f80, 0xa020,
1392 0xd000, 0xd004,
1393 0xd010, 0xd03c,
1394 0xdfc0, 0xdfe0,
1395 0xe000, 0x1106c,
1396 0x11074, 0x11088,
1397 0x1109c, 0x1117c,
1398 0x11190, 0x11204,
1399 0x19040, 0x1906c,
1400 0x19078, 0x19080,
1401 0x1908c, 0x190e8,
1402 0x190f0, 0x190f8,
1403 0x19100, 0x19110,
1404 0x19120, 0x19124,
1405 0x19150, 0x19194,
1406 0x1919c, 0x191b0,
1407 0x191d0, 0x191e8,
1408 0x19238, 0x19290,
1409 0x193f8, 0x19428,
1410 0x19430, 0x19444,
1411 0x1944c, 0x1946c,
1412 0x19474, 0x19474,
1413 0x19490, 0x194cc,
1414 0x194f0, 0x194f8,
1415 0x19c00, 0x19c08,
1416 0x19c10, 0x19c60,
1417 0x19c94, 0x19ce4,
1418 0x19cf0, 0x19d40,
1419 0x19d50, 0x19d94,
1420 0x19da0, 0x19de8,
1421 0x19df0, 0x19e10,
1422 0x19e50, 0x19e90,
1423 0x19ea0, 0x19f24,
1424 0x19f34, 0x19f34,
1425 0x19f40, 0x19f50,
1426 0x19f90, 0x19fb4,
1427 0x19fc4, 0x19fe4,
1428 0x1a000, 0x1a004,
1429 0x1a010, 0x1a06c,
1430 0x1a0b0, 0x1a0e4,
1431 0x1a0ec, 0x1a0f8,
1432 0x1a100, 0x1a108,
1433 0x1a114, 0x1a130,
1434 0x1a138, 0x1a1c4,
1435 0x1a1fc, 0x1a1fc,
1436 0x1e008, 0x1e00c,
1437 0x1e040, 0x1e044,
1438 0x1e04c, 0x1e04c,
1439 0x1e284, 0x1e290,
1440 0x1e2c0, 0x1e2c0,
1441 0x1e2e0, 0x1e2e0,
1442 0x1e300, 0x1e384,
1443 0x1e3c0, 0x1e3c8,
1444 0x1e408, 0x1e40c,
1445 0x1e440, 0x1e444,
1446 0x1e44c, 0x1e44c,
1447 0x1e684, 0x1e690,
1448 0x1e6c0, 0x1e6c0,
1449 0x1e6e0, 0x1e6e0,
1450 0x1e700, 0x1e784,
1451 0x1e7c0, 0x1e7c8,
1452 0x1e808, 0x1e80c,
1453 0x1e840, 0x1e844,
1454 0x1e84c, 0x1e84c,
1455 0x1ea84, 0x1ea90,
1456 0x1eac0, 0x1eac0,
1457 0x1eae0, 0x1eae0,
1458 0x1eb00, 0x1eb84,
1459 0x1ebc0, 0x1ebc8,
1460 0x1ec08, 0x1ec0c,
1461 0x1ec40, 0x1ec44,
1462 0x1ec4c, 0x1ec4c,
1463 0x1ee84, 0x1ee90,
1464 0x1eec0, 0x1eec0,
1465 0x1eee0, 0x1eee0,
1466 0x1ef00, 0x1ef84,
1467 0x1efc0, 0x1efc8,
1468 0x1f008, 0x1f00c,
1469 0x1f040, 0x1f044,
1470 0x1f04c, 0x1f04c,
1471 0x1f284, 0x1f290,
1472 0x1f2c0, 0x1f2c0,
1473 0x1f2e0, 0x1f2e0,
1474 0x1f300, 0x1f384,
1475 0x1f3c0, 0x1f3c8,
1476 0x1f408, 0x1f40c,
1477 0x1f440, 0x1f444,
1478 0x1f44c, 0x1f44c,
1479 0x1f684, 0x1f690,
1480 0x1f6c0, 0x1f6c0,
1481 0x1f6e0, 0x1f6e0,
1482 0x1f700, 0x1f784,
1483 0x1f7c0, 0x1f7c8,
1484 0x1f808, 0x1f80c,
1485 0x1f840, 0x1f844,
1486 0x1f84c, 0x1f84c,
1487 0x1fa84, 0x1fa90,
1488 0x1fac0, 0x1fac0,
1489 0x1fae0, 0x1fae0,
1490 0x1fb00, 0x1fb84,
1491 0x1fbc0, 0x1fbc8,
1492 0x1fc08, 0x1fc0c,
1493 0x1fc40, 0x1fc44,
1494 0x1fc4c, 0x1fc4c,
1495 0x1fe84, 0x1fe90,
1496 0x1fec0, 0x1fec0,
1497 0x1fee0, 0x1fee0,
1498 0x1ff00, 0x1ff84,
1499 0x1ffc0, 0x1ffc8,
1500 0x30000, 0x30030,
1501 0x30100, 0x30144,
1502 0x30190, 0x301a0,
1503 0x301a8, 0x301b8,
1504 0x301c4, 0x301c8,
1505 0x301d0, 0x301d0,
1506 0x30200, 0x30318,
1507 0x30400, 0x304b4,
1508 0x304c0, 0x3052c,
1509 0x30540, 0x3061c,
1510 0x30800, 0x30828,
1511 0x30834, 0x30834,
1512 0x308c0, 0x30908,
1513 0x30910, 0x309ac,
1514 0x30a00, 0x30a14,
1515 0x30a1c, 0x30a2c,
1516 0x30a44, 0x30a50,
1517 0x30a74, 0x30a74,
1518 0x30a7c, 0x30afc,
1519 0x30b08, 0x30c24,
1520 0x30d00, 0x30d00,
1521 0x30d08, 0x30d14,
1522 0x30d1c, 0x30d20,
1523 0x30d3c, 0x30d3c,
1524 0x30d48, 0x30d50,
1525 0x31200, 0x3120c,
1526 0x31220, 0x31220,
1527 0x31240, 0x31240,
1528 0x31600, 0x3160c,
1529 0x31a00, 0x31a1c,
1530 0x31e00, 0x31e20,
1531 0x31e38, 0x31e3c,
1532 0x31e80, 0x31e80,
1533 0x31e88, 0x31ea8,
1534 0x31eb0, 0x31eb4,
1535 0x31ec8, 0x31ed4,
1536 0x31fb8, 0x32004,
1537 0x32200, 0x32200,
1538 0x32208, 0x32240,
1539 0x32248, 0x32280,
1540 0x32288, 0x322c0,
1541 0x322c8, 0x322fc,
1542 0x32600, 0x32630,
1543 0x32a00, 0x32abc,
1544 0x32b00, 0x32b10,
1545 0x32b20, 0x32b30,
1546 0x32b40, 0x32b50,
1547 0x32b60, 0x32b70,
1548 0x33000, 0x33028,
1549 0x33030, 0x33048,
1550 0x33060, 0x33068,
1551 0x33070, 0x3309c,
1552 0x330f0, 0x33128,
1553 0x33130, 0x33148,
1554 0x33160, 0x33168,
1555 0x33170, 0x3319c,
1556 0x331f0, 0x33238,
1557 0x33240, 0x33240,
1558 0x33248, 0x33250,
1559 0x3325c, 0x33264,
1560 0x33270, 0x332b8,
1561 0x332c0, 0x332e4,
1562 0x332f8, 0x33338,
1563 0x33340, 0x33340,
1564 0x33348, 0x33350,
1565 0x3335c, 0x33364,
1566 0x33370, 0x333b8,
1567 0x333c0, 0x333e4,
1568 0x333f8, 0x33428,
1569 0x33430, 0x33448,
1570 0x33460, 0x33468,
1571 0x33470, 0x3349c,
1572 0x334f0, 0x33528,
1573 0x33530, 0x33548,
1574 0x33560, 0x33568,
1575 0x33570, 0x3359c,
1576 0x335f0, 0x33638,
1577 0x33640, 0x33640,
1578 0x33648, 0x33650,
1579 0x3365c, 0x33664,
1580 0x33670, 0x336b8,
1581 0x336c0, 0x336e4,
1582 0x336f8, 0x33738,
1583 0x33740, 0x33740,
1584 0x33748, 0x33750,
1585 0x3375c, 0x33764,
1586 0x33770, 0x337b8,
1587 0x337c0, 0x337e4,
1588 0x337f8, 0x337fc,
1589 0x33814, 0x33814,
1590 0x3382c, 0x3382c,
1591 0x33880, 0x3388c,
1592 0x338e8, 0x338ec,
1593 0x33900, 0x33928,
1594 0x33930, 0x33948,
1595 0x33960, 0x33968,
1596 0x33970, 0x3399c,
1597 0x339f0, 0x33a38,
1598 0x33a40, 0x33a40,
1599 0x33a48, 0x33a50,
1600 0x33a5c, 0x33a64,
1601 0x33a70, 0x33ab8,
1602 0x33ac0, 0x33ae4,
1603 0x33af8, 0x33b10,
1604 0x33b28, 0x33b28,
1605 0x33b3c, 0x33b50,
1606 0x33bf0, 0x33c10,
1607 0x33c28, 0x33c28,
1608 0x33c3c, 0x33c50,
1609 0x33cf0, 0x33cfc,
1610 0x34000, 0x34030,
1611 0x34100, 0x34144,
1612 0x34190, 0x341a0,
1613 0x341a8, 0x341b8,
1614 0x341c4, 0x341c8,
1615 0x341d0, 0x341d0,
1616 0x34200, 0x34318,
1617 0x34400, 0x344b4,
1618 0x344c0, 0x3452c,
1619 0x34540, 0x3461c,
1620 0x34800, 0x34828,
1621 0x34834, 0x34834,
1622 0x348c0, 0x34908,
1623 0x34910, 0x349ac,
1624 0x34a00, 0x34a14,
1625 0x34a1c, 0x34a2c,
1626 0x34a44, 0x34a50,
1627 0x34a74, 0x34a74,
1628 0x34a7c, 0x34afc,
1629 0x34b08, 0x34c24,
1630 0x34d00, 0x34d00,
1631 0x34d08, 0x34d14,
1632 0x34d1c, 0x34d20,
1633 0x34d3c, 0x34d3c,
1634 0x34d48, 0x34d50,
1635 0x35200, 0x3520c,
1636 0x35220, 0x35220,
1637 0x35240, 0x35240,
1638 0x35600, 0x3560c,
1639 0x35a00, 0x35a1c,
1640 0x35e00, 0x35e20,
1641 0x35e38, 0x35e3c,
1642 0x35e80, 0x35e80,
1643 0x35e88, 0x35ea8,
1644 0x35eb0, 0x35eb4,
1645 0x35ec8, 0x35ed4,
1646 0x35fb8, 0x36004,
1647 0x36200, 0x36200,
1648 0x36208, 0x36240,
1649 0x36248, 0x36280,
1650 0x36288, 0x362c0,
1651 0x362c8, 0x362fc,
1652 0x36600, 0x36630,
1653 0x36a00, 0x36abc,
1654 0x36b00, 0x36b10,
1655 0x36b20, 0x36b30,
1656 0x36b40, 0x36b50,
1657 0x36b60, 0x36b70,
1658 0x37000, 0x37028,
1659 0x37030, 0x37048,
1660 0x37060, 0x37068,
1661 0x37070, 0x3709c,
1662 0x370f0, 0x37128,
1663 0x37130, 0x37148,
1664 0x37160, 0x37168,
1665 0x37170, 0x3719c,
1666 0x371f0, 0x37238,
1667 0x37240, 0x37240,
1668 0x37248, 0x37250,
1669 0x3725c, 0x37264,
1670 0x37270, 0x372b8,
1671 0x372c0, 0x372e4,
1672 0x372f8, 0x37338,
1673 0x37340, 0x37340,
1674 0x37348, 0x37350,
1675 0x3735c, 0x37364,
1676 0x37370, 0x373b8,
1677 0x373c0, 0x373e4,
1678 0x373f8, 0x37428,
1679 0x37430, 0x37448,
1680 0x37460, 0x37468,
1681 0x37470, 0x3749c,
1682 0x374f0, 0x37528,
1683 0x37530, 0x37548,
1684 0x37560, 0x37568,
1685 0x37570, 0x3759c,
1686 0x375f0, 0x37638,
1687 0x37640, 0x37640,
1688 0x37648, 0x37650,
1689 0x3765c, 0x37664,
1690 0x37670, 0x376b8,
1691 0x376c0, 0x376e4,
1692 0x376f8, 0x37738,
1693 0x37740, 0x37740,
1694 0x37748, 0x37750,
1695 0x3775c, 0x37764,
1696 0x37770, 0x377b8,
1697 0x377c0, 0x377e4,
1698 0x377f8, 0x377fc,
1699 0x37814, 0x37814,
1700 0x3782c, 0x3782c,
1701 0x37880, 0x3788c,
1702 0x378e8, 0x378ec,
1703 0x37900, 0x37928,
1704 0x37930, 0x37948,
1705 0x37960, 0x37968,
1706 0x37970, 0x3799c,
1707 0x379f0, 0x37a38,
1708 0x37a40, 0x37a40,
1709 0x37a48, 0x37a50,
1710 0x37a5c, 0x37a64,
1711 0x37a70, 0x37ab8,
1712 0x37ac0, 0x37ae4,
1713 0x37af8, 0x37b10,
1714 0x37b28, 0x37b28,
1715 0x37b3c, 0x37b50,
1716 0x37bf0, 0x37c10,
1717 0x37c28, 0x37c28,
1718 0x37c3c, 0x37c50,
1719 0x37cf0, 0x37cfc,
1720 0x38000, 0x38030,
1721 0x38100, 0x38144,
1722 0x38190, 0x381a0,
1723 0x381a8, 0x381b8,
1724 0x381c4, 0x381c8,
1725 0x381d0, 0x381d0,
1726 0x38200, 0x38318,
1727 0x38400, 0x384b4,
1728 0x384c0, 0x3852c,
1729 0x38540, 0x3861c,
1730 0x38800, 0x38828,
1731 0x38834, 0x38834,
1732 0x388c0, 0x38908,
1733 0x38910, 0x389ac,
1734 0x38a00, 0x38a14,
1735 0x38a1c, 0x38a2c,
1736 0x38a44, 0x38a50,
1737 0x38a74, 0x38a74,
1738 0x38a7c, 0x38afc,
1739 0x38b08, 0x38c24,
1740 0x38d00, 0x38d00,
1741 0x38d08, 0x38d14,
1742 0x38d1c, 0x38d20,
1743 0x38d3c, 0x38d3c,
1744 0x38d48, 0x38d50,
1745 0x39200, 0x3920c,
1746 0x39220, 0x39220,
1747 0x39240, 0x39240,
1748 0x39600, 0x3960c,
1749 0x39a00, 0x39a1c,
1750 0x39e00, 0x39e20,
1751 0x39e38, 0x39e3c,
1752 0x39e80, 0x39e80,
1753 0x39e88, 0x39ea8,
1754 0x39eb0, 0x39eb4,
1755 0x39ec8, 0x39ed4,
1756 0x39fb8, 0x3a004,
1757 0x3a200, 0x3a200,
1758 0x3a208, 0x3a240,
1759 0x3a248, 0x3a280,
1760 0x3a288, 0x3a2c0,
1761 0x3a2c8, 0x3a2fc,
1762 0x3a600, 0x3a630,
1763 0x3aa00, 0x3aabc,
1764 0x3ab00, 0x3ab10,
1765 0x3ab20, 0x3ab30,
1766 0x3ab40, 0x3ab50,
1767 0x3ab60, 0x3ab70,
1768 0x3b000, 0x3b028,
1769 0x3b030, 0x3b048,
1770 0x3b060, 0x3b068,
1771 0x3b070, 0x3b09c,
1772 0x3b0f0, 0x3b128,
1773 0x3b130, 0x3b148,
1774 0x3b160, 0x3b168,
1775 0x3b170, 0x3b19c,
1776 0x3b1f0, 0x3b238,
1777 0x3b240, 0x3b240,
1778 0x3b248, 0x3b250,
1779 0x3b25c, 0x3b264,
1780 0x3b270, 0x3b2b8,
1781 0x3b2c0, 0x3b2e4,
1782 0x3b2f8, 0x3b338,
1783 0x3b340, 0x3b340,
1784 0x3b348, 0x3b350,
1785 0x3b35c, 0x3b364,
1786 0x3b370, 0x3b3b8,
1787 0x3b3c0, 0x3b3e4,
1788 0x3b3f8, 0x3b428,
1789 0x3b430, 0x3b448,
1790 0x3b460, 0x3b468,
1791 0x3b470, 0x3b49c,
1792 0x3b4f0, 0x3b528,
1793 0x3b530, 0x3b548,
1794 0x3b560, 0x3b568,
1795 0x3b570, 0x3b59c,
1796 0x3b5f0, 0x3b638,
1797 0x3b640, 0x3b640,
1798 0x3b648, 0x3b650,
1799 0x3b65c, 0x3b664,
1800 0x3b670, 0x3b6b8,
1801 0x3b6c0, 0x3b6e4,
1802 0x3b6f8, 0x3b738,
1803 0x3b740, 0x3b740,
1804 0x3b748, 0x3b750,
1805 0x3b75c, 0x3b764,
1806 0x3b770, 0x3b7b8,
1807 0x3b7c0, 0x3b7e4,
1808 0x3b7f8, 0x3b7fc,
1809 0x3b814, 0x3b814,
1810 0x3b82c, 0x3b82c,
1811 0x3b880, 0x3b88c,
1812 0x3b8e8, 0x3b8ec,
1813 0x3b900, 0x3b928,
1814 0x3b930, 0x3b948,
1815 0x3b960, 0x3b968,
1816 0x3b970, 0x3b99c,
1817 0x3b9f0, 0x3ba38,
1818 0x3ba40, 0x3ba40,
1819 0x3ba48, 0x3ba50,
1820 0x3ba5c, 0x3ba64,
1821 0x3ba70, 0x3bab8,
1822 0x3bac0, 0x3bae4,
1823 0x3baf8, 0x3bb10,
1824 0x3bb28, 0x3bb28,
1825 0x3bb3c, 0x3bb50,
1826 0x3bbf0, 0x3bc10,
1827 0x3bc28, 0x3bc28,
1828 0x3bc3c, 0x3bc50,
1829 0x3bcf0, 0x3bcfc,
1830 0x3c000, 0x3c030,
1831 0x3c100, 0x3c144,
1832 0x3c190, 0x3c1a0,
1833 0x3c1a8, 0x3c1b8,
1834 0x3c1c4, 0x3c1c8,
1835 0x3c1d0, 0x3c1d0,
1836 0x3c200, 0x3c318,
1837 0x3c400, 0x3c4b4,
1838 0x3c4c0, 0x3c52c,
1839 0x3c540, 0x3c61c,
1840 0x3c800, 0x3c828,
1841 0x3c834, 0x3c834,
1842 0x3c8c0, 0x3c908,
1843 0x3c910, 0x3c9ac,
1844 0x3ca00, 0x3ca14,
1845 0x3ca1c, 0x3ca2c,
1846 0x3ca44, 0x3ca50,
1847 0x3ca74, 0x3ca74,
1848 0x3ca7c, 0x3cafc,
1849 0x3cb08, 0x3cc24,
1850 0x3cd00, 0x3cd00,
1851 0x3cd08, 0x3cd14,
1852 0x3cd1c, 0x3cd20,
1853 0x3cd3c, 0x3cd3c,
1854 0x3cd48, 0x3cd50,
1855 0x3d200, 0x3d20c,
1856 0x3d220, 0x3d220,
1857 0x3d240, 0x3d240,
1858 0x3d600, 0x3d60c,
1859 0x3da00, 0x3da1c,
1860 0x3de00, 0x3de20,
1861 0x3de38, 0x3de3c,
1862 0x3de80, 0x3de80,
1863 0x3de88, 0x3dea8,
1864 0x3deb0, 0x3deb4,
1865 0x3dec8, 0x3ded4,
1866 0x3dfb8, 0x3e004,
1867 0x3e200, 0x3e200,
1868 0x3e208, 0x3e240,
1869 0x3e248, 0x3e280,
1870 0x3e288, 0x3e2c0,
1871 0x3e2c8, 0x3e2fc,
1872 0x3e600, 0x3e630,
1873 0x3ea00, 0x3eabc,
1874 0x3eb00, 0x3eb10,
1875 0x3eb20, 0x3eb30,
1876 0x3eb40, 0x3eb50,
1877 0x3eb60, 0x3eb70,
1878 0x3f000, 0x3f028,
1879 0x3f030, 0x3f048,
1880 0x3f060, 0x3f068,
1881 0x3f070, 0x3f09c,
1882 0x3f0f0, 0x3f128,
1883 0x3f130, 0x3f148,
1884 0x3f160, 0x3f168,
1885 0x3f170, 0x3f19c,
1886 0x3f1f0, 0x3f238,
1887 0x3f240, 0x3f240,
1888 0x3f248, 0x3f250,
1889 0x3f25c, 0x3f264,
1890 0x3f270, 0x3f2b8,
1891 0x3f2c0, 0x3f2e4,
1892 0x3f2f8, 0x3f338,
1893 0x3f340, 0x3f340,
1894 0x3f348, 0x3f350,
1895 0x3f35c, 0x3f364,
1896 0x3f370, 0x3f3b8,
1897 0x3f3c0, 0x3f3e4,
1898 0x3f3f8, 0x3f428,
1899 0x3f430, 0x3f448,
1900 0x3f460, 0x3f468,
1901 0x3f470, 0x3f49c,
1902 0x3f4f0, 0x3f528,
1903 0x3f530, 0x3f548,
1904 0x3f560, 0x3f568,
1905 0x3f570, 0x3f59c,
1906 0x3f5f0, 0x3f638,
1907 0x3f640, 0x3f640,
1908 0x3f648, 0x3f650,
1909 0x3f65c, 0x3f664,
1910 0x3f670, 0x3f6b8,
1911 0x3f6c0, 0x3f6e4,
1912 0x3f6f8, 0x3f738,
1913 0x3f740, 0x3f740,
1914 0x3f748, 0x3f750,
1915 0x3f75c, 0x3f764,
1916 0x3f770, 0x3f7b8,
1917 0x3f7c0, 0x3f7e4,
1918 0x3f7f8, 0x3f7fc,
1919 0x3f814, 0x3f814,
1920 0x3f82c, 0x3f82c,
1921 0x3f880, 0x3f88c,
1922 0x3f8e8, 0x3f8ec,
1923 0x3f900, 0x3f928,
1924 0x3f930, 0x3f948,
1925 0x3f960, 0x3f968,
1926 0x3f970, 0x3f99c,
1927 0x3f9f0, 0x3fa38,
1928 0x3fa40, 0x3fa40,
1929 0x3fa48, 0x3fa50,
1930 0x3fa5c, 0x3fa64,
1931 0x3fa70, 0x3fab8,
1932 0x3fac0, 0x3fae4,
1933 0x3faf8, 0x3fb10,
1934 0x3fb28, 0x3fb28,
1935 0x3fb3c, 0x3fb50,
1936 0x3fbf0, 0x3fc10,
1937 0x3fc28, 0x3fc28,
1938 0x3fc3c, 0x3fc50,
1939 0x3fcf0, 0x3fcfc,
1940 0x40000, 0x4000c,
1941 0x40040, 0x40050,
1942 0x40060, 0x40068,
1943 0x4007c, 0x4008c,
1944 0x40094, 0x400b0,
1945 0x400c0, 0x40144,
1946 0x40180, 0x4018c,
1947 0x40200, 0x40254,
1948 0x40260, 0x40264,
1949 0x40270, 0x40288,
1950 0x40290, 0x40298,
1951 0x402ac, 0x402c8,
1952 0x402d0, 0x402e0,
1953 0x402f0, 0x402f0,
1954 0x40300, 0x4033c,
1955 0x403f8, 0x403fc,
1956 0x41304, 0x413c4,
1957 0x41400, 0x4140c,
1958 0x41414, 0x4141c,
1959 0x41480, 0x414d0,
1960 0x44000, 0x44054,
1961 0x4405c, 0x44078,
1962 0x440c0, 0x44174,
1963 0x44180, 0x441ac,
1964 0x441b4, 0x441b8,
1965 0x441c0, 0x44254,
1966 0x4425c, 0x44278,
1967 0x442c0, 0x44374,
1968 0x44380, 0x443ac,
1969 0x443b4, 0x443b8,
1970 0x443c0, 0x44454,
1971 0x4445c, 0x44478,
1972 0x444c0, 0x44574,
1973 0x44580, 0x445ac,
1974 0x445b4, 0x445b8,
1975 0x445c0, 0x44654,
1976 0x4465c, 0x44678,
1977 0x446c0, 0x44774,
1978 0x44780, 0x447ac,
1979 0x447b4, 0x447b8,
1980 0x447c0, 0x44854,
1981 0x4485c, 0x44878,
1982 0x448c0, 0x44974,
1983 0x44980, 0x449ac,
1984 0x449b4, 0x449b8,
1985 0x449c0, 0x449fc,
1986 0x45000, 0x45004,
1987 0x45010, 0x45030,
1988 0x45040, 0x45060,
1989 0x45068, 0x45068,
1990 0x45080, 0x45084,
1991 0x450a0, 0x450b0,
1992 0x45200, 0x45204,
1993 0x45210, 0x45230,
1994 0x45240, 0x45260,
1995 0x45268, 0x45268,
1996 0x45280, 0x45284,
1997 0x452a0, 0x452b0,
1998 0x460c0, 0x460e4,
1999 0x47000, 0x4703c,
2000 0x47044, 0x4708c,
2001 0x47200, 0x47250,
2002 0x47400, 0x47408,
2003 0x47414, 0x47420,
2004 0x47600, 0x47618,
2005 0x47800, 0x47814,
2006 0x48000, 0x4800c,
2007 0x48040, 0x48050,
2008 0x48060, 0x48068,
2009 0x4807c, 0x4808c,
2010 0x48094, 0x480b0,
2011 0x480c0, 0x48144,
2012 0x48180, 0x4818c,
2013 0x48200, 0x48254,
2014 0x48260, 0x48264,
2015 0x48270, 0x48288,
2016 0x48290, 0x48298,
2017 0x482ac, 0x482c8,
2018 0x482d0, 0x482e0,
2019 0x482f0, 0x482f0,
2020 0x48300, 0x4833c,
2021 0x483f8, 0x483fc,
2022 0x49304, 0x493c4,
2023 0x49400, 0x4940c,
2024 0x49414, 0x4941c,
2025 0x49480, 0x494d0,
2026 0x4c000, 0x4c054,
2027 0x4c05c, 0x4c078,
2028 0x4c0c0, 0x4c174,
2029 0x4c180, 0x4c1ac,
2030 0x4c1b4, 0x4c1b8,
2031 0x4c1c0, 0x4c254,
2032 0x4c25c, 0x4c278,
2033 0x4c2c0, 0x4c374,
2034 0x4c380, 0x4c3ac,
2035 0x4c3b4, 0x4c3b8,
2036 0x4c3c0, 0x4c454,
2037 0x4c45c, 0x4c478,
2038 0x4c4c0, 0x4c574,
2039 0x4c580, 0x4c5ac,
2040 0x4c5b4, 0x4c5b8,
2041 0x4c5c0, 0x4c654,
2042 0x4c65c, 0x4c678,
2043 0x4c6c0, 0x4c774,
2044 0x4c780, 0x4c7ac,
2045 0x4c7b4, 0x4c7b8,
2046 0x4c7c0, 0x4c854,
2047 0x4c85c, 0x4c878,
2048 0x4c8c0, 0x4c974,
2049 0x4c980, 0x4c9ac,
2050 0x4c9b4, 0x4c9b8,
2051 0x4c9c0, 0x4c9fc,
2052 0x4d000, 0x4d004,
2053 0x4d010, 0x4d030,
2054 0x4d040, 0x4d060,
2055 0x4d068, 0x4d068,
2056 0x4d080, 0x4d084,
2057 0x4d0a0, 0x4d0b0,
2058 0x4d200, 0x4d204,
2059 0x4d210, 0x4d230,
2060 0x4d240, 0x4d260,
2061 0x4d268, 0x4d268,
2062 0x4d280, 0x4d284,
2063 0x4d2a0, 0x4d2b0,
2064 0x4e0c0, 0x4e0e4,
2065 0x4f000, 0x4f03c,
2066 0x4f044, 0x4f08c,
2067 0x4f200, 0x4f250,
2068 0x4f400, 0x4f408,
2069 0x4f414, 0x4f420,
2070 0x4f600, 0x4f618,
2071 0x4f800, 0x4f814,
2072 0x50000, 0x50084,
2073 0x50090, 0x500cc,
2074 0x50400, 0x50400,
2075 0x50800, 0x50884,
2076 0x50890, 0x508cc,
2077 0x50c00, 0x50c00,
2078 0x51000, 0x5101c,
2079 0x51300, 0x51308,
2080 };
2081
2082 static const unsigned int t6_reg_ranges[] = {
2083 0x1008, 0x101c,
2084 0x1024, 0x10a8,
2085 0x10b4, 0x10f8,
2086 0x1100, 0x1114,
2087 0x111c, 0x112c,
2088 0x1138, 0x113c,
2089 0x1144, 0x114c,
2090 0x1180, 0x1184,
2091 0x1190, 0x1194,
2092 0x11a0, 0x11a4,
2093 0x11b0, 0x11b4,
2094 0x11fc, 0x123c,
2095 0x1254, 0x1274,
2096 0x1280, 0x133c,
2097 0x1800, 0x18fc,
2098 0x3000, 0x302c,
2099 0x3060, 0x30b0,
2100 0x30b8, 0x30d8,
2101 0x30e0, 0x30fc,
2102 0x3140, 0x357c,
2103 0x35a8, 0x35cc,
2104 0x35ec, 0x35ec,
2105 0x3600, 0x5624,
2106 0x56cc, 0x56ec,
2107 0x56f4, 0x5720,
2108 0x5728, 0x575c,
2109 0x580c, 0x5814,
2110 0x5890, 0x589c,
2111 0x58a4, 0x58ac,
2112 0x58b8, 0x58bc,
2113 0x5940, 0x595c,
2114 0x5980, 0x598c,
2115 0x59b0, 0x59c8,
2116 0x59d0, 0x59dc,
2117 0x59fc, 0x5a18,
2118 0x5a60, 0x5a6c,
2119 0x5a80, 0x5a8c,
2120 0x5a94, 0x5a9c,
2121 0x5b94, 0x5bfc,
2122 0x5c10, 0x5e48,
2123 0x5e50, 0x5e94,
2124 0x5ea0, 0x5eb0,
2125 0x5ec0, 0x5ec0,
2126 0x5ec8, 0x5ed0,
2127 0x5ee0, 0x5ee0,
2128 0x5ef0, 0x5ef0,
2129 0x5f00, 0x5f00,
2130 0x6000, 0x6020,
2131 0x6028, 0x6040,
2132 0x6058, 0x609c,
2133 0x60a8, 0x619c,
2134 0x7700, 0x7798,
2135 0x77c0, 0x7880,
2136 0x78cc, 0x78fc,
2137 0x7b00, 0x7b58,
2138 0x7b60, 0x7b84,
2139 0x7b8c, 0x7c54,
2140 0x7d00, 0x7d38,
2141 0x7d40, 0x7d84,
2142 0x7d8c, 0x7ddc,
2143 0x7de4, 0x7e04,
2144 0x7e10, 0x7e1c,
2145 0x7e24, 0x7e38,
2146 0x7e40, 0x7e44,
2147 0x7e4c, 0x7e78,
2148 0x7e80, 0x7edc,
2149 0x7ee8, 0x7efc,
2150 0x8dc0, 0x8de4,
2151 0x8df8, 0x8e04,
2152 0x8e10, 0x8e84,
2153 0x8ea0, 0x8f88,
2154 0x8fb8, 0x9058,
2155 0x9060, 0x9060,
2156 0x9068, 0x90f8,
2157 0x9100, 0x9124,
2158 0x9400, 0x9470,
2159 0x9600, 0x9600,
2160 0x9608, 0x9638,
2161 0x9640, 0x9704,
2162 0x9710, 0x971c,
2163 0x9800, 0x9808,
2164 0x9810, 0x9864,
2165 0x9c00, 0x9c6c,
2166 0x9c80, 0x9cec,
2167 0x9d00, 0x9d6c,
2168 0x9d80, 0x9dec,
2169 0x9e00, 0x9e6c,
2170 0x9e80, 0x9eec,
2171 0x9f00, 0x9f6c,
2172 0x9f80, 0xa020,
2173 0xd000, 0xd03c,
2174 0xd100, 0xd118,
2175 0xd200, 0xd214,
2176 0xd220, 0xd234,
2177 0xd240, 0xd254,
2178 0xd260, 0xd274,
2179 0xd280, 0xd294,
2180 0xd2a0, 0xd2b4,
2181 0xd2c0, 0xd2d4,
2182 0xd2e0, 0xd2f4,
2183 0xd300, 0xd31c,
2184 0xdfc0, 0xdfe0,
2185 0xe000, 0xf008,
2186 0xf010, 0xf018,
2187 0xf020, 0xf028,
2188 0x11000, 0x11014,
2189 0x11048, 0x1106c,
2190 0x11074, 0x11088,
2191 0x11098, 0x11120,
2192 0x1112c, 0x1117c,
2193 0x11190, 0x112e0,
2194 0x11300, 0x1130c,
2195 0x12000, 0x1206c,
2196 0x19040, 0x1906c,
2197 0x19078, 0x19080,
2198 0x1908c, 0x190e8,
2199 0x190f0, 0x190f8,
2200 0x19100, 0x19110,
2201 0x19120, 0x19124,
2202 0x19150, 0x19194,
2203 0x1919c, 0x191b0,
2204 0x191d0, 0x191e8,
2205 0x19238, 0x19290,
2206 0x192a4, 0x192b0,
2207 0x192bc, 0x192bc,
2208 0x19348, 0x1934c,
2209 0x193f8, 0x19418,
2210 0x19420, 0x19428,
2211 0x19430, 0x19444,
2212 0x1944c, 0x1946c,
2213 0x19474, 0x19474,
2214 0x19490, 0x194cc,
2215 0x194f0, 0x194f8,
2216 0x19c00, 0x19c48,
2217 0x19c50, 0x19c80,
2218 0x19c94, 0x19c98,
2219 0x19ca0, 0x19cbc,
2220 0x19ce4, 0x19ce4,
2221 0x19cf0, 0x19cf8,
2222 0x19d00, 0x19d28,
2223 0x19d50, 0x19d78,
2224 0x19d94, 0x19d98,
2225 0x19da0, 0x19dc8,
2226 0x19df0, 0x19e10,
2227 0x19e50, 0x19e6c,
2228 0x19ea0, 0x19ebc,
2229 0x19ec4, 0x19ef4,
2230 0x19f04, 0x19f2c,
2231 0x19f34, 0x19f34,
2232 0x19f40, 0x19f50,
2233 0x19f90, 0x19fac,
2234 0x19fc4, 0x19fc8,
2235 0x19fd0, 0x19fe4,
2236 0x1a000, 0x1a004,
2237 0x1a010, 0x1a06c,
2238 0x1a0b0, 0x1a0e4,
2239 0x1a0ec, 0x1a0f8,
2240 0x1a100, 0x1a108,
2241 0x1a114, 0x1a130,
2242 0x1a138, 0x1a1c4,
2243 0x1a1fc, 0x1a1fc,
2244 0x1e008, 0x1e00c,
2245 0x1e040, 0x1e044,
2246 0x1e04c, 0x1e04c,
2247 0x1e284, 0x1e290,
2248 0x1e2c0, 0x1e2c0,
2249 0x1e2e0, 0x1e2e0,
2250 0x1e300, 0x1e384,
2251 0x1e3c0, 0x1e3c8,
2252 0x1e408, 0x1e40c,
2253 0x1e440, 0x1e444,
2254 0x1e44c, 0x1e44c,
2255 0x1e684, 0x1e690,
2256 0x1e6c0, 0x1e6c0,
2257 0x1e6e0, 0x1e6e0,
2258 0x1e700, 0x1e784,
2259 0x1e7c0, 0x1e7c8,
2260 0x1e808, 0x1e80c,
2261 0x1e840, 0x1e844,
2262 0x1e84c, 0x1e84c,
2263 0x1ea84, 0x1ea90,
2264 0x1eac0, 0x1eac0,
2265 0x1eae0, 0x1eae0,
2266 0x1eb00, 0x1eb84,
2267 0x1ebc0, 0x1ebc8,
2268 0x1ec08, 0x1ec0c,
2269 0x1ec40, 0x1ec44,
2270 0x1ec4c, 0x1ec4c,
2271 0x1ee84, 0x1ee90,
2272 0x1eec0, 0x1eec0,
2273 0x1eee0, 0x1eee0,
2274 0x1ef00, 0x1ef84,
2275 0x1efc0, 0x1efc8,
2276 0x1f008, 0x1f00c,
2277 0x1f040, 0x1f044,
2278 0x1f04c, 0x1f04c,
2279 0x1f284, 0x1f290,
2280 0x1f2c0, 0x1f2c0,
2281 0x1f2e0, 0x1f2e0,
2282 0x1f300, 0x1f384,
2283 0x1f3c0, 0x1f3c8,
2284 0x1f408, 0x1f40c,
2285 0x1f440, 0x1f444,
2286 0x1f44c, 0x1f44c,
2287 0x1f684, 0x1f690,
2288 0x1f6c0, 0x1f6c0,
2289 0x1f6e0, 0x1f6e0,
2290 0x1f700, 0x1f784,
2291 0x1f7c0, 0x1f7c8,
2292 0x1f808, 0x1f80c,
2293 0x1f840, 0x1f844,
2294 0x1f84c, 0x1f84c,
2295 0x1fa84, 0x1fa90,
2296 0x1fac0, 0x1fac0,
2297 0x1fae0, 0x1fae0,
2298 0x1fb00, 0x1fb84,
2299 0x1fbc0, 0x1fbc8,
2300 0x1fc08, 0x1fc0c,
2301 0x1fc40, 0x1fc44,
2302 0x1fc4c, 0x1fc4c,
2303 0x1fe84, 0x1fe90,
2304 0x1fec0, 0x1fec0,
2305 0x1fee0, 0x1fee0,
2306 0x1ff00, 0x1ff84,
2307 0x1ffc0, 0x1ffc8,
2308 0x30000, 0x30030,
2309 0x30100, 0x30168,
2310 0x30190, 0x301a0,
2311 0x301a8, 0x301b8,
2312 0x301c4, 0x301c8,
2313 0x301d0, 0x301d0,
2314 0x30200, 0x30320,
2315 0x30400, 0x304b4,
2316 0x304c0, 0x3052c,
2317 0x30540, 0x3061c,
2318 0x30800, 0x308a0,
2319 0x308c0, 0x30908,
2320 0x30910, 0x309b8,
2321 0x30a00, 0x30a04,
2322 0x30a0c, 0x30a14,
2323 0x30a1c, 0x30a2c,
2324 0x30a44, 0x30a50,
2325 0x30a74, 0x30a74,
2326 0x30a7c, 0x30afc,
2327 0x30b08, 0x30c24,
2328 0x30d00, 0x30d14,
2329 0x30d1c, 0x30d3c,
2330 0x30d44, 0x30d4c,
2331 0x30d54, 0x30d74,
2332 0x30d7c, 0x30d7c,
2333 0x30de0, 0x30de0,
2334 0x30e00, 0x30ed4,
2335 0x30f00, 0x30fa4,
2336 0x30fc0, 0x30fc4,
2337 0x31000, 0x31004,
2338 0x31080, 0x310fc,
2339 0x31208, 0x31220,
2340 0x3123c, 0x31254,
2341 0x31300, 0x31300,
2342 0x31308, 0x3131c,
2343 0x31338, 0x3133c,
2344 0x31380, 0x31380,
2345 0x31388, 0x313a8,
2346 0x313b4, 0x313b4,
2347 0x31400, 0x31420,
2348 0x31438, 0x3143c,
2349 0x31480, 0x31480,
2350 0x314a8, 0x314a8,
2351 0x314b0, 0x314b4,
2352 0x314c8, 0x314d4,
2353 0x31a40, 0x31a4c,
2354 0x31af0, 0x31b20,
2355 0x31b38, 0x31b3c,
2356 0x31b80, 0x31b80,
2357 0x31ba8, 0x31ba8,
2358 0x31bb0, 0x31bb4,
2359 0x31bc8, 0x31bd4,
2360 0x32140, 0x3218c,
2361 0x321f0, 0x321f4,
2362 0x32200, 0x32200,
2363 0x32218, 0x32218,
2364 0x32400, 0x32400,
2365 0x32408, 0x3241c,
2366 0x32618, 0x32620,
2367 0x32664, 0x32664,
2368 0x326a8, 0x326a8,
2369 0x326ec, 0x326ec,
2370 0x32a00, 0x32abc,
2371 0x32b00, 0x32b18,
2372 0x32b20, 0x32b38,
2373 0x32b40, 0x32b58,
2374 0x32b60, 0x32b78,
2375 0x32c00, 0x32c00,
2376 0x32c08, 0x32c3c,
2377 0x33000, 0x3302c,
2378 0x33034, 0x33050,
2379 0x33058, 0x33058,
2380 0x33060, 0x3308c,
2381 0x3309c, 0x330ac,
2382 0x330c0, 0x330c0,
2383 0x330c8, 0x330d0,
2384 0x330d8, 0x330e0,
2385 0x330ec, 0x3312c,
2386 0x33134, 0x33150,
2387 0x33158, 0x33158,
2388 0x33160, 0x3318c,
2389 0x3319c, 0x331ac,
2390 0x331c0, 0x331c0,
2391 0x331c8, 0x331d0,
2392 0x331d8, 0x331e0,
2393 0x331ec, 0x33290,
2394 0x33298, 0x332c4,
2395 0x332e4, 0x33390,
2396 0x33398, 0x333c4,
2397 0x333e4, 0x3342c,
2398 0x33434, 0x33450,
2399 0x33458, 0x33458,
2400 0x33460, 0x3348c,
2401 0x3349c, 0x334ac,
2402 0x334c0, 0x334c0,
2403 0x334c8, 0x334d0,
2404 0x334d8, 0x334e0,
2405 0x334ec, 0x3352c,
2406 0x33534, 0x33550,
2407 0x33558, 0x33558,
2408 0x33560, 0x3358c,
2409 0x3359c, 0x335ac,
2410 0x335c0, 0x335c0,
2411 0x335c8, 0x335d0,
2412 0x335d8, 0x335e0,
2413 0x335ec, 0x33690,
2414 0x33698, 0x336c4,
2415 0x336e4, 0x33790,
2416 0x33798, 0x337c4,
2417 0x337e4, 0x337fc,
2418 0x33814, 0x33814,
2419 0x33854, 0x33868,
2420 0x33880, 0x3388c,
2421 0x338c0, 0x338d0,
2422 0x338e8, 0x338ec,
2423 0x33900, 0x3392c,
2424 0x33934, 0x33950,
2425 0x33958, 0x33958,
2426 0x33960, 0x3398c,
2427 0x3399c, 0x339ac,
2428 0x339c0, 0x339c0,
2429 0x339c8, 0x339d0,
2430 0x339d8, 0x339e0,
2431 0x339ec, 0x33a90,
2432 0x33a98, 0x33ac4,
2433 0x33ae4, 0x33b10,
2434 0x33b24, 0x33b28,
2435 0x33b38, 0x33b50,
2436 0x33bf0, 0x33c10,
2437 0x33c24, 0x33c28,
2438 0x33c38, 0x33c50,
2439 0x33cf0, 0x33cfc,
2440 0x34000, 0x34030,
2441 0x34100, 0x34168,
2442 0x34190, 0x341a0,
2443 0x341a8, 0x341b8,
2444 0x341c4, 0x341c8,
2445 0x341d0, 0x341d0,
2446 0x34200, 0x34320,
2447 0x34400, 0x344b4,
2448 0x344c0, 0x3452c,
2449 0x34540, 0x3461c,
2450 0x34800, 0x348a0,
2451 0x348c0, 0x34908,
2452 0x34910, 0x349b8,
2453 0x34a00, 0x34a04,
2454 0x34a0c, 0x34a14,
2455 0x34a1c, 0x34a2c,
2456 0x34a44, 0x34a50,
2457 0x34a74, 0x34a74,
2458 0x34a7c, 0x34afc,
2459 0x34b08, 0x34c24,
2460 0x34d00, 0x34d14,
2461 0x34d1c, 0x34d3c,
2462 0x34d44, 0x34d4c,
2463 0x34d54, 0x34d74,
2464 0x34d7c, 0x34d7c,
2465 0x34de0, 0x34de0,
2466 0x34e00, 0x34ed4,
2467 0x34f00, 0x34fa4,
2468 0x34fc0, 0x34fc4,
2469 0x35000, 0x35004,
2470 0x35080, 0x350fc,
2471 0x35208, 0x35220,
2472 0x3523c, 0x35254,
2473 0x35300, 0x35300,
2474 0x35308, 0x3531c,
2475 0x35338, 0x3533c,
2476 0x35380, 0x35380,
2477 0x35388, 0x353a8,
2478 0x353b4, 0x353b4,
2479 0x35400, 0x35420,
2480 0x35438, 0x3543c,
2481 0x35480, 0x35480,
2482 0x354a8, 0x354a8,
2483 0x354b0, 0x354b4,
2484 0x354c8, 0x354d4,
2485 0x35a40, 0x35a4c,
2486 0x35af0, 0x35b20,
2487 0x35b38, 0x35b3c,
2488 0x35b80, 0x35b80,
2489 0x35ba8, 0x35ba8,
2490 0x35bb0, 0x35bb4,
2491 0x35bc8, 0x35bd4,
2492 0x36140, 0x3618c,
2493 0x361f0, 0x361f4,
2494 0x36200, 0x36200,
2495 0x36218, 0x36218,
2496 0x36400, 0x36400,
2497 0x36408, 0x3641c,
2498 0x36618, 0x36620,
2499 0x36664, 0x36664,
2500 0x366a8, 0x366a8,
2501 0x366ec, 0x366ec,
2502 0x36a00, 0x36abc,
2503 0x36b00, 0x36b18,
2504 0x36b20, 0x36b38,
2505 0x36b40, 0x36b58,
2506 0x36b60, 0x36b78,
2507 0x36c00, 0x36c00,
2508 0x36c08, 0x36c3c,
2509 0x37000, 0x3702c,
2510 0x37034, 0x37050,
2511 0x37058, 0x37058,
2512 0x37060, 0x3708c,
2513 0x3709c, 0x370ac,
2514 0x370c0, 0x370c0,
2515 0x370c8, 0x370d0,
2516 0x370d8, 0x370e0,
2517 0x370ec, 0x3712c,
2518 0x37134, 0x37150,
2519 0x37158, 0x37158,
2520 0x37160, 0x3718c,
2521 0x3719c, 0x371ac,
2522 0x371c0, 0x371c0,
2523 0x371c8, 0x371d0,
2524 0x371d8, 0x371e0,
2525 0x371ec, 0x37290,
2526 0x37298, 0x372c4,
2527 0x372e4, 0x37390,
2528 0x37398, 0x373c4,
2529 0x373e4, 0x3742c,
2530 0x37434, 0x37450,
2531 0x37458, 0x37458,
2532 0x37460, 0x3748c,
2533 0x3749c, 0x374ac,
2534 0x374c0, 0x374c0,
2535 0x374c8, 0x374d0,
2536 0x374d8, 0x374e0,
2537 0x374ec, 0x3752c,
2538 0x37534, 0x37550,
2539 0x37558, 0x37558,
2540 0x37560, 0x3758c,
2541 0x3759c, 0x375ac,
2542 0x375c0, 0x375c0,
2543 0x375c8, 0x375d0,
2544 0x375d8, 0x375e0,
2545 0x375ec, 0x37690,
2546 0x37698, 0x376c4,
2547 0x376e4, 0x37790,
2548 0x37798, 0x377c4,
2549 0x377e4, 0x377fc,
2550 0x37814, 0x37814,
2551 0x37854, 0x37868,
2552 0x37880, 0x3788c,
2553 0x378c0, 0x378d0,
2554 0x378e8, 0x378ec,
2555 0x37900, 0x3792c,
2556 0x37934, 0x37950,
2557 0x37958, 0x37958,
2558 0x37960, 0x3798c,
2559 0x3799c, 0x379ac,
2560 0x379c0, 0x379c0,
2561 0x379c8, 0x379d0,
2562 0x379d8, 0x379e0,
2563 0x379ec, 0x37a90,
2564 0x37a98, 0x37ac4,
2565 0x37ae4, 0x37b10,
2566 0x37b24, 0x37b28,
2567 0x37b38, 0x37b50,
2568 0x37bf0, 0x37c10,
2569 0x37c24, 0x37c28,
2570 0x37c38, 0x37c50,
2571 0x37cf0, 0x37cfc,
2572 0x40040, 0x40040,
2573 0x40080, 0x40084,
2574 0x40100, 0x40100,
2575 0x40140, 0x401bc,
2576 0x40200, 0x40214,
2577 0x40228, 0x40228,
2578 0x40240, 0x40258,
2579 0x40280, 0x40280,
2580 0x40304, 0x40304,
2581 0x40330, 0x4033c,
2582 0x41304, 0x413c8,
2583 0x413d0, 0x413dc,
2584 0x413f0, 0x413f0,
2585 0x41400, 0x4140c,
2586 0x41414, 0x4141c,
2587 0x41480, 0x414d0,
2588 0x44000, 0x4407c,
2589 0x440c0, 0x441ac,
2590 0x441b4, 0x4427c,
2591 0x442c0, 0x443ac,
2592 0x443b4, 0x4447c,
2593 0x444c0, 0x445ac,
2594 0x445b4, 0x4467c,
2595 0x446c0, 0x447ac,
2596 0x447b4, 0x4487c,
2597 0x448c0, 0x449ac,
2598 0x449b4, 0x44a7c,
2599 0x44ac0, 0x44bac,
2600 0x44bb4, 0x44c7c,
2601 0x44cc0, 0x44dac,
2602 0x44db4, 0x44e7c,
2603 0x44ec0, 0x44fac,
2604 0x44fb4, 0x4507c,
2605 0x450c0, 0x451ac,
2606 0x451b4, 0x451fc,
2607 0x45800, 0x45804,
2608 0x45810, 0x45830,
2609 0x45840, 0x45860,
2610 0x45868, 0x45868,
2611 0x45880, 0x45884,
2612 0x458a0, 0x458b0,
2613 0x45a00, 0x45a04,
2614 0x45a10, 0x45a30,
2615 0x45a40, 0x45a60,
2616 0x45a68, 0x45a68,
2617 0x45a80, 0x45a84,
2618 0x45aa0, 0x45ab0,
2619 0x460c0, 0x460e4,
2620 0x47000, 0x4703c,
2621 0x47044, 0x4708c,
2622 0x47200, 0x47250,
2623 0x47400, 0x47408,
2624 0x47414, 0x47420,
2625 0x47600, 0x47618,
2626 0x47800, 0x47814,
2627 0x47820, 0x4782c,
2628 0x50000, 0x50084,
2629 0x50090, 0x500cc,
2630 0x50300, 0x50384,
2631 0x50400, 0x50400,
2632 0x50800, 0x50884,
2633 0x50890, 0x508cc,
2634 0x50b00, 0x50b84,
2635 0x50c00, 0x50c00,
2636 0x51000, 0x51020,
2637 0x51028, 0x510b0,
2638 0x51300, 0x51324,
2639 };
2640
2641 u32 *buf_end = (u32 *)((char *)buf + buf_size);
2642 const unsigned int *reg_ranges;
2643 int reg_ranges_size, range;
2644 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2645
2646 /* Select the right set of register ranges to dump depending on the
2647 * adapter chip type.
2648 */
2649 switch (chip_version) {
2650 case CHELSIO_T4:
2651 reg_ranges = t4_reg_ranges;
2652 reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2653 break;
2654
2655 case CHELSIO_T5:
2656 reg_ranges = t5_reg_ranges;
2657 reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2658 break;
2659
2660 case CHELSIO_T6:
2661 reg_ranges = t6_reg_ranges;
2662 reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2663 break;
2664
2665 default:
2666 dev_err(adap->pdev_dev,
2667 "Unsupported chip version %d\n", chip_version);
2668 return;
2669 }
2670
2671 /* Clear the register buffer and insert the appropriate register
2672 * values selected by the above register ranges.
2673 */
2674 memset(buf, 0, buf_size);
2675 for (range = 0; range < reg_ranges_size; range += 2) {
2676 unsigned int reg = reg_ranges[range];
2677 unsigned int last_reg = reg_ranges[range + 1];
2678 u32 *bufp = (u32 *)((char *)buf + reg);
2679
2680 /* Iterate across the register range filling in the register
2681 * buffer but don't write past the end of the register buffer.
2682 */
2683 while (reg <= last_reg && bufp < buf_end) {
2684 *bufp++ = t4_read_reg(adap, reg);
2685 reg += sizeof(u32);
2686 }
2687 }
2688 }
2689
2690 #define EEPROM_STAT_ADDR 0x7bfc
2691 #define VPD_BASE 0x400
2692 #define VPD_BASE_OLD 0
2693 #define VPD_LEN 1024
2694
2695 /**
2696 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2697 * @phys_addr: the physical EEPROM address
2698 * @fn: the PCI function number
2699 * @sz: size of function-specific area
2700 *
2701 * Translate a physical EEPROM address to virtual. The first 1K is
2702 * accessed through virtual addresses starting at 31K, the rest is
2703 * accessed through virtual addresses starting at 0.
2704 *
2705 * The mapping is as follows:
2706 * [0..1K) -> [31K..32K)
2707 * [1K..1K+A) -> [31K-A..31K)
2708 * [1K+A..ES) -> [0..ES-A-1K)
2709 *
2710 * where A = @fn * @sz, and ES = EEPROM size.
2711 */
t4_eeprom_ptov(unsigned int phys_addr,unsigned int fn,unsigned int sz)2712 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2713 {
2714 fn *= sz;
2715 if (phys_addr < 1024)
2716 return phys_addr + (31 << 10);
2717 if (phys_addr < 1024 + fn)
2718 return 31744 - fn + phys_addr - 1024;
2719 if (phys_addr < EEPROMSIZE)
2720 return phys_addr - 1024 - fn;
2721 return -EINVAL;
2722 }
2723
2724 /**
2725 * t4_seeprom_wp - enable/disable EEPROM write protection
2726 * @adapter: the adapter
2727 * @enable: whether to enable or disable write protection
2728 *
2729 * Enables or disables write protection on the serial EEPROM.
2730 */
t4_seeprom_wp(struct adapter * adapter,bool enable)2731 int t4_seeprom_wp(struct adapter *adapter, bool enable)
2732 {
2733 unsigned int v = enable ? 0xc : 0;
2734 int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2735 return ret < 0 ? ret : 0;
2736 }
2737
2738 /**
2739 * t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2740 * @adapter: adapter to read
2741 * @p: where to store the parameters
2742 *
2743 * Reads card parameters stored in VPD EEPROM.
2744 */
t4_get_raw_vpd_params(struct adapter * adapter,struct vpd_params * p)2745 int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2746 {
2747 unsigned int id_len, pn_len, sn_len, na_len;
2748 int id, sn, pn, na, addr, ret = 0;
2749 u8 *vpd, base_val = 0;
2750
2751 vpd = vmalloc(VPD_LEN);
2752 if (!vpd)
2753 return -ENOMEM;
2754
2755 /* Card information normally starts at VPD_BASE but early cards had
2756 * it at 0.
2757 */
2758 ret = pci_read_vpd(adapter->pdev, VPD_BASE, 1, &base_val);
2759 if (ret < 0)
2760 goto out;
2761
2762 addr = base_val == PCI_VPD_LRDT_ID_STRING ? VPD_BASE : VPD_BASE_OLD;
2763
2764 ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2765 if (ret < 0)
2766 goto out;
2767
2768 ret = pci_vpd_find_id_string(vpd, VPD_LEN, &id_len);
2769 if (ret < 0)
2770 goto out;
2771 id = ret;
2772
2773 ret = pci_vpd_check_csum(vpd, VPD_LEN);
2774 if (ret) {
2775 dev_err(adapter->pdev_dev, "VPD checksum incorrect or missing\n");
2776 ret = -EINVAL;
2777 goto out;
2778 }
2779
2780 ret = pci_vpd_find_ro_info_keyword(vpd, VPD_LEN,
2781 PCI_VPD_RO_KEYWORD_SERIALNO, &sn_len);
2782 if (ret < 0)
2783 goto out;
2784 sn = ret;
2785
2786 ret = pci_vpd_find_ro_info_keyword(vpd, VPD_LEN,
2787 PCI_VPD_RO_KEYWORD_PARTNO, &pn_len);
2788 if (ret < 0)
2789 goto out;
2790 pn = ret;
2791
2792 ret = pci_vpd_find_ro_info_keyword(vpd, VPD_LEN, "NA", &na_len);
2793 if (ret < 0)
2794 goto out;
2795 na = ret;
2796
2797 memcpy(p->id, vpd + id, min_t(unsigned int, id_len, ID_LEN));
2798 strim(p->id);
2799 memcpy(p->sn, vpd + sn, min_t(unsigned int, sn_len, SERNUM_LEN));
2800 strim(p->sn);
2801 memcpy(p->pn, vpd + pn, min_t(unsigned int, pn_len, PN_LEN));
2802 strim(p->pn);
2803 memcpy(p->na, vpd + na, min_t(unsigned int, na_len, MACADDR_LEN));
2804 strim(p->na);
2805
2806 out:
2807 vfree(vpd);
2808 if (ret < 0) {
2809 dev_err(adapter->pdev_dev, "error reading VPD\n");
2810 return ret;
2811 }
2812
2813 return 0;
2814 }
2815
2816 /**
2817 * t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2818 * @adapter: adapter to read
2819 * @p: where to store the parameters
2820 *
2821 * Reads card parameters stored in VPD EEPROM and retrieves the Core
2822 * Clock. This can only be called after a connection to the firmware
2823 * is established.
2824 */
t4_get_vpd_params(struct adapter * adapter,struct vpd_params * p)2825 int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2826 {
2827 u32 cclk_param, cclk_val;
2828 int ret;
2829
2830 /* Grab the raw VPD parameters.
2831 */
2832 ret = t4_get_raw_vpd_params(adapter, p);
2833 if (ret)
2834 return ret;
2835
2836 /* Ask firmware for the Core Clock since it knows how to translate the
2837 * Reference Clock ('V2') VPD field into a Core Clock value ...
2838 */
2839 cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2840 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2841 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2842 1, &cclk_param, &cclk_val);
2843
2844 if (ret)
2845 return ret;
2846 p->cclk = cclk_val;
2847
2848 return 0;
2849 }
2850
2851 /**
2852 * t4_get_pfres - retrieve VF resource limits
2853 * @adapter: the adapter
2854 *
2855 * Retrieves configured resource limits and capabilities for a physical
2856 * function. The results are stored in @adapter->pfres.
2857 */
t4_get_pfres(struct adapter * adapter)2858 int t4_get_pfres(struct adapter *adapter)
2859 {
2860 struct pf_resources *pfres = &adapter->params.pfres;
2861 struct fw_pfvf_cmd cmd, rpl;
2862 int v;
2863 u32 word;
2864
2865 /* Execute PFVF Read command to get VF resource limits; bail out early
2866 * with error on command failure.
2867 */
2868 memset(&cmd, 0, sizeof(cmd));
2869 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
2870 FW_CMD_REQUEST_F |
2871 FW_CMD_READ_F |
2872 FW_PFVF_CMD_PFN_V(adapter->pf) |
2873 FW_PFVF_CMD_VFN_V(0));
2874 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2875 v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
2876 if (v != FW_SUCCESS)
2877 return v;
2878
2879 /* Extract PF resource limits and return success.
2880 */
2881 word = be32_to_cpu(rpl.niqflint_niq);
2882 pfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
2883 pfres->niq = FW_PFVF_CMD_NIQ_G(word);
2884
2885 word = be32_to_cpu(rpl.type_to_neq);
2886 pfres->neq = FW_PFVF_CMD_NEQ_G(word);
2887 pfres->pmask = FW_PFVF_CMD_PMASK_G(word);
2888
2889 word = be32_to_cpu(rpl.tc_to_nexactf);
2890 pfres->tc = FW_PFVF_CMD_TC_G(word);
2891 pfres->nvi = FW_PFVF_CMD_NVI_G(word);
2892 pfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
2893
2894 word = be32_to_cpu(rpl.r_caps_to_nethctrl);
2895 pfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
2896 pfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
2897 pfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
2898
2899 return 0;
2900 }
2901
2902 /* serial flash and firmware constants */
2903 enum {
2904 SF_ATTEMPTS = 10, /* max retries for SF operations */
2905
2906 /* flash command opcodes */
2907 SF_PROG_PAGE = 2, /* program page */
2908 SF_WR_DISABLE = 4, /* disable writes */
2909 SF_RD_STATUS = 5, /* read status register */
2910 SF_WR_ENABLE = 6, /* enable writes */
2911 SF_RD_DATA_FAST = 0xb, /* read flash */
2912 SF_RD_ID = 0x9f, /* read ID */
2913 SF_ERASE_SECTOR = 0xd8, /* erase sector */
2914 };
2915
2916 /**
2917 * sf1_read - read data from the serial flash
2918 * @adapter: the adapter
2919 * @byte_cnt: number of bytes to read
2920 * @cont: whether another operation will be chained
2921 * @lock: whether to lock SF for PL access only
2922 * @valp: where to store the read data
2923 *
2924 * Reads up to 4 bytes of data from the serial flash. The location of
2925 * the read needs to be specified prior to calling this by issuing the
2926 * appropriate commands to the serial flash.
2927 */
sf1_read(struct adapter * adapter,unsigned int byte_cnt,int cont,int lock,u32 * valp)2928 static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2929 int lock, u32 *valp)
2930 {
2931 int ret;
2932
2933 if (!byte_cnt || byte_cnt > 4)
2934 return -EINVAL;
2935 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2936 return -EBUSY;
2937 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2938 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2939 ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2940 if (!ret)
2941 *valp = t4_read_reg(adapter, SF_DATA_A);
2942 return ret;
2943 }
2944
2945 /**
2946 * sf1_write - write data to the serial flash
2947 * @adapter: the adapter
2948 * @byte_cnt: number of bytes to write
2949 * @cont: whether another operation will be chained
2950 * @lock: whether to lock SF for PL access only
2951 * @val: value to write
2952 *
2953 * Writes up to 4 bytes of data to the serial flash. The location of
2954 * the write needs to be specified prior to calling this by issuing the
2955 * appropriate commands to the serial flash.
2956 */
sf1_write(struct adapter * adapter,unsigned int byte_cnt,int cont,int lock,u32 val)2957 static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2958 int lock, u32 val)
2959 {
2960 if (!byte_cnt || byte_cnt > 4)
2961 return -EINVAL;
2962 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2963 return -EBUSY;
2964 t4_write_reg(adapter, SF_DATA_A, val);
2965 t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2966 SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2967 return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2968 }
2969
2970 /**
2971 * flash_wait_op - wait for a flash operation to complete
2972 * @adapter: the adapter
2973 * @attempts: max number of polls of the status register
2974 * @delay: delay between polls in ms
2975 *
2976 * Wait for a flash operation to complete by polling the status register.
2977 */
flash_wait_op(struct adapter * adapter,int attempts,int delay)2978 static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
2979 {
2980 int ret;
2981 u32 status;
2982
2983 while (1) {
2984 if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
2985 (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
2986 return ret;
2987 if (!(status & 1))
2988 return 0;
2989 if (--attempts == 0)
2990 return -EAGAIN;
2991 if (delay)
2992 msleep(delay);
2993 }
2994 }
2995
2996 /**
2997 * t4_read_flash - read words from serial flash
2998 * @adapter: the adapter
2999 * @addr: the start address for the read
3000 * @nwords: how many 32-bit words to read
3001 * @data: where to store the read data
3002 * @byte_oriented: whether to store data as bytes or as words
3003 *
3004 * Read the specified number of 32-bit words from the serial flash.
3005 * If @byte_oriented is set the read data is stored as a byte array
3006 * (i.e., big-endian), otherwise as 32-bit words in the platform's
3007 * natural endianness.
3008 */
t4_read_flash(struct adapter * adapter,unsigned int addr,unsigned int nwords,u32 * data,int byte_oriented)3009 int t4_read_flash(struct adapter *adapter, unsigned int addr,
3010 unsigned int nwords, u32 *data, int byte_oriented)
3011 {
3012 int ret;
3013
3014 if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3015 return -EINVAL;
3016
3017 addr = swab32(addr) | SF_RD_DATA_FAST;
3018
3019 if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3020 (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3021 return ret;
3022
3023 for ( ; nwords; nwords--, data++) {
3024 ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3025 if (nwords == 1)
3026 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3027 if (ret)
3028 return ret;
3029 if (byte_oriented)
3030 *data = (__force __u32)(cpu_to_be32(*data));
3031 }
3032 return 0;
3033 }
3034
3035 /**
3036 * t4_write_flash - write up to a page of data to the serial flash
3037 * @adapter: the adapter
3038 * @addr: the start address to write
3039 * @n: length of data to write in bytes
3040 * @data: the data to write
3041 * @byte_oriented: whether to store data as bytes or as words
3042 *
3043 * Writes up to a page of data (256 bytes) to the serial flash starting
3044 * at the given address. All the data must be written to the same page.
3045 * If @byte_oriented is set the write data is stored as byte stream
3046 * (i.e. matches what on disk), otherwise in big-endian.
3047 */
t4_write_flash(struct adapter * adapter,unsigned int addr,unsigned int n,const u8 * data,bool byte_oriented)3048 static int t4_write_flash(struct adapter *adapter, unsigned int addr,
3049 unsigned int n, const u8 *data, bool byte_oriented)
3050 {
3051 unsigned int i, c, left, val, offset = addr & 0xff;
3052 u32 buf[64];
3053 int ret;
3054
3055 if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3056 return -EINVAL;
3057
3058 val = swab32(addr) | SF_PROG_PAGE;
3059
3060 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3061 (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3062 goto unlock;
3063
3064 for (left = n; left; left -= c, data += c) {
3065 c = min(left, 4U);
3066 for (val = 0, i = 0; i < c; ++i) {
3067 if (byte_oriented)
3068 val = (val << 8) + data[i];
3069 else
3070 val = (val << 8) + data[c - i - 1];
3071 }
3072
3073 ret = sf1_write(adapter, c, c != left, 1, val);
3074 if (ret)
3075 goto unlock;
3076 }
3077 ret = flash_wait_op(adapter, 8, 1);
3078 if (ret)
3079 goto unlock;
3080
3081 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3082
3083 /* Read the page to verify the write succeeded */
3084 ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3085 byte_oriented);
3086 if (ret)
3087 return ret;
3088
3089 if (memcmp(data - n, (u8 *)buf + offset, n)) {
3090 dev_err(adapter->pdev_dev,
3091 "failed to correctly write the flash page at %#x\n",
3092 addr);
3093 return -EIO;
3094 }
3095 return 0;
3096
3097 unlock:
3098 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3099 return ret;
3100 }
3101
3102 /**
3103 * t4_get_fw_version - read the firmware version
3104 * @adapter: the adapter
3105 * @vers: where to place the version
3106 *
3107 * Reads the FW version from flash.
3108 */
t4_get_fw_version(struct adapter * adapter,u32 * vers)3109 int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3110 {
3111 return t4_read_flash(adapter, FLASH_FW_START +
3112 offsetof(struct fw_hdr, fw_ver), 1,
3113 vers, 0);
3114 }
3115
3116 /**
3117 * t4_get_bs_version - read the firmware bootstrap version
3118 * @adapter: the adapter
3119 * @vers: where to place the version
3120 *
3121 * Reads the FW Bootstrap version from flash.
3122 */
t4_get_bs_version(struct adapter * adapter,u32 * vers)3123 int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3124 {
3125 return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3126 offsetof(struct fw_hdr, fw_ver), 1,
3127 vers, 0);
3128 }
3129
3130 /**
3131 * t4_get_tp_version - read the TP microcode version
3132 * @adapter: the adapter
3133 * @vers: where to place the version
3134 *
3135 * Reads the TP microcode version from flash.
3136 */
t4_get_tp_version(struct adapter * adapter,u32 * vers)3137 int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3138 {
3139 return t4_read_flash(adapter, FLASH_FW_START +
3140 offsetof(struct fw_hdr, tp_microcode_ver),
3141 1, vers, 0);
3142 }
3143
3144 /**
3145 * t4_get_exprom_version - return the Expansion ROM version (if any)
3146 * @adap: the adapter
3147 * @vers: where to place the version
3148 *
3149 * Reads the Expansion ROM header from FLASH and returns the version
3150 * number (if present) through the @vers return value pointer. We return
3151 * this in the Firmware Version Format since it's convenient. Return
3152 * 0 on success, -ENOENT if no Expansion ROM is present.
3153 */
t4_get_exprom_version(struct adapter * adap,u32 * vers)3154 int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3155 {
3156 struct exprom_header {
3157 unsigned char hdr_arr[16]; /* must start with 0x55aa */
3158 unsigned char hdr_ver[4]; /* Expansion ROM version */
3159 } *hdr;
3160 u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3161 sizeof(u32))];
3162 int ret;
3163
3164 ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3165 ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3166 0);
3167 if (ret)
3168 return ret;
3169
3170 hdr = (struct exprom_header *)exprom_header_buf;
3171 if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3172 return -ENOENT;
3173
3174 *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3175 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3176 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3177 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3178 return 0;
3179 }
3180
3181 /**
3182 * t4_get_vpd_version - return the VPD version
3183 * @adapter: the adapter
3184 * @vers: where to place the version
3185 *
3186 * Reads the VPD via the Firmware interface (thus this can only be called
3187 * once we're ready to issue Firmware commands). The format of the
3188 * VPD version is adapter specific. Returns 0 on success, an error on
3189 * failure.
3190 *
3191 * Note that early versions of the Firmware didn't include the ability
3192 * to retrieve the VPD version, so we zero-out the return-value parameter
3193 * in that case to avoid leaving it with garbage in it.
3194 *
3195 * Also note that the Firmware will return its cached copy of the VPD
3196 * Revision ID, not the actual Revision ID as written in the Serial
3197 * EEPROM. This is only an issue if a new VPD has been written and the
3198 * Firmware/Chip haven't yet gone through a RESET sequence. So it's best
3199 * to defer calling this routine till after a FW_RESET_CMD has been issued
3200 * if the Host Driver will be performing a full adapter initialization.
3201 */
t4_get_vpd_version(struct adapter * adapter,u32 * vers)3202 int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3203 {
3204 u32 vpdrev_param;
3205 int ret;
3206
3207 vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3208 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3209 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3210 1, &vpdrev_param, vers);
3211 if (ret)
3212 *vers = 0;
3213 return ret;
3214 }
3215
3216 /**
3217 * t4_get_scfg_version - return the Serial Configuration version
3218 * @adapter: the adapter
3219 * @vers: where to place the version
3220 *
3221 * Reads the Serial Configuration Version via the Firmware interface
3222 * (thus this can only be called once we're ready to issue Firmware
3223 * commands). The format of the Serial Configuration version is
3224 * adapter specific. Returns 0 on success, an error on failure.
3225 *
3226 * Note that early versions of the Firmware didn't include the ability
3227 * to retrieve the Serial Configuration version, so we zero-out the
3228 * return-value parameter in that case to avoid leaving it with
3229 * garbage in it.
3230 *
3231 * Also note that the Firmware will return its cached copy of the Serial
3232 * Initialization Revision ID, not the actual Revision ID as written in
3233 * the Serial EEPROM. This is only an issue if a new VPD has been written
3234 * and the Firmware/Chip haven't yet gone through a RESET sequence. So
3235 * it's best to defer calling this routine till after a FW_RESET_CMD has
3236 * been issued if the Host Driver will be performing a full adapter
3237 * initialization.
3238 */
t4_get_scfg_version(struct adapter * adapter,u32 * vers)3239 int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3240 {
3241 u32 scfgrev_param;
3242 int ret;
3243
3244 scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3245 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3246 ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3247 1, &scfgrev_param, vers);
3248 if (ret)
3249 *vers = 0;
3250 return ret;
3251 }
3252
3253 /**
3254 * t4_get_version_info - extract various chip/firmware version information
3255 * @adapter: the adapter
3256 *
3257 * Reads various chip/firmware version numbers and stores them into the
3258 * adapter Adapter Parameters structure. If any of the efforts fails
3259 * the first failure will be returned, but all of the version numbers
3260 * will be read.
3261 */
t4_get_version_info(struct adapter * adapter)3262 int t4_get_version_info(struct adapter *adapter)
3263 {
3264 int ret = 0;
3265
3266 #define FIRST_RET(__getvinfo) \
3267 do { \
3268 int __ret = __getvinfo; \
3269 if (__ret && !ret) \
3270 ret = __ret; \
3271 } while (0)
3272
3273 FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3274 FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3275 FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3276 FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3277 FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3278 FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3279
3280 #undef FIRST_RET
3281 return ret;
3282 }
3283
3284 /**
3285 * t4_dump_version_info - dump all of the adapter configuration IDs
3286 * @adapter: the adapter
3287 *
3288 * Dumps all of the various bits of adapter configuration version/revision
3289 * IDs information. This is typically called at some point after
3290 * t4_get_version_info() has been called.
3291 */
t4_dump_version_info(struct adapter * adapter)3292 void t4_dump_version_info(struct adapter *adapter)
3293 {
3294 /* Device information */
3295 dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3296 adapter->params.vpd.id,
3297 CHELSIO_CHIP_RELEASE(adapter->params.chip));
3298 dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3299 adapter->params.vpd.sn, adapter->params.vpd.pn);
3300
3301 /* Firmware Version */
3302 if (!adapter->params.fw_vers)
3303 dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3304 else
3305 dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3306 FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3307 FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3308 FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3309 FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3310
3311 /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3312 * Firmware, so dev_info() is more appropriate here.)
3313 */
3314 if (!adapter->params.bs_vers)
3315 dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3316 else
3317 dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3318 FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3319 FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3320 FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3321 FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3322
3323 /* TP Microcode Version */
3324 if (!adapter->params.tp_vers)
3325 dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3326 else
3327 dev_info(adapter->pdev_dev,
3328 "TP Microcode version: %u.%u.%u.%u\n",
3329 FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3330 FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3331 FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3332 FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3333
3334 /* Expansion ROM version */
3335 if (!adapter->params.er_vers)
3336 dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3337 else
3338 dev_info(adapter->pdev_dev,
3339 "Expansion ROM version: %u.%u.%u.%u\n",
3340 FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3341 FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3342 FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3343 FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3344
3345 /* Serial Configuration version */
3346 dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3347 adapter->params.scfg_vers);
3348
3349 /* VPD Version */
3350 dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3351 adapter->params.vpd_vers);
3352 }
3353
3354 /**
3355 * t4_check_fw_version - check if the FW is supported with this driver
3356 * @adap: the adapter
3357 *
3358 * Checks if an adapter's FW is compatible with the driver. Returns 0
3359 * if there's exact match, a negative error if the version could not be
3360 * read or there's a major version mismatch
3361 */
t4_check_fw_version(struct adapter * adap)3362 int t4_check_fw_version(struct adapter *adap)
3363 {
3364 int i, ret, major, minor, micro;
3365 int exp_major, exp_minor, exp_micro;
3366 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3367
3368 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3369 /* Try multiple times before returning error */
3370 for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3371 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3372
3373 if (ret)
3374 return ret;
3375
3376 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3377 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3378 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3379
3380 switch (chip_version) {
3381 case CHELSIO_T4:
3382 exp_major = T4FW_MIN_VERSION_MAJOR;
3383 exp_minor = T4FW_MIN_VERSION_MINOR;
3384 exp_micro = T4FW_MIN_VERSION_MICRO;
3385 break;
3386 case CHELSIO_T5:
3387 exp_major = T5FW_MIN_VERSION_MAJOR;
3388 exp_minor = T5FW_MIN_VERSION_MINOR;
3389 exp_micro = T5FW_MIN_VERSION_MICRO;
3390 break;
3391 case CHELSIO_T6:
3392 exp_major = T6FW_MIN_VERSION_MAJOR;
3393 exp_minor = T6FW_MIN_VERSION_MINOR;
3394 exp_micro = T6FW_MIN_VERSION_MICRO;
3395 break;
3396 default:
3397 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3398 adap->chip);
3399 return -EINVAL;
3400 }
3401
3402 if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3403 (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3404 dev_err(adap->pdev_dev,
3405 "Card has firmware version %u.%u.%u, minimum "
3406 "supported firmware is %u.%u.%u.\n", major, minor,
3407 micro, exp_major, exp_minor, exp_micro);
3408 return -EFAULT;
3409 }
3410 return 0;
3411 }
3412
3413 /* Is the given firmware API compatible with the one the driver was compiled
3414 * with?
3415 */
fw_compatible(const struct fw_hdr * hdr1,const struct fw_hdr * hdr2)3416 static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3417 {
3418
3419 /* short circuit if it's the exact same firmware version */
3420 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3421 return 1;
3422
3423 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3424 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3425 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3426 return 1;
3427 #undef SAME_INTF
3428
3429 return 0;
3430 }
3431
3432 /* The firmware in the filesystem is usable, but should it be installed?
3433 * This routine explains itself in detail if it indicates the filesystem
3434 * firmware should be installed.
3435 */
should_install_fs_fw(struct adapter * adap,int card_fw_usable,int k,int c)3436 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3437 int k, int c)
3438 {
3439 const char *reason;
3440
3441 if (!card_fw_usable) {
3442 reason = "incompatible or unusable";
3443 goto install;
3444 }
3445
3446 if (k > c) {
3447 reason = "older than the version supported with this driver";
3448 goto install;
3449 }
3450
3451 return 0;
3452
3453 install:
3454 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3455 "installing firmware %u.%u.%u.%u on card.\n",
3456 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3457 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3458 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3459 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3460
3461 return 1;
3462 }
3463
t4_prep_fw(struct adapter * adap,struct fw_info * fw_info,const u8 * fw_data,unsigned int fw_size,struct fw_hdr * card_fw,enum dev_state state,int * reset)3464 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3465 const u8 *fw_data, unsigned int fw_size,
3466 struct fw_hdr *card_fw, enum dev_state state,
3467 int *reset)
3468 {
3469 int ret, card_fw_usable, fs_fw_usable;
3470 const struct fw_hdr *fs_fw;
3471 const struct fw_hdr *drv_fw;
3472
3473 drv_fw = &fw_info->fw_hdr;
3474
3475 /* Read the header of the firmware on the card */
3476 ret = t4_read_flash(adap, FLASH_FW_START,
3477 sizeof(*card_fw) / sizeof(uint32_t),
3478 (uint32_t *)card_fw, 1);
3479 if (ret == 0) {
3480 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3481 } else {
3482 dev_err(adap->pdev_dev,
3483 "Unable to read card's firmware header: %d\n", ret);
3484 card_fw_usable = 0;
3485 }
3486
3487 if (fw_data != NULL) {
3488 fs_fw = (const void *)fw_data;
3489 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3490 } else {
3491 fs_fw = NULL;
3492 fs_fw_usable = 0;
3493 }
3494
3495 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3496 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3497 /* Common case: the firmware on the card is an exact match and
3498 * the filesystem one is an exact match too, or the filesystem
3499 * one is absent/incompatible.
3500 */
3501 } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3502 should_install_fs_fw(adap, card_fw_usable,
3503 be32_to_cpu(fs_fw->fw_ver),
3504 be32_to_cpu(card_fw->fw_ver))) {
3505 ret = t4_fw_upgrade(adap, adap->mbox, fw_data,
3506 fw_size, 0);
3507 if (ret != 0) {
3508 dev_err(adap->pdev_dev,
3509 "failed to install firmware: %d\n", ret);
3510 goto bye;
3511 }
3512
3513 /* Installed successfully, update the cached header too. */
3514 *card_fw = *fs_fw;
3515 card_fw_usable = 1;
3516 *reset = 0; /* already reset as part of load_fw */
3517 }
3518
3519 if (!card_fw_usable) {
3520 uint32_t d, c, k;
3521
3522 d = be32_to_cpu(drv_fw->fw_ver);
3523 c = be32_to_cpu(card_fw->fw_ver);
3524 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3525
3526 dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3527 "chip state %d, "
3528 "driver compiled with %d.%d.%d.%d, "
3529 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3530 state,
3531 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3532 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3533 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3534 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3535 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3536 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3537 ret = -EINVAL;
3538 goto bye;
3539 }
3540
3541 /* We're using whatever's on the card and it's known to be good. */
3542 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3543 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3544
3545 bye:
3546 return ret;
3547 }
3548
3549 /**
3550 * t4_flash_erase_sectors - erase a range of flash sectors
3551 * @adapter: the adapter
3552 * @start: the first sector to erase
3553 * @end: the last sector to erase
3554 *
3555 * Erases the sectors in the given inclusive range.
3556 */
t4_flash_erase_sectors(struct adapter * adapter,int start,int end)3557 static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3558 {
3559 int ret = 0;
3560
3561 if (end >= adapter->params.sf_nsec)
3562 return -EINVAL;
3563
3564 while (start <= end) {
3565 if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3566 (ret = sf1_write(adapter, 4, 0, 1,
3567 SF_ERASE_SECTOR | (start << 8))) != 0 ||
3568 (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3569 dev_err(adapter->pdev_dev,
3570 "erase of flash sector %d failed, error %d\n",
3571 start, ret);
3572 break;
3573 }
3574 start++;
3575 }
3576 t4_write_reg(adapter, SF_OP_A, 0); /* unlock SF */
3577 return ret;
3578 }
3579
3580 /**
3581 * t4_flash_cfg_addr - return the address of the flash configuration file
3582 * @adapter: the adapter
3583 *
3584 * Return the address within the flash where the Firmware Configuration
3585 * File is stored.
3586 */
t4_flash_cfg_addr(struct adapter * adapter)3587 unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3588 {
3589 if (adapter->params.sf_size == 0x100000)
3590 return FLASH_FPGA_CFG_START;
3591 else
3592 return FLASH_CFG_START;
3593 }
3594
3595 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
3596 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
3597 * and emit an error message for mismatched firmware to save our caller the
3598 * effort ...
3599 */
t4_fw_matches_chip(const struct adapter * adap,const struct fw_hdr * hdr)3600 static bool t4_fw_matches_chip(const struct adapter *adap,
3601 const struct fw_hdr *hdr)
3602 {
3603 /* The expression below will return FALSE for any unsupported adapter
3604 * which will keep us "honest" in the future ...
3605 */
3606 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3607 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3608 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3609 return true;
3610
3611 dev_err(adap->pdev_dev,
3612 "FW image (%d) is not suitable for this adapter (%d)\n",
3613 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3614 return false;
3615 }
3616
3617 /**
3618 * t4_load_fw - download firmware
3619 * @adap: the adapter
3620 * @fw_data: the firmware image to write
3621 * @size: image size
3622 *
3623 * Write the supplied firmware image to the card's serial flash.
3624 */
t4_load_fw(struct adapter * adap,const u8 * fw_data,unsigned int size)3625 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3626 {
3627 u32 csum;
3628 int ret, addr;
3629 unsigned int i;
3630 u8 first_page[SF_PAGE_SIZE];
3631 const __be32 *p = (const __be32 *)fw_data;
3632 const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3633 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3634 unsigned int fw_start_sec = FLASH_FW_START_SEC;
3635 unsigned int fw_size = FLASH_FW_MAX_SIZE;
3636 unsigned int fw_start = FLASH_FW_START;
3637
3638 if (!size) {
3639 dev_err(adap->pdev_dev, "FW image has no data\n");
3640 return -EINVAL;
3641 }
3642 if (size & 511) {
3643 dev_err(adap->pdev_dev,
3644 "FW image size not multiple of 512 bytes\n");
3645 return -EINVAL;
3646 }
3647 if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3648 dev_err(adap->pdev_dev,
3649 "FW image size differs from size in FW header\n");
3650 return -EINVAL;
3651 }
3652 if (size > fw_size) {
3653 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3654 fw_size);
3655 return -EFBIG;
3656 }
3657 if (!t4_fw_matches_chip(adap, hdr))
3658 return -EINVAL;
3659
3660 for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3661 csum += be32_to_cpu(p[i]);
3662
3663 if (csum != 0xffffffff) {
3664 dev_err(adap->pdev_dev,
3665 "corrupted firmware image, checksum %#x\n", csum);
3666 return -EINVAL;
3667 }
3668
3669 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
3670 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3671 if (ret)
3672 goto out;
3673
3674 /*
3675 * We write the correct version at the end so the driver can see a bad
3676 * version if the FW write fails. Start by writing a copy of the
3677 * first page with a bad version.
3678 */
3679 memcpy(first_page, fw_data, SF_PAGE_SIZE);
3680 ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3681 ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, true);
3682 if (ret)
3683 goto out;
3684
3685 addr = fw_start;
3686 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3687 addr += SF_PAGE_SIZE;
3688 fw_data += SF_PAGE_SIZE;
3689 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, true);
3690 if (ret)
3691 goto out;
3692 }
3693
3694 ret = t4_write_flash(adap, fw_start + offsetof(struct fw_hdr, fw_ver),
3695 sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver,
3696 true);
3697 out:
3698 if (ret)
3699 dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3700 ret);
3701 else
3702 ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3703 return ret;
3704 }
3705
3706 /**
3707 * t4_phy_fw_ver - return current PHY firmware version
3708 * @adap: the adapter
3709 * @phy_fw_ver: return value buffer for PHY firmware version
3710 *
3711 * Returns the current version of external PHY firmware on the
3712 * adapter.
3713 */
t4_phy_fw_ver(struct adapter * adap,int * phy_fw_ver)3714 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3715 {
3716 u32 param, val;
3717 int ret;
3718
3719 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3720 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3721 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3722 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3723 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3724 ¶m, &val);
3725 if (ret)
3726 return ret;
3727 *phy_fw_ver = val;
3728 return 0;
3729 }
3730
3731 /**
3732 * t4_load_phy_fw - download port PHY firmware
3733 * @adap: the adapter
3734 * @win: the PCI-E Memory Window index to use for t4_memory_rw()
3735 * @phy_fw_version: function to check PHY firmware versions
3736 * @phy_fw_data: the PHY firmware image to write
3737 * @phy_fw_size: image size
3738 *
3739 * Transfer the specified PHY firmware to the adapter. If a non-NULL
3740 * @phy_fw_version is supplied, then it will be used to determine if
3741 * it's necessary to perform the transfer by comparing the version
3742 * of any existing adapter PHY firmware with that of the passed in
3743 * PHY firmware image.
3744 *
3745 * A negative error number will be returned if an error occurs. If
3746 * version number support is available and there's no need to upgrade
3747 * the firmware, 0 will be returned. If firmware is successfully
3748 * transferred to the adapter, 1 will be returned.
3749 *
3750 * NOTE: some adapters only have local RAM to store the PHY firmware. As
3751 * a result, a RESET of the adapter would cause that RAM to lose its
3752 * contents. Thus, loading PHY firmware on such adapters must happen
3753 * after any FW_RESET_CMDs ...
3754 */
t4_load_phy_fw(struct adapter * adap,int win,int (* phy_fw_version)(const u8 *,size_t),const u8 * phy_fw_data,size_t phy_fw_size)3755 int t4_load_phy_fw(struct adapter *adap, int win,
3756 int (*phy_fw_version)(const u8 *, size_t),
3757 const u8 *phy_fw_data, size_t phy_fw_size)
3758 {
3759 int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3760 unsigned long mtype = 0, maddr = 0;
3761 u32 param, val;
3762 int ret;
3763
3764 /* If we have version number support, then check to see if the adapter
3765 * already has up-to-date PHY firmware loaded.
3766 */
3767 if (phy_fw_version) {
3768 new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3769 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3770 if (ret < 0)
3771 return ret;
3772
3773 if (cur_phy_fw_ver >= new_phy_fw_vers) {
3774 CH_WARN(adap, "PHY Firmware already up-to-date, "
3775 "version %#x\n", cur_phy_fw_ver);
3776 return 0;
3777 }
3778 }
3779
3780 /* Ask the firmware where it wants us to copy the PHY firmware image.
3781 * The size of the file requires a special version of the READ command
3782 * which will pass the file size via the values field in PARAMS_CMD and
3783 * retrieve the return value from firmware and place it in the same
3784 * buffer values
3785 */
3786 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3787 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3788 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3789 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3790 val = phy_fw_size;
3791 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3792 ¶m, &val, 1, true);
3793 if (ret < 0)
3794 return ret;
3795 mtype = val >> 8;
3796 maddr = (val & 0xff) << 16;
3797
3798 /* Copy the supplied PHY Firmware image to the adapter memory location
3799 * allocated by the adapter firmware.
3800 */
3801 spin_lock_bh(&adap->win0_lock);
3802 ret = t4_memory_rw(adap, win, mtype, maddr,
3803 phy_fw_size, (__be32 *)phy_fw_data,
3804 T4_MEMORY_WRITE);
3805 spin_unlock_bh(&adap->win0_lock);
3806 if (ret)
3807 return ret;
3808
3809 /* Tell the firmware that the PHY firmware image has been written to
3810 * RAM and it can now start copying it over to the PHYs. The chip
3811 * firmware will RESET the affected PHYs as part of this operation
3812 * leaving them running the new PHY firmware image.
3813 */
3814 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3815 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3816 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3817 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3818 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3819 ¶m, &val, 30000);
3820 if (ret)
3821 return ret;
3822
3823 /* If we have version number support, then check to see that the new
3824 * firmware got loaded properly.
3825 */
3826 if (phy_fw_version) {
3827 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3828 if (ret < 0)
3829 return ret;
3830
3831 if (cur_phy_fw_ver != new_phy_fw_vers) {
3832 CH_WARN(adap, "PHY Firmware did not update: "
3833 "version on adapter %#x, "
3834 "version flashed %#x\n",
3835 cur_phy_fw_ver, new_phy_fw_vers);
3836 return -ENXIO;
3837 }
3838 }
3839
3840 return 1;
3841 }
3842
3843 /**
3844 * t4_fwcache - firmware cache operation
3845 * @adap: the adapter
3846 * @op : the operation (flush or flush and invalidate)
3847 */
t4_fwcache(struct adapter * adap,enum fw_params_param_dev_fwcache op)3848 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3849 {
3850 struct fw_params_cmd c;
3851
3852 memset(&c, 0, sizeof(c));
3853 c.op_to_vfn =
3854 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3855 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3856 FW_PARAMS_CMD_PFN_V(adap->pf) |
3857 FW_PARAMS_CMD_VFN_V(0));
3858 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3859 c.param[0].mnem =
3860 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3861 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3862 c.param[0].val = cpu_to_be32(op);
3863
3864 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3865 }
3866
t4_cim_read_pif_la(struct adapter * adap,u32 * pif_req,u32 * pif_rsp,unsigned int * pif_req_wrptr,unsigned int * pif_rsp_wrptr)3867 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3868 unsigned int *pif_req_wrptr,
3869 unsigned int *pif_rsp_wrptr)
3870 {
3871 int i, j;
3872 u32 cfg, val, req, rsp;
3873
3874 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3875 if (cfg & LADBGEN_F)
3876 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3877
3878 val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3879 req = POLADBGWRPTR_G(val);
3880 rsp = PILADBGWRPTR_G(val);
3881 if (pif_req_wrptr)
3882 *pif_req_wrptr = req;
3883 if (pif_rsp_wrptr)
3884 *pif_rsp_wrptr = rsp;
3885
3886 for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3887 for (j = 0; j < 6; j++) {
3888 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3889 PILADBGRDPTR_V(rsp));
3890 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3891 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3892 req++;
3893 rsp++;
3894 }
3895 req = (req + 2) & POLADBGRDPTR_M;
3896 rsp = (rsp + 2) & PILADBGRDPTR_M;
3897 }
3898 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3899 }
3900
t4_cim_read_ma_la(struct adapter * adap,u32 * ma_req,u32 * ma_rsp)3901 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3902 {
3903 u32 cfg;
3904 int i, j, idx;
3905
3906 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3907 if (cfg & LADBGEN_F)
3908 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3909
3910 for (i = 0; i < CIM_MALA_SIZE; i++) {
3911 for (j = 0; j < 5; j++) {
3912 idx = 8 * i + j;
3913 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3914 PILADBGRDPTR_V(idx));
3915 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3916 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3917 }
3918 }
3919 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3920 }
3921
t4_ulprx_read_la(struct adapter * adap,u32 * la_buf)3922 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3923 {
3924 unsigned int i, j;
3925
3926 for (i = 0; i < 8; i++) {
3927 u32 *p = la_buf + i;
3928
3929 t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3930 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3931 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3932 for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3933 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3934 }
3935 }
3936
3937 /* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
3938 * Capabilities which we control with separate controls -- see, for instance,
3939 * Pause Frames and Forward Error Correction. In order to determine what the
3940 * full set of Advertised Port Capabilities are, the base Advertised Port
3941 * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
3942 * Port Capabilities associated with those other controls. See
3943 * t4_link_acaps() for how this is done.
3944 */
3945 #define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3946 FW_PORT_CAP32_ANEG)
3947
3948 /**
3949 * fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3950 * @caps16: a 16-bit Port Capabilities value
3951 *
3952 * Returns the equivalent 32-bit Port Capabilities value.
3953 */
fwcaps16_to_caps32(fw_port_cap16_t caps16)3954 static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3955 {
3956 fw_port_cap32_t caps32 = 0;
3957
3958 #define CAP16_TO_CAP32(__cap) \
3959 do { \
3960 if (caps16 & FW_PORT_CAP_##__cap) \
3961 caps32 |= FW_PORT_CAP32_##__cap; \
3962 } while (0)
3963
3964 CAP16_TO_CAP32(SPEED_100M);
3965 CAP16_TO_CAP32(SPEED_1G);
3966 CAP16_TO_CAP32(SPEED_25G);
3967 CAP16_TO_CAP32(SPEED_10G);
3968 CAP16_TO_CAP32(SPEED_40G);
3969 CAP16_TO_CAP32(SPEED_100G);
3970 CAP16_TO_CAP32(FC_RX);
3971 CAP16_TO_CAP32(FC_TX);
3972 CAP16_TO_CAP32(ANEG);
3973 CAP16_TO_CAP32(FORCE_PAUSE);
3974 CAP16_TO_CAP32(MDIAUTO);
3975 CAP16_TO_CAP32(MDISTRAIGHT);
3976 CAP16_TO_CAP32(FEC_RS);
3977 CAP16_TO_CAP32(FEC_BASER_RS);
3978 CAP16_TO_CAP32(802_3_PAUSE);
3979 CAP16_TO_CAP32(802_3_ASM_DIR);
3980
3981 #undef CAP16_TO_CAP32
3982
3983 return caps32;
3984 }
3985
3986 /**
3987 * fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
3988 * @caps32: a 32-bit Port Capabilities value
3989 *
3990 * Returns the equivalent 16-bit Port Capabilities value. Note that
3991 * not all 32-bit Port Capabilities can be represented in the 16-bit
3992 * Port Capabilities and some fields/values may not make it.
3993 */
fwcaps32_to_caps16(fw_port_cap32_t caps32)3994 static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
3995 {
3996 fw_port_cap16_t caps16 = 0;
3997
3998 #define CAP32_TO_CAP16(__cap) \
3999 do { \
4000 if (caps32 & FW_PORT_CAP32_##__cap) \
4001 caps16 |= FW_PORT_CAP_##__cap; \
4002 } while (0)
4003
4004 CAP32_TO_CAP16(SPEED_100M);
4005 CAP32_TO_CAP16(SPEED_1G);
4006 CAP32_TO_CAP16(SPEED_10G);
4007 CAP32_TO_CAP16(SPEED_25G);
4008 CAP32_TO_CAP16(SPEED_40G);
4009 CAP32_TO_CAP16(SPEED_100G);
4010 CAP32_TO_CAP16(FC_RX);
4011 CAP32_TO_CAP16(FC_TX);
4012 CAP32_TO_CAP16(802_3_PAUSE);
4013 CAP32_TO_CAP16(802_3_ASM_DIR);
4014 CAP32_TO_CAP16(ANEG);
4015 CAP32_TO_CAP16(FORCE_PAUSE);
4016 CAP32_TO_CAP16(MDIAUTO);
4017 CAP32_TO_CAP16(MDISTRAIGHT);
4018 CAP32_TO_CAP16(FEC_RS);
4019 CAP32_TO_CAP16(FEC_BASER_RS);
4020
4021 #undef CAP32_TO_CAP16
4022
4023 return caps16;
4024 }
4025
4026 /* Translate Firmware Port Capabilities Pause specification to Common Code */
fwcap_to_cc_pause(fw_port_cap32_t fw_pause)4027 static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
4028 {
4029 enum cc_pause cc_pause = 0;
4030
4031 if (fw_pause & FW_PORT_CAP32_FC_RX)
4032 cc_pause |= PAUSE_RX;
4033 if (fw_pause & FW_PORT_CAP32_FC_TX)
4034 cc_pause |= PAUSE_TX;
4035
4036 return cc_pause;
4037 }
4038
4039 /* Translate Common Code Pause specification into Firmware Port Capabilities */
cc_to_fwcap_pause(enum cc_pause cc_pause)4040 static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
4041 {
4042 /* Translate orthogonal RX/TX Pause Controls for L1 Configure
4043 * commands, etc.
4044 */
4045 fw_port_cap32_t fw_pause = 0;
4046
4047 if (cc_pause & PAUSE_RX)
4048 fw_pause |= FW_PORT_CAP32_FC_RX;
4049 if (cc_pause & PAUSE_TX)
4050 fw_pause |= FW_PORT_CAP32_FC_TX;
4051 if (!(cc_pause & PAUSE_AUTONEG))
4052 fw_pause |= FW_PORT_CAP32_FORCE_PAUSE;
4053
4054 /* Translate orthogonal Pause controls into IEEE 802.3 Pause,
4055 * Asymmetrical Pause for use in reporting to upper layer OS code, etc.
4056 * Note that these bits are ignored in L1 Configure commands.
4057 */
4058 if (cc_pause & PAUSE_RX) {
4059 if (cc_pause & PAUSE_TX)
4060 fw_pause |= FW_PORT_CAP32_802_3_PAUSE;
4061 else
4062 fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR |
4063 FW_PORT_CAP32_802_3_PAUSE;
4064 } else if (cc_pause & PAUSE_TX) {
4065 fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR;
4066 }
4067
4068 return fw_pause;
4069 }
4070
4071 /* Translate Firmware Forward Error Correction specification to Common Code */
fwcap_to_cc_fec(fw_port_cap32_t fw_fec)4072 static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
4073 {
4074 enum cc_fec cc_fec = 0;
4075
4076 if (fw_fec & FW_PORT_CAP32_FEC_RS)
4077 cc_fec |= FEC_RS;
4078 if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
4079 cc_fec |= FEC_BASER_RS;
4080
4081 return cc_fec;
4082 }
4083
4084 /* Translate Common Code Forward Error Correction specification to Firmware */
cc_to_fwcap_fec(enum cc_fec cc_fec)4085 static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
4086 {
4087 fw_port_cap32_t fw_fec = 0;
4088
4089 if (cc_fec & FEC_RS)
4090 fw_fec |= FW_PORT_CAP32_FEC_RS;
4091 if (cc_fec & FEC_BASER_RS)
4092 fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
4093
4094 return fw_fec;
4095 }
4096
4097 /**
4098 * t4_link_acaps - compute Link Advertised Port Capabilities
4099 * @adapter: the adapter
4100 * @port: the Port ID
4101 * @lc: the Port's Link Configuration
4102 *
4103 * Synthesize the Advertised Port Capabilities we'll be using based on
4104 * the base Advertised Port Capabilities (which have been filtered by
4105 * ADVERT_MASK) plus the individual controls for things like Pause
4106 * Frames, Forward Error Correction, MDI, etc.
4107 */
t4_link_acaps(struct adapter * adapter,unsigned int port,struct link_config * lc)4108 fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
4109 struct link_config *lc)
4110 {
4111 fw_port_cap32_t fw_fc, fw_fec, acaps;
4112 unsigned int fw_mdi;
4113 char cc_fec;
4114
4115 fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps);
4116
4117 /* Convert driver coding of Pause Frame Flow Control settings into the
4118 * Firmware's API.
4119 */
4120 fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4121
4122 /* Convert Common Code Forward Error Control settings into the
4123 * Firmware's API. If the current Requested FEC has "Automatic"
4124 * (IEEE 802.3) specified, then we use whatever the Firmware
4125 * sent us as part of its IEEE 802.3-based interpretation of
4126 * the Transceiver Module EPROM FEC parameters. Otherwise we
4127 * use whatever is in the current Requested FEC settings.
4128 */
4129 if (lc->requested_fec & FEC_AUTO)
4130 cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4131 else
4132 cc_fec = lc->requested_fec;
4133 fw_fec = cc_to_fwcap_fec(cc_fec);
4134
4135 /* Figure out what our Requested Port Capabilities are going to be.
4136 * Note parallel structure in t4_handle_get_port_info() and
4137 * init_link_config().
4138 */
4139 if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4140 acaps = lc->acaps | fw_fc | fw_fec;
4141 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4142 lc->fec = cc_fec;
4143 } else if (lc->autoneg == AUTONEG_DISABLE) {
4144 acaps = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4145 lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4146 lc->fec = cc_fec;
4147 } else {
4148 acaps = lc->acaps | fw_fc | fw_fec | fw_mdi;
4149 }
4150
4151 /* Some Requested Port Capabilities are trivially wrong if they exceed
4152 * the Physical Port Capabilities. We can check that here and provide
4153 * moderately useful feedback in the system log.
4154 *
4155 * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4156 * we need to exclude this from this check in order to maintain
4157 * compatibility ...
4158 */
4159 if ((acaps & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) {
4160 dev_err(adapter->pdev_dev, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4161 acaps, lc->pcaps);
4162 return -EINVAL;
4163 }
4164
4165 return acaps;
4166 }
4167
4168 /**
4169 * t4_link_l1cfg_core - apply link configuration to MAC/PHY
4170 * @adapter: the adapter
4171 * @mbox: the Firmware Mailbox to use
4172 * @port: the Port ID
4173 * @lc: the Port's Link Configuration
4174 * @sleep_ok: if true we may sleep while awaiting command completion
4175 * @timeout: time to wait for command to finish before timing out
4176 * (negative implies @sleep_ok=false)
4177 *
4178 * Set up a port's MAC and PHY according to a desired link configuration.
4179 * - If the PHY can auto-negotiate first decide what to advertise, then
4180 * enable/disable auto-negotiation as desired, and reset.
4181 * - If the PHY does not auto-negotiate just reset it.
4182 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4183 * otherwise do it later based on the outcome of auto-negotiation.
4184 */
t4_link_l1cfg_core(struct adapter * adapter,unsigned int mbox,unsigned int port,struct link_config * lc,u8 sleep_ok,int timeout)4185 int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
4186 unsigned int port, struct link_config *lc,
4187 u8 sleep_ok, int timeout)
4188 {
4189 unsigned int fw_caps = adapter->params.fw_caps_support;
4190 struct fw_port_cmd cmd;
4191 fw_port_cap32_t rcap;
4192 int ret;
4193
4194 if (!(lc->pcaps & FW_PORT_CAP32_ANEG) &&
4195 lc->autoneg == AUTONEG_ENABLE) {
4196 return -EINVAL;
4197 }
4198
4199 /* Compute our Requested Port Capabilities and send that on to the
4200 * Firmware.
4201 */
4202 rcap = t4_link_acaps(adapter, port, lc);
4203 memset(&cmd, 0, sizeof(cmd));
4204 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4205 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4206 FW_PORT_CMD_PORTID_V(port));
4207 cmd.action_to_len16 =
4208 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4209 ? FW_PORT_ACTION_L1_CFG
4210 : FW_PORT_ACTION_L1_CFG32) |
4211 FW_LEN16(cmd));
4212 if (fw_caps == FW_CAPS16)
4213 cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4214 else
4215 cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4216
4217 ret = t4_wr_mbox_meat_timeout(adapter, mbox, &cmd, sizeof(cmd), NULL,
4218 sleep_ok, timeout);
4219
4220 /* Unfortunately, even if the Requested Port Capabilities "fit" within
4221 * the Physical Port Capabilities, some combinations of features may
4222 * still not be legal. For example, 40Gb/s and Reed-Solomon Forward
4223 * Error Correction. So if the Firmware rejects the L1 Configure
4224 * request, flag that here.
4225 */
4226 if (ret) {
4227 dev_err(adapter->pdev_dev,
4228 "Requested Port Capabilities %#x rejected, error %d\n",
4229 rcap, -ret);
4230 return ret;
4231 }
4232 return 0;
4233 }
4234
4235 /**
4236 * t4_restart_aneg - restart autonegotiation
4237 * @adap: the adapter
4238 * @mbox: mbox to use for the FW command
4239 * @port: the port id
4240 *
4241 * Restarts autonegotiation for the selected port.
4242 */
t4_restart_aneg(struct adapter * adap,unsigned int mbox,unsigned int port)4243 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4244 {
4245 unsigned int fw_caps = adap->params.fw_caps_support;
4246 struct fw_port_cmd c;
4247
4248 memset(&c, 0, sizeof(c));
4249 c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4250 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4251 FW_PORT_CMD_PORTID_V(port));
4252 c.action_to_len16 =
4253 cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4254 ? FW_PORT_ACTION_L1_CFG
4255 : FW_PORT_ACTION_L1_CFG32) |
4256 FW_LEN16(c));
4257 if (fw_caps == FW_CAPS16)
4258 c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4259 else
4260 c.u.l1cfg32.rcap32 = cpu_to_be32(FW_PORT_CAP32_ANEG);
4261 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4262 }
4263
4264 typedef void (*int_handler_t)(struct adapter *adap);
4265
4266 struct intr_info {
4267 unsigned int mask; /* bits to check in interrupt status */
4268 const char *msg; /* message to print or NULL */
4269 short stat_idx; /* stat counter to increment or -1 */
4270 unsigned short fatal; /* whether the condition reported is fatal */
4271 int_handler_t int_handler; /* platform-specific int handler */
4272 };
4273
4274 /**
4275 * t4_handle_intr_status - table driven interrupt handler
4276 * @adapter: the adapter that generated the interrupt
4277 * @reg: the interrupt status register to process
4278 * @acts: table of interrupt actions
4279 *
4280 * A table driven interrupt handler that applies a set of masks to an
4281 * interrupt status word and performs the corresponding actions if the
4282 * interrupts described by the mask have occurred. The actions include
4283 * optionally emitting a warning or alert message. The table is terminated
4284 * by an entry specifying mask 0. Returns the number of fatal interrupt
4285 * conditions.
4286 */
t4_handle_intr_status(struct adapter * adapter,unsigned int reg,const struct intr_info * acts)4287 static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4288 const struct intr_info *acts)
4289 {
4290 int fatal = 0;
4291 unsigned int mask = 0;
4292 unsigned int status = t4_read_reg(adapter, reg);
4293
4294 for ( ; acts->mask; ++acts) {
4295 if (!(status & acts->mask))
4296 continue;
4297 if (acts->fatal) {
4298 fatal++;
4299 dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4300 status & acts->mask);
4301 } else if (acts->msg && printk_ratelimit())
4302 dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4303 status & acts->mask);
4304 if (acts->int_handler)
4305 acts->int_handler(adapter);
4306 mask |= acts->mask;
4307 }
4308 status &= mask;
4309 if (status) /* clear processed interrupts */
4310 t4_write_reg(adapter, reg, status);
4311 return fatal;
4312 }
4313
4314 /*
4315 * Interrupt handler for the PCIE module.
4316 */
pcie_intr_handler(struct adapter * adapter)4317 static void pcie_intr_handler(struct adapter *adapter)
4318 {
4319 static const struct intr_info sysbus_intr_info[] = {
4320 { RNPP_F, "RXNP array parity error", -1, 1 },
4321 { RPCP_F, "RXPC array parity error", -1, 1 },
4322 { RCIP_F, "RXCIF array parity error", -1, 1 },
4323 { RCCP_F, "Rx completions control array parity error", -1, 1 },
4324 { RFTP_F, "RXFT array parity error", -1, 1 },
4325 { 0 }
4326 };
4327 static const struct intr_info pcie_port_intr_info[] = {
4328 { TPCP_F, "TXPC array parity error", -1, 1 },
4329 { TNPP_F, "TXNP array parity error", -1, 1 },
4330 { TFTP_F, "TXFT array parity error", -1, 1 },
4331 { TCAP_F, "TXCA array parity error", -1, 1 },
4332 { TCIP_F, "TXCIF array parity error", -1, 1 },
4333 { RCAP_F, "RXCA array parity error", -1, 1 },
4334 { OTDD_F, "outbound request TLP discarded", -1, 1 },
4335 { RDPE_F, "Rx data parity error", -1, 1 },
4336 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4337 { 0 }
4338 };
4339 static const struct intr_info pcie_intr_info[] = {
4340 { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4341 { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4342 { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4343 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4344 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4345 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4346 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4347 { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4348 { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4349 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4350 { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4351 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4352 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4353 { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4354 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4355 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4356 { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4357 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4358 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4359 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4360 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4361 { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4362 { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4363 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4364 { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4365 { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4366 { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4367 { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4368 { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4369 { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4370 -1, 0 },
4371 { 0 }
4372 };
4373
4374 static struct intr_info t5_pcie_intr_info[] = {
4375 { MSTGRPPERR_F, "Master Response Read Queue parity error",
4376 -1, 1 },
4377 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4378 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4379 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4380 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4381 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4382 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4383 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4384 -1, 1 },
4385 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4386 -1, 1 },
4387 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4388 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4389 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4390 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4391 { DREQWRPERR_F, "PCI DMA channel write request parity error",
4392 -1, 1 },
4393 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4394 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4395 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4396 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4397 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4398 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4399 { FIDPERR_F, "PCI FID parity error", -1, 1 },
4400 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4401 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4402 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4403 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4404 -1, 1 },
4405 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4406 -1, 1 },
4407 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4408 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4409 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4410 { READRSPERR_F, "Outbound read error", -1, 0 },
4411 { 0 }
4412 };
4413
4414 int fat;
4415
4416 if (is_t4(adapter->params.chip))
4417 fat = t4_handle_intr_status(adapter,
4418 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4419 sysbus_intr_info) +
4420 t4_handle_intr_status(adapter,
4421 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4422 pcie_port_intr_info) +
4423 t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4424 pcie_intr_info);
4425 else
4426 fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4427 t5_pcie_intr_info);
4428
4429 if (fat)
4430 t4_fatal_err(adapter);
4431 }
4432
4433 /*
4434 * TP interrupt handler.
4435 */
tp_intr_handler(struct adapter * adapter)4436 static void tp_intr_handler(struct adapter *adapter)
4437 {
4438 static const struct intr_info tp_intr_info[] = {
4439 { 0x3fffffff, "TP parity error", -1, 1 },
4440 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4441 { 0 }
4442 };
4443
4444 if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4445 t4_fatal_err(adapter);
4446 }
4447
4448 /*
4449 * SGE interrupt handler.
4450 */
sge_intr_handler(struct adapter * adapter)4451 static void sge_intr_handler(struct adapter *adapter)
4452 {
4453 u32 v = 0, perr;
4454 u32 err;
4455
4456 static const struct intr_info sge_intr_info[] = {
4457 { ERR_CPL_EXCEED_IQE_SIZE_F,
4458 "SGE received CPL exceeding IQE size", -1, 1 },
4459 { ERR_INVALID_CIDX_INC_F,
4460 "SGE GTS CIDX increment too large", -1, 0 },
4461 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4462 { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4463 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4464 "SGE IQID > 1023 received CPL for FL", -1, 0 },
4465 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4466 0 },
4467 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4468 0 },
4469 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4470 0 },
4471 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4472 0 },
4473 { ERR_ING_CTXT_PRIO_F,
4474 "SGE too many priority ingress contexts", -1, 0 },
4475 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4476 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4477 { 0 }
4478 };
4479
4480 static struct intr_info t4t5_sge_intr_info[] = {
4481 { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4482 { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4483 { ERR_EGR_CTXT_PRIO_F,
4484 "SGE too many priority egress contexts", -1, 0 },
4485 { 0 }
4486 };
4487
4488 perr = t4_read_reg(adapter, SGE_INT_CAUSE1_A);
4489 if (perr) {
4490 v |= perr;
4491 dev_alert(adapter->pdev_dev, "SGE Cause1 Parity Error %#x\n",
4492 perr);
4493 }
4494
4495 perr = t4_read_reg(adapter, SGE_INT_CAUSE2_A);
4496 if (perr) {
4497 v |= perr;
4498 dev_alert(adapter->pdev_dev, "SGE Cause2 Parity Error %#x\n",
4499 perr);
4500 }
4501
4502 if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {
4503 perr = t4_read_reg(adapter, SGE_INT_CAUSE5_A);
4504 /* Parity error (CRC) for err_T_RxCRC is trivial, ignore it */
4505 perr &= ~ERR_T_RXCRC_F;
4506 if (perr) {
4507 v |= perr;
4508 dev_alert(adapter->pdev_dev,
4509 "SGE Cause5 Parity Error %#x\n", perr);
4510 }
4511 }
4512
4513 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4514 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4515 v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4516 t4t5_sge_intr_info);
4517
4518 err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4519 if (err & ERROR_QID_VALID_F) {
4520 dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4521 ERROR_QID_G(err));
4522 if (err & UNCAPTURED_ERROR_F)
4523 dev_err(adapter->pdev_dev,
4524 "SGE UNCAPTURED_ERROR set (clearing)\n");
4525 t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4526 UNCAPTURED_ERROR_F);
4527 }
4528
4529 if (v != 0)
4530 t4_fatal_err(adapter);
4531 }
4532
4533 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4534 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4535 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4536 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4537
4538 /*
4539 * CIM interrupt handler.
4540 */
cim_intr_handler(struct adapter * adapter)4541 static void cim_intr_handler(struct adapter *adapter)
4542 {
4543 static const struct intr_info cim_intr_info[] = {
4544 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4545 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4546 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4547 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4548 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4549 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4550 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4551 { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4552 { 0 }
4553 };
4554 static const struct intr_info cim_upintr_info[] = {
4555 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4556 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4557 { ILLWRINT_F, "CIM illegal write", -1, 1 },
4558 { ILLRDINT_F, "CIM illegal read", -1, 1 },
4559 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4560 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4561 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4562 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4563 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4564 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4565 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4566 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4567 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4568 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4569 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4570 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4571 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4572 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4573 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4574 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4575 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4576 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4577 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4578 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4579 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4580 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4581 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4582 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4583 { 0 }
4584 };
4585
4586 u32 val, fw_err;
4587 int fat;
4588
4589 fw_err = t4_read_reg(adapter, PCIE_FW_A);
4590 if (fw_err & PCIE_FW_ERR_F)
4591 t4_report_fw_error(adapter);
4592
4593 /* When the Firmware detects an internal error which normally
4594 * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4595 * in order to make sure the Host sees the Firmware Crash. So
4596 * if we have a Timer0 interrupt and don't see a Firmware Crash,
4597 * ignore the Timer0 interrupt.
4598 */
4599
4600 val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4601 if (val & TIMER0INT_F)
4602 if (!(fw_err & PCIE_FW_ERR_F) ||
4603 (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4604 t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4605 TIMER0INT_F);
4606
4607 fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4608 cim_intr_info) +
4609 t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4610 cim_upintr_info);
4611 if (fat)
4612 t4_fatal_err(adapter);
4613 }
4614
4615 /*
4616 * ULP RX interrupt handler.
4617 */
ulprx_intr_handler(struct adapter * adapter)4618 static void ulprx_intr_handler(struct adapter *adapter)
4619 {
4620 static const struct intr_info ulprx_intr_info[] = {
4621 { 0x1800000, "ULPRX context error", -1, 1 },
4622 { 0x7fffff, "ULPRX parity error", -1, 1 },
4623 { 0 }
4624 };
4625
4626 if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4627 t4_fatal_err(adapter);
4628 }
4629
4630 /*
4631 * ULP TX interrupt handler.
4632 */
ulptx_intr_handler(struct adapter * adapter)4633 static void ulptx_intr_handler(struct adapter *adapter)
4634 {
4635 static const struct intr_info ulptx_intr_info[] = {
4636 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4637 0 },
4638 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4639 0 },
4640 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4641 0 },
4642 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4643 0 },
4644 { 0xfffffff, "ULPTX parity error", -1, 1 },
4645 { 0 }
4646 };
4647
4648 if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4649 t4_fatal_err(adapter);
4650 }
4651
4652 /*
4653 * PM TX interrupt handler.
4654 */
pmtx_intr_handler(struct adapter * adapter)4655 static void pmtx_intr_handler(struct adapter *adapter)
4656 {
4657 static const struct intr_info pmtx_intr_info[] = {
4658 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
4659 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
4660 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
4661 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
4662 { PMTX_FRAMING_ERROR_F, "PMTX framing error", -1, 1 },
4663 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
4664 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error",
4665 -1, 1 },
4666 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
4667 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
4668 { 0 }
4669 };
4670
4671 if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE_A, pmtx_intr_info))
4672 t4_fatal_err(adapter);
4673 }
4674
4675 /*
4676 * PM RX interrupt handler.
4677 */
pmrx_intr_handler(struct adapter * adapter)4678 static void pmrx_intr_handler(struct adapter *adapter)
4679 {
4680 static const struct intr_info pmrx_intr_info[] = {
4681 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
4682 { PMRX_FRAMING_ERROR_F, "PMRX framing error", -1, 1 },
4683 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
4684 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error",
4685 -1, 1 },
4686 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
4687 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
4688 { 0 }
4689 };
4690
4691 if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE_A, pmrx_intr_info))
4692 t4_fatal_err(adapter);
4693 }
4694
4695 /*
4696 * CPL switch interrupt handler.
4697 */
cplsw_intr_handler(struct adapter * adapter)4698 static void cplsw_intr_handler(struct adapter *adapter)
4699 {
4700 static const struct intr_info cplsw_intr_info[] = {
4701 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
4702 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
4703 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
4704 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
4705 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
4706 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
4707 { 0 }
4708 };
4709
4710 if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE_A, cplsw_intr_info))
4711 t4_fatal_err(adapter);
4712 }
4713
4714 /*
4715 * LE interrupt handler.
4716 */
le_intr_handler(struct adapter * adap)4717 static void le_intr_handler(struct adapter *adap)
4718 {
4719 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip);
4720 static const struct intr_info le_intr_info[] = {
4721 { LIPMISS_F, "LE LIP miss", -1, 0 },
4722 { LIP0_F, "LE 0 LIP error", -1, 0 },
4723 { PARITYERR_F, "LE parity error", -1, 1 },
4724 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4725 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
4726 { 0 }
4727 };
4728
4729 static struct intr_info t6_le_intr_info[] = {
4730 { T6_LIPMISS_F, "LE LIP miss", -1, 0 },
4731 { T6_LIP0_F, "LE 0 LIP error", -1, 0 },
4732 { CMDTIDERR_F, "LE cmd tid error", -1, 1 },
4733 { TCAMINTPERR_F, "LE parity error", -1, 1 },
4734 { T6_UNKNOWNCMD_F, "LE unknown command", -1, 1 },
4735 { SSRAMINTPERR_F, "LE request queue parity error", -1, 1 },
4736 { HASHTBLMEMCRCERR_F, "LE hash table mem crc error", -1, 0 },
4737 { 0 }
4738 };
4739
4740 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A,
4741 (chip <= CHELSIO_T5) ?
4742 le_intr_info : t6_le_intr_info))
4743 t4_fatal_err(adap);
4744 }
4745
4746 /*
4747 * MPS interrupt handler.
4748 */
mps_intr_handler(struct adapter * adapter)4749 static void mps_intr_handler(struct adapter *adapter)
4750 {
4751 static const struct intr_info mps_rx_intr_info[] = {
4752 { 0xffffff, "MPS Rx parity error", -1, 1 },
4753 { 0 }
4754 };
4755 static const struct intr_info mps_tx_intr_info[] = {
4756 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4757 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4758 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4759 -1, 1 },
4760 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4761 -1, 1 },
4762 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
4763 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4764 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4765 { 0 }
4766 };
4767 static const struct intr_info t6_mps_tx_intr_info[] = {
4768 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
4769 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
4770 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
4771 -1, 1 },
4772 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
4773 -1, 1 },
4774 /* MPS Tx Bubble is normal for T6 */
4775 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
4776 { FRMERR_F, "MPS Tx framing error", -1, 1 },
4777 { 0 }
4778 };
4779 static const struct intr_info mps_trc_intr_info[] = {
4780 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
4781 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
4782 -1, 1 },
4783 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
4784 { 0 }
4785 };
4786 static const struct intr_info mps_stat_sram_intr_info[] = {
4787 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
4788 { 0 }
4789 };
4790 static const struct intr_info mps_stat_tx_intr_info[] = {
4791 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
4792 { 0 }
4793 };
4794 static const struct intr_info mps_stat_rx_intr_info[] = {
4795 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
4796 { 0 }
4797 };
4798 static const struct intr_info mps_cls_intr_info[] = {
4799 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
4800 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
4801 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
4802 { 0 }
4803 };
4804
4805 int fat;
4806
4807 fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE_A,
4808 mps_rx_intr_info) +
4809 t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE_A,
4810 is_t6(adapter->params.chip)
4811 ? t6_mps_tx_intr_info
4812 : mps_tx_intr_info) +
4813 t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE_A,
4814 mps_trc_intr_info) +
4815 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
4816 mps_stat_sram_intr_info) +
4817 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
4818 mps_stat_tx_intr_info) +
4819 t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
4820 mps_stat_rx_intr_info) +
4821 t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE_A,
4822 mps_cls_intr_info);
4823
4824 t4_write_reg(adapter, MPS_INT_CAUSE_A, 0);
4825 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */
4826 if (fat)
4827 t4_fatal_err(adapter);
4828 }
4829
4830 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
4831 ECC_UE_INT_CAUSE_F)
4832
4833 /*
4834 * EDC/MC interrupt handler.
4835 */
mem_intr_handler(struct adapter * adapter,int idx)4836 static void mem_intr_handler(struct adapter *adapter, int idx)
4837 {
4838 static const char name[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
4839
4840 unsigned int addr, cnt_addr, v;
4841
4842 if (idx <= MEM_EDC1) {
4843 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
4844 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
4845 } else if (idx == MEM_MC) {
4846 if (is_t4(adapter->params.chip)) {
4847 addr = MC_INT_CAUSE_A;
4848 cnt_addr = MC_ECC_STATUS_A;
4849 } else {
4850 addr = MC_P_INT_CAUSE_A;
4851 cnt_addr = MC_P_ECC_STATUS_A;
4852 }
4853 } else {
4854 addr = MC_REG(MC_P_INT_CAUSE_A, 1);
4855 cnt_addr = MC_REG(MC_P_ECC_STATUS_A, 1);
4856 }
4857
4858 v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
4859 if (v & PERR_INT_CAUSE_F)
4860 dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
4861 name[idx]);
4862 if (v & ECC_CE_INT_CAUSE_F) {
4863 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr));
4864
4865 t4_edc_err_read(adapter, idx);
4866
4867 t4_write_reg(adapter, cnt_addr, ECC_CECNT_V(ECC_CECNT_M));
4868 if (printk_ratelimit())
4869 dev_warn(adapter->pdev_dev,
4870 "%u %s correctable ECC data error%s\n",
4871 cnt, name[idx], str_plural(cnt));
4872 }
4873 if (v & ECC_UE_INT_CAUSE_F)
4874 dev_alert(adapter->pdev_dev,
4875 "%s uncorrectable ECC data error\n", name[idx]);
4876
4877 t4_write_reg(adapter, addr, v);
4878 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
4879 t4_fatal_err(adapter);
4880 }
4881
4882 /*
4883 * MA interrupt handler.
4884 */
ma_intr_handler(struct adapter * adap)4885 static void ma_intr_handler(struct adapter *adap)
4886 {
4887 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A);
4888
4889 if (status & MEM_PERR_INT_CAUSE_F) {
4890 dev_alert(adap->pdev_dev,
4891 "MA parity error, parity status %#x\n",
4892 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A));
4893 if (is_t5(adap->params.chip))
4894 dev_alert(adap->pdev_dev,
4895 "MA parity error, parity status %#x\n",
4896 t4_read_reg(adap,
4897 MA_PARITY_ERROR_STATUS2_A));
4898 }
4899 if (status & MEM_WRAP_INT_CAUSE_F) {
4900 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A);
4901 dev_alert(adap->pdev_dev, "MA address wrap-around error by "
4902 "client %u to address %#x\n",
4903 MEM_WRAP_CLIENT_NUM_G(v),
4904 MEM_WRAP_ADDRESS_G(v) << 4);
4905 }
4906 t4_write_reg(adap, MA_INT_CAUSE_A, status);
4907 t4_fatal_err(adap);
4908 }
4909
4910 /*
4911 * SMB interrupt handler.
4912 */
smb_intr_handler(struct adapter * adap)4913 static void smb_intr_handler(struct adapter *adap)
4914 {
4915 static const struct intr_info smb_intr_info[] = {
4916 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
4917 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
4918 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
4919 { 0 }
4920 };
4921
4922 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info))
4923 t4_fatal_err(adap);
4924 }
4925
4926 /*
4927 * NC-SI interrupt handler.
4928 */
ncsi_intr_handler(struct adapter * adap)4929 static void ncsi_intr_handler(struct adapter *adap)
4930 {
4931 static const struct intr_info ncsi_intr_info[] = {
4932 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
4933 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
4934 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
4935 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
4936 { 0 }
4937 };
4938
4939 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info))
4940 t4_fatal_err(adap);
4941 }
4942
4943 /*
4944 * XGMAC interrupt handler.
4945 */
xgmac_intr_handler(struct adapter * adap,int port)4946 static void xgmac_intr_handler(struct adapter *adap, int port)
4947 {
4948 u32 v, int_cause_reg;
4949
4950 if (is_t4(adap->params.chip))
4951 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE_A);
4952 else
4953 int_cause_reg = T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A);
4954
4955 v = t4_read_reg(adap, int_cause_reg);
4956
4957 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
4958 if (!v)
4959 return;
4960
4961 if (v & TXFIFO_PRTY_ERR_F)
4962 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
4963 port);
4964 if (v & RXFIFO_PRTY_ERR_F)
4965 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
4966 port);
4967 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v);
4968 t4_fatal_err(adap);
4969 }
4970
4971 /*
4972 * PL interrupt handler.
4973 */
pl_intr_handler(struct adapter * adap)4974 static void pl_intr_handler(struct adapter *adap)
4975 {
4976 static const struct intr_info pl_intr_info[] = {
4977 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
4978 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
4979 { 0 }
4980 };
4981
4982 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info))
4983 t4_fatal_err(adap);
4984 }
4985
4986 #define PF_INTR_MASK (PFSW_F)
4987 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
4988 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
4989 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
4990
4991 /**
4992 * t4_slow_intr_handler - control path interrupt handler
4993 * @adapter: the adapter
4994 *
4995 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
4996 * The designation 'slow' is because it involves register reads, while
4997 * data interrupts typically don't involve any MMIOs.
4998 */
t4_slow_intr_handler(struct adapter * adapter)4999 int t4_slow_intr_handler(struct adapter *adapter)
5000 {
5001 /* There are rare cases where a PL_INT_CAUSE bit may end up getting
5002 * set when the corresponding PL_INT_ENABLE bit isn't set. It's
5003 * easiest just to mask that case here.
5004 */
5005 u32 raw_cause = t4_read_reg(adapter, PL_INT_CAUSE_A);
5006 u32 enable = t4_read_reg(adapter, PL_INT_ENABLE_A);
5007 u32 cause = raw_cause & enable;
5008
5009 if (!(cause & GLBL_INTR_MASK))
5010 return 0;
5011 if (cause & CIM_F)
5012 cim_intr_handler(adapter);
5013 if (cause & MPS_F)
5014 mps_intr_handler(adapter);
5015 if (cause & NCSI_F)
5016 ncsi_intr_handler(adapter);
5017 if (cause & PL_F)
5018 pl_intr_handler(adapter);
5019 if (cause & SMB_F)
5020 smb_intr_handler(adapter);
5021 if (cause & XGMAC0_F)
5022 xgmac_intr_handler(adapter, 0);
5023 if (cause & XGMAC1_F)
5024 xgmac_intr_handler(adapter, 1);
5025 if (cause & XGMAC_KR0_F)
5026 xgmac_intr_handler(adapter, 2);
5027 if (cause & XGMAC_KR1_F)
5028 xgmac_intr_handler(adapter, 3);
5029 if (cause & PCIE_F)
5030 pcie_intr_handler(adapter);
5031 if (cause & MC_F)
5032 mem_intr_handler(adapter, MEM_MC);
5033 if (is_t5(adapter->params.chip) && (cause & MC1_F))
5034 mem_intr_handler(adapter, MEM_MC1);
5035 if (cause & EDC0_F)
5036 mem_intr_handler(adapter, MEM_EDC0);
5037 if (cause & EDC1_F)
5038 mem_intr_handler(adapter, MEM_EDC1);
5039 if (cause & LE_F)
5040 le_intr_handler(adapter);
5041 if (cause & TP_F)
5042 tp_intr_handler(adapter);
5043 if (cause & MA_F)
5044 ma_intr_handler(adapter);
5045 if (cause & PM_TX_F)
5046 pmtx_intr_handler(adapter);
5047 if (cause & PM_RX_F)
5048 pmrx_intr_handler(adapter);
5049 if (cause & ULP_RX_F)
5050 ulprx_intr_handler(adapter);
5051 if (cause & CPL_SWITCH_F)
5052 cplsw_intr_handler(adapter);
5053 if (cause & SGE_F)
5054 sge_intr_handler(adapter);
5055 if (cause & ULP_TX_F)
5056 ulptx_intr_handler(adapter);
5057
5058 /* Clear the interrupts just processed for which we are the master. */
5059 t4_write_reg(adapter, PL_INT_CAUSE_A, raw_cause & GLBL_INTR_MASK);
5060 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */
5061 return 1;
5062 }
5063
5064 /**
5065 * t4_intr_enable - enable interrupts
5066 * @adapter: the adapter whose interrupts should be enabled
5067 *
5068 * Enable PF-specific interrupts for the calling function and the top-level
5069 * interrupt concentrator for global interrupts. Interrupts are already
5070 * enabled at each module, here we just enable the roots of the interrupt
5071 * hierarchies.
5072 *
5073 * Note: this function should be called only when the driver manages
5074 * non PF-specific interrupts from the various HW modules. Only one PCI
5075 * function at a time should be doing this.
5076 */
t4_intr_enable(struct adapter * adapter)5077 void t4_intr_enable(struct adapter *adapter)
5078 {
5079 u32 val = 0;
5080 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5081 u32 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5082 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5083
5084 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
5085 val = ERR_DROPPED_DB_F | ERR_EGR_CTXT_PRIO_F | DBFIFO_HP_INT_F;
5086 t4_write_reg(adapter, SGE_INT_ENABLE3_A, ERR_CPL_EXCEED_IQE_SIZE_F |
5087 ERR_INVALID_CIDX_INC_F | ERR_CPL_OPCODE_0_F |
5088 ERR_DATA_CPL_ON_HIGH_QID1_F | INGRESS_SIZE_ERR_F |
5089 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
5090 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
5091 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
5092 DBFIFO_LP_INT_F | EGRESS_SIZE_ERR_F | val);
5093 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), PF_INTR_MASK);
5094 t4_set_reg_field(adapter, PL_INT_MAP0_A, 0, 1 << pf);
5095 }
5096
5097 /**
5098 * t4_intr_disable - disable interrupts
5099 * @adapter: the adapter whose interrupts should be disabled
5100 *
5101 * Disable interrupts. We only disable the top-level interrupt
5102 * concentrators. The caller must be a PCI function managing global
5103 * interrupts.
5104 */
t4_intr_disable(struct adapter * adapter)5105 void t4_intr_disable(struct adapter *adapter)
5106 {
5107 u32 whoami, pf;
5108
5109 if (pci_channel_offline(adapter->pdev))
5110 return;
5111
5112 whoami = t4_read_reg(adapter, PL_WHOAMI_A);
5113 pf = CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5 ?
5114 SOURCEPF_G(whoami) : T6_SOURCEPF_G(whoami);
5115
5116 t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE_A), 0);
5117 t4_set_reg_field(adapter, PL_INT_MAP0_A, 1 << pf, 0);
5118 }
5119
t4_chip_rss_size(struct adapter * adap)5120 unsigned int t4_chip_rss_size(struct adapter *adap)
5121 {
5122 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
5123 return RSS_NENTRIES;
5124 else
5125 return T6_RSS_NENTRIES;
5126 }
5127
5128 /**
5129 * t4_config_rss_range - configure a portion of the RSS mapping table
5130 * @adapter: the adapter
5131 * @mbox: mbox to use for the FW command
5132 * @viid: virtual interface whose RSS subtable is to be written
5133 * @start: start entry in the table to write
5134 * @n: how many table entries to write
5135 * @rspq: values for the response queue lookup table
5136 * @nrspq: number of values in @rspq
5137 *
5138 * Programs the selected part of the VI's RSS mapping table with the
5139 * provided values. If @nrspq < @n the supplied values are used repeatedly
5140 * until the full table range is populated.
5141 *
5142 * The caller must ensure the values in @rspq are in the range allowed for
5143 * @viid.
5144 */
t4_config_rss_range(struct adapter * adapter,int mbox,unsigned int viid,int start,int n,const u16 * rspq,unsigned int nrspq)5145 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
5146 int start, int n, const u16 *rspq, unsigned int nrspq)
5147 {
5148 int ret;
5149 const u16 *rsp = rspq;
5150 const u16 *rsp_end = rspq + nrspq;
5151 struct fw_rss_ind_tbl_cmd cmd;
5152
5153 memset(&cmd, 0, sizeof(cmd));
5154 cmd.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD) |
5155 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5156 FW_RSS_IND_TBL_CMD_VIID_V(viid));
5157 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
5158
5159 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
5160 while (n > 0) {
5161 int nq = min(n, 32);
5162 __be32 *qp = &cmd.iq0_to_iq2;
5163
5164 cmd.niqid = cpu_to_be16(nq);
5165 cmd.startidx = cpu_to_be16(start);
5166
5167 start += nq;
5168 n -= nq;
5169
5170 while (nq > 0) {
5171 unsigned int v;
5172
5173 v = FW_RSS_IND_TBL_CMD_IQ0_V(*rsp);
5174 if (++rsp >= rsp_end)
5175 rsp = rspq;
5176 v |= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp);
5177 if (++rsp >= rsp_end)
5178 rsp = rspq;
5179 v |= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp);
5180 if (++rsp >= rsp_end)
5181 rsp = rspq;
5182
5183 *qp++ = cpu_to_be32(v);
5184 nq -= 3;
5185 }
5186
5187 ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
5188 if (ret)
5189 return ret;
5190 }
5191 return 0;
5192 }
5193
5194 /**
5195 * t4_config_glbl_rss - configure the global RSS mode
5196 * @adapter: the adapter
5197 * @mbox: mbox to use for the FW command
5198 * @mode: global RSS mode
5199 * @flags: mode-specific flags
5200 *
5201 * Sets the global RSS mode.
5202 */
t4_config_glbl_rss(struct adapter * adapter,int mbox,unsigned int mode,unsigned int flags)5203 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
5204 unsigned int flags)
5205 {
5206 struct fw_rss_glb_config_cmd c;
5207
5208 memset(&c, 0, sizeof(c));
5209 c.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD) |
5210 FW_CMD_REQUEST_F | FW_CMD_WRITE_F);
5211 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5212 if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
5213 c.u.manual.mode_pkd =
5214 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5215 } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
5216 c.u.basicvirtual.mode_pkd =
5217 cpu_to_be32(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode));
5218 c.u.basicvirtual.synmapen_to_hashtoeplitz = cpu_to_be32(flags);
5219 } else
5220 return -EINVAL;
5221 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5222 }
5223
5224 /**
5225 * t4_config_vi_rss - configure per VI RSS settings
5226 * @adapter: the adapter
5227 * @mbox: mbox to use for the FW command
5228 * @viid: the VI id
5229 * @flags: RSS flags
5230 * @defq: id of the default RSS queue for the VI.
5231 *
5232 * Configures VI-specific RSS properties.
5233 */
t4_config_vi_rss(struct adapter * adapter,int mbox,unsigned int viid,unsigned int flags,unsigned int defq)5234 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
5235 unsigned int flags, unsigned int defq)
5236 {
5237 struct fw_rss_vi_config_cmd c;
5238
5239 memset(&c, 0, sizeof(c));
5240 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
5241 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
5242 FW_RSS_VI_CONFIG_CMD_VIID_V(viid));
5243 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
5244 c.u.basicvirtual.defaultq_to_udpen = cpu_to_be32(flags |
5245 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(defq));
5246 return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
5247 }
5248
5249 /* Read an RSS table row */
rd_rss_row(struct adapter * adap,int row,u32 * val)5250 static int rd_rss_row(struct adapter *adap, int row, u32 *val)
5251 {
5252 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row);
5253 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1,
5254 5, 0, val);
5255 }
5256
5257 /**
5258 * t4_read_rss - read the contents of the RSS mapping table
5259 * @adapter: the adapter
5260 * @map: holds the contents of the RSS mapping table
5261 *
5262 * Reads the contents of the RSS hash->queue mapping table.
5263 */
t4_read_rss(struct adapter * adapter,u16 * map)5264 int t4_read_rss(struct adapter *adapter, u16 *map)
5265 {
5266 int i, ret, nentries;
5267 u32 val;
5268
5269 nentries = t4_chip_rss_size(adapter);
5270 for (i = 0; i < nentries / 2; ++i) {
5271 ret = rd_rss_row(adapter, i, &val);
5272 if (ret)
5273 return ret;
5274 *map++ = LKPTBLQUEUE0_G(val);
5275 *map++ = LKPTBLQUEUE1_G(val);
5276 }
5277 return 0;
5278 }
5279
t4_use_ldst(struct adapter * adap)5280 static unsigned int t4_use_ldst(struct adapter *adap)
5281 {
5282 return (adap->flags & CXGB4_FW_OK) && !adap->use_bd;
5283 }
5284
5285 /**
5286 * t4_tp_fw_ldst_rw - Access TP indirect register through LDST
5287 * @adap: the adapter
5288 * @cmd: TP fw ldst address space type
5289 * @vals: where the indirect register values are stored/written
5290 * @nregs: how many indirect registers to read/write
5291 * @start_index: index of first indirect register to read/write
5292 * @rw: Read (1) or Write (0)
5293 * @sleep_ok: if true we may sleep while awaiting command completion
5294 *
5295 * Access TP indirect registers through LDST
5296 */
t4_tp_fw_ldst_rw(struct adapter * adap,int cmd,u32 * vals,unsigned int nregs,unsigned int start_index,unsigned int rw,bool sleep_ok)5297 static int t4_tp_fw_ldst_rw(struct adapter *adap, int cmd, u32 *vals,
5298 unsigned int nregs, unsigned int start_index,
5299 unsigned int rw, bool sleep_ok)
5300 {
5301 int ret = 0;
5302 unsigned int i;
5303 struct fw_ldst_cmd c;
5304
5305 for (i = 0; i < nregs; i++) {
5306 memset(&c, 0, sizeof(c));
5307 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
5308 FW_CMD_REQUEST_F |
5309 (rw ? FW_CMD_READ_F :
5310 FW_CMD_WRITE_F) |
5311 FW_LDST_CMD_ADDRSPACE_V(cmd));
5312 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
5313
5314 c.u.addrval.addr = cpu_to_be32(start_index + i);
5315 c.u.addrval.val = rw ? 0 : cpu_to_be32(vals[i]);
5316 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c,
5317 sleep_ok);
5318 if (ret)
5319 return ret;
5320
5321 if (rw)
5322 vals[i] = be32_to_cpu(c.u.addrval.val);
5323 }
5324 return 0;
5325 }
5326
5327 /**
5328 * t4_tp_indirect_rw - Read/Write TP indirect register through LDST or backdoor
5329 * @adap: the adapter
5330 * @reg_addr: Address Register
5331 * @reg_data: Data register
5332 * @buff: where the indirect register values are stored/written
5333 * @nregs: how many indirect registers to read/write
5334 * @start_index: index of first indirect register to read/write
5335 * @rw: READ(1) or WRITE(0)
5336 * @sleep_ok: if true we may sleep while awaiting command completion
5337 *
5338 * Read/Write TP indirect registers through LDST if possible.
5339 * Else, use backdoor access
5340 **/
t4_tp_indirect_rw(struct adapter * adap,u32 reg_addr,u32 reg_data,u32 * buff,u32 nregs,u32 start_index,int rw,bool sleep_ok)5341 static void t4_tp_indirect_rw(struct adapter *adap, u32 reg_addr, u32 reg_data,
5342 u32 *buff, u32 nregs, u32 start_index, int rw,
5343 bool sleep_ok)
5344 {
5345 int rc = -EINVAL;
5346 int cmd;
5347
5348 switch (reg_addr) {
5349 case TP_PIO_ADDR_A:
5350 cmd = FW_LDST_ADDRSPC_TP_PIO;
5351 break;
5352 case TP_TM_PIO_ADDR_A:
5353 cmd = FW_LDST_ADDRSPC_TP_TM_PIO;
5354 break;
5355 case TP_MIB_INDEX_A:
5356 cmd = FW_LDST_ADDRSPC_TP_MIB;
5357 break;
5358 default:
5359 goto indirect_access;
5360 }
5361
5362 if (t4_use_ldst(adap))
5363 rc = t4_tp_fw_ldst_rw(adap, cmd, buff, nregs, start_index, rw,
5364 sleep_ok);
5365
5366 indirect_access:
5367
5368 if (rc) {
5369 if (rw)
5370 t4_read_indirect(adap, reg_addr, reg_data, buff, nregs,
5371 start_index);
5372 else
5373 t4_write_indirect(adap, reg_addr, reg_data, buff, nregs,
5374 start_index);
5375 }
5376 }
5377
5378 /**
5379 * t4_tp_pio_read - Read TP PIO registers
5380 * @adap: the adapter
5381 * @buff: where the indirect register values are written
5382 * @nregs: how many indirect registers to read
5383 * @start_index: index of first indirect register to read
5384 * @sleep_ok: if true we may sleep while awaiting command completion
5385 *
5386 * Read TP PIO Registers
5387 **/
t4_tp_pio_read(struct adapter * adap,u32 * buff,u32 nregs,u32 start_index,bool sleep_ok)5388 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5389 u32 start_index, bool sleep_ok)
5390 {
5391 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5392 start_index, 1, sleep_ok);
5393 }
5394
5395 /**
5396 * t4_tp_pio_write - Write TP PIO registers
5397 * @adap: the adapter
5398 * @buff: where the indirect register values are stored
5399 * @nregs: how many indirect registers to write
5400 * @start_index: index of first indirect register to write
5401 * @sleep_ok: if true we may sleep while awaiting command completion
5402 *
5403 * Write TP PIO Registers
5404 **/
t4_tp_pio_write(struct adapter * adap,u32 * buff,u32 nregs,u32 start_index,bool sleep_ok)5405 static void t4_tp_pio_write(struct adapter *adap, u32 *buff, u32 nregs,
5406 u32 start_index, bool sleep_ok)
5407 {
5408 t4_tp_indirect_rw(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, buff, nregs,
5409 start_index, 0, sleep_ok);
5410 }
5411
5412 /**
5413 * t4_tp_tm_pio_read - Read TP TM PIO registers
5414 * @adap: the adapter
5415 * @buff: where the indirect register values are written
5416 * @nregs: how many indirect registers to read
5417 * @start_index: index of first indirect register to read
5418 * @sleep_ok: if true we may sleep while awaiting command completion
5419 *
5420 * Read TP TM PIO Registers
5421 **/
t4_tp_tm_pio_read(struct adapter * adap,u32 * buff,u32 nregs,u32 start_index,bool sleep_ok)5422 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
5423 u32 start_index, bool sleep_ok)
5424 {
5425 t4_tp_indirect_rw(adap, TP_TM_PIO_ADDR_A, TP_TM_PIO_DATA_A, buff,
5426 nregs, start_index, 1, sleep_ok);
5427 }
5428
5429 /**
5430 * t4_tp_mib_read - Read TP MIB registers
5431 * @adap: the adapter
5432 * @buff: where the indirect register values are written
5433 * @nregs: how many indirect registers to read
5434 * @start_index: index of first indirect register to read
5435 * @sleep_ok: if true we may sleep while awaiting command completion
5436 *
5437 * Read TP MIB Registers
5438 **/
t4_tp_mib_read(struct adapter * adap,u32 * buff,u32 nregs,u32 start_index,bool sleep_ok)5439 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs, u32 start_index,
5440 bool sleep_ok)
5441 {
5442 t4_tp_indirect_rw(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, buff, nregs,
5443 start_index, 1, sleep_ok);
5444 }
5445
5446 /**
5447 * t4_read_rss_key - read the global RSS key
5448 * @adap: the adapter
5449 * @key: 10-entry array holding the 320-bit RSS key
5450 * @sleep_ok: if true we may sleep while awaiting command completion
5451 *
5452 * Reads the global 320-bit RSS key.
5453 */
t4_read_rss_key(struct adapter * adap,u32 * key,bool sleep_ok)5454 void t4_read_rss_key(struct adapter *adap, u32 *key, bool sleep_ok)
5455 {
5456 t4_tp_pio_read(adap, key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5457 }
5458
5459 /**
5460 * t4_write_rss_key - program one of the RSS keys
5461 * @adap: the adapter
5462 * @key: 10-entry array holding the 320-bit RSS key
5463 * @idx: which RSS key to write
5464 * @sleep_ok: if true we may sleep while awaiting command completion
5465 *
5466 * Writes one of the RSS keys with the given 320-bit value. If @idx is
5467 * 0..15 the corresponding entry in the RSS key table is written,
5468 * otherwise the global RSS key is written.
5469 */
t4_write_rss_key(struct adapter * adap,const u32 * key,int idx,bool sleep_ok)5470 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
5471 bool sleep_ok)
5472 {
5473 u8 rss_key_addr_cnt = 16;
5474 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A);
5475
5476 /* T6 and later: for KeyMode 3 (per-vf and per-vf scramble),
5477 * allows access to key addresses 16-63 by using KeyWrAddrX
5478 * as index[5:4](upper 2) into key table
5479 */
5480 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) &&
5481 (vrt & KEYEXTEND_F) && (KEYMODE_G(vrt) == 3))
5482 rss_key_addr_cnt = 32;
5483
5484 t4_tp_pio_write(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, sleep_ok);
5485
5486 if (idx >= 0 && idx < rss_key_addr_cnt) {
5487 if (rss_key_addr_cnt > 16)
5488 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5489 KEYWRADDRX_V(idx >> 4) |
5490 T6_VFWRADDR_V(idx) | KEYWREN_F);
5491 else
5492 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A,
5493 KEYWRADDR_V(idx) | KEYWREN_F);
5494 }
5495 }
5496
5497 /**
5498 * t4_read_rss_pf_config - read PF RSS Configuration Table
5499 * @adapter: the adapter
5500 * @index: the entry in the PF RSS table to read
5501 * @valp: where to store the returned value
5502 * @sleep_ok: if true we may sleep while awaiting command completion
5503 *
5504 * Reads the PF RSS Configuration Table at the specified index and returns
5505 * the value found there.
5506 */
t4_read_rss_pf_config(struct adapter * adapter,unsigned int index,u32 * valp,bool sleep_ok)5507 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
5508 u32 *valp, bool sleep_ok)
5509 {
5510 t4_tp_pio_read(adapter, valp, 1, TP_RSS_PF0_CONFIG_A + index, sleep_ok);
5511 }
5512
5513 /**
5514 * t4_read_rss_vf_config - read VF RSS Configuration Table
5515 * @adapter: the adapter
5516 * @index: the entry in the VF RSS table to read
5517 * @vfl: where to store the returned VFL
5518 * @vfh: where to store the returned VFH
5519 * @sleep_ok: if true we may sleep while awaiting command completion
5520 *
5521 * Reads the VF RSS Configuration Table at the specified index and returns
5522 * the (VFL, VFH) values found there.
5523 */
t4_read_rss_vf_config(struct adapter * adapter,unsigned int index,u32 * vfl,u32 * vfh,bool sleep_ok)5524 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
5525 u32 *vfl, u32 *vfh, bool sleep_ok)
5526 {
5527 u32 vrt, mask, data;
5528
5529 if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5) {
5530 mask = VFWRADDR_V(VFWRADDR_M);
5531 data = VFWRADDR_V(index);
5532 } else {
5533 mask = T6_VFWRADDR_V(T6_VFWRADDR_M);
5534 data = T6_VFWRADDR_V(index);
5535 }
5536
5537 /* Request that the index'th VF Table values be read into VFL/VFH.
5538 */
5539 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A);
5540 vrt &= ~(VFRDRG_F | VFWREN_F | KEYWREN_F | mask);
5541 vrt |= data | VFRDEN_F;
5542 t4_write_reg(adapter, TP_RSS_CONFIG_VRT_A, vrt);
5543
5544 /* Grab the VFL/VFH values ...
5545 */
5546 t4_tp_pio_read(adapter, vfl, 1, TP_RSS_VFL_CONFIG_A, sleep_ok);
5547 t4_tp_pio_read(adapter, vfh, 1, TP_RSS_VFH_CONFIG_A, sleep_ok);
5548 }
5549
5550 /**
5551 * t4_read_rss_pf_map - read PF RSS Map
5552 * @adapter: the adapter
5553 * @sleep_ok: if true we may sleep while awaiting command completion
5554 *
5555 * Reads the PF RSS Map register and returns its value.
5556 */
t4_read_rss_pf_map(struct adapter * adapter,bool sleep_ok)5557 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok)
5558 {
5559 u32 pfmap;
5560
5561 t4_tp_pio_read(adapter, &pfmap, 1, TP_RSS_PF_MAP_A, sleep_ok);
5562 return pfmap;
5563 }
5564
5565 /**
5566 * t4_read_rss_pf_mask - read PF RSS Mask
5567 * @adapter: the adapter
5568 * @sleep_ok: if true we may sleep while awaiting command completion
5569 *
5570 * Reads the PF RSS Mask register and returns its value.
5571 */
t4_read_rss_pf_mask(struct adapter * adapter,bool sleep_ok)5572 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok)
5573 {
5574 u32 pfmask;
5575
5576 t4_tp_pio_read(adapter, &pfmask, 1, TP_RSS_PF_MSK_A, sleep_ok);
5577 return pfmask;
5578 }
5579
5580 /**
5581 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
5582 * @adap: the adapter
5583 * @v4: holds the TCP/IP counter values
5584 * @v6: holds the TCP/IPv6 counter values
5585 * @sleep_ok: if true we may sleep while awaiting command completion
5586 *
5587 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
5588 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
5589 */
t4_tp_get_tcp_stats(struct adapter * adap,struct tp_tcp_stats * v4,struct tp_tcp_stats * v6,bool sleep_ok)5590 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
5591 struct tp_tcp_stats *v6, bool sleep_ok)
5592 {
5593 u32 val[TP_MIB_TCP_RXT_SEG_LO_A - TP_MIB_TCP_OUT_RST_A + 1];
5594
5595 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
5596 #define STAT(x) val[STAT_IDX(x)]
5597 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
5598
5599 if (v4) {
5600 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5601 TP_MIB_TCP_OUT_RST_A, sleep_ok);
5602 v4->tcp_out_rsts = STAT(OUT_RST);
5603 v4->tcp_in_segs = STAT64(IN_SEG);
5604 v4->tcp_out_segs = STAT64(OUT_SEG);
5605 v4->tcp_retrans_segs = STAT64(RXT_SEG);
5606 }
5607 if (v6) {
5608 t4_tp_mib_read(adap, val, ARRAY_SIZE(val),
5609 TP_MIB_TCP_V6OUT_RST_A, sleep_ok);
5610 v6->tcp_out_rsts = STAT(OUT_RST);
5611 v6->tcp_in_segs = STAT64(IN_SEG);
5612 v6->tcp_out_segs = STAT64(OUT_SEG);
5613 v6->tcp_retrans_segs = STAT64(RXT_SEG);
5614 }
5615 #undef STAT64
5616 #undef STAT
5617 #undef STAT_IDX
5618 }
5619
5620 /**
5621 * t4_tp_get_err_stats - read TP's error MIB counters
5622 * @adap: the adapter
5623 * @st: holds the counter values
5624 * @sleep_ok: if true we may sleep while awaiting command completion
5625 *
5626 * Returns the values of TP's error counters.
5627 */
t4_tp_get_err_stats(struct adapter * adap,struct tp_err_stats * st,bool sleep_ok)5628 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
5629 bool sleep_ok)
5630 {
5631 int nchan = adap->params.arch.nchan;
5632
5633 t4_tp_mib_read(adap, st->mac_in_errs, nchan, TP_MIB_MAC_IN_ERR_0_A,
5634 sleep_ok);
5635 t4_tp_mib_read(adap, st->hdr_in_errs, nchan, TP_MIB_HDR_IN_ERR_0_A,
5636 sleep_ok);
5637 t4_tp_mib_read(adap, st->tcp_in_errs, nchan, TP_MIB_TCP_IN_ERR_0_A,
5638 sleep_ok);
5639 t4_tp_mib_read(adap, st->tnl_cong_drops, nchan,
5640 TP_MIB_TNL_CNG_DROP_0_A, sleep_ok);
5641 t4_tp_mib_read(adap, st->ofld_chan_drops, nchan,
5642 TP_MIB_OFD_CHN_DROP_0_A, sleep_ok);
5643 t4_tp_mib_read(adap, st->tnl_tx_drops, nchan, TP_MIB_TNL_DROP_0_A,
5644 sleep_ok);
5645 t4_tp_mib_read(adap, st->ofld_vlan_drops, nchan,
5646 TP_MIB_OFD_VLN_DROP_0_A, sleep_ok);
5647 t4_tp_mib_read(adap, st->tcp6_in_errs, nchan,
5648 TP_MIB_TCP_V6IN_ERR_0_A, sleep_ok);
5649 t4_tp_mib_read(adap, &st->ofld_no_neigh, 2, TP_MIB_OFD_ARP_DROP_A,
5650 sleep_ok);
5651 }
5652
5653 /**
5654 * t4_tp_get_cpl_stats - read TP's CPL MIB counters
5655 * @adap: the adapter
5656 * @st: holds the counter values
5657 * @sleep_ok: if true we may sleep while awaiting command completion
5658 *
5659 * Returns the values of TP's CPL counters.
5660 */
t4_tp_get_cpl_stats(struct adapter * adap,struct tp_cpl_stats * st,bool sleep_ok)5661 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
5662 bool sleep_ok)
5663 {
5664 int nchan = adap->params.arch.nchan;
5665
5666 t4_tp_mib_read(adap, st->req, nchan, TP_MIB_CPL_IN_REQ_0_A, sleep_ok);
5667
5668 t4_tp_mib_read(adap, st->rsp, nchan, TP_MIB_CPL_OUT_RSP_0_A, sleep_ok);
5669 }
5670
5671 /**
5672 * t4_tp_get_rdma_stats - read TP's RDMA MIB counters
5673 * @adap: the adapter
5674 * @st: holds the counter values
5675 * @sleep_ok: if true we may sleep while awaiting command completion
5676 *
5677 * Returns the values of TP's RDMA counters.
5678 */
t4_tp_get_rdma_stats(struct adapter * adap,struct tp_rdma_stats * st,bool sleep_ok)5679 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
5680 bool sleep_ok)
5681 {
5682 t4_tp_mib_read(adap, &st->rqe_dfr_pkt, 2, TP_MIB_RQE_DFR_PKT_A,
5683 sleep_ok);
5684 }
5685
5686 /**
5687 * t4_get_fcoe_stats - read TP's FCoE MIB counters for a port
5688 * @adap: the adapter
5689 * @idx: the port index
5690 * @st: holds the counter values
5691 * @sleep_ok: if true we may sleep while awaiting command completion
5692 *
5693 * Returns the values of TP's FCoE counters for the selected port.
5694 */
t4_get_fcoe_stats(struct adapter * adap,unsigned int idx,struct tp_fcoe_stats * st,bool sleep_ok)5695 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
5696 struct tp_fcoe_stats *st, bool sleep_ok)
5697 {
5698 u32 val[2];
5699
5700 t4_tp_mib_read(adap, &st->frames_ddp, 1, TP_MIB_FCOE_DDP_0_A + idx,
5701 sleep_ok);
5702
5703 t4_tp_mib_read(adap, &st->frames_drop, 1,
5704 TP_MIB_FCOE_DROP_0_A + idx, sleep_ok);
5705
5706 t4_tp_mib_read(adap, val, 2, TP_MIB_FCOE_BYTE_0_HI_A + 2 * idx,
5707 sleep_ok);
5708
5709 st->octets_ddp = ((u64)val[0] << 32) | val[1];
5710 }
5711
5712 /**
5713 * t4_get_usm_stats - read TP's non-TCP DDP MIB counters
5714 * @adap: the adapter
5715 * @st: holds the counter values
5716 * @sleep_ok: if true we may sleep while awaiting command completion
5717 *
5718 * Returns the values of TP's counters for non-TCP directly-placed packets.
5719 */
t4_get_usm_stats(struct adapter * adap,struct tp_usm_stats * st,bool sleep_ok)5720 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
5721 bool sleep_ok)
5722 {
5723 u32 val[4];
5724
5725 t4_tp_mib_read(adap, val, 4, TP_MIB_USM_PKTS_A, sleep_ok);
5726 st->frames = val[0];
5727 st->drops = val[1];
5728 st->octets = ((u64)val[2] << 32) | val[3];
5729 }
5730
5731 /**
5732 * t4_read_mtu_tbl - returns the values in the HW path MTU table
5733 * @adap: the adapter
5734 * @mtus: where to store the MTU values
5735 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
5736 *
5737 * Reads the HW path MTU table.
5738 */
t4_read_mtu_tbl(struct adapter * adap,u16 * mtus,u8 * mtu_log)5739 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
5740 {
5741 u32 v;
5742 int i;
5743
5744 for (i = 0; i < NMTUS; ++i) {
5745 t4_write_reg(adap, TP_MTU_TABLE_A,
5746 MTUINDEX_V(0xff) | MTUVALUE_V(i));
5747 v = t4_read_reg(adap, TP_MTU_TABLE_A);
5748 mtus[i] = MTUVALUE_G(v);
5749 if (mtu_log)
5750 mtu_log[i] = MTUWIDTH_G(v);
5751 }
5752 }
5753
5754 /**
5755 * t4_read_cong_tbl - reads the congestion control table
5756 * @adap: the adapter
5757 * @incr: where to store the alpha values
5758 *
5759 * Reads the additive increments programmed into the HW congestion
5760 * control table.
5761 */
t4_read_cong_tbl(struct adapter * adap,u16 incr[NMTUS][NCCTRL_WIN])5762 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN])
5763 {
5764 unsigned int mtu, w;
5765
5766 for (mtu = 0; mtu < NMTUS; ++mtu)
5767 for (w = 0; w < NCCTRL_WIN; ++w) {
5768 t4_write_reg(adap, TP_CCTRL_TABLE_A,
5769 ROWINDEX_V(0xffff) | (mtu << 5) | w);
5770 incr[mtu][w] = (u16)t4_read_reg(adap,
5771 TP_CCTRL_TABLE_A) & 0x1fff;
5772 }
5773 }
5774
5775 /**
5776 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
5777 * @adap: the adapter
5778 * @addr: the indirect TP register address
5779 * @mask: specifies the field within the register to modify
5780 * @val: new value for the field
5781 *
5782 * Sets a field of an indirect TP register to the given value.
5783 */
t4_tp_wr_bits_indirect(struct adapter * adap,unsigned int addr,unsigned int mask,unsigned int val)5784 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
5785 unsigned int mask, unsigned int val)
5786 {
5787 t4_write_reg(adap, TP_PIO_ADDR_A, addr);
5788 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask;
5789 t4_write_reg(adap, TP_PIO_DATA_A, val);
5790 }
5791
5792 /**
5793 * init_cong_ctrl - initialize congestion control parameters
5794 * @a: the alpha values for congestion control
5795 * @b: the beta values for congestion control
5796 *
5797 * Initialize the congestion control parameters.
5798 */
init_cong_ctrl(unsigned short * a,unsigned short * b)5799 static void init_cong_ctrl(unsigned short *a, unsigned short *b)
5800 {
5801 a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
5802 a[9] = 2;
5803 a[10] = 3;
5804 a[11] = 4;
5805 a[12] = 5;
5806 a[13] = 6;
5807 a[14] = 7;
5808 a[15] = 8;
5809 a[16] = 9;
5810 a[17] = 10;
5811 a[18] = 14;
5812 a[19] = 17;
5813 a[20] = 21;
5814 a[21] = 25;
5815 a[22] = 30;
5816 a[23] = 35;
5817 a[24] = 45;
5818 a[25] = 60;
5819 a[26] = 80;
5820 a[27] = 100;
5821 a[28] = 200;
5822 a[29] = 300;
5823 a[30] = 400;
5824 a[31] = 500;
5825
5826 b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
5827 b[9] = b[10] = 1;
5828 b[11] = b[12] = 2;
5829 b[13] = b[14] = b[15] = b[16] = 3;
5830 b[17] = b[18] = b[19] = b[20] = b[21] = 4;
5831 b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
5832 b[28] = b[29] = 6;
5833 b[30] = b[31] = 7;
5834 }
5835
5836 /* The minimum additive increment value for the congestion control table */
5837 #define CC_MIN_INCR 2U
5838
5839 /**
5840 * t4_load_mtus - write the MTU and congestion control HW tables
5841 * @adap: the adapter
5842 * @mtus: the values for the MTU table
5843 * @alpha: the values for the congestion control alpha parameter
5844 * @beta: the values for the congestion control beta parameter
5845 *
5846 * Write the HW MTU table with the supplied MTUs and the high-speed
5847 * congestion control table with the supplied alpha, beta, and MTUs.
5848 * We write the two tables together because the additive increments
5849 * depend on the MTUs.
5850 */
t4_load_mtus(struct adapter * adap,const unsigned short * mtus,const unsigned short * alpha,const unsigned short * beta)5851 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
5852 const unsigned short *alpha, const unsigned short *beta)
5853 {
5854 static const unsigned int avg_pkts[NCCTRL_WIN] = {
5855 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
5856 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
5857 28672, 40960, 57344, 81920, 114688, 163840, 229376
5858 };
5859
5860 unsigned int i, w;
5861
5862 for (i = 0; i < NMTUS; ++i) {
5863 unsigned int mtu = mtus[i];
5864 unsigned int log2 = fls(mtu);
5865
5866 if (!(mtu & ((1 << log2) >> 2))) /* round */
5867 log2--;
5868 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) |
5869 MTUWIDTH_V(log2) | MTUVALUE_V(mtu));
5870
5871 for (w = 0; w < NCCTRL_WIN; ++w) {
5872 unsigned int inc;
5873
5874 inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
5875 CC_MIN_INCR);
5876
5877 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) |
5878 (w << 16) | (beta[w] << 13) | inc);
5879 }
5880 }
5881 }
5882
5883 /* Calculates a rate in bytes/s given the number of 256-byte units per 4K core
5884 * clocks. The formula is
5885 *
5886 * bytes/s = bytes256 * 256 * ClkFreq / 4096
5887 *
5888 * which is equivalent to
5889 *
5890 * bytes/s = 62.5 * bytes256 * ClkFreq_ms
5891 */
chan_rate(struct adapter * adap,unsigned int bytes256)5892 static u64 chan_rate(struct adapter *adap, unsigned int bytes256)
5893 {
5894 u64 v = bytes256 * adap->params.vpd.cclk;
5895
5896 return v * 62 + v / 2;
5897 }
5898
5899 /**
5900 * t4_get_chan_txrate - get the current per channel Tx rates
5901 * @adap: the adapter
5902 * @nic_rate: rates for NIC traffic
5903 * @ofld_rate: rates for offloaded traffic
5904 *
5905 * Return the current Tx rates in bytes/s for NIC and offloaded traffic
5906 * for each channel.
5907 */
t4_get_chan_txrate(struct adapter * adap,u64 * nic_rate,u64 * ofld_rate)5908 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate)
5909 {
5910 u32 v;
5911
5912 v = t4_read_reg(adap, TP_TX_TRATE_A);
5913 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v));
5914 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v));
5915 if (adap->params.arch.nchan == NCHAN) {
5916 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v));
5917 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v));
5918 }
5919
5920 v = t4_read_reg(adap, TP_TX_ORATE_A);
5921 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v));
5922 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v));
5923 if (adap->params.arch.nchan == NCHAN) {
5924 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v));
5925 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v));
5926 }
5927 }
5928
5929 /**
5930 * t4_set_trace_filter - configure one of the tracing filters
5931 * @adap: the adapter
5932 * @tp: the desired trace filter parameters
5933 * @idx: which filter to configure
5934 * @enable: whether to enable or disable the filter
5935 *
5936 * Configures one of the tracing filters available in HW. If @enable is
5937 * %0 @tp is not examined and may be %NULL. The user is responsible to
5938 * set the single/multiple trace mode by writing to MPS_TRC_CFG_A register
5939 */
t4_set_trace_filter(struct adapter * adap,const struct trace_params * tp,int idx,int enable)5940 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp,
5941 int idx, int enable)
5942 {
5943 int i, ofst = idx * 4;
5944 u32 data_reg, mask_reg, cfg;
5945
5946 if (!enable) {
5947 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5948 return 0;
5949 }
5950
5951 cfg = t4_read_reg(adap, MPS_TRC_CFG_A);
5952 if (cfg & TRCMULTIFILTER_F) {
5953 /* If multiple tracers are enabled, then maximum
5954 * capture size is 2.5KB (FIFO size of a single channel)
5955 * minus 2 flits for CPL_TRACE_PKT header.
5956 */
5957 if (tp->snap_len > ((10 * 1024 / 4) - (2 * 8)))
5958 return -EINVAL;
5959 } else {
5960 /* If multiple tracers are disabled, to avoid deadlocks
5961 * maximum packet capture size of 9600 bytes is recommended.
5962 * Also in this mode, only trace0 can be enabled and running.
5963 */
5964 if (tp->snap_len > 9600 || idx)
5965 return -EINVAL;
5966 }
5967
5968 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 ||
5969 tp->skip_len > TFLENGTH_M || tp->skip_ofst > TFOFFSET_M ||
5970 tp->min_len > TFMINPKTSIZE_M)
5971 return -EINVAL;
5972
5973 /* stop the tracer we'll be changing */
5974 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0);
5975
5976 idx *= (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A);
5977 data_reg = MPS_TRC_FILTER0_MATCH_A + idx;
5978 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + idx;
5979
5980 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
5981 t4_write_reg(adap, data_reg, tp->data[i]);
5982 t4_write_reg(adap, mask_reg, ~tp->mask[i]);
5983 }
5984 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst,
5985 TFCAPTUREMAX_V(tp->snap_len) |
5986 TFMINPKTSIZE_V(tp->min_len));
5987 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst,
5988 TFOFFSET_V(tp->skip_ofst) | TFLENGTH_V(tp->skip_len) |
5989 (is_t4(adap->params.chip) ?
5990 TFPORT_V(tp->port) | TFEN_F | TFINVERTMATCH_V(tp->invert) :
5991 T5_TFPORT_V(tp->port) | T5_TFEN_F |
5992 T5_TFINVERTMATCH_V(tp->invert)));
5993
5994 return 0;
5995 }
5996
5997 /**
5998 * t4_get_trace_filter - query one of the tracing filters
5999 * @adap: the adapter
6000 * @tp: the current trace filter parameters
6001 * @idx: which trace filter to query
6002 * @enabled: non-zero if the filter is enabled
6003 *
6004 * Returns the current settings of one of the HW tracing filters.
6005 */
t4_get_trace_filter(struct adapter * adap,struct trace_params * tp,int idx,int * enabled)6006 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx,
6007 int *enabled)
6008 {
6009 u32 ctla, ctlb;
6010 int i, ofst = idx * 4;
6011 u32 data_reg, mask_reg;
6012
6013 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst);
6014 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst);
6015
6016 if (is_t4(adap->params.chip)) {
6017 *enabled = !!(ctla & TFEN_F);
6018 tp->port = TFPORT_G(ctla);
6019 tp->invert = !!(ctla & TFINVERTMATCH_F);
6020 } else {
6021 *enabled = !!(ctla & T5_TFEN_F);
6022 tp->port = T5_TFPORT_G(ctla);
6023 tp->invert = !!(ctla & T5_TFINVERTMATCH_F);
6024 }
6025 tp->snap_len = TFCAPTUREMAX_G(ctlb);
6026 tp->min_len = TFMINPKTSIZE_G(ctlb);
6027 tp->skip_ofst = TFOFFSET_G(ctla);
6028 tp->skip_len = TFLENGTH_G(ctla);
6029
6030 ofst = (MPS_TRC_FILTER1_MATCH_A - MPS_TRC_FILTER0_MATCH_A) * idx;
6031 data_reg = MPS_TRC_FILTER0_MATCH_A + ofst;
6032 mask_reg = MPS_TRC_FILTER0_DONT_CARE_A + ofst;
6033
6034 for (i = 0; i < TRACE_LEN / 4; i++, data_reg += 4, mask_reg += 4) {
6035 tp->mask[i] = ~t4_read_reg(adap, mask_reg);
6036 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i];
6037 }
6038 }
6039
6040 /**
6041 * t4_pmtx_get_stats - returns the HW stats from PMTX
6042 * @adap: the adapter
6043 * @cnt: where to store the count statistics
6044 * @cycles: where to store the cycle statistics
6045 *
6046 * Returns performance statistics from PMTX.
6047 */
t4_pmtx_get_stats(struct adapter * adap,u32 cnt[],u64 cycles[])6048 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6049 {
6050 int i;
6051 u32 data[2];
6052
6053 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6054 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1);
6055 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A);
6056 if (is_t4(adap->params.chip)) {
6057 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A);
6058 } else {
6059 t4_read_indirect(adap, PM_TX_DBG_CTRL_A,
6060 PM_TX_DBG_DATA_A, data, 2,
6061 PM_TX_DBG_STAT_MSB_A);
6062 cycles[i] = (((u64)data[0] << 32) | data[1]);
6063 }
6064 }
6065 }
6066
6067 /**
6068 * t4_pmrx_get_stats - returns the HW stats from PMRX
6069 * @adap: the adapter
6070 * @cnt: where to store the count statistics
6071 * @cycles: where to store the cycle statistics
6072 *
6073 * Returns performance statistics from PMRX.
6074 */
t4_pmrx_get_stats(struct adapter * adap,u32 cnt[],u64 cycles[])6075 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[])
6076 {
6077 int i;
6078 u32 data[2];
6079
6080 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) {
6081 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1);
6082 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A);
6083 if (is_t4(adap->params.chip)) {
6084 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A);
6085 } else {
6086 t4_read_indirect(adap, PM_RX_DBG_CTRL_A,
6087 PM_RX_DBG_DATA_A, data, 2,
6088 PM_RX_DBG_STAT_MSB_A);
6089 cycles[i] = (((u64)data[0] << 32) | data[1]);
6090 }
6091 }
6092 }
6093
6094 /**
6095 * compute_mps_bg_map - compute the MPS Buffer Group Map for a Port
6096 * @adapter: the adapter
6097 * @pidx: the port index
6098 *
6099 * Computes and returns a bitmap indicating which MPS buffer groups are
6100 * associated with the given Port. Bit i is set if buffer group i is
6101 * used by the Port.
6102 */
compute_mps_bg_map(struct adapter * adapter,int pidx)6103 static inline unsigned int compute_mps_bg_map(struct adapter *adapter,
6104 int pidx)
6105 {
6106 unsigned int chip_version, nports;
6107
6108 chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6109 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6110
6111 switch (chip_version) {
6112 case CHELSIO_T4:
6113 case CHELSIO_T5:
6114 switch (nports) {
6115 case 1: return 0xf;
6116 case 2: return 3 << (2 * pidx);
6117 case 4: return 1 << pidx;
6118 }
6119 break;
6120
6121 case CHELSIO_T6:
6122 switch (nports) {
6123 case 2: return 1 << (2 * pidx);
6124 }
6125 break;
6126 }
6127
6128 dev_err(adapter->pdev_dev, "Need MPS Buffer Group Map for Chip %0x, Nports %d\n",
6129 chip_version, nports);
6130
6131 return 0;
6132 }
6133
6134 /**
6135 * t4_get_mps_bg_map - return the buffer groups associated with a port
6136 * @adapter: the adapter
6137 * @pidx: the port index
6138 *
6139 * Returns a bitmap indicating which MPS buffer groups are associated
6140 * with the given Port. Bit i is set if buffer group i is used by the
6141 * Port.
6142 */
t4_get_mps_bg_map(struct adapter * adapter,int pidx)6143 unsigned int t4_get_mps_bg_map(struct adapter *adapter, int pidx)
6144 {
6145 u8 *mps_bg_map;
6146 unsigned int nports;
6147
6148 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6149 if (pidx >= nports) {
6150 CH_WARN(adapter, "MPS Port Index %d >= Nports %d\n",
6151 pidx, nports);
6152 return 0;
6153 }
6154
6155 /* If we've already retrieved/computed this, just return the result.
6156 */
6157 mps_bg_map = adapter->params.mps_bg_map;
6158 if (mps_bg_map[pidx])
6159 return mps_bg_map[pidx];
6160
6161 /* Newer Firmware can tell us what the MPS Buffer Group Map is.
6162 * If we're talking to such Firmware, let it tell us. If the new
6163 * API isn't supported, revert back to old hardcoded way. The value
6164 * obtained from Firmware is encoded in below format:
6165 *
6166 * val = (( MPSBGMAP[Port 3] << 24 ) |
6167 * ( MPSBGMAP[Port 2] << 16 ) |
6168 * ( MPSBGMAP[Port 1] << 8 ) |
6169 * ( MPSBGMAP[Port 0] << 0 ))
6170 */
6171 if (adapter->flags & CXGB4_FW_OK) {
6172 u32 param, val;
6173 int ret;
6174
6175 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6176 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_MPSBGMAP));
6177 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6178 0, 1, ¶m, &val);
6179 if (!ret) {
6180 int p;
6181
6182 /* Store the BG Map for all of the Ports in order to
6183 * avoid more calls to the Firmware in the future.
6184 */
6185 for (p = 0; p < MAX_NPORTS; p++, val >>= 8)
6186 mps_bg_map[p] = val & 0xff;
6187
6188 return mps_bg_map[pidx];
6189 }
6190 }
6191
6192 /* Either we're not talking to the Firmware or we're dealing with
6193 * older Firmware which doesn't support the new API to get the MPS
6194 * Buffer Group Map. Fall back to computing it ourselves.
6195 */
6196 mps_bg_map[pidx] = compute_mps_bg_map(adapter, pidx);
6197 return mps_bg_map[pidx];
6198 }
6199
6200 /**
6201 * t4_get_tp_e2c_map - return the E2C channel map associated with a port
6202 * @adapter: the adapter
6203 * @pidx: the port index
6204 */
t4_get_tp_e2c_map(struct adapter * adapter,int pidx)6205 static unsigned int t4_get_tp_e2c_map(struct adapter *adapter, int pidx)
6206 {
6207 unsigned int nports;
6208 u32 param, val = 0;
6209 int ret;
6210
6211 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A));
6212 if (pidx >= nports) {
6213 CH_WARN(adapter, "TP E2C Channel Port Index %d >= Nports %d\n",
6214 pidx, nports);
6215 return 0;
6216 }
6217
6218 /* FW version >= 1.16.44.0 can determine E2C channel map using
6219 * FW_PARAMS_PARAM_DEV_TPCHMAP API.
6220 */
6221 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6222 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_TPCHMAP));
6223 ret = t4_query_params_ns(adapter, adapter->mbox, adapter->pf,
6224 0, 1, ¶m, &val);
6225 if (!ret)
6226 return (val >> (8 * pidx)) & 0xff;
6227
6228 return 0;
6229 }
6230
6231 /**
6232 * t4_get_tp_ch_map - return TP ingress channels associated with a port
6233 * @adap: the adapter
6234 * @pidx: the port index
6235 *
6236 * Returns a bitmap indicating which TP Ingress Channels are associated
6237 * with a given Port. Bit i is set if TP Ingress Channel i is used by
6238 * the Port.
6239 */
t4_get_tp_ch_map(struct adapter * adap,int pidx)6240 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx)
6241 {
6242 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
6243 unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A));
6244
6245 if (pidx >= nports) {
6246 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n",
6247 pidx, nports);
6248 return 0;
6249 }
6250
6251 switch (chip_version) {
6252 case CHELSIO_T4:
6253 case CHELSIO_T5:
6254 /* Note that this happens to be the same values as the MPS
6255 * Buffer Group Map for these Chips. But we replicate the code
6256 * here because they're really separate concepts.
6257 */
6258 switch (nports) {
6259 case 1: return 0xf;
6260 case 2: return 3 << (2 * pidx);
6261 case 4: return 1 << pidx;
6262 }
6263 break;
6264
6265 case CHELSIO_T6:
6266 switch (nports) {
6267 case 1:
6268 case 2: return 1 << pidx;
6269 }
6270 break;
6271 }
6272
6273 dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n",
6274 chip_version, nports);
6275 return 0;
6276 }
6277
6278 /**
6279 * t4_get_port_type_description - return Port Type string description
6280 * @port_type: firmware Port Type enumeration
6281 */
t4_get_port_type_description(enum fw_port_type port_type)6282 const char *t4_get_port_type_description(enum fw_port_type port_type)
6283 {
6284 static const char *const port_type_description[] = {
6285 "Fiber_XFI",
6286 "Fiber_XAUI",
6287 "BT_SGMII",
6288 "BT_XFI",
6289 "BT_XAUI",
6290 "KX4",
6291 "CX4",
6292 "KX",
6293 "KR",
6294 "SFP",
6295 "BP_AP",
6296 "BP4_AP",
6297 "QSFP_10G",
6298 "QSA",
6299 "QSFP",
6300 "BP40_BA",
6301 "KR4_100G",
6302 "CR4_QSFP",
6303 "CR_QSFP",
6304 "CR2_QSFP",
6305 "SFP28",
6306 "KR_SFP28",
6307 "KR_XLAUI"
6308 };
6309
6310 if (port_type < ARRAY_SIZE(port_type_description))
6311 return port_type_description[port_type];
6312 return "UNKNOWN";
6313 }
6314
6315 /**
6316 * t4_get_port_stats_offset - collect port stats relative to a previous
6317 * snapshot
6318 * @adap: The adapter
6319 * @idx: The port
6320 * @stats: Current stats to fill
6321 * @offset: Previous stats snapshot
6322 */
t4_get_port_stats_offset(struct adapter * adap,int idx,struct port_stats * stats,struct port_stats * offset)6323 void t4_get_port_stats_offset(struct adapter *adap, int idx,
6324 struct port_stats *stats,
6325 struct port_stats *offset)
6326 {
6327 u64 *s, *o;
6328 int i;
6329
6330 t4_get_port_stats(adap, idx, stats);
6331 for (i = 0, s = (u64 *)stats, o = (u64 *)offset;
6332 i < (sizeof(struct port_stats) / sizeof(u64));
6333 i++, s++, o++)
6334 *s -= *o;
6335 }
6336
6337 /**
6338 * t4_get_port_stats - collect port statistics
6339 * @adap: the adapter
6340 * @idx: the port index
6341 * @p: the stats structure to fill
6342 *
6343 * Collect statistics related to the given port from HW.
6344 */
t4_get_port_stats(struct adapter * adap,int idx,struct port_stats * p)6345 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
6346 {
6347 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6348 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A);
6349
6350 #define GET_STAT(name) \
6351 t4_read_reg64(adap, \
6352 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
6353 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
6354 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6355
6356 p->tx_octets = GET_STAT(TX_PORT_BYTES);
6357 p->tx_frames = GET_STAT(TX_PORT_FRAMES);
6358 p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
6359 p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
6360 p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
6361 p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
6362 p->tx_frames_64 = GET_STAT(TX_PORT_64B);
6363 p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
6364 p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
6365 p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
6366 p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
6367 p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
6368 p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
6369 p->tx_drop = GET_STAT(TX_PORT_DROP);
6370 p->tx_pause = GET_STAT(TX_PORT_PAUSE);
6371 p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
6372 p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
6373 p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
6374 p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
6375 p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
6376 p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
6377 p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
6378 p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
6379
6380 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6381 if (stat_ctl & COUNTPAUSESTATTX_F)
6382 p->tx_frames_64 -= p->tx_pause;
6383 if (stat_ctl & COUNTPAUSEMCTX_F)
6384 p->tx_mcast_frames -= p->tx_pause;
6385 }
6386 p->rx_octets = GET_STAT(RX_PORT_BYTES);
6387 p->rx_frames = GET_STAT(RX_PORT_FRAMES);
6388 p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
6389 p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
6390 p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
6391 p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
6392 p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
6393 p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
6394 p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
6395 p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
6396 p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
6397 p->rx_frames_64 = GET_STAT(RX_PORT_64B);
6398 p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
6399 p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
6400 p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
6401 p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
6402 p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
6403 p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
6404 p->rx_pause = GET_STAT(RX_PORT_PAUSE);
6405 p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
6406 p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
6407 p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
6408 p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
6409 p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
6410 p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
6411 p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
6412 p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
6413
6414 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) {
6415 if (stat_ctl & COUNTPAUSESTATRX_F)
6416 p->rx_frames_64 -= p->rx_pause;
6417 if (stat_ctl & COUNTPAUSEMCRX_F)
6418 p->rx_mcast_frames -= p->rx_pause;
6419 }
6420
6421 p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
6422 p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
6423 p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
6424 p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
6425 p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
6426 p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
6427 p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
6428 p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
6429
6430 #undef GET_STAT
6431 #undef GET_STAT_COM
6432 }
6433
6434 /**
6435 * t4_get_lb_stats - collect loopback port statistics
6436 * @adap: the adapter
6437 * @idx: the loopback port index
6438 * @p: the stats structure to fill
6439 *
6440 * Return HW statistics for the given loopback port.
6441 */
t4_get_lb_stats(struct adapter * adap,int idx,struct lb_port_stats * p)6442 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p)
6443 {
6444 u32 bgmap = t4_get_mps_bg_map(adap, idx);
6445
6446 #define GET_STAT(name) \
6447 t4_read_reg64(adap, \
6448 (is_t4(adap->params.chip) ? \
6449 PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L) : \
6450 T5_PORT_REG(idx, MPS_PORT_STAT_LB_PORT_##name##_L)))
6451 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
6452
6453 p->octets = GET_STAT(BYTES);
6454 p->frames = GET_STAT(FRAMES);
6455 p->bcast_frames = GET_STAT(BCAST);
6456 p->mcast_frames = GET_STAT(MCAST);
6457 p->ucast_frames = GET_STAT(UCAST);
6458 p->error_frames = GET_STAT(ERROR);
6459
6460 p->frames_64 = GET_STAT(64B);
6461 p->frames_65_127 = GET_STAT(65B_127B);
6462 p->frames_128_255 = GET_STAT(128B_255B);
6463 p->frames_256_511 = GET_STAT(256B_511B);
6464 p->frames_512_1023 = GET_STAT(512B_1023B);
6465 p->frames_1024_1518 = GET_STAT(1024B_1518B);
6466 p->frames_1519_max = GET_STAT(1519B_MAX);
6467 p->drop = GET_STAT(DROP_FRAMES);
6468
6469 p->ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_DROP_FRAME) : 0;
6470 p->ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_DROP_FRAME) : 0;
6471 p->ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_DROP_FRAME) : 0;
6472 p->ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_DROP_FRAME) : 0;
6473 p->trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_LB_TRUNC_FRAME) : 0;
6474 p->trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_LB_TRUNC_FRAME) : 0;
6475 p->trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_LB_TRUNC_FRAME) : 0;
6476 p->trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_LB_TRUNC_FRAME) : 0;
6477
6478 #undef GET_STAT
6479 #undef GET_STAT_COM
6480 }
6481
6482 /* t4_mk_filtdelwr - create a delete filter WR
6483 * @ftid: the filter ID
6484 * @wr: the filter work request to populate
6485 * @qid: ingress queue to receive the delete notification
6486 *
6487 * Creates a filter work request to delete the supplied filter. If @qid is
6488 * negative the delete notification is suppressed.
6489 */
t4_mk_filtdelwr(unsigned int ftid,struct fw_filter_wr * wr,int qid)6490 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
6491 {
6492 memset(wr, 0, sizeof(*wr));
6493 wr->op_pkd = cpu_to_be32(FW_WR_OP_V(FW_FILTER_WR));
6494 wr->len16_pkd = cpu_to_be32(FW_WR_LEN16_V(sizeof(*wr) / 16));
6495 wr->tid_to_iq = cpu_to_be32(FW_FILTER_WR_TID_V(ftid) |
6496 FW_FILTER_WR_NOREPLY_V(qid < 0));
6497 wr->del_filter_to_l2tix = cpu_to_be32(FW_FILTER_WR_DEL_FILTER_F);
6498 if (qid >= 0)
6499 wr->rx_chan_rx_rpl_iq =
6500 cpu_to_be16(FW_FILTER_WR_RX_RPL_IQ_V(qid));
6501 }
6502
6503 #define INIT_CMD(var, cmd, rd_wr) do { \
6504 (var).op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_##cmd##_CMD) | \
6505 FW_CMD_REQUEST_F | \
6506 FW_CMD_##rd_wr##_F); \
6507 (var).retval_len16 = cpu_to_be32(FW_LEN16(var)); \
6508 } while (0)
6509
t4_fwaddrspace_write(struct adapter * adap,unsigned int mbox,u32 addr,u32 val)6510 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
6511 u32 addr, u32 val)
6512 {
6513 u32 ldst_addrspace;
6514 struct fw_ldst_cmd c;
6515
6516 memset(&c, 0, sizeof(c));
6517 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE);
6518 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6519 FW_CMD_REQUEST_F |
6520 FW_CMD_WRITE_F |
6521 ldst_addrspace);
6522 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6523 c.u.addrval.addr = cpu_to_be32(addr);
6524 c.u.addrval.val = cpu_to_be32(val);
6525
6526 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6527 }
6528
6529 /**
6530 * t4_mdio_rd - read a PHY register through MDIO
6531 * @adap: the adapter
6532 * @mbox: mailbox to use for the FW command
6533 * @phy_addr: the PHY address
6534 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6535 * @reg: the register to read
6536 * @valp: where to store the value
6537 *
6538 * Issues a FW command through the given mailbox to read a PHY register.
6539 */
t4_mdio_rd(struct adapter * adap,unsigned int mbox,unsigned int phy_addr,unsigned int mmd,unsigned int reg,u16 * valp)6540 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6541 unsigned int mmd, unsigned int reg, u16 *valp)
6542 {
6543 int ret;
6544 u32 ldst_addrspace;
6545 struct fw_ldst_cmd c;
6546
6547 memset(&c, 0, sizeof(c));
6548 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6549 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6550 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6551 ldst_addrspace);
6552 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6553 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6554 FW_LDST_CMD_MMD_V(mmd));
6555 c.u.mdio.raddr = cpu_to_be16(reg);
6556
6557 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6558 if (ret == 0)
6559 *valp = be16_to_cpu(c.u.mdio.rval);
6560 return ret;
6561 }
6562
6563 /**
6564 * t4_mdio_wr - write a PHY register through MDIO
6565 * @adap: the adapter
6566 * @mbox: mailbox to use for the FW command
6567 * @phy_addr: the PHY address
6568 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
6569 * @reg: the register to write
6570 * @val: value to write
6571 *
6572 * Issues a FW command through the given mailbox to write a PHY register.
6573 */
t4_mdio_wr(struct adapter * adap,unsigned int mbox,unsigned int phy_addr,unsigned int mmd,unsigned int reg,u16 val)6574 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
6575 unsigned int mmd, unsigned int reg, u16 val)
6576 {
6577 u32 ldst_addrspace;
6578 struct fw_ldst_cmd c;
6579
6580 memset(&c, 0, sizeof(c));
6581 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO);
6582 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6583 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
6584 ldst_addrspace);
6585 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6586 c.u.mdio.paddr_mmd = cpu_to_be16(FW_LDST_CMD_PADDR_V(phy_addr) |
6587 FW_LDST_CMD_MMD_V(mmd));
6588 c.u.mdio.raddr = cpu_to_be16(reg);
6589 c.u.mdio.rval = cpu_to_be16(val);
6590
6591 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6592 }
6593
6594 /**
6595 * t4_sge_decode_idma_state - decode the idma state
6596 * @adapter: the adapter
6597 * @state: the state idma is stuck in
6598 */
t4_sge_decode_idma_state(struct adapter * adapter,int state)6599 void t4_sge_decode_idma_state(struct adapter *adapter, int state)
6600 {
6601 static const char * const t4_decode[] = {
6602 "IDMA_IDLE",
6603 "IDMA_PUSH_MORE_CPL_FIFO",
6604 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6605 "Not used",
6606 "IDMA_PHYSADDR_SEND_PCIEHDR",
6607 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6608 "IDMA_PHYSADDR_SEND_PAYLOAD",
6609 "IDMA_SEND_FIFO_TO_IMSG",
6610 "IDMA_FL_REQ_DATA_FL_PREP",
6611 "IDMA_FL_REQ_DATA_FL",
6612 "IDMA_FL_DROP",
6613 "IDMA_FL_H_REQ_HEADER_FL",
6614 "IDMA_FL_H_SEND_PCIEHDR",
6615 "IDMA_FL_H_PUSH_CPL_FIFO",
6616 "IDMA_FL_H_SEND_CPL",
6617 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6618 "IDMA_FL_H_SEND_IP_HDR",
6619 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6620 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6621 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6622 "IDMA_FL_D_SEND_PCIEHDR",
6623 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6624 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6625 "IDMA_FL_SEND_PCIEHDR",
6626 "IDMA_FL_PUSH_CPL_FIFO",
6627 "IDMA_FL_SEND_CPL",
6628 "IDMA_FL_SEND_PAYLOAD_FIRST",
6629 "IDMA_FL_SEND_PAYLOAD",
6630 "IDMA_FL_REQ_NEXT_DATA_FL",
6631 "IDMA_FL_SEND_NEXT_PCIEHDR",
6632 "IDMA_FL_SEND_PADDING",
6633 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6634 "IDMA_FL_SEND_FIFO_TO_IMSG",
6635 "IDMA_FL_REQ_DATAFL_DONE",
6636 "IDMA_FL_REQ_HEADERFL_DONE",
6637 };
6638 static const char * const t5_decode[] = {
6639 "IDMA_IDLE",
6640 "IDMA_ALMOST_IDLE",
6641 "IDMA_PUSH_MORE_CPL_FIFO",
6642 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6643 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6644 "IDMA_PHYSADDR_SEND_PCIEHDR",
6645 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6646 "IDMA_PHYSADDR_SEND_PAYLOAD",
6647 "IDMA_SEND_FIFO_TO_IMSG",
6648 "IDMA_FL_REQ_DATA_FL",
6649 "IDMA_FL_DROP",
6650 "IDMA_FL_DROP_SEND_INC",
6651 "IDMA_FL_H_REQ_HEADER_FL",
6652 "IDMA_FL_H_SEND_PCIEHDR",
6653 "IDMA_FL_H_PUSH_CPL_FIFO",
6654 "IDMA_FL_H_SEND_CPL",
6655 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6656 "IDMA_FL_H_SEND_IP_HDR",
6657 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6658 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6659 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6660 "IDMA_FL_D_SEND_PCIEHDR",
6661 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6662 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6663 "IDMA_FL_SEND_PCIEHDR",
6664 "IDMA_FL_PUSH_CPL_FIFO",
6665 "IDMA_FL_SEND_CPL",
6666 "IDMA_FL_SEND_PAYLOAD_FIRST",
6667 "IDMA_FL_SEND_PAYLOAD",
6668 "IDMA_FL_REQ_NEXT_DATA_FL",
6669 "IDMA_FL_SEND_NEXT_PCIEHDR",
6670 "IDMA_FL_SEND_PADDING",
6671 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6672 };
6673 static const char * const t6_decode[] = {
6674 "IDMA_IDLE",
6675 "IDMA_PUSH_MORE_CPL_FIFO",
6676 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
6677 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
6678 "IDMA_PHYSADDR_SEND_PCIEHDR",
6679 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
6680 "IDMA_PHYSADDR_SEND_PAYLOAD",
6681 "IDMA_FL_REQ_DATA_FL",
6682 "IDMA_FL_DROP",
6683 "IDMA_FL_DROP_SEND_INC",
6684 "IDMA_FL_H_REQ_HEADER_FL",
6685 "IDMA_FL_H_SEND_PCIEHDR",
6686 "IDMA_FL_H_PUSH_CPL_FIFO",
6687 "IDMA_FL_H_SEND_CPL",
6688 "IDMA_FL_H_SEND_IP_HDR_FIRST",
6689 "IDMA_FL_H_SEND_IP_HDR",
6690 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
6691 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
6692 "IDMA_FL_H_SEND_IP_HDR_PADDING",
6693 "IDMA_FL_D_SEND_PCIEHDR",
6694 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
6695 "IDMA_FL_D_REQ_NEXT_DATA_FL",
6696 "IDMA_FL_SEND_PCIEHDR",
6697 "IDMA_FL_PUSH_CPL_FIFO",
6698 "IDMA_FL_SEND_CPL",
6699 "IDMA_FL_SEND_PAYLOAD_FIRST",
6700 "IDMA_FL_SEND_PAYLOAD",
6701 "IDMA_FL_REQ_NEXT_DATA_FL",
6702 "IDMA_FL_SEND_NEXT_PCIEHDR",
6703 "IDMA_FL_SEND_PADDING",
6704 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
6705 };
6706 static const u32 sge_regs[] = {
6707 SGE_DEBUG_DATA_LOW_INDEX_2_A,
6708 SGE_DEBUG_DATA_LOW_INDEX_3_A,
6709 SGE_DEBUG_DATA_HIGH_INDEX_10_A,
6710 };
6711 const char **sge_idma_decode;
6712 int sge_idma_decode_nstates;
6713 int i;
6714 unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
6715
6716 /* Select the right set of decode strings to dump depending on the
6717 * adapter chip type.
6718 */
6719 switch (chip_version) {
6720 case CHELSIO_T4:
6721 sge_idma_decode = (const char **)t4_decode;
6722 sge_idma_decode_nstates = ARRAY_SIZE(t4_decode);
6723 break;
6724
6725 case CHELSIO_T5:
6726 sge_idma_decode = (const char **)t5_decode;
6727 sge_idma_decode_nstates = ARRAY_SIZE(t5_decode);
6728 break;
6729
6730 case CHELSIO_T6:
6731 sge_idma_decode = (const char **)t6_decode;
6732 sge_idma_decode_nstates = ARRAY_SIZE(t6_decode);
6733 break;
6734
6735 default:
6736 dev_err(adapter->pdev_dev,
6737 "Unsupported chip version %d\n", chip_version);
6738 return;
6739 }
6740
6741 if (state < sge_idma_decode_nstates)
6742 CH_WARN(adapter, "idma state %s\n", sge_idma_decode[state]);
6743 else
6744 CH_WARN(adapter, "idma state %d unknown\n", state);
6745
6746 for (i = 0; i < ARRAY_SIZE(sge_regs); i++)
6747 CH_WARN(adapter, "SGE register %#x value %#x\n",
6748 sge_regs[i], t4_read_reg(adapter, sge_regs[i]));
6749 }
6750
6751 /**
6752 * t4_sge_ctxt_flush - flush the SGE context cache
6753 * @adap: the adapter
6754 * @mbox: mailbox to use for the FW command
6755 * @ctxt_type: Egress or Ingress
6756 *
6757 * Issues a FW command through the given mailbox to flush the
6758 * SGE context cache.
6759 */
t4_sge_ctxt_flush(struct adapter * adap,unsigned int mbox,int ctxt_type)6760 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox, int ctxt_type)
6761 {
6762 int ret;
6763 u32 ldst_addrspace;
6764 struct fw_ldst_cmd c;
6765
6766 memset(&c, 0, sizeof(c));
6767 ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(ctxt_type == CTXT_EGRESS ?
6768 FW_LDST_ADDRSPC_SGE_EGRC :
6769 FW_LDST_ADDRSPC_SGE_INGC);
6770 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
6771 FW_CMD_REQUEST_F | FW_CMD_READ_F |
6772 ldst_addrspace);
6773 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
6774 c.u.idctxt.msg_ctxtflush = cpu_to_be32(FW_LDST_CMD_CTXTFLUSH_F);
6775
6776 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6777 return ret;
6778 }
6779
6780 /**
6781 * t4_read_sge_dbqtimers - read SGE Doorbell Queue Timer values
6782 * @adap: the adapter
6783 * @ndbqtimers: size of the provided SGE Doorbell Queue Timer table
6784 * @dbqtimers: SGE Doorbell Queue Timer table
6785 *
6786 * Reads the SGE Doorbell Queue Timer values into the provided table.
6787 * Returns 0 on success (Firmware and Hardware support this feature),
6788 * an error on failure.
6789 */
t4_read_sge_dbqtimers(struct adapter * adap,unsigned int ndbqtimers,u16 * dbqtimers)6790 int t4_read_sge_dbqtimers(struct adapter *adap, unsigned int ndbqtimers,
6791 u16 *dbqtimers)
6792 {
6793 int ret, dbqtimerix;
6794
6795 ret = 0;
6796 dbqtimerix = 0;
6797 while (dbqtimerix < ndbqtimers) {
6798 int nparams, param;
6799 u32 params[7], vals[7];
6800
6801 nparams = ndbqtimers - dbqtimerix;
6802 if (nparams > ARRAY_SIZE(params))
6803 nparams = ARRAY_SIZE(params);
6804
6805 for (param = 0; param < nparams; param++)
6806 params[param] =
6807 (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
6808 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_DBQ_TIMER) |
6809 FW_PARAMS_PARAM_Y_V(dbqtimerix + param));
6810 ret = t4_query_params(adap, adap->mbox, adap->pf, 0,
6811 nparams, params, vals);
6812 if (ret)
6813 break;
6814
6815 for (param = 0; param < nparams; param++)
6816 dbqtimers[dbqtimerix++] = vals[param];
6817 }
6818 return ret;
6819 }
6820
6821 /**
6822 * t4_fw_hello - establish communication with FW
6823 * @adap: the adapter
6824 * @mbox: mailbox to use for the FW command
6825 * @evt_mbox: mailbox to receive async FW events
6826 * @master: specifies the caller's willingness to be the device master
6827 * @state: returns the current device state (if non-NULL)
6828 *
6829 * Issues a command to establish communication with FW. Returns either
6830 * an error (negative integer) or the mailbox of the Master PF.
6831 */
t4_fw_hello(struct adapter * adap,unsigned int mbox,unsigned int evt_mbox,enum dev_master master,enum dev_state * state)6832 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
6833 enum dev_master master, enum dev_state *state)
6834 {
6835 int ret;
6836 struct fw_hello_cmd c;
6837 u32 v;
6838 unsigned int master_mbox;
6839 int retries = FW_CMD_HELLO_RETRIES;
6840
6841 retry:
6842 memset(&c, 0, sizeof(c));
6843 INIT_CMD(c, HELLO, WRITE);
6844 c.err_to_clearinit = cpu_to_be32(
6845 FW_HELLO_CMD_MASTERDIS_V(master == MASTER_CANT) |
6846 FW_HELLO_CMD_MASTERFORCE_V(master == MASTER_MUST) |
6847 FW_HELLO_CMD_MBMASTER_V(master == MASTER_MUST ?
6848 mbox : FW_HELLO_CMD_MBMASTER_M) |
6849 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox) |
6850 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os) |
6851 FW_HELLO_CMD_CLEARINIT_F);
6852
6853 /*
6854 * Issue the HELLO command to the firmware. If it's not successful
6855 * but indicates that we got a "busy" or "timeout" condition, retry
6856 * the HELLO until we exhaust our retry limit. If we do exceed our
6857 * retry limit, check to see if the firmware left us any error
6858 * information and report that if so.
6859 */
6860 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
6861 if (ret < 0) {
6862 if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
6863 goto retry;
6864 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F)
6865 t4_report_fw_error(adap);
6866 return ret;
6867 }
6868
6869 v = be32_to_cpu(c.err_to_clearinit);
6870 master_mbox = FW_HELLO_CMD_MBMASTER_G(v);
6871 if (state) {
6872 if (v & FW_HELLO_CMD_ERR_F)
6873 *state = DEV_STATE_ERR;
6874 else if (v & FW_HELLO_CMD_INIT_F)
6875 *state = DEV_STATE_INIT;
6876 else
6877 *state = DEV_STATE_UNINIT;
6878 }
6879
6880 /*
6881 * If we're not the Master PF then we need to wait around for the
6882 * Master PF Driver to finish setting up the adapter.
6883 *
6884 * Note that we also do this wait if we're a non-Master-capable PF and
6885 * there is no current Master PF; a Master PF may show up momentarily
6886 * and we wouldn't want to fail pointlessly. (This can happen when an
6887 * OS loads lots of different drivers rapidly at the same time). In
6888 * this case, the Master PF returned by the firmware will be
6889 * PCIE_FW_MASTER_M so the test below will work ...
6890 */
6891 if ((v & (FW_HELLO_CMD_ERR_F|FW_HELLO_CMD_INIT_F)) == 0 &&
6892 master_mbox != mbox) {
6893 int waiting = FW_CMD_HELLO_TIMEOUT;
6894
6895 /*
6896 * Wait for the firmware to either indicate an error or
6897 * initialized state. If we see either of these we bail out
6898 * and report the issue to the caller. If we exhaust the
6899 * "hello timeout" and we haven't exhausted our retries, try
6900 * again. Otherwise bail with a timeout error.
6901 */
6902 for (;;) {
6903 u32 pcie_fw;
6904
6905 msleep(50);
6906 waiting -= 50;
6907
6908 /*
6909 * If neither Error nor Initialized are indicated
6910 * by the firmware keep waiting till we exhaust our
6911 * timeout ... and then retry if we haven't exhausted
6912 * our retries ...
6913 */
6914 pcie_fw = t4_read_reg(adap, PCIE_FW_A);
6915 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
6916 if (waiting <= 0) {
6917 if (retries-- > 0)
6918 goto retry;
6919
6920 return -ETIMEDOUT;
6921 }
6922 continue;
6923 }
6924
6925 /*
6926 * We either have an Error or Initialized condition
6927 * report errors preferentially.
6928 */
6929 if (state) {
6930 if (pcie_fw & PCIE_FW_ERR_F)
6931 *state = DEV_STATE_ERR;
6932 else if (pcie_fw & PCIE_FW_INIT_F)
6933 *state = DEV_STATE_INIT;
6934 }
6935
6936 /*
6937 * If we arrived before a Master PF was selected and
6938 * there's not a valid Master PF, grab its identity
6939 * for our caller.
6940 */
6941 if (master_mbox == PCIE_FW_MASTER_M &&
6942 (pcie_fw & PCIE_FW_MASTER_VLD_F))
6943 master_mbox = PCIE_FW_MASTER_G(pcie_fw);
6944 break;
6945 }
6946 }
6947
6948 return master_mbox;
6949 }
6950
6951 /**
6952 * t4_fw_bye - end communication with FW
6953 * @adap: the adapter
6954 * @mbox: mailbox to use for the FW command
6955 *
6956 * Issues a command to terminate communication with FW.
6957 */
t4_fw_bye(struct adapter * adap,unsigned int mbox)6958 int t4_fw_bye(struct adapter *adap, unsigned int mbox)
6959 {
6960 struct fw_bye_cmd c;
6961
6962 memset(&c, 0, sizeof(c));
6963 INIT_CMD(c, BYE, WRITE);
6964 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6965 }
6966
6967 /**
6968 * t4_early_init - ask FW to initialize the device
6969 * @adap: the adapter
6970 * @mbox: mailbox to use for the FW command
6971 *
6972 * Issues a command to FW to partially initialize the device. This
6973 * performs initialization that generally doesn't depend on user input.
6974 */
t4_early_init(struct adapter * adap,unsigned int mbox)6975 int t4_early_init(struct adapter *adap, unsigned int mbox)
6976 {
6977 struct fw_initialize_cmd c;
6978
6979 memset(&c, 0, sizeof(c));
6980 INIT_CMD(c, INITIALIZE, WRITE);
6981 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
6982 }
6983
6984 /**
6985 * t4_fw_reset - issue a reset to FW
6986 * @adap: the adapter
6987 * @mbox: mailbox to use for the FW command
6988 * @reset: specifies the type of reset to perform
6989 *
6990 * Issues a reset command of the specified type to FW.
6991 */
t4_fw_reset(struct adapter * adap,unsigned int mbox,int reset)6992 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
6993 {
6994 struct fw_reset_cmd c;
6995
6996 memset(&c, 0, sizeof(c));
6997 INIT_CMD(c, RESET, WRITE);
6998 c.val = cpu_to_be32(reset);
6999 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7000 }
7001
7002 /**
7003 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
7004 * @adap: the adapter
7005 * @mbox: mailbox to use for the FW RESET command (if desired)
7006 * @force: force uP into RESET even if FW RESET command fails
7007 *
7008 * Issues a RESET command to firmware (if desired) with a HALT indication
7009 * and then puts the microprocessor into RESET state. The RESET command
7010 * will only be issued if a legitimate mailbox is provided (mbox <=
7011 * PCIE_FW_MASTER_M).
7012 *
7013 * This is generally used in order for the host to safely manipulate the
7014 * adapter without fear of conflicting with whatever the firmware might
7015 * be doing. The only way out of this state is to RESTART the firmware
7016 * ...
7017 */
t4_fw_halt(struct adapter * adap,unsigned int mbox,int force)7018 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
7019 {
7020 int ret = 0;
7021
7022 /*
7023 * If a legitimate mailbox is provided, issue a RESET command
7024 * with a HALT indication.
7025 */
7026 if (mbox <= PCIE_FW_MASTER_M) {
7027 struct fw_reset_cmd c;
7028
7029 memset(&c, 0, sizeof(c));
7030 INIT_CMD(c, RESET, WRITE);
7031 c.val = cpu_to_be32(PIORST_F | PIORSTMODE_F);
7032 c.halt_pkd = cpu_to_be32(FW_RESET_CMD_HALT_F);
7033 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7034 }
7035
7036 /*
7037 * Normally we won't complete the operation if the firmware RESET
7038 * command fails but if our caller insists we'll go ahead and put the
7039 * uP into RESET. This can be useful if the firmware is hung or even
7040 * missing ... We'll have to take the risk of putting the uP into
7041 * RESET without the cooperation of firmware in that case.
7042 *
7043 * We also force the firmware's HALT flag to be on in case we bypassed
7044 * the firmware RESET command above or we're dealing with old firmware
7045 * which doesn't have the HALT capability. This will serve as a flag
7046 * for the incoming firmware to know that it's coming out of a HALT
7047 * rather than a RESET ... if it's new enough to understand that ...
7048 */
7049 if (ret == 0 || force) {
7050 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
7051 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F,
7052 PCIE_FW_HALT_F);
7053 }
7054
7055 /*
7056 * And we always return the result of the firmware RESET command
7057 * even when we force the uP into RESET ...
7058 */
7059 return ret;
7060 }
7061
7062 /**
7063 * t4_fw_restart - restart the firmware by taking the uP out of RESET
7064 * @adap: the adapter
7065 * @mbox: mailbox to use for the FW command
7066 * @reset: if we want to do a RESET to restart things
7067 *
7068 * Restart firmware previously halted by t4_fw_halt(). On successful
7069 * return the previous PF Master remains as the new PF Master and there
7070 * is no need to issue a new HELLO command, etc.
7071 *
7072 * We do this in two ways:
7073 *
7074 * 1. If we're dealing with newer firmware we'll simply want to take
7075 * the chip's microprocessor out of RESET. This will cause the
7076 * firmware to start up from its start vector. And then we'll loop
7077 * until the firmware indicates it's started again (PCIE_FW.HALT
7078 * reset to 0) or we timeout.
7079 *
7080 * 2. If we're dealing with older firmware then we'll need to RESET
7081 * the chip since older firmware won't recognize the PCIE_FW.HALT
7082 * flag and automatically RESET itself on startup.
7083 */
t4_fw_restart(struct adapter * adap,unsigned int mbox,int reset)7084 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
7085 {
7086 if (reset) {
7087 /*
7088 * Since we're directing the RESET instead of the firmware
7089 * doing it automatically, we need to clear the PCIE_FW.HALT
7090 * bit.
7091 */
7092 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0);
7093
7094 /*
7095 * If we've been given a valid mailbox, first try to get the
7096 * firmware to do the RESET. If that works, great and we can
7097 * return success. Otherwise, if we haven't been given a
7098 * valid mailbox or the RESET command failed, fall back to
7099 * hitting the chip with a hammer.
7100 */
7101 if (mbox <= PCIE_FW_MASTER_M) {
7102 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7103 msleep(100);
7104 if (t4_fw_reset(adap, mbox,
7105 PIORST_F | PIORSTMODE_F) == 0)
7106 return 0;
7107 }
7108
7109 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F);
7110 msleep(2000);
7111 } else {
7112 int ms;
7113
7114 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0);
7115 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
7116 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F))
7117 return 0;
7118 msleep(100);
7119 ms += 100;
7120 }
7121 return -ETIMEDOUT;
7122 }
7123 return 0;
7124 }
7125
7126 /**
7127 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
7128 * @adap: the adapter
7129 * @mbox: mailbox to use for the FW RESET command (if desired)
7130 * @fw_data: the firmware image to write
7131 * @size: image size
7132 * @force: force upgrade even if firmware doesn't cooperate
7133 *
7134 * Perform all of the steps necessary for upgrading an adapter's
7135 * firmware image. Normally this requires the cooperation of the
7136 * existing firmware in order to halt all existing activities
7137 * but if an invalid mailbox token is passed in we skip that step
7138 * (though we'll still put the adapter microprocessor into RESET in
7139 * that case).
7140 *
7141 * On successful return the new firmware will have been loaded and
7142 * the adapter will have been fully RESET losing all previous setup
7143 * state. On unsuccessful return the adapter may be completely hosed ...
7144 * positive errno indicates that the adapter is ~probably~ intact, a
7145 * negative errno indicates that things are looking bad ...
7146 */
t4_fw_upgrade(struct adapter * adap,unsigned int mbox,const u8 * fw_data,unsigned int size,int force)7147 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
7148 const u8 *fw_data, unsigned int size, int force)
7149 {
7150 const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
7151 int reset, ret;
7152
7153 if (!t4_fw_matches_chip(adap, fw_hdr))
7154 return -EINVAL;
7155
7156 /* Disable CXGB4_FW_OK flag so that mbox commands with CXGB4_FW_OK flag
7157 * set wont be sent when we are flashing FW.
7158 */
7159 adap->flags &= ~CXGB4_FW_OK;
7160
7161 ret = t4_fw_halt(adap, mbox, force);
7162 if (ret < 0 && !force)
7163 goto out;
7164
7165 ret = t4_load_fw(adap, fw_data, size);
7166 if (ret < 0)
7167 goto out;
7168
7169 /*
7170 * If there was a Firmware Configuration File stored in FLASH,
7171 * there's a good chance that it won't be compatible with the new
7172 * Firmware. In order to prevent difficult to diagnose adapter
7173 * initialization issues, we clear out the Firmware Configuration File
7174 * portion of the FLASH . The user will need to re-FLASH a new
7175 * Firmware Configuration File which is compatible with the new
7176 * Firmware if that's desired.
7177 */
7178 (void)t4_load_cfg(adap, NULL, 0);
7179
7180 /*
7181 * Older versions of the firmware don't understand the new
7182 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
7183 * restart. So for newly loaded older firmware we'll have to do the
7184 * RESET for it so it starts up on a clean slate. We can tell if
7185 * the newly loaded firmware will handle this right by checking
7186 * its header flags to see if it advertises the capability.
7187 */
7188 reset = ((be32_to_cpu(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
7189 ret = t4_fw_restart(adap, mbox, reset);
7190
7191 /* Grab potentially new Firmware Device Log parameters so we can see
7192 * how healthy the new Firmware is. It's okay to contact the new
7193 * Firmware for these parameters even though, as far as it's
7194 * concerned, we've never said "HELLO" to it ...
7195 */
7196 (void)t4_init_devlog_params(adap);
7197 out:
7198 adap->flags |= CXGB4_FW_OK;
7199 return ret;
7200 }
7201
7202 /**
7203 * t4_fl_pkt_align - return the fl packet alignment
7204 * @adap: the adapter
7205 *
7206 * T4 has a single field to specify the packing and padding boundary.
7207 * T5 onwards has separate fields for this and hence the alignment for
7208 * next packet offset is maximum of these two.
7209 *
7210 */
t4_fl_pkt_align(struct adapter * adap)7211 int t4_fl_pkt_align(struct adapter *adap)
7212 {
7213 u32 sge_control, sge_control2;
7214 unsigned int ingpadboundary, ingpackboundary, fl_align, ingpad_shift;
7215
7216 sge_control = t4_read_reg(adap, SGE_CONTROL_A);
7217
7218 /* T4 uses a single control field to specify both the PCIe Padding and
7219 * Packing Boundary. T5 introduced the ability to specify these
7220 * separately. The actual Ingress Packet Data alignment boundary
7221 * within Packed Buffer Mode is the maximum of these two
7222 * specifications. (Note that it makes no real practical sense to
7223 * have the Padding Boundary be larger than the Packing Boundary but you
7224 * could set the chip up that way and, in fact, legacy T4 code would
7225 * end doing this because it would initialize the Padding Boundary and
7226 * leave the Packing Boundary initialized to 0 (16 bytes).)
7227 * Padding Boundary values in T6 starts from 8B,
7228 * where as it is 32B for T4 and T5.
7229 */
7230 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
7231 ingpad_shift = INGPADBOUNDARY_SHIFT_X;
7232 else
7233 ingpad_shift = T6_INGPADBOUNDARY_SHIFT_X;
7234
7235 ingpadboundary = 1 << (INGPADBOUNDARY_G(sge_control) + ingpad_shift);
7236
7237 fl_align = ingpadboundary;
7238 if (!is_t4(adap->params.chip)) {
7239 /* T5 has a weird interpretation of one of the PCIe Packing
7240 * Boundary values. No idea why ...
7241 */
7242 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A);
7243 ingpackboundary = INGPACKBOUNDARY_G(sge_control2);
7244 if (ingpackboundary == INGPACKBOUNDARY_16B_X)
7245 ingpackboundary = 16;
7246 else
7247 ingpackboundary = 1 << (ingpackboundary +
7248 INGPACKBOUNDARY_SHIFT_X);
7249
7250 fl_align = max(ingpadboundary, ingpackboundary);
7251 }
7252 return fl_align;
7253 }
7254
7255 /**
7256 * t4_fixup_host_params - fix up host-dependent parameters
7257 * @adap: the adapter
7258 * @page_size: the host's Base Page Size
7259 * @cache_line_size: the host's Cache Line Size
7260 *
7261 * Various registers in T4 contain values which are dependent on the
7262 * host's Base Page and Cache Line Sizes. This function will fix all of
7263 * those registers with the appropriate values as passed in ...
7264 */
t4_fixup_host_params(struct adapter * adap,unsigned int page_size,unsigned int cache_line_size)7265 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
7266 unsigned int cache_line_size)
7267 {
7268 unsigned int page_shift = fls(page_size) - 1;
7269 unsigned int sge_hps = page_shift - 10;
7270 unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
7271 unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
7272 unsigned int fl_align_log = fls(fl_align) - 1;
7273
7274 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A,
7275 HOSTPAGESIZEPF0_V(sge_hps) |
7276 HOSTPAGESIZEPF1_V(sge_hps) |
7277 HOSTPAGESIZEPF2_V(sge_hps) |
7278 HOSTPAGESIZEPF3_V(sge_hps) |
7279 HOSTPAGESIZEPF4_V(sge_hps) |
7280 HOSTPAGESIZEPF5_V(sge_hps) |
7281 HOSTPAGESIZEPF6_V(sge_hps) |
7282 HOSTPAGESIZEPF7_V(sge_hps));
7283
7284 if (is_t4(adap->params.chip)) {
7285 t4_set_reg_field(adap, SGE_CONTROL_A,
7286 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7287 EGRSTATUSPAGESIZE_F,
7288 INGPADBOUNDARY_V(fl_align_log -
7289 INGPADBOUNDARY_SHIFT_X) |
7290 EGRSTATUSPAGESIZE_V(stat_len != 64));
7291 } else {
7292 unsigned int pack_align;
7293 unsigned int ingpad, ingpack;
7294
7295 /* T5 introduced the separation of the Free List Padding and
7296 * Packing Boundaries. Thus, we can select a smaller Padding
7297 * Boundary to avoid uselessly chewing up PCIe Link and Memory
7298 * Bandwidth, and use a Packing Boundary which is large enough
7299 * to avoid false sharing between CPUs, etc.
7300 *
7301 * For the PCI Link, the smaller the Padding Boundary the
7302 * better. For the Memory Controller, a smaller Padding
7303 * Boundary is better until we cross under the Memory Line
7304 * Size (the minimum unit of transfer to/from Memory). If we
7305 * have a Padding Boundary which is smaller than the Memory
7306 * Line Size, that'll involve a Read-Modify-Write cycle on the
7307 * Memory Controller which is never good.
7308 */
7309
7310 /* We want the Packing Boundary to be based on the Cache Line
7311 * Size in order to help avoid False Sharing performance
7312 * issues between CPUs, etc. We also want the Packing
7313 * Boundary to incorporate the PCI-E Maximum Payload Size. We
7314 * get best performance when the Packing Boundary is a
7315 * multiple of the Maximum Payload Size.
7316 */
7317 pack_align = fl_align;
7318 if (pci_is_pcie(adap->pdev)) {
7319 unsigned int mps, mps_log;
7320 u16 devctl;
7321
7322 /* The PCIe Device Control Maximum Payload Size field
7323 * [bits 7:5] encodes sizes as powers of 2 starting at
7324 * 128 bytes.
7325 */
7326 pcie_capability_read_word(adap->pdev, PCI_EXP_DEVCTL,
7327 &devctl);
7328 mps_log = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5) + 7;
7329 mps = 1 << mps_log;
7330 if (mps > pack_align)
7331 pack_align = mps;
7332 }
7333
7334 /* N.B. T5/T6 have a crazy special interpretation of the "0"
7335 * value for the Packing Boundary. This corresponds to 16
7336 * bytes instead of the expected 32 bytes. So if we want 32
7337 * bytes, the best we can really do is 64 bytes ...
7338 */
7339 if (pack_align <= 16) {
7340 ingpack = INGPACKBOUNDARY_16B_X;
7341 fl_align = 16;
7342 } else if (pack_align == 32) {
7343 ingpack = INGPACKBOUNDARY_64B_X;
7344 fl_align = 64;
7345 } else {
7346 unsigned int pack_align_log = fls(pack_align) - 1;
7347
7348 ingpack = pack_align_log - INGPACKBOUNDARY_SHIFT_X;
7349 fl_align = pack_align;
7350 }
7351
7352 /* Use the smallest Ingress Padding which isn't smaller than
7353 * the Memory Controller Read/Write Size. We'll take that as
7354 * being 8 bytes since we don't know of any system with a
7355 * wider Memory Controller Bus Width.
7356 */
7357 if (is_t5(adap->params.chip))
7358 ingpad = INGPADBOUNDARY_32B_X;
7359 else
7360 ingpad = T6_INGPADBOUNDARY_8B_X;
7361
7362 t4_set_reg_field(adap, SGE_CONTROL_A,
7363 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
7364 EGRSTATUSPAGESIZE_F,
7365 INGPADBOUNDARY_V(ingpad) |
7366 EGRSTATUSPAGESIZE_V(stat_len != 64));
7367 t4_set_reg_field(adap, SGE_CONTROL2_A,
7368 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M),
7369 INGPACKBOUNDARY_V(ingpack));
7370 }
7371 /*
7372 * Adjust various SGE Free List Host Buffer Sizes.
7373 *
7374 * This is something of a crock since we're using fixed indices into
7375 * the array which are also known by the sge.c code and the T4
7376 * Firmware Configuration File. We need to come up with a much better
7377 * approach to managing this array. For now, the first four entries
7378 * are:
7379 *
7380 * 0: Host Page Size
7381 * 1: 64KB
7382 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
7383 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
7384 *
7385 * For the single-MTU buffers in unpacked mode we need to include
7386 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
7387 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
7388 * Padding boundary. All of these are accommodated in the Factory
7389 * Default Firmware Configuration File but we need to adjust it for
7390 * this host's cache line size.
7391 */
7392 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size);
7393 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A,
7394 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1)
7395 & ~(fl_align-1));
7396 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A,
7397 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1)
7398 & ~(fl_align-1));
7399
7400 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12));
7401
7402 return 0;
7403 }
7404
7405 /**
7406 * t4_fw_initialize - ask FW to initialize the device
7407 * @adap: the adapter
7408 * @mbox: mailbox to use for the FW command
7409 *
7410 * Issues a command to FW to partially initialize the device. This
7411 * performs initialization that generally doesn't depend on user input.
7412 */
t4_fw_initialize(struct adapter * adap,unsigned int mbox)7413 int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
7414 {
7415 struct fw_initialize_cmd c;
7416
7417 memset(&c, 0, sizeof(c));
7418 INIT_CMD(c, INITIALIZE, WRITE);
7419 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7420 }
7421
7422 /**
7423 * t4_query_params_rw - query FW or device parameters
7424 * @adap: the adapter
7425 * @mbox: mailbox to use for the FW command
7426 * @pf: the PF
7427 * @vf: the VF
7428 * @nparams: the number of parameters
7429 * @params: the parameter names
7430 * @val: the parameter values
7431 * @rw: Write and read flag
7432 * @sleep_ok: if true, we may sleep awaiting mbox cmd completion
7433 *
7434 * Reads the value of FW or device parameters. Up to 7 parameters can be
7435 * queried at once.
7436 */
t4_query_params_rw(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,u32 * val,int rw,bool sleep_ok)7437 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
7438 unsigned int vf, unsigned int nparams, const u32 *params,
7439 u32 *val, int rw, bool sleep_ok)
7440 {
7441 int i, ret;
7442 struct fw_params_cmd c;
7443 __be32 *p = &c.param[0].mnem;
7444
7445 if (nparams > 7)
7446 return -EINVAL;
7447
7448 memset(&c, 0, sizeof(c));
7449 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7450 FW_CMD_REQUEST_F | FW_CMD_READ_F |
7451 FW_PARAMS_CMD_PFN_V(pf) |
7452 FW_PARAMS_CMD_VFN_V(vf));
7453 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7454
7455 for (i = 0; i < nparams; i++) {
7456 *p++ = cpu_to_be32(*params++);
7457 if (rw)
7458 *p = cpu_to_be32(*(val + i));
7459 p++;
7460 }
7461
7462 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
7463 if (ret == 0)
7464 for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
7465 *val++ = be32_to_cpu(*p);
7466 return ret;
7467 }
7468
t4_query_params(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,u32 * val)7469 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7470 unsigned int vf, unsigned int nparams, const u32 *params,
7471 u32 *val)
7472 {
7473 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7474 true);
7475 }
7476
t4_query_params_ns(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,u32 * val)7477 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf,
7478 unsigned int vf, unsigned int nparams, const u32 *params,
7479 u32 *val)
7480 {
7481 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0,
7482 false);
7483 }
7484
7485 /**
7486 * t4_set_params_timeout - sets FW or device parameters
7487 * @adap: the adapter
7488 * @mbox: mailbox to use for the FW command
7489 * @pf: the PF
7490 * @vf: the VF
7491 * @nparams: the number of parameters
7492 * @params: the parameter names
7493 * @val: the parameter values
7494 * @timeout: the timeout time
7495 *
7496 * Sets the value of FW or device parameters. Up to 7 parameters can be
7497 * specified at once.
7498 */
t4_set_params_timeout(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,const u32 * val,int timeout)7499 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
7500 unsigned int pf, unsigned int vf,
7501 unsigned int nparams, const u32 *params,
7502 const u32 *val, int timeout)
7503 {
7504 struct fw_params_cmd c;
7505 __be32 *p = &c.param[0].mnem;
7506
7507 if (nparams > 7)
7508 return -EINVAL;
7509
7510 memset(&c, 0, sizeof(c));
7511 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
7512 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7513 FW_PARAMS_CMD_PFN_V(pf) |
7514 FW_PARAMS_CMD_VFN_V(vf));
7515 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7516
7517 while (nparams--) {
7518 *p++ = cpu_to_be32(*params++);
7519 *p++ = cpu_to_be32(*val++);
7520 }
7521
7522 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout);
7523 }
7524
7525 /**
7526 * t4_set_params - sets FW or device parameters
7527 * @adap: the adapter
7528 * @mbox: mailbox to use for the FW command
7529 * @pf: the PF
7530 * @vf: the VF
7531 * @nparams: the number of parameters
7532 * @params: the parameter names
7533 * @val: the parameter values
7534 *
7535 * Sets the value of FW or device parameters. Up to 7 parameters can be
7536 * specified at once.
7537 */
t4_set_params(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int nparams,const u32 * params,const u32 * val)7538 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
7539 unsigned int vf, unsigned int nparams, const u32 *params,
7540 const u32 *val)
7541 {
7542 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val,
7543 FW_CMD_MAX_TIMEOUT);
7544 }
7545
7546 /**
7547 * t4_cfg_pfvf - configure PF/VF resource limits
7548 * @adap: the adapter
7549 * @mbox: mailbox to use for the FW command
7550 * @pf: the PF being configured
7551 * @vf: the VF being configured
7552 * @txq: the max number of egress queues
7553 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
7554 * @rxqi: the max number of interrupt-capable ingress queues
7555 * @rxq: the max number of interruptless ingress queues
7556 * @tc: the PCI traffic class
7557 * @vi: the max number of virtual interfaces
7558 * @cmask: the channel access rights mask for the PF/VF
7559 * @pmask: the port access rights mask for the PF/VF
7560 * @nexact: the maximum number of exact MPS filters
7561 * @rcaps: read capabilities
7562 * @wxcaps: write/execute capabilities
7563 *
7564 * Configures resource limits and capabilities for a physical or virtual
7565 * function.
7566 */
t4_cfg_pfvf(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int txq,unsigned int txq_eth_ctrl,unsigned int rxqi,unsigned int rxq,unsigned int tc,unsigned int vi,unsigned int cmask,unsigned int pmask,unsigned int nexact,unsigned int rcaps,unsigned int wxcaps)7567 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
7568 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
7569 unsigned int rxqi, unsigned int rxq, unsigned int tc,
7570 unsigned int vi, unsigned int cmask, unsigned int pmask,
7571 unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
7572 {
7573 struct fw_pfvf_cmd c;
7574
7575 memset(&c, 0, sizeof(c));
7576 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) | FW_CMD_REQUEST_F |
7577 FW_CMD_WRITE_F | FW_PFVF_CMD_PFN_V(pf) |
7578 FW_PFVF_CMD_VFN_V(vf));
7579 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7580 c.niqflint_niq = cpu_to_be32(FW_PFVF_CMD_NIQFLINT_V(rxqi) |
7581 FW_PFVF_CMD_NIQ_V(rxq));
7582 c.type_to_neq = cpu_to_be32(FW_PFVF_CMD_CMASK_V(cmask) |
7583 FW_PFVF_CMD_PMASK_V(pmask) |
7584 FW_PFVF_CMD_NEQ_V(txq));
7585 c.tc_to_nexactf = cpu_to_be32(FW_PFVF_CMD_TC_V(tc) |
7586 FW_PFVF_CMD_NVI_V(vi) |
7587 FW_PFVF_CMD_NEXACTF_V(nexact));
7588 c.r_caps_to_nethctrl = cpu_to_be32(FW_PFVF_CMD_R_CAPS_V(rcaps) |
7589 FW_PFVF_CMD_WX_CAPS_V(wxcaps) |
7590 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl));
7591 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
7592 }
7593
7594 /**
7595 * t4_alloc_vi - allocate a virtual interface
7596 * @adap: the adapter
7597 * @mbox: mailbox to use for the FW command
7598 * @port: physical port associated with the VI
7599 * @pf: the PF owning the VI
7600 * @vf: the VF owning the VI
7601 * @nmac: number of MAC addresses needed (1 to 5)
7602 * @mac: the MAC addresses of the VI
7603 * @rss_size: size of RSS table slice associated with this VI
7604 * @vivld: the destination to store the VI Valid value.
7605 * @vin: the destination to store the VIN value.
7606 *
7607 * Allocates a virtual interface for the given physical port. If @mac is
7608 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
7609 * @mac should be large enough to hold @nmac Ethernet addresses, they are
7610 * stored consecutively so the space needed is @nmac * 6 bytes.
7611 * Returns a negative error number or the non-negative VI id.
7612 */
t4_alloc_vi(struct adapter * adap,unsigned int mbox,unsigned int port,unsigned int pf,unsigned int vf,unsigned int nmac,u8 * mac,unsigned int * rss_size,u8 * vivld,u8 * vin)7613 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
7614 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
7615 unsigned int *rss_size, u8 *vivld, u8 *vin)
7616 {
7617 int ret;
7618 struct fw_vi_cmd c;
7619
7620 memset(&c, 0, sizeof(c));
7621 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) | FW_CMD_REQUEST_F |
7622 FW_CMD_WRITE_F | FW_CMD_EXEC_F |
7623 FW_VI_CMD_PFN_V(pf) | FW_VI_CMD_VFN_V(vf));
7624 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_ALLOC_F | FW_LEN16(c));
7625 c.portid_pkd = FW_VI_CMD_PORTID_V(port);
7626 c.nmac = nmac - 1;
7627
7628 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7629 if (ret)
7630 return ret;
7631
7632 if (mac) {
7633 memcpy(mac, c.mac, sizeof(c.mac));
7634 switch (nmac) {
7635 case 5:
7636 memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
7637 fallthrough;
7638 case 4:
7639 memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
7640 fallthrough;
7641 case 3:
7642 memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
7643 fallthrough;
7644 case 2:
7645 memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
7646 }
7647 }
7648 if (rss_size)
7649 *rss_size = FW_VI_CMD_RSSSIZE_G(be16_to_cpu(c.rsssize_pkd));
7650
7651 if (vivld)
7652 *vivld = FW_VI_CMD_VFVLD_G(be32_to_cpu(c.alloc_to_len16));
7653
7654 if (vin)
7655 *vin = FW_VI_CMD_VIN_G(be32_to_cpu(c.alloc_to_len16));
7656
7657 return FW_VI_CMD_VIID_G(be16_to_cpu(c.type_viid));
7658 }
7659
7660 /**
7661 * t4_free_vi - free a virtual interface
7662 * @adap: the adapter
7663 * @mbox: mailbox to use for the FW command
7664 * @pf: the PF owning the VI
7665 * @vf: the VF owning the VI
7666 * @viid: virtual interface identifiler
7667 *
7668 * Free a previously allocated virtual interface.
7669 */
t4_free_vi(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int viid)7670 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf,
7671 unsigned int vf, unsigned int viid)
7672 {
7673 struct fw_vi_cmd c;
7674
7675 memset(&c, 0, sizeof(c));
7676 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_VI_CMD) |
7677 FW_CMD_REQUEST_F |
7678 FW_CMD_EXEC_F |
7679 FW_VI_CMD_PFN_V(pf) |
7680 FW_VI_CMD_VFN_V(vf));
7681 c.alloc_to_len16 = cpu_to_be32(FW_VI_CMD_FREE_F | FW_LEN16(c));
7682 c.type_viid = cpu_to_be16(FW_VI_CMD_VIID_V(viid));
7683
7684 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
7685 }
7686
7687 /**
7688 * t4_set_rxmode - set Rx properties of a virtual interface
7689 * @adap: the adapter
7690 * @mbox: mailbox to use for the FW command
7691 * @viid: the VI id
7692 * @viid_mirror: the mirror VI id
7693 * @mtu: the new MTU or -1
7694 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
7695 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
7696 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
7697 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
7698 * @sleep_ok: if true we may sleep while awaiting command completion
7699 *
7700 * Sets Rx properties of a virtual interface.
7701 */
t4_set_rxmode(struct adapter * adap,unsigned int mbox,unsigned int viid,unsigned int viid_mirror,int mtu,int promisc,int all_multi,int bcast,int vlanex,bool sleep_ok)7702 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
7703 unsigned int viid_mirror, int mtu, int promisc, int all_multi,
7704 int bcast, int vlanex, bool sleep_ok)
7705 {
7706 struct fw_vi_rxmode_cmd c, c_mirror;
7707 int ret;
7708
7709 /* convert to FW values */
7710 if (mtu < 0)
7711 mtu = FW_RXMODE_MTU_NO_CHG;
7712 if (promisc < 0)
7713 promisc = FW_VI_RXMODE_CMD_PROMISCEN_M;
7714 if (all_multi < 0)
7715 all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_M;
7716 if (bcast < 0)
7717 bcast = FW_VI_RXMODE_CMD_BROADCASTEN_M;
7718 if (vlanex < 0)
7719 vlanex = FW_VI_RXMODE_CMD_VLANEXEN_M;
7720
7721 memset(&c, 0, sizeof(c));
7722 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7723 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7724 FW_VI_RXMODE_CMD_VIID_V(viid));
7725 c.retval_len16 = cpu_to_be32(FW_LEN16(c));
7726 c.mtu_to_vlanexen =
7727 cpu_to_be32(FW_VI_RXMODE_CMD_MTU_V(mtu) |
7728 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc) |
7729 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi) |
7730 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast) |
7731 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex));
7732
7733 if (viid_mirror) {
7734 memcpy(&c_mirror, &c, sizeof(c_mirror));
7735 c_mirror.op_to_viid =
7736 cpu_to_be32(FW_CMD_OP_V(FW_VI_RXMODE_CMD) |
7737 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7738 FW_VI_RXMODE_CMD_VIID_V(viid_mirror));
7739 }
7740
7741 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
7742 if (ret)
7743 return ret;
7744
7745 if (viid_mirror)
7746 ret = t4_wr_mbox_meat(adap, mbox, &c_mirror, sizeof(c_mirror),
7747 NULL, sleep_ok);
7748
7749 return ret;
7750 }
7751
7752 /**
7753 * t4_free_encap_mac_filt - frees MPS entry at given index
7754 * @adap: the adapter
7755 * @viid: the VI id
7756 * @idx: index of MPS entry to be freed
7757 * @sleep_ok: call is allowed to sleep
7758 *
7759 * Frees the MPS entry at supplied index
7760 *
7761 * Returns a negative error number or zero on success
7762 */
t4_free_encap_mac_filt(struct adapter * adap,unsigned int viid,int idx,bool sleep_ok)7763 int t4_free_encap_mac_filt(struct adapter *adap, unsigned int viid,
7764 int idx, bool sleep_ok)
7765 {
7766 struct fw_vi_mac_exact *p;
7767 struct fw_vi_mac_cmd c;
7768 int ret = 0;
7769 u32 exact;
7770
7771 memset(&c, 0, sizeof(c));
7772 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7773 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7774 FW_CMD_EXEC_V(0) |
7775 FW_VI_MAC_CMD_VIID_V(viid));
7776 exact = FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC);
7777 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7778 exact |
7779 FW_CMD_LEN16_V(1));
7780 p = c.u.exact;
7781 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7782 FW_VI_MAC_CMD_IDX_V(idx));
7783 eth_zero_addr(p->macaddr);
7784 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7785 return ret;
7786 }
7787
7788 /**
7789 * t4_free_raw_mac_filt - Frees a raw mac entry in mps tcam
7790 * @adap: the adapter
7791 * @viid: the VI id
7792 * @addr: the MAC address
7793 * @mask: the mask
7794 * @idx: index of the entry in mps tcam
7795 * @lookup_type: MAC address for inner (1) or outer (0) header
7796 * @port_id: the port index
7797 * @sleep_ok: call is allowed to sleep
7798 *
7799 * Removes the mac entry at the specified index using raw mac interface.
7800 *
7801 * Returns a negative error number on failure.
7802 */
t4_free_raw_mac_filt(struct adapter * adap,unsigned int viid,const u8 * addr,const u8 * mask,unsigned int idx,u8 lookup_type,u8 port_id,bool sleep_ok)7803 int t4_free_raw_mac_filt(struct adapter *adap, unsigned int viid,
7804 const u8 *addr, const u8 *mask, unsigned int idx,
7805 u8 lookup_type, u8 port_id, bool sleep_ok)
7806 {
7807 struct fw_vi_mac_cmd c;
7808 struct fw_vi_mac_raw *p = &c.u.raw;
7809 u32 val;
7810
7811 memset(&c, 0, sizeof(c));
7812 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7813 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7814 FW_CMD_EXEC_V(0) |
7815 FW_VI_MAC_CMD_VIID_V(viid));
7816 val = FW_CMD_LEN16_V(1) |
7817 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7818 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
7819 FW_CMD_LEN16_V(val));
7820
7821 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx) |
7822 FW_VI_MAC_ID_BASED_FREE);
7823
7824 /* Lookup Type. Outer header: 0, Inner header: 1 */
7825 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7826 DATAPORTNUM_V(port_id));
7827 /* Lookup mask and port mask */
7828 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7829 DATAPORTNUM_V(DATAPORTNUM_M));
7830
7831 /* Copy the address and the mask */
7832 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7833 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7834
7835 return t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7836 }
7837
7838 /**
7839 * t4_alloc_encap_mac_filt - Adds a mac entry in mps tcam with VNI support
7840 * @adap: the adapter
7841 * @viid: the VI id
7842 * @addr: the MAC address
7843 * @mask: the mask
7844 * @vni: the VNI id for the tunnel protocol
7845 * @vni_mask: mask for the VNI id
7846 * @dip_hit: to enable DIP match for the MPS entry
7847 * @lookup_type: MAC address for inner (1) or outer (0) header
7848 * @sleep_ok: call is allowed to sleep
7849 *
7850 * Allocates an MPS entry with specified MAC address and VNI value.
7851 *
7852 * Returns a negative error number or the allocated index for this mac.
7853 */
t4_alloc_encap_mac_filt(struct adapter * adap,unsigned int viid,const u8 * addr,const u8 * mask,unsigned int vni,unsigned int vni_mask,u8 dip_hit,u8 lookup_type,bool sleep_ok)7854 int t4_alloc_encap_mac_filt(struct adapter *adap, unsigned int viid,
7855 const u8 *addr, const u8 *mask, unsigned int vni,
7856 unsigned int vni_mask, u8 dip_hit, u8 lookup_type,
7857 bool sleep_ok)
7858 {
7859 struct fw_vi_mac_cmd c;
7860 struct fw_vi_mac_vni *p = c.u.exact_vni;
7861 int ret = 0;
7862 u32 val;
7863
7864 memset(&c, 0, sizeof(c));
7865 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7866 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7867 FW_VI_MAC_CMD_VIID_V(viid));
7868 val = FW_CMD_LEN16_V(1) |
7869 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_EXACTMAC_VNI);
7870 c.freemacs_to_len16 = cpu_to_be32(val);
7871 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7872 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC));
7873 memcpy(p->macaddr, addr, sizeof(p->macaddr));
7874 memcpy(p->macaddr_mask, mask, sizeof(p->macaddr_mask));
7875
7876 p->lookup_type_to_vni =
7877 cpu_to_be32(FW_VI_MAC_CMD_VNI_V(vni) |
7878 FW_VI_MAC_CMD_DIP_HIT_V(dip_hit) |
7879 FW_VI_MAC_CMD_LOOKUP_TYPE_V(lookup_type));
7880 p->vni_mask_pkd = cpu_to_be32(FW_VI_MAC_CMD_VNI_MASK_V(vni_mask));
7881 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7882 if (ret == 0)
7883 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
7884 return ret;
7885 }
7886
7887 /**
7888 * t4_alloc_raw_mac_filt - Adds a mac entry in mps tcam
7889 * @adap: the adapter
7890 * @viid: the VI id
7891 * @addr: the MAC address
7892 * @mask: the mask
7893 * @idx: index at which to add this entry
7894 * @lookup_type: MAC address for inner (1) or outer (0) header
7895 * @port_id: the port index
7896 * @sleep_ok: call is allowed to sleep
7897 *
7898 * Adds the mac entry at the specified index using raw mac interface.
7899 *
7900 * Returns a negative error number or the allocated index for this mac.
7901 */
t4_alloc_raw_mac_filt(struct adapter * adap,unsigned int viid,const u8 * addr,const u8 * mask,unsigned int idx,u8 lookup_type,u8 port_id,bool sleep_ok)7902 int t4_alloc_raw_mac_filt(struct adapter *adap, unsigned int viid,
7903 const u8 *addr, const u8 *mask, unsigned int idx,
7904 u8 lookup_type, u8 port_id, bool sleep_ok)
7905 {
7906 int ret = 0;
7907 struct fw_vi_mac_cmd c;
7908 struct fw_vi_mac_raw *p = &c.u.raw;
7909 u32 val;
7910
7911 memset(&c, 0, sizeof(c));
7912 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7913 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
7914 FW_VI_MAC_CMD_VIID_V(viid));
7915 val = FW_CMD_LEN16_V(1) |
7916 FW_VI_MAC_CMD_ENTRY_TYPE_V(FW_VI_MAC_TYPE_RAW);
7917 c.freemacs_to_len16 = cpu_to_be32(val);
7918
7919 /* Specify that this is an inner mac address */
7920 p->raw_idx_pkd = cpu_to_be32(FW_VI_MAC_CMD_RAW_IDX_V(idx));
7921
7922 /* Lookup Type. Outer header: 0, Inner header: 1 */
7923 p->data0_pkd = cpu_to_be32(DATALKPTYPE_V(lookup_type) |
7924 DATAPORTNUM_V(port_id));
7925 /* Lookup mask and port mask */
7926 p->data0m_pkd = cpu_to_be64(DATALKPTYPE_V(DATALKPTYPE_M) |
7927 DATAPORTNUM_V(DATAPORTNUM_M));
7928
7929 /* Copy the address and the mask */
7930 memcpy((u8 *)&p->data1[0] + 2, addr, ETH_ALEN);
7931 memcpy((u8 *)&p->data1m[0] + 2, mask, ETH_ALEN);
7932
7933 ret = t4_wr_mbox_meat(adap, adap->mbox, &c, sizeof(c), &c, sleep_ok);
7934 if (ret == 0) {
7935 ret = FW_VI_MAC_CMD_RAW_IDX_G(be32_to_cpu(p->raw_idx_pkd));
7936 if (ret != idx)
7937 ret = -ENOMEM;
7938 }
7939
7940 return ret;
7941 }
7942
7943 /**
7944 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
7945 * @adap: the adapter
7946 * @mbox: mailbox to use for the FW command
7947 * @viid: the VI id
7948 * @free: if true any existing filters for this VI id are first removed
7949 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
7950 * @addr: the MAC address(es)
7951 * @idx: where to store the index of each allocated filter
7952 * @hash: pointer to hash address filter bitmap
7953 * @sleep_ok: call is allowed to sleep
7954 *
7955 * Allocates an exact-match filter for each of the supplied addresses and
7956 * sets it to the corresponding address. If @idx is not %NULL it should
7957 * have at least @naddr entries, each of which will be set to the index of
7958 * the filter allocated for the corresponding MAC address. If a filter
7959 * could not be allocated for an address its index is set to 0xffff.
7960 * If @hash is not %NULL addresses that fail to allocate an exact filter
7961 * are hashed and update the hash filter bitmap pointed at by @hash.
7962 *
7963 * Returns a negative error number or the number of filters allocated.
7964 */
t4_alloc_mac_filt(struct adapter * adap,unsigned int mbox,unsigned int viid,bool free,unsigned int naddr,const u8 ** addr,u16 * idx,u64 * hash,bool sleep_ok)7965 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
7966 unsigned int viid, bool free, unsigned int naddr,
7967 const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
7968 {
7969 int offset, ret = 0;
7970 struct fw_vi_mac_cmd c;
7971 unsigned int nfilters = 0;
7972 unsigned int max_naddr = adap->params.arch.mps_tcam_size;
7973 unsigned int rem = naddr;
7974
7975 if (naddr > max_naddr)
7976 return -EINVAL;
7977
7978 for (offset = 0; offset < naddr ; /**/) {
7979 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact) ?
7980 rem : ARRAY_SIZE(c.u.exact));
7981 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
7982 u.exact[fw_naddr]), 16);
7983 struct fw_vi_mac_exact *p;
7984 int i;
7985
7986 memset(&c, 0, sizeof(c));
7987 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
7988 FW_CMD_REQUEST_F |
7989 FW_CMD_WRITE_F |
7990 FW_CMD_EXEC_V(free) |
7991 FW_VI_MAC_CMD_VIID_V(viid));
7992 c.freemacs_to_len16 =
7993 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(free) |
7994 FW_CMD_LEN16_V(len16));
7995
7996 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
7997 p->valid_to_idx =
7998 cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
7999 FW_VI_MAC_CMD_IDX_V(
8000 FW_VI_MAC_ADD_MAC));
8001 memcpy(p->macaddr, addr[offset + i],
8002 sizeof(p->macaddr));
8003 }
8004
8005 /* It's okay if we run out of space in our MAC address arena.
8006 * Some of the addresses we submit may get stored so we need
8007 * to run through the reply to see what the results were ...
8008 */
8009 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8010 if (ret && ret != -FW_ENOMEM)
8011 break;
8012
8013 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8014 u16 index = FW_VI_MAC_CMD_IDX_G(
8015 be16_to_cpu(p->valid_to_idx));
8016
8017 if (idx)
8018 idx[offset + i] = (index >= max_naddr ?
8019 0xffff : index);
8020 if (index < max_naddr)
8021 nfilters++;
8022 else if (hash)
8023 *hash |= (1ULL <<
8024 hash_mac_addr(addr[offset + i]));
8025 }
8026
8027 free = false;
8028 offset += fw_naddr;
8029 rem -= fw_naddr;
8030 }
8031
8032 if (ret == 0 || ret == -FW_ENOMEM)
8033 ret = nfilters;
8034 return ret;
8035 }
8036
8037 /**
8038 * t4_free_mac_filt - frees exact-match filters of given MAC addresses
8039 * @adap: the adapter
8040 * @mbox: mailbox to use for the FW command
8041 * @viid: the VI id
8042 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
8043 * @addr: the MAC address(es)
8044 * @sleep_ok: call is allowed to sleep
8045 *
8046 * Frees the exact-match filter for each of the supplied addresses
8047 *
8048 * Returns a negative error number or the number of filters freed.
8049 */
t4_free_mac_filt(struct adapter * adap,unsigned int mbox,unsigned int viid,unsigned int naddr,const u8 ** addr,bool sleep_ok)8050 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox,
8051 unsigned int viid, unsigned int naddr,
8052 const u8 **addr, bool sleep_ok)
8053 {
8054 int offset, ret = 0;
8055 struct fw_vi_mac_cmd c;
8056 unsigned int nfilters = 0;
8057 unsigned int max_naddr = is_t4(adap->params.chip) ?
8058 NUM_MPS_CLS_SRAM_L_INSTANCES :
8059 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
8060 unsigned int rem = naddr;
8061
8062 if (naddr > max_naddr)
8063 return -EINVAL;
8064
8065 for (offset = 0; offset < (int)naddr ; /**/) {
8066 unsigned int fw_naddr = (rem < ARRAY_SIZE(c.u.exact)
8067 ? rem
8068 : ARRAY_SIZE(c.u.exact));
8069 size_t len16 = DIV_ROUND_UP(offsetof(struct fw_vi_mac_cmd,
8070 u.exact[fw_naddr]), 16);
8071 struct fw_vi_mac_exact *p;
8072 int i;
8073
8074 memset(&c, 0, sizeof(c));
8075 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8076 FW_CMD_REQUEST_F |
8077 FW_CMD_WRITE_F |
8078 FW_CMD_EXEC_V(0) |
8079 FW_VI_MAC_CMD_VIID_V(viid));
8080 c.freemacs_to_len16 =
8081 cpu_to_be32(FW_VI_MAC_CMD_FREEMACS_V(0) |
8082 FW_CMD_LEN16_V(len16));
8083
8084 for (i = 0, p = c.u.exact; i < (int)fw_naddr; i++, p++) {
8085 p->valid_to_idx = cpu_to_be16(
8086 FW_VI_MAC_CMD_VALID_F |
8087 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_MAC_BASED_FREE));
8088 memcpy(p->macaddr, addr[offset+i], sizeof(p->macaddr));
8089 }
8090
8091 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
8092 if (ret)
8093 break;
8094
8095 for (i = 0, p = c.u.exact; i < fw_naddr; i++, p++) {
8096 u16 index = FW_VI_MAC_CMD_IDX_G(
8097 be16_to_cpu(p->valid_to_idx));
8098
8099 if (index < max_naddr)
8100 nfilters++;
8101 }
8102
8103 offset += fw_naddr;
8104 rem -= fw_naddr;
8105 }
8106
8107 if (ret == 0)
8108 ret = nfilters;
8109 return ret;
8110 }
8111
8112 /**
8113 * t4_change_mac - modifies the exact-match filter for a MAC address
8114 * @adap: the adapter
8115 * @mbox: mailbox to use for the FW command
8116 * @viid: the VI id
8117 * @idx: index of existing filter for old value of MAC address, or -1
8118 * @addr: the new MAC address value
8119 * @persist: whether a new MAC allocation should be persistent
8120 * @smt_idx: the destination to store the new SMT index.
8121 *
8122 * Modifies an exact-match filter and sets it to the new MAC address.
8123 * Note that in general it is not possible to modify the value of a given
8124 * filter so the generic way to modify an address filter is to free the one
8125 * being used by the old address value and allocate a new filter for the
8126 * new address value. @idx can be -1 if the address is a new addition.
8127 *
8128 * Returns a negative error number or the index of the filter with the new
8129 * MAC value.
8130 */
t4_change_mac(struct adapter * adap,unsigned int mbox,unsigned int viid,int idx,const u8 * addr,bool persist,u8 * smt_idx)8131 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
8132 int idx, const u8 *addr, bool persist, u8 *smt_idx)
8133 {
8134 int ret, mode;
8135 struct fw_vi_mac_cmd c;
8136 struct fw_vi_mac_exact *p = c.u.exact;
8137 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size;
8138
8139 if (idx < 0) /* new allocation */
8140 idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
8141 mode = smt_idx ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
8142
8143 memset(&c, 0, sizeof(c));
8144 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8145 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8146 FW_VI_MAC_CMD_VIID_V(viid));
8147 c.freemacs_to_len16 = cpu_to_be32(FW_CMD_LEN16_V(1));
8148 p->valid_to_idx = cpu_to_be16(FW_VI_MAC_CMD_VALID_F |
8149 FW_VI_MAC_CMD_SMAC_RESULT_V(mode) |
8150 FW_VI_MAC_CMD_IDX_V(idx));
8151 memcpy(p->macaddr, addr, sizeof(p->macaddr));
8152
8153 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
8154 if (ret == 0) {
8155 ret = FW_VI_MAC_CMD_IDX_G(be16_to_cpu(p->valid_to_idx));
8156 if (ret >= max_mac_addr)
8157 ret = -ENOMEM;
8158 if (smt_idx) {
8159 if (adap->params.viid_smt_extn_support) {
8160 *smt_idx = FW_VI_MAC_CMD_SMTID_G
8161 (be32_to_cpu(c.op_to_viid));
8162 } else {
8163 /* In T4/T5, SMT contains 256 SMAC entries
8164 * organized in 128 rows of 2 entries each.
8165 * In T6, SMT contains 256 SMAC entries in
8166 * 256 rows.
8167 */
8168 if (CHELSIO_CHIP_VERSION(adap->params.chip) <=
8169 CHELSIO_T5)
8170 *smt_idx = (viid & FW_VIID_VIN_M) << 1;
8171 else
8172 *smt_idx = (viid & FW_VIID_VIN_M);
8173 }
8174 }
8175 }
8176 return ret;
8177 }
8178
8179 /**
8180 * t4_set_addr_hash - program the MAC inexact-match hash filter
8181 * @adap: the adapter
8182 * @mbox: mailbox to use for the FW command
8183 * @viid: the VI id
8184 * @ucast: whether the hash filter should also match unicast addresses
8185 * @vec: the value to be written to the hash filter
8186 * @sleep_ok: call is allowed to sleep
8187 *
8188 * Sets the 64-bit inexact-match hash filter for a virtual interface.
8189 */
t4_set_addr_hash(struct adapter * adap,unsigned int mbox,unsigned int viid,bool ucast,u64 vec,bool sleep_ok)8190 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
8191 bool ucast, u64 vec, bool sleep_ok)
8192 {
8193 struct fw_vi_mac_cmd c;
8194
8195 memset(&c, 0, sizeof(c));
8196 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_MAC_CMD) |
8197 FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
8198 FW_VI_ENABLE_CMD_VIID_V(viid));
8199 c.freemacs_to_len16 = cpu_to_be32(FW_VI_MAC_CMD_HASHVECEN_F |
8200 FW_VI_MAC_CMD_HASHUNIEN_V(ucast) |
8201 FW_CMD_LEN16_V(1));
8202 c.u.hash.hashvec = cpu_to_be64(vec);
8203 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
8204 }
8205
8206 /**
8207 * t4_enable_vi_params - enable/disable a virtual interface
8208 * @adap: the adapter
8209 * @mbox: mailbox to use for the FW command
8210 * @viid: the VI id
8211 * @rx_en: 1=enable Rx, 0=disable Rx
8212 * @tx_en: 1=enable Tx, 0=disable Tx
8213 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8214 *
8215 * Enables/disables a virtual interface. Note that setting DCB Enable
8216 * only makes sense when enabling a Virtual Interface ...
8217 */
t4_enable_vi_params(struct adapter * adap,unsigned int mbox,unsigned int viid,bool rx_en,bool tx_en,bool dcb_en)8218 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
8219 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en)
8220 {
8221 struct fw_vi_enable_cmd c;
8222
8223 memset(&c, 0, sizeof(c));
8224 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8225 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8226 FW_VI_ENABLE_CMD_VIID_V(viid));
8227 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_IEN_V(rx_en) |
8228 FW_VI_ENABLE_CMD_EEN_V(tx_en) |
8229 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en) |
8230 FW_LEN16(c));
8231 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL);
8232 }
8233
8234 /**
8235 * t4_enable_vi - enable/disable a virtual interface
8236 * @adap: the adapter
8237 * @mbox: mailbox to use for the FW command
8238 * @viid: the VI id
8239 * @rx_en: 1=enable Rx, 0=disable Rx
8240 * @tx_en: 1=enable Tx, 0=disable Tx
8241 *
8242 * Enables/disables a virtual interface.
8243 */
t4_enable_vi(struct adapter * adap,unsigned int mbox,unsigned int viid,bool rx_en,bool tx_en)8244 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
8245 bool rx_en, bool tx_en)
8246 {
8247 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0);
8248 }
8249
8250 /**
8251 * t4_enable_pi_params - enable/disable a Port's Virtual Interface
8252 * @adap: the adapter
8253 * @mbox: mailbox to use for the FW command
8254 * @pi: the Port Information structure
8255 * @rx_en: 1=enable Rx, 0=disable Rx
8256 * @tx_en: 1=enable Tx, 0=disable Tx
8257 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
8258 *
8259 * Enables/disables a Port's Virtual Interface. Note that setting DCB
8260 * Enable only makes sense when enabling a Virtual Interface ...
8261 * If the Virtual Interface enable/disable operation is successful,
8262 * we notify the OS-specific code of a potential Link Status change
8263 * via the OS Contract API t4_os_link_changed().
8264 */
t4_enable_pi_params(struct adapter * adap,unsigned int mbox,struct port_info * pi,bool rx_en,bool tx_en,bool dcb_en)8265 int t4_enable_pi_params(struct adapter *adap, unsigned int mbox,
8266 struct port_info *pi,
8267 bool rx_en, bool tx_en, bool dcb_en)
8268 {
8269 int ret = t4_enable_vi_params(adap, mbox, pi->viid,
8270 rx_en, tx_en, dcb_en);
8271 if (ret)
8272 return ret;
8273 t4_os_link_changed(adap, pi->port_id,
8274 rx_en && tx_en && pi->link_cfg.link_ok);
8275 return 0;
8276 }
8277
8278 /**
8279 * t4_identify_port - identify a VI's port by blinking its LED
8280 * @adap: the adapter
8281 * @mbox: mailbox to use for the FW command
8282 * @viid: the VI id
8283 * @nblinks: how many times to blink LED at 2.5 Hz
8284 *
8285 * Identifies a VI's port by blinking its LED.
8286 */
t4_identify_port(struct adapter * adap,unsigned int mbox,unsigned int viid,unsigned int nblinks)8287 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
8288 unsigned int nblinks)
8289 {
8290 struct fw_vi_enable_cmd c;
8291
8292 memset(&c, 0, sizeof(c));
8293 c.op_to_viid = cpu_to_be32(FW_CMD_OP_V(FW_VI_ENABLE_CMD) |
8294 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8295 FW_VI_ENABLE_CMD_VIID_V(viid));
8296 c.ien_to_len16 = cpu_to_be32(FW_VI_ENABLE_CMD_LED_F | FW_LEN16(c));
8297 c.blinkdur = cpu_to_be16(nblinks);
8298 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8299 }
8300
8301 /**
8302 * t4_iq_stop - stop an ingress queue and its FLs
8303 * @adap: the adapter
8304 * @mbox: mailbox to use for the FW command
8305 * @pf: the PF owning the queues
8306 * @vf: the VF owning the queues
8307 * @iqtype: the ingress queue type (FW_IQ_TYPE_FL_INT_CAP, etc.)
8308 * @iqid: ingress queue id
8309 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8310 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8311 *
8312 * Stops an ingress queue and its associated FLs, if any. This causes
8313 * any current or future data/messages destined for these queues to be
8314 * tossed.
8315 */
t4_iq_stop(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int iqtype,unsigned int iqid,unsigned int fl0id,unsigned int fl1id)8316 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
8317 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8318 unsigned int fl0id, unsigned int fl1id)
8319 {
8320 struct fw_iq_cmd c;
8321
8322 memset(&c, 0, sizeof(c));
8323 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8324 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8325 FW_IQ_CMD_VFN_V(vf));
8326 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_IQSTOP_F | FW_LEN16(c));
8327 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8328 c.iqid = cpu_to_be16(iqid);
8329 c.fl0id = cpu_to_be16(fl0id);
8330 c.fl1id = cpu_to_be16(fl1id);
8331 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8332 }
8333
8334 /**
8335 * t4_iq_free - free an ingress queue and its FLs
8336 * @adap: the adapter
8337 * @mbox: mailbox to use for the FW command
8338 * @pf: the PF owning the queues
8339 * @vf: the VF owning the queues
8340 * @iqtype: the ingress queue type
8341 * @iqid: ingress queue id
8342 * @fl0id: FL0 queue id or 0xffff if no attached FL0
8343 * @fl1id: FL1 queue id or 0xffff if no attached FL1
8344 *
8345 * Frees an ingress queue and its associated FLs, if any.
8346 */
t4_iq_free(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int iqtype,unsigned int iqid,unsigned int fl0id,unsigned int fl1id)8347 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8348 unsigned int vf, unsigned int iqtype, unsigned int iqid,
8349 unsigned int fl0id, unsigned int fl1id)
8350 {
8351 struct fw_iq_cmd c;
8352
8353 memset(&c, 0, sizeof(c));
8354 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_IQ_CMD) | FW_CMD_REQUEST_F |
8355 FW_CMD_EXEC_F | FW_IQ_CMD_PFN_V(pf) |
8356 FW_IQ_CMD_VFN_V(vf));
8357 c.alloc_to_len16 = cpu_to_be32(FW_IQ_CMD_FREE_F | FW_LEN16(c));
8358 c.type_to_iqandstindex = cpu_to_be32(FW_IQ_CMD_TYPE_V(iqtype));
8359 c.iqid = cpu_to_be16(iqid);
8360 c.fl0id = cpu_to_be16(fl0id);
8361 c.fl1id = cpu_to_be16(fl1id);
8362 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8363 }
8364
8365 /**
8366 * t4_eth_eq_free - free an Ethernet egress queue
8367 * @adap: the adapter
8368 * @mbox: mailbox to use for the FW command
8369 * @pf: the PF owning the queue
8370 * @vf: the VF owning the queue
8371 * @eqid: egress queue id
8372 *
8373 * Frees an Ethernet egress queue.
8374 */
t4_eth_eq_free(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int eqid)8375 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8376 unsigned int vf, unsigned int eqid)
8377 {
8378 struct fw_eq_eth_cmd c;
8379
8380 memset(&c, 0, sizeof(c));
8381 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_ETH_CMD) |
8382 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8383 FW_EQ_ETH_CMD_PFN_V(pf) |
8384 FW_EQ_ETH_CMD_VFN_V(vf));
8385 c.alloc_to_len16 = cpu_to_be32(FW_EQ_ETH_CMD_FREE_F | FW_LEN16(c));
8386 c.eqid_pkd = cpu_to_be32(FW_EQ_ETH_CMD_EQID_V(eqid));
8387 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8388 }
8389
8390 /**
8391 * t4_ctrl_eq_free - free a control egress queue
8392 * @adap: the adapter
8393 * @mbox: mailbox to use for the FW command
8394 * @pf: the PF owning the queue
8395 * @vf: the VF owning the queue
8396 * @eqid: egress queue id
8397 *
8398 * Frees a control egress queue.
8399 */
t4_ctrl_eq_free(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int eqid)8400 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8401 unsigned int vf, unsigned int eqid)
8402 {
8403 struct fw_eq_ctrl_cmd c;
8404
8405 memset(&c, 0, sizeof(c));
8406 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_CTRL_CMD) |
8407 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8408 FW_EQ_CTRL_CMD_PFN_V(pf) |
8409 FW_EQ_CTRL_CMD_VFN_V(vf));
8410 c.alloc_to_len16 = cpu_to_be32(FW_EQ_CTRL_CMD_FREE_F | FW_LEN16(c));
8411 c.cmpliqid_eqid = cpu_to_be32(FW_EQ_CTRL_CMD_EQID_V(eqid));
8412 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8413 }
8414
8415 /**
8416 * t4_ofld_eq_free - free an offload egress queue
8417 * @adap: the adapter
8418 * @mbox: mailbox to use for the FW command
8419 * @pf: the PF owning the queue
8420 * @vf: the VF owning the queue
8421 * @eqid: egress queue id
8422 *
8423 * Frees a control egress queue.
8424 */
t4_ofld_eq_free(struct adapter * adap,unsigned int mbox,unsigned int pf,unsigned int vf,unsigned int eqid)8425 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
8426 unsigned int vf, unsigned int eqid)
8427 {
8428 struct fw_eq_ofld_cmd c;
8429
8430 memset(&c, 0, sizeof(c));
8431 c.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_EQ_OFLD_CMD) |
8432 FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
8433 FW_EQ_OFLD_CMD_PFN_V(pf) |
8434 FW_EQ_OFLD_CMD_VFN_V(vf));
8435 c.alloc_to_len16 = cpu_to_be32(FW_EQ_OFLD_CMD_FREE_F | FW_LEN16(c));
8436 c.eqid_pkd = cpu_to_be32(FW_EQ_OFLD_CMD_EQID_V(eqid));
8437 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
8438 }
8439
8440 /**
8441 * t4_link_down_rc_str - return a string for a Link Down Reason Code
8442 * @link_down_rc: Link Down Reason Code
8443 *
8444 * Returns a string representation of the Link Down Reason Code.
8445 */
t4_link_down_rc_str(unsigned char link_down_rc)8446 static const char *t4_link_down_rc_str(unsigned char link_down_rc)
8447 {
8448 static const char * const reason[] = {
8449 "Link Down",
8450 "Remote Fault",
8451 "Auto-negotiation Failure",
8452 "Reserved",
8453 "Insufficient Airflow",
8454 "Unable To Determine Reason",
8455 "No RX Signal Detected",
8456 "Reserved",
8457 };
8458
8459 if (link_down_rc >= ARRAY_SIZE(reason))
8460 return "Bad Reason Code";
8461
8462 return reason[link_down_rc];
8463 }
8464
8465 /* Return the highest speed set in the port capabilities, in Mb/s. */
fwcap_to_speed(fw_port_cap32_t caps)8466 static unsigned int fwcap_to_speed(fw_port_cap32_t caps)
8467 {
8468 #define TEST_SPEED_RETURN(__caps_speed, __speed) \
8469 do { \
8470 if (caps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8471 return __speed; \
8472 } while (0)
8473
8474 TEST_SPEED_RETURN(400G, 400000);
8475 TEST_SPEED_RETURN(200G, 200000);
8476 TEST_SPEED_RETURN(100G, 100000);
8477 TEST_SPEED_RETURN(50G, 50000);
8478 TEST_SPEED_RETURN(40G, 40000);
8479 TEST_SPEED_RETURN(25G, 25000);
8480 TEST_SPEED_RETURN(10G, 10000);
8481 TEST_SPEED_RETURN(1G, 1000);
8482 TEST_SPEED_RETURN(100M, 100);
8483
8484 #undef TEST_SPEED_RETURN
8485
8486 return 0;
8487 }
8488
8489 /**
8490 * fwcap_to_fwspeed - return highest speed in Port Capabilities
8491 * @acaps: advertised Port Capabilities
8492 *
8493 * Get the highest speed for the port from the advertised Port
8494 * Capabilities. It will be either the highest speed from the list of
8495 * speeds or whatever user has set using ethtool.
8496 */
fwcap_to_fwspeed(fw_port_cap32_t acaps)8497 static fw_port_cap32_t fwcap_to_fwspeed(fw_port_cap32_t acaps)
8498 {
8499 #define TEST_SPEED_RETURN(__caps_speed) \
8500 do { \
8501 if (acaps & FW_PORT_CAP32_SPEED_##__caps_speed) \
8502 return FW_PORT_CAP32_SPEED_##__caps_speed; \
8503 } while (0)
8504
8505 TEST_SPEED_RETURN(400G);
8506 TEST_SPEED_RETURN(200G);
8507 TEST_SPEED_RETURN(100G);
8508 TEST_SPEED_RETURN(50G);
8509 TEST_SPEED_RETURN(40G);
8510 TEST_SPEED_RETURN(25G);
8511 TEST_SPEED_RETURN(10G);
8512 TEST_SPEED_RETURN(1G);
8513 TEST_SPEED_RETURN(100M);
8514
8515 #undef TEST_SPEED_RETURN
8516
8517 return 0;
8518 }
8519
8520 /**
8521 * lstatus_to_fwcap - translate old lstatus to 32-bit Port Capabilities
8522 * @lstatus: old FW_PORT_ACTION_GET_PORT_INFO lstatus value
8523 *
8524 * Translates old FW_PORT_ACTION_GET_PORT_INFO lstatus field into new
8525 * 32-bit Port Capabilities value.
8526 */
lstatus_to_fwcap(u32 lstatus)8527 static fw_port_cap32_t lstatus_to_fwcap(u32 lstatus)
8528 {
8529 fw_port_cap32_t linkattr = 0;
8530
8531 /* Unfortunately the format of the Link Status in the old
8532 * 16-bit Port Information message isn't the same as the
8533 * 16-bit Port Capabilities bitfield used everywhere else ...
8534 */
8535 if (lstatus & FW_PORT_CMD_RXPAUSE_F)
8536 linkattr |= FW_PORT_CAP32_FC_RX;
8537 if (lstatus & FW_PORT_CMD_TXPAUSE_F)
8538 linkattr |= FW_PORT_CAP32_FC_TX;
8539 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M))
8540 linkattr |= FW_PORT_CAP32_SPEED_100M;
8541 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G))
8542 linkattr |= FW_PORT_CAP32_SPEED_1G;
8543 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G))
8544 linkattr |= FW_PORT_CAP32_SPEED_10G;
8545 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_25G))
8546 linkattr |= FW_PORT_CAP32_SPEED_25G;
8547 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G))
8548 linkattr |= FW_PORT_CAP32_SPEED_40G;
8549 if (lstatus & FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100G))
8550 linkattr |= FW_PORT_CAP32_SPEED_100G;
8551
8552 return linkattr;
8553 }
8554
8555 /**
8556 * t4_handle_get_port_info - process a FW reply message
8557 * @pi: the port info
8558 * @rpl: start of the FW message
8559 *
8560 * Processes a GET_PORT_INFO FW reply message.
8561 */
t4_handle_get_port_info(struct port_info * pi,const __be64 * rpl)8562 void t4_handle_get_port_info(struct port_info *pi, const __be64 *rpl)
8563 {
8564 const struct fw_port_cmd *cmd = (const void *)rpl;
8565 fw_port_cap32_t pcaps, acaps, lpacaps, linkattr;
8566 struct link_config *lc = &pi->link_cfg;
8567 struct adapter *adapter = pi->adapter;
8568 unsigned int speed, fc, fec, adv_fc;
8569 enum fw_port_module_type mod_type;
8570 int action, link_ok, linkdnrc;
8571 enum fw_port_type port_type;
8572
8573 /* Extract the various fields from the Port Information message.
8574 */
8575 action = FW_PORT_CMD_ACTION_G(be32_to_cpu(cmd->action_to_len16));
8576 switch (action) {
8577 case FW_PORT_ACTION_GET_PORT_INFO: {
8578 u32 lstatus = be32_to_cpu(cmd->u.info.lstatus_to_modtype);
8579
8580 link_ok = (lstatus & FW_PORT_CMD_LSTATUS_F) != 0;
8581 linkdnrc = FW_PORT_CMD_LINKDNRC_G(lstatus);
8582 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
8583 mod_type = FW_PORT_CMD_MODTYPE_G(lstatus);
8584 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.pcap));
8585 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.acap));
8586 lpacaps = fwcaps16_to_caps32(be16_to_cpu(cmd->u.info.lpacap));
8587 linkattr = lstatus_to_fwcap(lstatus);
8588 break;
8589 }
8590
8591 case FW_PORT_ACTION_GET_PORT_INFO32: {
8592 u32 lstatus32;
8593
8594 lstatus32 = be32_to_cpu(cmd->u.info32.lstatus32_to_cbllen32);
8595 link_ok = (lstatus32 & FW_PORT_CMD_LSTATUS32_F) != 0;
8596 linkdnrc = FW_PORT_CMD_LINKDNRC32_G(lstatus32);
8597 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
8598 mod_type = FW_PORT_CMD_MODTYPE32_G(lstatus32);
8599 pcaps = be32_to_cpu(cmd->u.info32.pcaps32);
8600 acaps = be32_to_cpu(cmd->u.info32.acaps32);
8601 lpacaps = be32_to_cpu(cmd->u.info32.lpacaps32);
8602 linkattr = be32_to_cpu(cmd->u.info32.linkattr32);
8603 break;
8604 }
8605
8606 default:
8607 dev_err(adapter->pdev_dev, "Handle Port Information: Bad Command/Action %#x\n",
8608 be32_to_cpu(cmd->action_to_len16));
8609 return;
8610 }
8611
8612 fec = fwcap_to_cc_fec(acaps);
8613 adv_fc = fwcap_to_cc_pause(acaps);
8614 fc = fwcap_to_cc_pause(linkattr);
8615 speed = fwcap_to_speed(linkattr);
8616
8617 /* Reset state for communicating new Transceiver Module status and
8618 * whether the OS-dependent layer wants us to redo the current
8619 * "sticky" L1 Configure Link Parameters.
8620 */
8621 lc->new_module = false;
8622 lc->redo_l1cfg = false;
8623
8624 if (mod_type != pi->mod_type) {
8625 /* With the newer SFP28 and QSFP28 Transceiver Module Types,
8626 * various fundamental Port Capabilities which used to be
8627 * immutable can now change radically. We can now have
8628 * Speeds, Auto-Negotiation, Forward Error Correction, etc.
8629 * all change based on what Transceiver Module is inserted.
8630 * So we need to record the Physical "Port" Capabilities on
8631 * every Transceiver Module change.
8632 */
8633 lc->pcaps = pcaps;
8634
8635 /* When a new Transceiver Module is inserted, the Firmware
8636 * will examine its i2c EPROM to determine its type and
8637 * general operating parameters including things like Forward
8638 * Error Control, etc. Various IEEE 802.3 standards dictate
8639 * how to interpret these i2c values to determine default
8640 * "sutomatic" settings. We record these for future use when
8641 * the user explicitly requests these standards-based values.
8642 */
8643 lc->def_acaps = acaps;
8644
8645 /* Some versions of the early T6 Firmware "cheated" when
8646 * handling different Transceiver Modules by changing the
8647 * underlaying Port Type reported to the Host Drivers. As
8648 * such we need to capture whatever Port Type the Firmware
8649 * sends us and record it in case it's different from what we
8650 * were told earlier. Unfortunately, since Firmware is
8651 * forever, we'll need to keep this code here forever, but in
8652 * later T6 Firmware it should just be an assignment of the
8653 * same value already recorded.
8654 */
8655 pi->port_type = port_type;
8656
8657 /* Record new Module Type information.
8658 */
8659 pi->mod_type = mod_type;
8660
8661 /* Let the OS-dependent layer know if we have a new
8662 * Transceiver Module inserted.
8663 */
8664 lc->new_module = t4_is_inserted_mod_type(mod_type);
8665
8666 t4_os_portmod_changed(adapter, pi->port_id);
8667 }
8668
8669 if (link_ok != lc->link_ok || speed != lc->speed ||
8670 fc != lc->fc || adv_fc != lc->advertised_fc ||
8671 fec != lc->fec) {
8672 /* something changed */
8673 if (!link_ok && lc->link_ok) {
8674 lc->link_down_rc = linkdnrc;
8675 dev_warn_ratelimited(adapter->pdev_dev,
8676 "Port %d link down, reason: %s\n",
8677 pi->tx_chan,
8678 t4_link_down_rc_str(linkdnrc));
8679 }
8680 lc->link_ok = link_ok;
8681 lc->speed = speed;
8682 lc->advertised_fc = adv_fc;
8683 lc->fc = fc;
8684 lc->fec = fec;
8685
8686 lc->lpacaps = lpacaps;
8687 lc->acaps = acaps & ADVERT_MASK;
8688
8689 /* If we're not physically capable of Auto-Negotiation, note
8690 * this as Auto-Negotiation disabled. Otherwise, we track
8691 * what Auto-Negotiation settings we have. Note parallel
8692 * structure in t4_link_l1cfg_core() and init_link_config().
8693 */
8694 if (!(lc->acaps & FW_PORT_CAP32_ANEG)) {
8695 lc->autoneg = AUTONEG_DISABLE;
8696 } else if (lc->acaps & FW_PORT_CAP32_ANEG) {
8697 lc->autoneg = AUTONEG_ENABLE;
8698 } else {
8699 /* When Autoneg is disabled, user needs to set
8700 * single speed.
8701 * Similar to cxgb4_ethtool.c: set_link_ksettings
8702 */
8703 lc->acaps = 0;
8704 lc->speed_caps = fwcap_to_fwspeed(acaps);
8705 lc->autoneg = AUTONEG_DISABLE;
8706 }
8707
8708 t4_os_link_changed(adapter, pi->port_id, link_ok);
8709 }
8710
8711 /* If we have a new Transceiver Module and the OS-dependent code has
8712 * told us that it wants us to redo whatever "sticky" L1 Configuration
8713 * Link Parameters are set, do that now.
8714 */
8715 if (lc->new_module && lc->redo_l1cfg) {
8716 struct link_config old_lc;
8717 int ret;
8718
8719 /* Save the current L1 Configuration and restore it if an
8720 * error occurs. We probably should fix the l1_cfg*()
8721 * routines not to change the link_config when an error
8722 * occurs ...
8723 */
8724 old_lc = *lc;
8725 ret = t4_link_l1cfg_ns(adapter, adapter->mbox, pi->lport, lc);
8726 if (ret) {
8727 *lc = old_lc;
8728 dev_warn(adapter->pdev_dev,
8729 "Attempt to update new Transceiver Module settings failed\n");
8730 }
8731 }
8732 lc->new_module = false;
8733 lc->redo_l1cfg = false;
8734 }
8735
8736 /**
8737 * t4_update_port_info - retrieve and update port information if changed
8738 * @pi: the port_info
8739 *
8740 * We issue a Get Port Information Command to the Firmware and, if
8741 * successful, we check to see if anything is different from what we
8742 * last recorded and update things accordingly.
8743 */
t4_update_port_info(struct port_info * pi)8744 int t4_update_port_info(struct port_info *pi)
8745 {
8746 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8747 struct fw_port_cmd port_cmd;
8748 int ret;
8749
8750 memset(&port_cmd, 0, sizeof(port_cmd));
8751 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8752 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8753 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8754 port_cmd.action_to_len16 = cpu_to_be32(
8755 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
8756 ? FW_PORT_ACTION_GET_PORT_INFO
8757 : FW_PORT_ACTION_GET_PORT_INFO32) |
8758 FW_LEN16(port_cmd));
8759 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8760 &port_cmd, sizeof(port_cmd), &port_cmd);
8761 if (ret)
8762 return ret;
8763
8764 t4_handle_get_port_info(pi, (__be64 *)&port_cmd);
8765 return 0;
8766 }
8767
8768 /**
8769 * t4_get_link_params - retrieve basic link parameters for given port
8770 * @pi: the port
8771 * @link_okp: value return pointer for link up/down
8772 * @speedp: value return pointer for speed (Mb/s)
8773 * @mtup: value return pointer for mtu
8774 *
8775 * Retrieves basic link parameters for a port: link up/down, speed (Mb/s),
8776 * and MTU for a specified port. A negative error is returned on
8777 * failure; 0 on success.
8778 */
t4_get_link_params(struct port_info * pi,unsigned int * link_okp,unsigned int * speedp,unsigned int * mtup)8779 int t4_get_link_params(struct port_info *pi, unsigned int *link_okp,
8780 unsigned int *speedp, unsigned int *mtup)
8781 {
8782 unsigned int fw_caps = pi->adapter->params.fw_caps_support;
8783 unsigned int action, link_ok, mtu;
8784 struct fw_port_cmd port_cmd;
8785 fw_port_cap32_t linkattr;
8786 int ret;
8787
8788 memset(&port_cmd, 0, sizeof(port_cmd));
8789 port_cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
8790 FW_CMD_REQUEST_F | FW_CMD_READ_F |
8791 FW_PORT_CMD_PORTID_V(pi->tx_chan));
8792 action = (fw_caps == FW_CAPS16
8793 ? FW_PORT_ACTION_GET_PORT_INFO
8794 : FW_PORT_ACTION_GET_PORT_INFO32);
8795 port_cmd.action_to_len16 = cpu_to_be32(
8796 FW_PORT_CMD_ACTION_V(action) |
8797 FW_LEN16(port_cmd));
8798 ret = t4_wr_mbox(pi->adapter, pi->adapter->mbox,
8799 &port_cmd, sizeof(port_cmd), &port_cmd);
8800 if (ret)
8801 return ret;
8802
8803 if (action == FW_PORT_ACTION_GET_PORT_INFO) {
8804 u32 lstatus = be32_to_cpu(port_cmd.u.info.lstatus_to_modtype);
8805
8806 link_ok = !!(lstatus & FW_PORT_CMD_LSTATUS_F);
8807 linkattr = lstatus_to_fwcap(lstatus);
8808 mtu = be16_to_cpu(port_cmd.u.info.mtu);
8809 } else {
8810 u32 lstatus32 =
8811 be32_to_cpu(port_cmd.u.info32.lstatus32_to_cbllen32);
8812
8813 link_ok = !!(lstatus32 & FW_PORT_CMD_LSTATUS32_F);
8814 linkattr = be32_to_cpu(port_cmd.u.info32.linkattr32);
8815 mtu = FW_PORT_CMD_MTU32_G(
8816 be32_to_cpu(port_cmd.u.info32.auxlinfo32_mtu32));
8817 }
8818
8819 if (link_okp)
8820 *link_okp = link_ok;
8821 if (speedp)
8822 *speedp = fwcap_to_speed(linkattr);
8823 if (mtup)
8824 *mtup = mtu;
8825
8826 return 0;
8827 }
8828
8829 /**
8830 * t4_handle_fw_rpl - process a FW reply message
8831 * @adap: the adapter
8832 * @rpl: start of the FW message
8833 *
8834 * Processes a FW message, such as link state change messages.
8835 */
t4_handle_fw_rpl(struct adapter * adap,const __be64 * rpl)8836 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
8837 {
8838 u8 opcode = *(const u8 *)rpl;
8839
8840 /* This might be a port command ... this simplifies the following
8841 * conditionals ... We can get away with pre-dereferencing
8842 * action_to_len16 because it's in the first 16 bytes and all messages
8843 * will be at least that long.
8844 */
8845 const struct fw_port_cmd *p = (const void *)rpl;
8846 unsigned int action =
8847 FW_PORT_CMD_ACTION_G(be32_to_cpu(p->action_to_len16));
8848
8849 if (opcode == FW_PORT_CMD &&
8850 (action == FW_PORT_ACTION_GET_PORT_INFO ||
8851 action == FW_PORT_ACTION_GET_PORT_INFO32)) {
8852 int i;
8853 int chan = FW_PORT_CMD_PORTID_G(be32_to_cpu(p->op_to_portid));
8854 struct port_info *pi = NULL;
8855
8856 for_each_port(adap, i) {
8857 pi = adap2pinfo(adap, i);
8858 if (pi->tx_chan == chan)
8859 break;
8860 }
8861
8862 t4_handle_get_port_info(pi, rpl);
8863 } else {
8864 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n",
8865 opcode);
8866 return -EINVAL;
8867 }
8868 return 0;
8869 }
8870
get_pci_mode(struct adapter * adapter,struct pci_params * p)8871 static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
8872 {
8873 u16 val;
8874
8875 if (pci_is_pcie(adapter->pdev)) {
8876 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
8877 p->speed = val & PCI_EXP_LNKSTA_CLS;
8878 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
8879 }
8880 }
8881
8882 /**
8883 * init_link_config - initialize a link's SW state
8884 * @lc: pointer to structure holding the link state
8885 * @pcaps: link Port Capabilities
8886 * @acaps: link current Advertised Port Capabilities
8887 *
8888 * Initializes the SW state maintained for each link, including the link's
8889 * capabilities and default speed/flow-control/autonegotiation settings.
8890 */
init_link_config(struct link_config * lc,fw_port_cap32_t pcaps,fw_port_cap32_t acaps)8891 static void init_link_config(struct link_config *lc, fw_port_cap32_t pcaps,
8892 fw_port_cap32_t acaps)
8893 {
8894 lc->pcaps = pcaps;
8895 lc->def_acaps = acaps;
8896 lc->lpacaps = 0;
8897 lc->speed_caps = 0;
8898 lc->speed = 0;
8899 lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
8900
8901 /* For Forward Error Control, we default to whatever the Firmware
8902 * tells us the Link is currently advertising.
8903 */
8904 lc->requested_fec = FEC_AUTO;
8905 lc->fec = fwcap_to_cc_fec(lc->def_acaps);
8906
8907 /* If the Port is capable of Auto-Negtotiation, initialize it as
8908 * "enabled" and copy over all of the Physical Port Capabilities
8909 * to the Advertised Port Capabilities. Otherwise mark it as
8910 * Auto-Negotiate disabled and select the highest supported speed
8911 * for the link. Note parallel structure in t4_link_l1cfg_core()
8912 * and t4_handle_get_port_info().
8913 */
8914 if (lc->pcaps & FW_PORT_CAP32_ANEG) {
8915 lc->acaps = lc->pcaps & ADVERT_MASK;
8916 lc->autoneg = AUTONEG_ENABLE;
8917 lc->requested_fc |= PAUSE_AUTONEG;
8918 } else {
8919 lc->acaps = 0;
8920 lc->autoneg = AUTONEG_DISABLE;
8921 lc->speed_caps = fwcap_to_fwspeed(acaps);
8922 }
8923 }
8924
8925 #define CIM_PF_NOACCESS 0xeeeeeeee
8926
t4_wait_dev_ready(void __iomem * regs)8927 int t4_wait_dev_ready(void __iomem *regs)
8928 {
8929 u32 whoami;
8930
8931 whoami = readl(regs + PL_WHOAMI_A);
8932 if (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS)
8933 return 0;
8934
8935 msleep(500);
8936 whoami = readl(regs + PL_WHOAMI_A);
8937 return (whoami != 0xffffffff && whoami != CIM_PF_NOACCESS ? 0 : -EIO);
8938 }
8939
8940 struct flash_desc {
8941 u32 vendor_and_model_id;
8942 u32 size_mb;
8943 };
8944
t4_get_flash_params(struct adapter * adap)8945 static int t4_get_flash_params(struct adapter *adap)
8946 {
8947 /* Table for non-Numonix supported flash parts. Numonix parts are left
8948 * to the preexisting code. All flash parts have 64KB sectors.
8949 */
8950 static struct flash_desc supported_flash[] = {
8951 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
8952 };
8953
8954 unsigned int part, manufacturer;
8955 unsigned int density, size = 0;
8956 u32 flashid = 0;
8957 int ret;
8958
8959 /* Issue a Read ID Command to the Flash part. We decode supported
8960 * Flash parts and their sizes from this. There's a newer Query
8961 * Command which can retrieve detailed geometry information but many
8962 * Flash parts don't support it.
8963 */
8964
8965 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
8966 if (!ret)
8967 ret = sf1_read(adap, 3, 0, 1, &flashid);
8968 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */
8969 if (ret)
8970 return ret;
8971
8972 /* Check to see if it's one of our non-standard supported Flash parts.
8973 */
8974 for (part = 0; part < ARRAY_SIZE(supported_flash); part++)
8975 if (supported_flash[part].vendor_and_model_id == flashid) {
8976 adap->params.sf_size = supported_flash[part].size_mb;
8977 adap->params.sf_nsec =
8978 adap->params.sf_size / SF_SEC_SIZE;
8979 goto found;
8980 }
8981
8982 /* Decode Flash part size. The code below looks repetitive with
8983 * common encodings, but that's not guaranteed in the JEDEC
8984 * specification for the Read JEDEC ID command. The only thing that
8985 * we're guaranteed by the JEDEC specification is where the
8986 * Manufacturer ID is in the returned result. After that each
8987 * Manufacturer ~could~ encode things completely differently.
8988 * Note, all Flash parts must have 64KB sectors.
8989 */
8990 manufacturer = flashid & 0xff;
8991 switch (manufacturer) {
8992 case 0x20: { /* Micron/Numonix */
8993 /* This Density -> Size decoding table is taken from Micron
8994 * Data Sheets.
8995 */
8996 density = (flashid >> 16) & 0xff;
8997 switch (density) {
8998 case 0x14: /* 1MB */
8999 size = 1 << 20;
9000 break;
9001 case 0x15: /* 2MB */
9002 size = 1 << 21;
9003 break;
9004 case 0x16: /* 4MB */
9005 size = 1 << 22;
9006 break;
9007 case 0x17: /* 8MB */
9008 size = 1 << 23;
9009 break;
9010 case 0x18: /* 16MB */
9011 size = 1 << 24;
9012 break;
9013 case 0x19: /* 32MB */
9014 size = 1 << 25;
9015 break;
9016 case 0x20: /* 64MB */
9017 size = 1 << 26;
9018 break;
9019 case 0x21: /* 128MB */
9020 size = 1 << 27;
9021 break;
9022 case 0x22: /* 256MB */
9023 size = 1 << 28;
9024 break;
9025 }
9026 break;
9027 }
9028 case 0x9d: { /* ISSI -- Integrated Silicon Solution, Inc. */
9029 /* This Density -> Size decoding table is taken from ISSI
9030 * Data Sheets.
9031 */
9032 density = (flashid >> 16) & 0xff;
9033 switch (density) {
9034 case 0x16: /* 32 MB */
9035 size = 1 << 25;
9036 break;
9037 case 0x17: /* 64MB */
9038 size = 1 << 26;
9039 break;
9040 }
9041 break;
9042 }
9043 case 0xc2: { /* Macronix */
9044 /* This Density -> Size decoding table is taken from Macronix
9045 * Data Sheets.
9046 */
9047 density = (flashid >> 16) & 0xff;
9048 switch (density) {
9049 case 0x17: /* 8MB */
9050 size = 1 << 23;
9051 break;
9052 case 0x18: /* 16MB */
9053 size = 1 << 24;
9054 break;
9055 }
9056 break;
9057 }
9058 case 0xef: { /* Winbond */
9059 /* This Density -> Size decoding table is taken from Winbond
9060 * Data Sheets.
9061 */
9062 density = (flashid >> 16) & 0xff;
9063 switch (density) {
9064 case 0x17: /* 8MB */
9065 size = 1 << 23;
9066 break;
9067 case 0x18: /* 16MB */
9068 size = 1 << 24;
9069 break;
9070 }
9071 break;
9072 }
9073 }
9074
9075 /* If we didn't recognize the FLASH part, that's no real issue: the
9076 * Hardware/Software contract says that Hardware will _*ALWAYS*_
9077 * use a FLASH part which is at least 4MB in size and has 64KB
9078 * sectors. The unrecognized FLASH part is likely to be much larger
9079 * than 4MB, but that's all we really need.
9080 */
9081 if (size == 0) {
9082 dev_warn(adap->pdev_dev, "Unknown Flash Part, ID = %#x, assuming 4MB\n",
9083 flashid);
9084 size = 1 << 22;
9085 }
9086
9087 /* Store decoded Flash size and fall through into vetting code. */
9088 adap->params.sf_size = size;
9089 adap->params.sf_nsec = size / SF_SEC_SIZE;
9090
9091 found:
9092 if (adap->params.sf_size < FLASH_MIN_SIZE)
9093 dev_warn(adap->pdev_dev, "WARNING: Flash Part ID %#x, size %#x < %#x\n",
9094 flashid, adap->params.sf_size, FLASH_MIN_SIZE);
9095 return 0;
9096 }
9097
9098 /**
9099 * t4_prep_adapter - prepare SW and HW for operation
9100 * @adapter: the adapter
9101 *
9102 * Initialize adapter SW state for the various HW modules, set initial
9103 * values for some adapter tunables, take PHYs out of reset, and
9104 * initialize the MDIO interface.
9105 */
t4_prep_adapter(struct adapter * adapter)9106 int t4_prep_adapter(struct adapter *adapter)
9107 {
9108 int ret, ver;
9109 uint16_t device_id;
9110 u32 pl_rev;
9111
9112 get_pci_mode(adapter, &adapter->params.pci);
9113 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A));
9114
9115 ret = t4_get_flash_params(adapter);
9116 if (ret < 0) {
9117 dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
9118 return ret;
9119 }
9120
9121 /* Retrieve adapter's device ID
9122 */
9123 pci_read_config_word(adapter->pdev, PCI_DEVICE_ID, &device_id);
9124 ver = device_id >> 12;
9125 adapter->params.chip = 0;
9126 switch (ver) {
9127 case CHELSIO_T4:
9128 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T4, pl_rev);
9129 adapter->params.arch.sge_fl_db = DBPRIO_F;
9130 adapter->params.arch.mps_tcam_size =
9131 NUM_MPS_CLS_SRAM_L_INSTANCES;
9132 adapter->params.arch.mps_rplc_size = 128;
9133 adapter->params.arch.nchan = NCHAN;
9134 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9135 adapter->params.arch.vfcount = 128;
9136 /* Congestion map is for 4 channels so that
9137 * MPS can have 4 priority per port.
9138 */
9139 adapter->params.arch.cng_ch_bits_log = 2;
9140 break;
9141 case CHELSIO_T5:
9142 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T5, pl_rev);
9143 adapter->params.arch.sge_fl_db = DBPRIO_F | DBTYPE_F;
9144 adapter->params.arch.mps_tcam_size =
9145 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9146 adapter->params.arch.mps_rplc_size = 128;
9147 adapter->params.arch.nchan = NCHAN;
9148 adapter->params.arch.pm_stats_cnt = PM_NSTATS;
9149 adapter->params.arch.vfcount = 128;
9150 adapter->params.arch.cng_ch_bits_log = 2;
9151 break;
9152 case CHELSIO_T6:
9153 adapter->params.chip |= CHELSIO_CHIP_CODE(CHELSIO_T6, pl_rev);
9154 adapter->params.arch.sge_fl_db = 0;
9155 adapter->params.arch.mps_tcam_size =
9156 NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
9157 adapter->params.arch.mps_rplc_size = 256;
9158 adapter->params.arch.nchan = 2;
9159 adapter->params.arch.pm_stats_cnt = T6_PM_NSTATS;
9160 adapter->params.arch.vfcount = 256;
9161 /* Congestion map will be for 2 channels so that
9162 * MPS can have 8 priority per port.
9163 */
9164 adapter->params.arch.cng_ch_bits_log = 3;
9165 break;
9166 default:
9167 dev_err(adapter->pdev_dev, "Device %d is not supported\n",
9168 device_id);
9169 return -EINVAL;
9170 }
9171
9172 adapter->params.cim_la_size = CIMLA_SIZE;
9173 init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
9174
9175 /*
9176 * Default port for debugging in case we can't reach FW.
9177 */
9178 adapter->params.nports = 1;
9179 adapter->params.portvec = 1;
9180 adapter->params.vpd.cclk = 50000;
9181
9182 /* Set PCIe completion timeout to 4 seconds. */
9183 pcie_capability_clear_and_set_word(adapter->pdev, PCI_EXP_DEVCTL2,
9184 PCI_EXP_DEVCTL2_COMP_TIMEOUT, 0xd);
9185 return 0;
9186 }
9187
9188 /**
9189 * t4_shutdown_adapter - shut down adapter, host & wire
9190 * @adapter: the adapter
9191 *
9192 * Perform an emergency shutdown of the adapter and stop it from
9193 * continuing any further communication on the ports or DMA to the
9194 * host. This is typically used when the adapter and/or firmware
9195 * have crashed and we want to prevent any further accidental
9196 * communication with the rest of the world. This will also force
9197 * the port Link Status to go down -- if register writes work --
9198 * which should help our peers figure out that we're down.
9199 */
t4_shutdown_adapter(struct adapter * adapter)9200 int t4_shutdown_adapter(struct adapter *adapter)
9201 {
9202 int port;
9203
9204 t4_intr_disable(adapter);
9205 t4_write_reg(adapter, DBG_GPIO_EN_A, 0);
9206 for_each_port(adapter, port) {
9207 u32 a_port_cfg = is_t4(adapter->params.chip) ?
9208 PORT_REG(port, XGMAC_PORT_CFG_A) :
9209 T5_PORT_REG(port, MAC_PORT_CFG_A);
9210
9211 t4_write_reg(adapter, a_port_cfg,
9212 t4_read_reg(adapter, a_port_cfg)
9213 & ~SIGNAL_DET_V(1));
9214 }
9215 t4_set_reg_field(adapter, SGE_CONTROL_A, GLOBALENABLE_F, 0);
9216
9217 return 0;
9218 }
9219
9220 /**
9221 * t4_bar2_sge_qregs - return BAR2 SGE Queue register information
9222 * @adapter: the adapter
9223 * @qid: the Queue ID
9224 * @qtype: the Ingress or Egress type for @qid
9225 * @user: true if this request is for a user mode queue
9226 * @pbar2_qoffset: BAR2 Queue Offset
9227 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
9228 *
9229 * Returns the BAR2 SGE Queue Registers information associated with the
9230 * indicated Absolute Queue ID. These are passed back in return value
9231 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
9232 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
9233 *
9234 * This may return an error which indicates that BAR2 SGE Queue
9235 * registers aren't available. If an error is not returned, then the
9236 * following values are returned:
9237 *
9238 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
9239 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
9240 *
9241 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
9242 * require the "Inferred Queue ID" ability may be used. E.g. the
9243 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
9244 * then these "Inferred Queue ID" register may not be used.
9245 */
t4_bar2_sge_qregs(struct adapter * adapter,unsigned int qid,enum t4_bar2_qtype qtype,int user,u64 * pbar2_qoffset,unsigned int * pbar2_qid)9246 int t4_bar2_sge_qregs(struct adapter *adapter,
9247 unsigned int qid,
9248 enum t4_bar2_qtype qtype,
9249 int user,
9250 u64 *pbar2_qoffset,
9251 unsigned int *pbar2_qid)
9252 {
9253 unsigned int page_shift, page_size, qpp_shift, qpp_mask;
9254 u64 bar2_page_offset, bar2_qoffset;
9255 unsigned int bar2_qid, bar2_qid_offset, bar2_qinferred;
9256
9257 /* T4 doesn't support BAR2 SGE Queue registers for kernel mode queues */
9258 if (!user && is_t4(adapter->params.chip))
9259 return -EINVAL;
9260
9261 /* Get our SGE Page Size parameters.
9262 */
9263 page_shift = adapter->params.sge.hps + 10;
9264 page_size = 1 << page_shift;
9265
9266 /* Get the right Queues per Page parameters for our Queue.
9267 */
9268 qpp_shift = (qtype == T4_BAR2_QTYPE_EGRESS
9269 ? adapter->params.sge.eq_qpp
9270 : adapter->params.sge.iq_qpp);
9271 qpp_mask = (1 << qpp_shift) - 1;
9272
9273 /* Calculate the basics of the BAR2 SGE Queue register area:
9274 * o The BAR2 page the Queue registers will be in.
9275 * o The BAR2 Queue ID.
9276 * o The BAR2 Queue ID Offset into the BAR2 page.
9277 */
9278 bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
9279 bar2_qid = qid & qpp_mask;
9280 bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
9281
9282 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
9283 * hardware will infer the Absolute Queue ID simply from the writes to
9284 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
9285 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
9286 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
9287 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
9288 * from the BAR2 Page and BAR2 Queue ID.
9289 *
9290 * One important censequence of this is that some BAR2 SGE registers
9291 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
9292 * there. But other registers synthesize the SGE Queue ID purely
9293 * from the writes to the registers -- the Write Combined Doorbell
9294 * Buffer is a good example. These BAR2 SGE Registers are only
9295 * available for those BAR2 SGE Register areas where the SGE Absolute
9296 * Queue ID can be inferred from simple writes.
9297 */
9298 bar2_qoffset = bar2_page_offset;
9299 bar2_qinferred = (bar2_qid_offset < page_size);
9300 if (bar2_qinferred) {
9301 bar2_qoffset += bar2_qid_offset;
9302 bar2_qid = 0;
9303 }
9304
9305 *pbar2_qoffset = bar2_qoffset;
9306 *pbar2_qid = bar2_qid;
9307 return 0;
9308 }
9309
9310 /**
9311 * t4_init_devlog_params - initialize adapter->params.devlog
9312 * @adap: the adapter
9313 *
9314 * Initialize various fields of the adapter's Firmware Device Log
9315 * Parameters structure.
9316 */
t4_init_devlog_params(struct adapter * adap)9317 int t4_init_devlog_params(struct adapter *adap)
9318 {
9319 struct devlog_params *dparams = &adap->params.devlog;
9320 u32 pf_dparams;
9321 unsigned int devlog_meminfo;
9322 struct fw_devlog_cmd devlog_cmd;
9323 int ret;
9324
9325 /* If we're dealing with newer firmware, the Device Log Parameters
9326 * are stored in a designated register which allows us to access the
9327 * Device Log even if we can't talk to the firmware.
9328 */
9329 pf_dparams =
9330 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG));
9331 if (pf_dparams) {
9332 unsigned int nentries, nentries128;
9333
9334 dparams->memtype = PCIE_FW_PF_DEVLOG_MEMTYPE_G(pf_dparams);
9335 dparams->start = PCIE_FW_PF_DEVLOG_ADDR16_G(pf_dparams) << 4;
9336
9337 nentries128 = PCIE_FW_PF_DEVLOG_NENTRIES128_G(pf_dparams);
9338 nentries = (nentries128 + 1) * 128;
9339 dparams->size = nentries * sizeof(struct fw_devlog_e);
9340
9341 return 0;
9342 }
9343
9344 /* Otherwise, ask the firmware for its Device Log Parameters.
9345 */
9346 memset(&devlog_cmd, 0, sizeof(devlog_cmd));
9347 devlog_cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_DEVLOG_CMD) |
9348 FW_CMD_REQUEST_F | FW_CMD_READ_F);
9349 devlog_cmd.retval_len16 = cpu_to_be32(FW_LEN16(devlog_cmd));
9350 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd),
9351 &devlog_cmd);
9352 if (ret)
9353 return ret;
9354
9355 devlog_meminfo =
9356 be32_to_cpu(devlog_cmd.memtype_devlog_memaddr16_devlog);
9357 dparams->memtype = FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(devlog_meminfo);
9358 dparams->start = FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(devlog_meminfo) << 4;
9359 dparams->size = be32_to_cpu(devlog_cmd.memsize_devlog);
9360
9361 return 0;
9362 }
9363
9364 /**
9365 * t4_init_sge_params - initialize adap->params.sge
9366 * @adapter: the adapter
9367 *
9368 * Initialize various fields of the adapter's SGE Parameters structure.
9369 */
t4_init_sge_params(struct adapter * adapter)9370 int t4_init_sge_params(struct adapter *adapter)
9371 {
9372 struct sge_params *sge_params = &adapter->params.sge;
9373 u32 hps, qpp;
9374 unsigned int s_hps, s_qpp;
9375
9376 /* Extract the SGE Page Size for our PF.
9377 */
9378 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A);
9379 s_hps = (HOSTPAGESIZEPF0_S +
9380 (HOSTPAGESIZEPF1_S - HOSTPAGESIZEPF0_S) * adapter->pf);
9381 sge_params->hps = ((hps >> s_hps) & HOSTPAGESIZEPF0_M);
9382
9383 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
9384 */
9385 s_qpp = (QUEUESPERPAGEPF0_S +
9386 (QUEUESPERPAGEPF1_S - QUEUESPERPAGEPF0_S) * adapter->pf);
9387 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A);
9388 sge_params->eq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9389 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A);
9390 sge_params->iq_qpp = ((qpp >> s_qpp) & QUEUESPERPAGEPF0_M);
9391
9392 return 0;
9393 }
9394
9395 /**
9396 * t4_init_tp_params - initialize adap->params.tp
9397 * @adap: the adapter
9398 * @sleep_ok: if true we may sleep while awaiting command completion
9399 *
9400 * Initialize various fields of the adapter's TP Parameters structure.
9401 */
t4_init_tp_params(struct adapter * adap,bool sleep_ok)9402 int t4_init_tp_params(struct adapter *adap, bool sleep_ok)
9403 {
9404 u32 param, val, v;
9405 int chan, ret;
9406
9407
9408 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A);
9409 adap->params.tp.tre = TIMERRESOLUTION_G(v);
9410 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v);
9411
9412 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
9413 for (chan = 0; chan < NCHAN; chan++)
9414 adap->params.tp.tx_modq[chan] = chan;
9415
9416 /* Cache the adapter's Compressed Filter Mode/Mask and global Ingress
9417 * Configuration.
9418 */
9419 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
9420 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FILTER) |
9421 FW_PARAMS_PARAM_Y_V(FW_PARAM_DEV_FILTER_MODE_MASK));
9422
9423 /* Read current value */
9424 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
9425 ¶m, &val);
9426 if (ret == 0) {
9427 dev_info(adap->pdev_dev,
9428 "Current filter mode/mask 0x%x:0x%x\n",
9429 FW_PARAMS_PARAM_FILTER_MODE_G(val),
9430 FW_PARAMS_PARAM_FILTER_MASK_G(val));
9431 adap->params.tp.vlan_pri_map =
9432 FW_PARAMS_PARAM_FILTER_MODE_G(val);
9433 adap->params.tp.filter_mask =
9434 FW_PARAMS_PARAM_FILTER_MASK_G(val);
9435 } else {
9436 dev_info(adap->pdev_dev,
9437 "Failed to read filter mode/mask via fw api, using indirect-reg-read\n");
9438
9439 /* Incase of older-fw (which doesn't expose the api
9440 * FW_PARAM_DEV_FILTER_MODE_MASK) and newer-driver (which uses
9441 * the fw api) combination, fall-back to older method of reading
9442 * the filter mode from indirect-register
9443 */
9444 t4_tp_pio_read(adap, &adap->params.tp.vlan_pri_map, 1,
9445 TP_VLAN_PRI_MAP_A, sleep_ok);
9446
9447 /* With the older-fw and newer-driver combination we might run
9448 * into an issue when user wants to use hash filter region but
9449 * the filter_mask is zero, in this case filter_mask validation
9450 * is tough. To avoid that we set the filter_mask same as filter
9451 * mode, which will behave exactly as the older way of ignoring
9452 * the filter mask validation.
9453 */
9454 adap->params.tp.filter_mask = adap->params.tp.vlan_pri_map;
9455 }
9456
9457 t4_tp_pio_read(adap, &adap->params.tp.ingress_config, 1,
9458 TP_INGRESS_CONFIG_A, sleep_ok);
9459
9460 /* For T6, cache the adapter's compressed error vector
9461 * and passing outer header info for encapsulated packets.
9462 */
9463 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
9464 v = t4_read_reg(adap, TP_OUT_CONFIG_A);
9465 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0;
9466 }
9467
9468 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
9469 * shift positions of several elements of the Compressed Filter Tuple
9470 * for this adapter which we need frequently ...
9471 */
9472 adap->params.tp.fcoe_shift = t4_filter_field_shift(adap, FCOE_F);
9473 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F);
9474 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F);
9475 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F);
9476 adap->params.tp.tos_shift = t4_filter_field_shift(adap, TOS_F);
9477 adap->params.tp.protocol_shift = t4_filter_field_shift(adap,
9478 PROTOCOL_F);
9479 adap->params.tp.ethertype_shift = t4_filter_field_shift(adap,
9480 ETHERTYPE_F);
9481 adap->params.tp.macmatch_shift = t4_filter_field_shift(adap,
9482 MACMATCH_F);
9483 adap->params.tp.matchtype_shift = t4_filter_field_shift(adap,
9484 MPSHITTYPE_F);
9485 adap->params.tp.frag_shift = t4_filter_field_shift(adap,
9486 FRAGMENTATION_F);
9487
9488 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
9489 * represents the presence of an Outer VLAN instead of a VNIC ID.
9490 */
9491 if ((adap->params.tp.ingress_config & VNIC_F) == 0)
9492 adap->params.tp.vnic_shift = -1;
9493
9494 v = t4_read_reg(adap, LE_3_DB_HASH_MASK_GEN_IPV4_T6_A);
9495 adap->params.tp.hash_filter_mask = v;
9496 v = t4_read_reg(adap, LE_4_DB_HASH_MASK_GEN_IPV4_T6_A);
9497 adap->params.tp.hash_filter_mask |= ((u64)v << 32);
9498 return 0;
9499 }
9500
9501 /**
9502 * t4_filter_field_shift - calculate filter field shift
9503 * @adap: the adapter
9504 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
9505 *
9506 * Return the shift position of a filter field within the Compressed
9507 * Filter Tuple. The filter field is specified via its selection bit
9508 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
9509 */
t4_filter_field_shift(const struct adapter * adap,int filter_sel)9510 int t4_filter_field_shift(const struct adapter *adap, int filter_sel)
9511 {
9512 unsigned int filter_mode = adap->params.tp.vlan_pri_map;
9513 unsigned int sel;
9514 int field_shift;
9515
9516 if ((filter_mode & filter_sel) == 0)
9517 return -1;
9518
9519 for (sel = 1, field_shift = 0; sel < filter_sel; sel <<= 1) {
9520 switch (filter_mode & sel) {
9521 case FCOE_F:
9522 field_shift += FT_FCOE_W;
9523 break;
9524 case PORT_F:
9525 field_shift += FT_PORT_W;
9526 break;
9527 case VNIC_ID_F:
9528 field_shift += FT_VNIC_ID_W;
9529 break;
9530 case VLAN_F:
9531 field_shift += FT_VLAN_W;
9532 break;
9533 case TOS_F:
9534 field_shift += FT_TOS_W;
9535 break;
9536 case PROTOCOL_F:
9537 field_shift += FT_PROTOCOL_W;
9538 break;
9539 case ETHERTYPE_F:
9540 field_shift += FT_ETHERTYPE_W;
9541 break;
9542 case MACMATCH_F:
9543 field_shift += FT_MACMATCH_W;
9544 break;
9545 case MPSHITTYPE_F:
9546 field_shift += FT_MPSHITTYPE_W;
9547 break;
9548 case FRAGMENTATION_F:
9549 field_shift += FT_FRAGMENTATION_W;
9550 break;
9551 }
9552 }
9553 return field_shift;
9554 }
9555
t4_init_rss_mode(struct adapter * adap,int mbox)9556 int t4_init_rss_mode(struct adapter *adap, int mbox)
9557 {
9558 int i, ret;
9559 struct fw_rss_vi_config_cmd rvc;
9560
9561 memset(&rvc, 0, sizeof(rvc));
9562
9563 for_each_port(adap, i) {
9564 struct port_info *p = adap2pinfo(adap, i);
9565
9566 rvc.op_to_viid =
9567 cpu_to_be32(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD) |
9568 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9569 FW_RSS_VI_CONFIG_CMD_VIID_V(p->viid));
9570 rvc.retval_len16 = cpu_to_be32(FW_LEN16(rvc));
9571 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
9572 if (ret)
9573 return ret;
9574 p->rss_mode = be32_to_cpu(rvc.u.basicvirtual.defaultq_to_udpen);
9575 }
9576 return 0;
9577 }
9578
9579 /**
9580 * t4_init_portinfo - allocate a virtual interface and initialize port_info
9581 * @pi: the port_info
9582 * @mbox: mailbox to use for the FW command
9583 * @port: physical port associated with the VI
9584 * @pf: the PF owning the VI
9585 * @vf: the VF owning the VI
9586 * @mac: the MAC address of the VI
9587 *
9588 * Allocates a virtual interface for the given physical port. If @mac is
9589 * not %NULL it contains the MAC address of the VI as assigned by FW.
9590 * @mac should be large enough to hold an Ethernet address.
9591 * Returns < 0 on error.
9592 */
t4_init_portinfo(struct port_info * pi,int mbox,int port,int pf,int vf,u8 mac[])9593 int t4_init_portinfo(struct port_info *pi, int mbox,
9594 int port, int pf, int vf, u8 mac[])
9595 {
9596 struct adapter *adapter = pi->adapter;
9597 unsigned int fw_caps = adapter->params.fw_caps_support;
9598 struct fw_port_cmd cmd;
9599 unsigned int rss_size;
9600 enum fw_port_type port_type;
9601 int mdio_addr;
9602 fw_port_cap32_t pcaps, acaps;
9603 u8 vivld = 0, vin = 0;
9604 int ret;
9605
9606 /* If we haven't yet determined whether we're talking to Firmware
9607 * which knows the new 32-bit Port Capabilities, it's time to find
9608 * out now. This will also tell new Firmware to send us Port Status
9609 * Updates using the new 32-bit Port Capabilities version of the
9610 * Port Information message.
9611 */
9612 if (fw_caps == FW_CAPS_UNKNOWN) {
9613 u32 param, val;
9614
9615 param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_PFVF) |
9616 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_PFVF_PORT_CAPS32));
9617 val = 1;
9618 ret = t4_set_params(adapter, mbox, pf, vf, 1, ¶m, &val);
9619 fw_caps = (ret == 0 ? FW_CAPS32 : FW_CAPS16);
9620 adapter->params.fw_caps_support = fw_caps;
9621 }
9622
9623 memset(&cmd, 0, sizeof(cmd));
9624 cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
9625 FW_CMD_REQUEST_F | FW_CMD_READ_F |
9626 FW_PORT_CMD_PORTID_V(port));
9627 cmd.action_to_len16 = cpu_to_be32(
9628 FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
9629 ? FW_PORT_ACTION_GET_PORT_INFO
9630 : FW_PORT_ACTION_GET_PORT_INFO32) |
9631 FW_LEN16(cmd));
9632 ret = t4_wr_mbox(pi->adapter, mbox, &cmd, sizeof(cmd), &cmd);
9633 if (ret)
9634 return ret;
9635
9636 /* Extract the various fields from the Port Information message.
9637 */
9638 if (fw_caps == FW_CAPS16) {
9639 u32 lstatus = be32_to_cpu(cmd.u.info.lstatus_to_modtype);
9640
9641 port_type = FW_PORT_CMD_PTYPE_G(lstatus);
9642 mdio_addr = ((lstatus & FW_PORT_CMD_MDIOCAP_F)
9643 ? FW_PORT_CMD_MDIOADDR_G(lstatus)
9644 : -1);
9645 pcaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.pcap));
9646 acaps = fwcaps16_to_caps32(be16_to_cpu(cmd.u.info.acap));
9647 } else {
9648 u32 lstatus32 = be32_to_cpu(cmd.u.info32.lstatus32_to_cbllen32);
9649
9650 port_type = FW_PORT_CMD_PORTTYPE32_G(lstatus32);
9651 mdio_addr = ((lstatus32 & FW_PORT_CMD_MDIOCAP32_F)
9652 ? FW_PORT_CMD_MDIOADDR32_G(lstatus32)
9653 : -1);
9654 pcaps = be32_to_cpu(cmd.u.info32.pcaps32);
9655 acaps = be32_to_cpu(cmd.u.info32.acaps32);
9656 }
9657
9658 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, mac, &rss_size,
9659 &vivld, &vin);
9660 if (ret < 0)
9661 return ret;
9662
9663 pi->viid = ret;
9664 pi->tx_chan = port;
9665 pi->lport = port;
9666 pi->rss_size = rss_size;
9667 pi->rx_cchan = t4_get_tp_e2c_map(pi->adapter, port);
9668
9669 /* If fw supports returning the VIN as part of FW_VI_CMD,
9670 * save the returned values.
9671 */
9672 if (adapter->params.viid_smt_extn_support) {
9673 pi->vivld = vivld;
9674 pi->vin = vin;
9675 } else {
9676 /* Retrieve the values from VIID */
9677 pi->vivld = FW_VIID_VIVLD_G(pi->viid);
9678 pi->vin = FW_VIID_VIN_G(pi->viid);
9679 }
9680
9681 pi->port_type = port_type;
9682 pi->mdio_addr = mdio_addr;
9683 pi->mod_type = FW_PORT_MOD_TYPE_NA;
9684
9685 init_link_config(&pi->link_cfg, pcaps, acaps);
9686 return 0;
9687 }
9688
t4_port_init(struct adapter * adap,int mbox,int pf,int vf)9689 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
9690 {
9691 u8 addr[6];
9692 int ret, i, j = 0;
9693
9694 for_each_port(adap, i) {
9695 struct port_info *pi = adap2pinfo(adap, i);
9696
9697 while ((adap->params.portvec & (1 << j)) == 0)
9698 j++;
9699
9700 ret = t4_init_portinfo(pi, mbox, j, pf, vf, addr);
9701 if (ret)
9702 return ret;
9703
9704 eth_hw_addr_set(adap->port[i], addr);
9705 j++;
9706 }
9707 return 0;
9708 }
9709
t4_init_port_mirror(struct port_info * pi,u8 mbox,u8 port,u8 pf,u8 vf,u16 * mirror_viid)9710 int t4_init_port_mirror(struct port_info *pi, u8 mbox, u8 port, u8 pf, u8 vf,
9711 u16 *mirror_viid)
9712 {
9713 int ret;
9714
9715 ret = t4_alloc_vi(pi->adapter, mbox, port, pf, vf, 1, NULL, NULL,
9716 NULL, NULL);
9717 if (ret < 0)
9718 return ret;
9719
9720 if (mirror_viid)
9721 *mirror_viid = ret;
9722
9723 return 0;
9724 }
9725
9726 /**
9727 * t4_read_cimq_cfg - read CIM queue configuration
9728 * @adap: the adapter
9729 * @base: holds the queue base addresses in bytes
9730 * @size: holds the queue sizes in bytes
9731 * @thres: holds the queue full thresholds in bytes
9732 *
9733 * Returns the current configuration of the CIM queues, starting with
9734 * the IBQs, then the OBQs.
9735 */
t4_read_cimq_cfg(struct adapter * adap,u16 * base,u16 * size,u16 * thres)9736 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres)
9737 {
9738 unsigned int i, v;
9739 int cim_num_obq = is_t4(adap->params.chip) ?
9740 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9741
9742 for (i = 0; i < CIM_NUM_IBQ; i++) {
9743 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F |
9744 QUENUMSELECT_V(i));
9745 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9746 /* value is in 256-byte units */
9747 *base++ = CIMQBASE_G(v) * 256;
9748 *size++ = CIMQSIZE_G(v) * 256;
9749 *thres++ = QUEFULLTHRSH_G(v) * 8; /* 8-byte unit */
9750 }
9751 for (i = 0; i < cim_num_obq; i++) {
9752 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9753 QUENUMSELECT_V(i));
9754 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9755 /* value is in 256-byte units */
9756 *base++ = CIMQBASE_G(v) * 256;
9757 *size++ = CIMQSIZE_G(v) * 256;
9758 }
9759 }
9760
9761 /**
9762 * t4_read_cim_ibq - read the contents of a CIM inbound queue
9763 * @adap: the adapter
9764 * @qid: the queue index
9765 * @data: where to store the queue contents
9766 * @n: capacity of @data in 32-bit words
9767 *
9768 * Reads the contents of the selected CIM queue starting at address 0 up
9769 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9770 * error and the number of 32-bit words actually read on success.
9771 */
t4_read_cim_ibq(struct adapter * adap,unsigned int qid,u32 * data,size_t n)9772 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9773 {
9774 int i, err, attempts;
9775 unsigned int addr;
9776 const unsigned int nwords = CIM_IBQ_SIZE * 4;
9777
9778 if (qid > 5 || (n & 3))
9779 return -EINVAL;
9780
9781 addr = qid * nwords;
9782 if (n > nwords)
9783 n = nwords;
9784
9785 /* It might take 3-10ms before the IBQ debug read access is allowed.
9786 * Wait for 1 Sec with a delay of 1 usec.
9787 */
9788 attempts = 1000000;
9789
9790 for (i = 0; i < n; i++, addr++) {
9791 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) |
9792 IBQDBGEN_F);
9793 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0,
9794 attempts, 1);
9795 if (err)
9796 return err;
9797 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A);
9798 }
9799 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0);
9800 return i;
9801 }
9802
9803 /**
9804 * t4_read_cim_obq - read the contents of a CIM outbound queue
9805 * @adap: the adapter
9806 * @qid: the queue index
9807 * @data: where to store the queue contents
9808 * @n: capacity of @data in 32-bit words
9809 *
9810 * Reads the contents of the selected CIM queue starting at address 0 up
9811 * to the capacity of @data. @n must be a multiple of 4. Returns < 0 on
9812 * error and the number of 32-bit words actually read on success.
9813 */
t4_read_cim_obq(struct adapter * adap,unsigned int qid,u32 * data,size_t n)9814 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n)
9815 {
9816 int i, err;
9817 unsigned int addr, v, nwords;
9818 int cim_num_obq = is_t4(adap->params.chip) ?
9819 CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
9820
9821 if ((qid > (cim_num_obq - 1)) || (n & 3))
9822 return -EINVAL;
9823
9824 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F |
9825 QUENUMSELECT_V(qid));
9826 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A);
9827
9828 addr = CIMQBASE_G(v) * 64; /* muliple of 256 -> muliple of 4 */
9829 nwords = CIMQSIZE_G(v) * 64; /* same */
9830 if (n > nwords)
9831 n = nwords;
9832
9833 for (i = 0; i < n; i++, addr++) {
9834 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) |
9835 OBQDBGEN_F);
9836 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0,
9837 2, 1);
9838 if (err)
9839 return err;
9840 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A);
9841 }
9842 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0);
9843 return i;
9844 }
9845
9846 /**
9847 * t4_cim_read - read a block from CIM internal address space
9848 * @adap: the adapter
9849 * @addr: the start address within the CIM address space
9850 * @n: number of words to read
9851 * @valp: where to store the result
9852 *
9853 * Reads a block of 4-byte words from the CIM intenal address space.
9854 */
t4_cim_read(struct adapter * adap,unsigned int addr,unsigned int n,unsigned int * valp)9855 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
9856 unsigned int *valp)
9857 {
9858 int ret = 0;
9859
9860 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9861 return -EBUSY;
9862
9863 for ( ; !ret && n--; addr += 4) {
9864 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr);
9865 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9866 0, 5, 2);
9867 if (!ret)
9868 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A);
9869 }
9870 return ret;
9871 }
9872
9873 /**
9874 * t4_cim_write - write a block into CIM internal address space
9875 * @adap: the adapter
9876 * @addr: the start address within the CIM address space
9877 * @n: number of words to write
9878 * @valp: set of values to write
9879 *
9880 * Writes a block of 4-byte words into the CIM intenal address space.
9881 */
t4_cim_write(struct adapter * adap,unsigned int addr,unsigned int n,const unsigned int * valp)9882 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
9883 const unsigned int *valp)
9884 {
9885 int ret = 0;
9886
9887 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F)
9888 return -EBUSY;
9889
9890 for ( ; !ret && n--; addr += 4) {
9891 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++);
9892 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F);
9893 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F,
9894 0, 5, 2);
9895 }
9896 return ret;
9897 }
9898
t4_cim_write1(struct adapter * adap,unsigned int addr,unsigned int val)9899 static int t4_cim_write1(struct adapter *adap, unsigned int addr,
9900 unsigned int val)
9901 {
9902 return t4_cim_write(adap, addr, 1, &val);
9903 }
9904
9905 /**
9906 * t4_cim_read_la - read CIM LA capture buffer
9907 * @adap: the adapter
9908 * @la_buf: where to store the LA data
9909 * @wrptr: the HW write pointer within the capture buffer
9910 *
9911 * Reads the contents of the CIM LA buffer with the most recent entry at
9912 * the end of the returned data and with the entry at @wrptr first.
9913 * We try to leave the LA in the running state we find it in.
9914 */
t4_cim_read_la(struct adapter * adap,u32 * la_buf,unsigned int * wrptr)9915 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr)
9916 {
9917 int i, ret;
9918 unsigned int cfg, val, idx;
9919
9920 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg);
9921 if (ret)
9922 return ret;
9923
9924 if (cfg & UPDBGLAEN_F) { /* LA is running, freeze it */
9925 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0);
9926 if (ret)
9927 return ret;
9928 }
9929
9930 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9931 if (ret)
9932 goto restart;
9933
9934 idx = UPDBGLAWRPTR_G(val);
9935 if (wrptr)
9936 *wrptr = idx;
9937
9938 for (i = 0; i < adap->params.cim_la_size; i++) {
9939 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9940 UPDBGLARDPTR_V(idx) | UPDBGLARDEN_F);
9941 if (ret)
9942 break;
9943 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val);
9944 if (ret)
9945 break;
9946 if (val & UPDBGLARDEN_F) {
9947 ret = -ETIMEDOUT;
9948 break;
9949 }
9950 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]);
9951 if (ret)
9952 break;
9953
9954 /* Bits 0-3 of UpDbgLaRdPtr can be between 0000 to 1001 to
9955 * identify the 32-bit portion of the full 312-bit data
9956 */
9957 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9)
9958 idx = (idx & 0xff0) + 0x10;
9959 else
9960 idx++;
9961 /* address can't exceed 0xfff */
9962 idx &= UPDBGLARDPTR_M;
9963 }
9964 restart:
9965 if (cfg & UPDBGLAEN_F) {
9966 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A,
9967 cfg & ~UPDBGLARDEN_F);
9968 if (!ret)
9969 ret = r;
9970 }
9971 return ret;
9972 }
9973
9974 /**
9975 * t4_tp_read_la - read TP LA capture buffer
9976 * @adap: the adapter
9977 * @la_buf: where to store the LA data
9978 * @wrptr: the HW write pointer within the capture buffer
9979 *
9980 * Reads the contents of the TP LA buffer with the most recent entry at
9981 * the end of the returned data and with the entry at @wrptr first.
9982 * We leave the LA in the running state we find it in.
9983 */
t4_tp_read_la(struct adapter * adap,u64 * la_buf,unsigned int * wrptr)9984 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr)
9985 {
9986 bool last_incomplete;
9987 unsigned int i, cfg, val, idx;
9988
9989 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff;
9990 if (cfg & DBGLAENABLE_F) /* freeze LA */
9991 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
9992 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F));
9993
9994 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A);
9995 idx = DBGLAWPTR_G(val);
9996 last_incomplete = DBGLAMODE_G(val) >= 2 && (val & DBGLAWHLF_F) == 0;
9997 if (last_incomplete)
9998 idx = (idx + 1) & DBGLARPTR_M;
9999 if (wrptr)
10000 *wrptr = idx;
10001
10002 val &= 0xffff;
10003 val &= ~DBGLARPTR_V(DBGLARPTR_M);
10004 val |= adap->params.tp.la_mask;
10005
10006 for (i = 0; i < TPLA_SIZE; i++) {
10007 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val);
10008 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A);
10009 idx = (idx + 1) & DBGLARPTR_M;
10010 }
10011
10012 /* Wipe out last entry if it isn't valid */
10013 if (last_incomplete)
10014 la_buf[TPLA_SIZE - 1] = ~0ULL;
10015
10016 if (cfg & DBGLAENABLE_F) /* restore running state */
10017 t4_write_reg(adap, TP_DBG_LA_CONFIG_A,
10018 cfg | adap->params.tp.la_mask);
10019 }
10020
10021 /* SGE Hung Ingress DMA Warning Threshold time and Warning Repeat Rate (in
10022 * seconds). If we find one of the SGE Ingress DMA State Machines in the same
10023 * state for more than the Warning Threshold then we'll issue a warning about
10024 * a potential hang. We'll repeat the warning as the SGE Ingress DMA Channel
10025 * appears to be hung every Warning Repeat second till the situation clears.
10026 * If the situation clears, we'll note that as well.
10027 */
10028 #define SGE_IDMA_WARN_THRESH 1
10029 #define SGE_IDMA_WARN_REPEAT 300
10030
10031 /**
10032 * t4_idma_monitor_init - initialize SGE Ingress DMA Monitor
10033 * @adapter: the adapter
10034 * @idma: the adapter IDMA Monitor state
10035 *
10036 * Initialize the state of an SGE Ingress DMA Monitor.
10037 */
t4_idma_monitor_init(struct adapter * adapter,struct sge_idma_monitor_state * idma)10038 void t4_idma_monitor_init(struct adapter *adapter,
10039 struct sge_idma_monitor_state *idma)
10040 {
10041 /* Initialize the state variables for detecting an SGE Ingress DMA
10042 * hang. The SGE has internal counters which count up on each clock
10043 * tick whenever the SGE finds its Ingress DMA State Engines in the
10044 * same state they were on the previous clock tick. The clock used is
10045 * the Core Clock so we have a limit on the maximum "time" they can
10046 * record; typically a very small number of seconds. For instance,
10047 * with a 600MHz Core Clock, we can only count up to a bit more than
10048 * 7s. So we'll synthesize a larger counter in order to not run the
10049 * risk of having the "timers" overflow and give us the flexibility to
10050 * maintain a Hung SGE State Machine of our own which operates across
10051 * a longer time frame.
10052 */
10053 idma->idma_1s_thresh = core_ticks_per_usec(adapter) * 1000000; /* 1s */
10054 idma->idma_stalled[0] = 0;
10055 idma->idma_stalled[1] = 0;
10056 }
10057
10058 /**
10059 * t4_idma_monitor - monitor SGE Ingress DMA state
10060 * @adapter: the adapter
10061 * @idma: the adapter IDMA Monitor state
10062 * @hz: number of ticks/second
10063 * @ticks: number of ticks since the last IDMA Monitor call
10064 */
t4_idma_monitor(struct adapter * adapter,struct sge_idma_monitor_state * idma,int hz,int ticks)10065 void t4_idma_monitor(struct adapter *adapter,
10066 struct sge_idma_monitor_state *idma,
10067 int hz, int ticks)
10068 {
10069 int i, idma_same_state_cnt[2];
10070
10071 /* Read the SGE Debug Ingress DMA Same State Count registers. These
10072 * are counters inside the SGE which count up on each clock when the
10073 * SGE finds its Ingress DMA State Engines in the same states they
10074 * were in the previous clock. The counters will peg out at
10075 * 0xffffffff without wrapping around so once they pass the 1s
10076 * threshold they'll stay above that till the IDMA state changes.
10077 */
10078 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 13);
10079 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A);
10080 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10081
10082 for (i = 0; i < 2; i++) {
10083 u32 debug0, debug11;
10084
10085 /* If the Ingress DMA Same State Counter ("timer") is less
10086 * than 1s, then we can reset our synthesized Stall Timer and
10087 * continue. If we have previously emitted warnings about a
10088 * potential stalled Ingress Queue, issue a note indicating
10089 * that the Ingress Queue has resumed forward progress.
10090 */
10091 if (idma_same_state_cnt[i] < idma->idma_1s_thresh) {
10092 if (idma->idma_stalled[i] >= SGE_IDMA_WARN_THRESH * hz)
10093 dev_warn(adapter->pdev_dev, "SGE idma%d, queue %u, "
10094 "resumed after %d seconds\n",
10095 i, idma->idma_qid[i],
10096 idma->idma_stalled[i] / hz);
10097 idma->idma_stalled[i] = 0;
10098 continue;
10099 }
10100
10101 /* Synthesize an SGE Ingress DMA Same State Timer in the Hz
10102 * domain. The first time we get here it'll be because we
10103 * passed the 1s Threshold; each additional time it'll be
10104 * because the RX Timer Callback is being fired on its regular
10105 * schedule.
10106 *
10107 * If the stall is below our Potential Hung Ingress Queue
10108 * Warning Threshold, continue.
10109 */
10110 if (idma->idma_stalled[i] == 0) {
10111 idma->idma_stalled[i] = hz;
10112 idma->idma_warn[i] = 0;
10113 } else {
10114 idma->idma_stalled[i] += ticks;
10115 idma->idma_warn[i] -= ticks;
10116 }
10117
10118 if (idma->idma_stalled[i] < SGE_IDMA_WARN_THRESH * hz)
10119 continue;
10120
10121 /* We'll issue a warning every SGE_IDMA_WARN_REPEAT seconds.
10122 */
10123 if (idma->idma_warn[i] > 0)
10124 continue;
10125 idma->idma_warn[i] = SGE_IDMA_WARN_REPEAT * hz;
10126
10127 /* Read and save the SGE IDMA State and Queue ID information.
10128 * We do this every time in case it changes across time ...
10129 * can't be too careful ...
10130 */
10131 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 0);
10132 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10133 idma->idma_state[i] = (debug0 >> (i * 9)) & 0x3f;
10134
10135 t4_write_reg(adapter, SGE_DEBUG_INDEX_A, 11);
10136 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A);
10137 idma->idma_qid[i] = (debug11 >> (i * 16)) & 0xffff;
10138
10139 dev_warn(adapter->pdev_dev, "SGE idma%u, queue %u, potentially stuck in "
10140 "state %u for %d seconds (debug0=%#x, debug11=%#x)\n",
10141 i, idma->idma_qid[i], idma->idma_state[i],
10142 idma->idma_stalled[i] / hz,
10143 debug0, debug11);
10144 t4_sge_decode_idma_state(adapter, idma->idma_state[i]);
10145 }
10146 }
10147
10148 /**
10149 * t4_load_cfg - download config file
10150 * @adap: the adapter
10151 * @cfg_data: the cfg text file to write
10152 * @size: text file size
10153 *
10154 * Write the supplied config text file to the card's serial flash.
10155 */
t4_load_cfg(struct adapter * adap,const u8 * cfg_data,unsigned int size)10156 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10157 {
10158 int ret, i, n, cfg_addr;
10159 unsigned int addr;
10160 unsigned int flash_cfg_start_sec;
10161 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10162
10163 cfg_addr = t4_flash_cfg_addr(adap);
10164 if (cfg_addr < 0)
10165 return cfg_addr;
10166
10167 addr = cfg_addr;
10168 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10169
10170 if (size > FLASH_CFG_MAX_SIZE) {
10171 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
10172 FLASH_CFG_MAX_SIZE);
10173 return -EFBIG;
10174 }
10175
10176 i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
10177 sf_sec_size);
10178 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10179 flash_cfg_start_sec + i - 1);
10180 /* If size == 0 then we're simply erasing the FLASH sectors associated
10181 * with the on-adapter Firmware Configuration File.
10182 */
10183 if (ret || size == 0)
10184 goto out;
10185
10186 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10187 for (i = 0; i < size; i += SF_PAGE_SIZE) {
10188 if ((size - i) < SF_PAGE_SIZE)
10189 n = size - i;
10190 else
10191 n = SF_PAGE_SIZE;
10192 ret = t4_write_flash(adap, addr, n, cfg_data, true);
10193 if (ret)
10194 goto out;
10195
10196 addr += SF_PAGE_SIZE;
10197 cfg_data += SF_PAGE_SIZE;
10198 }
10199
10200 out:
10201 if (ret)
10202 dev_err(adap->pdev_dev, "config file %s failed %d\n",
10203 (size == 0 ? "clear" : "download"), ret);
10204 return ret;
10205 }
10206
10207 /**
10208 * t4_set_vf_mac_acl - Set MAC address for the specified VF
10209 * @adapter: The adapter
10210 * @vf: one of the VFs instantiated by the specified PF
10211 * @start: The start port id associated with specified VF
10212 * @naddr: the number of MAC addresses
10213 * @addr: the MAC address(es) to be set to the specified VF
10214 */
t4_set_vf_mac_acl(struct adapter * adapter,unsigned int vf,u8 start,unsigned int naddr,u8 * addr)10215 int t4_set_vf_mac_acl(struct adapter *adapter, unsigned int vf,
10216 u8 start, unsigned int naddr, u8 *addr)
10217 {
10218 struct fw_acl_mac_cmd cmd;
10219
10220 memset(&cmd, 0, sizeof(cmd));
10221 cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_MAC_CMD) |
10222 FW_CMD_REQUEST_F |
10223 FW_CMD_WRITE_F |
10224 FW_ACL_MAC_CMD_PFN_V(adapter->pf) |
10225 FW_ACL_MAC_CMD_VFN_V(vf));
10226
10227 /* Note: Do not enable the ACL */
10228 cmd.en_to_len16 = cpu_to_be32((unsigned int)FW_LEN16(cmd));
10229 cmd.nmac = naddr;
10230
10231 switch (start) {
10232 case 3:
10233 memcpy(cmd.macaddr3, addr, sizeof(cmd.macaddr3));
10234 break;
10235 case 2:
10236 memcpy(cmd.macaddr2, addr, sizeof(cmd.macaddr2));
10237 break;
10238 case 1:
10239 memcpy(cmd.macaddr1, addr, sizeof(cmd.macaddr1));
10240 break;
10241 case 0:
10242 memcpy(cmd.macaddr0, addr, sizeof(cmd.macaddr0));
10243 break;
10244 }
10245
10246 return t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &cmd);
10247 }
10248
10249 /**
10250 * t4_read_pace_tbl - read the pace table
10251 * @adap: the adapter
10252 * @pace_vals: holds the returned values
10253 *
10254 * Returns the values of TP's pace table in microseconds.
10255 */
t4_read_pace_tbl(struct adapter * adap,unsigned int pace_vals[NTX_SCHED])10256 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED])
10257 {
10258 unsigned int i, v;
10259
10260 for (i = 0; i < NTX_SCHED; i++) {
10261 t4_write_reg(adap, TP_PACE_TABLE_A, 0xffff0000 + i);
10262 v = t4_read_reg(adap, TP_PACE_TABLE_A);
10263 pace_vals[i] = dack_ticks_to_usec(adap, v);
10264 }
10265 }
10266
10267 /**
10268 * t4_get_tx_sched - get the configuration of a Tx HW traffic scheduler
10269 * @adap: the adapter
10270 * @sched: the scheduler index
10271 * @kbps: the byte rate in Kbps
10272 * @ipg: the interpacket delay in tenths of nanoseconds
10273 * @sleep_ok: if true we may sleep while awaiting command completion
10274 *
10275 * Return the current configuration of a HW Tx scheduler.
10276 */
t4_get_tx_sched(struct adapter * adap,unsigned int sched,unsigned int * kbps,unsigned int * ipg,bool sleep_ok)10277 void t4_get_tx_sched(struct adapter *adap, unsigned int sched,
10278 unsigned int *kbps, unsigned int *ipg, bool sleep_ok)
10279 {
10280 unsigned int v, addr, bpt, cpt;
10281
10282 if (kbps) {
10283 addr = TP_TX_MOD_Q1_Q0_RATE_LIMIT_A - sched / 2;
10284 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10285 if (sched & 1)
10286 v >>= 16;
10287 bpt = (v >> 8) & 0xff;
10288 cpt = v & 0xff;
10289 if (!cpt) {
10290 *kbps = 0; /* scheduler disabled */
10291 } else {
10292 v = (adap->params.vpd.cclk * 1000) / cpt; /* ticks/s */
10293 *kbps = (v * bpt) / 125;
10294 }
10295 }
10296 if (ipg) {
10297 addr = TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR_A - sched / 2;
10298 t4_tp_tm_pio_read(adap, &v, 1, addr, sleep_ok);
10299 if (sched & 1)
10300 v >>= 16;
10301 v &= 0xffff;
10302 *ipg = (10000 * v) / core_ticks_per_usec(adap);
10303 }
10304 }
10305
10306 /* t4_sge_ctxt_rd - read an SGE context through FW
10307 * @adap: the adapter
10308 * @mbox: mailbox to use for the FW command
10309 * @cid: the context id
10310 * @ctype: the context type
10311 * @data: where to store the context data
10312 *
10313 * Issues a FW command through the given mailbox to read an SGE context.
10314 */
t4_sge_ctxt_rd(struct adapter * adap,unsigned int mbox,unsigned int cid,enum ctxt_type ctype,u32 * data)10315 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
10316 enum ctxt_type ctype, u32 *data)
10317 {
10318 struct fw_ldst_cmd c;
10319 int ret;
10320
10321 if (ctype == CTXT_FLM)
10322 ret = FW_LDST_ADDRSPC_SGE_FLMC;
10323 else
10324 ret = FW_LDST_ADDRSPC_SGE_CONMC;
10325
10326 memset(&c, 0, sizeof(c));
10327 c.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10328 FW_CMD_REQUEST_F | FW_CMD_READ_F |
10329 FW_LDST_CMD_ADDRSPACE_V(ret));
10330 c.cycles_to_len16 = cpu_to_be32(FW_LEN16(c));
10331 c.u.idctxt.physid = cpu_to_be32(cid);
10332
10333 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
10334 if (ret == 0) {
10335 data[0] = be32_to_cpu(c.u.idctxt.ctxt_data0);
10336 data[1] = be32_to_cpu(c.u.idctxt.ctxt_data1);
10337 data[2] = be32_to_cpu(c.u.idctxt.ctxt_data2);
10338 data[3] = be32_to_cpu(c.u.idctxt.ctxt_data3);
10339 data[4] = be32_to_cpu(c.u.idctxt.ctxt_data4);
10340 data[5] = be32_to_cpu(c.u.idctxt.ctxt_data5);
10341 }
10342 return ret;
10343 }
10344
10345 /**
10346 * t4_sge_ctxt_rd_bd - read an SGE context bypassing FW
10347 * @adap: the adapter
10348 * @cid: the context id
10349 * @ctype: the context type
10350 * @data: where to store the context data
10351 *
10352 * Reads an SGE context directly, bypassing FW. This is only for
10353 * debugging when FW is unavailable.
10354 */
t4_sge_ctxt_rd_bd(struct adapter * adap,unsigned int cid,enum ctxt_type ctype,u32 * data)10355 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid,
10356 enum ctxt_type ctype, u32 *data)
10357 {
10358 int i, ret;
10359
10360 t4_write_reg(adap, SGE_CTXT_CMD_A, CTXTQID_V(cid) | CTXTTYPE_V(ctype));
10361 ret = t4_wait_op_done(adap, SGE_CTXT_CMD_A, BUSY_F, 0, 3, 1);
10362 if (!ret)
10363 for (i = SGE_CTXT_DATA0_A; i <= SGE_CTXT_DATA5_A; i += 4)
10364 *data++ = t4_read_reg(adap, i);
10365 return ret;
10366 }
10367
t4_sched_params(struct adapter * adapter,u8 type,u8 level,u8 mode,u8 rateunit,u8 ratemode,u8 channel,u8 class,u32 minrate,u32 maxrate,u16 weight,u16 pktsize,u16 burstsize)10368 int t4_sched_params(struct adapter *adapter, u8 type, u8 level, u8 mode,
10369 u8 rateunit, u8 ratemode, u8 channel, u8 class,
10370 u32 minrate, u32 maxrate, u16 weight, u16 pktsize,
10371 u16 burstsize)
10372 {
10373 struct fw_sched_cmd cmd;
10374
10375 memset(&cmd, 0, sizeof(cmd));
10376 cmd.op_to_write = cpu_to_be32(FW_CMD_OP_V(FW_SCHED_CMD) |
10377 FW_CMD_REQUEST_F |
10378 FW_CMD_WRITE_F);
10379 cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
10380
10381 cmd.u.params.sc = FW_SCHED_SC_PARAMS;
10382 cmd.u.params.type = type;
10383 cmd.u.params.level = level;
10384 cmd.u.params.mode = mode;
10385 cmd.u.params.ch = channel;
10386 cmd.u.params.cl = class;
10387 cmd.u.params.unit = rateunit;
10388 cmd.u.params.rate = ratemode;
10389 cmd.u.params.min = cpu_to_be32(minrate);
10390 cmd.u.params.max = cpu_to_be32(maxrate);
10391 cmd.u.params.weight = cpu_to_be16(weight);
10392 cmd.u.params.pktsize = cpu_to_be16(pktsize);
10393 cmd.u.params.burstsize = cpu_to_be16(burstsize);
10394
10395 return t4_wr_mbox_meat(adapter, adapter->mbox, &cmd, sizeof(cmd),
10396 NULL, 1);
10397 }
10398
10399 /**
10400 * t4_i2c_rd - read I2C data from adapter
10401 * @adap: the adapter
10402 * @mbox: mailbox to use for the FW command
10403 * @port: Port number if per-port device; <0 if not
10404 * @devid: per-port device ID or absolute device ID
10405 * @offset: byte offset into device I2C space
10406 * @len: byte length of I2C space data
10407 * @buf: buffer in which to return I2C data
10408 *
10409 * Reads the I2C data from the indicated device and location.
10410 */
t4_i2c_rd(struct adapter * adap,unsigned int mbox,int port,unsigned int devid,unsigned int offset,unsigned int len,u8 * buf)10411 int t4_i2c_rd(struct adapter *adap, unsigned int mbox, int port,
10412 unsigned int devid, unsigned int offset,
10413 unsigned int len, u8 *buf)
10414 {
10415 struct fw_ldst_cmd ldst_cmd, ldst_rpl;
10416 unsigned int i2c_max = sizeof(ldst_cmd.u.i2c.data);
10417 int ret = 0;
10418
10419 if (len > I2C_PAGE_SIZE)
10420 return -EINVAL;
10421
10422 /* Dont allow reads that spans multiple pages */
10423 if (offset < I2C_PAGE_SIZE && offset + len > I2C_PAGE_SIZE)
10424 return -EINVAL;
10425
10426 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
10427 ldst_cmd.op_to_addrspace =
10428 cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
10429 FW_CMD_REQUEST_F |
10430 FW_CMD_READ_F |
10431 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_I2C));
10432 ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
10433 ldst_cmd.u.i2c.pid = (port < 0 ? 0xff : port);
10434 ldst_cmd.u.i2c.did = devid;
10435
10436 while (len > 0) {
10437 unsigned int i2c_len = (len < i2c_max) ? len : i2c_max;
10438
10439 ldst_cmd.u.i2c.boffset = offset;
10440 ldst_cmd.u.i2c.blen = i2c_len;
10441
10442 ret = t4_wr_mbox(adap, mbox, &ldst_cmd, sizeof(ldst_cmd),
10443 &ldst_rpl);
10444 if (ret)
10445 break;
10446
10447 memcpy(buf, ldst_rpl.u.i2c.data, i2c_len);
10448 offset += i2c_len;
10449 buf += i2c_len;
10450 len -= i2c_len;
10451 }
10452
10453 return ret;
10454 }
10455
10456 /**
10457 * t4_set_vlan_acl - Set a VLAN id for the specified VF
10458 * @adap: the adapter
10459 * @mbox: mailbox to use for the FW command
10460 * @vf: one of the VFs instantiated by the specified PF
10461 * @vlan: The vlanid to be set
10462 */
t4_set_vlan_acl(struct adapter * adap,unsigned int mbox,unsigned int vf,u16 vlan)10463 int t4_set_vlan_acl(struct adapter *adap, unsigned int mbox, unsigned int vf,
10464 u16 vlan)
10465 {
10466 struct fw_acl_vlan_cmd vlan_cmd;
10467 unsigned int enable;
10468
10469 enable = (vlan ? FW_ACL_VLAN_CMD_EN_F : 0);
10470 memset(&vlan_cmd, 0, sizeof(vlan_cmd));
10471 vlan_cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_ACL_VLAN_CMD) |
10472 FW_CMD_REQUEST_F |
10473 FW_CMD_WRITE_F |
10474 FW_CMD_EXEC_F |
10475 FW_ACL_VLAN_CMD_PFN_V(adap->pf) |
10476 FW_ACL_VLAN_CMD_VFN_V(vf));
10477 vlan_cmd.en_to_len16 = cpu_to_be32(enable | FW_LEN16(vlan_cmd));
10478 /* Drop all packets that donot match vlan id */
10479 vlan_cmd.dropnovlan_fm = (enable
10480 ? (FW_ACL_VLAN_CMD_DROPNOVLAN_F |
10481 FW_ACL_VLAN_CMD_FM_F) : 0);
10482 if (enable != 0) {
10483 vlan_cmd.nvlan = 1;
10484 vlan_cmd.vlanid[0] = cpu_to_be16(vlan);
10485 }
10486
10487 return t4_wr_mbox(adap, adap->mbox, &vlan_cmd, sizeof(vlan_cmd), NULL);
10488 }
10489
10490 /**
10491 * modify_device_id - Modifies the device ID of the Boot BIOS image
10492 * @device_id: the device ID to write.
10493 * @boot_data: the boot image to modify.
10494 *
10495 * Write the supplied device ID to the boot BIOS image.
10496 */
modify_device_id(int device_id,u8 * boot_data)10497 static void modify_device_id(int device_id, u8 *boot_data)
10498 {
10499 struct cxgb4_pcir_data *pcir_header;
10500 struct legacy_pci_rom_hdr *header;
10501 u8 *cur_header = boot_data;
10502 u16 pcir_offset;
10503
10504 /* Loop through all chained images and change the device ID's */
10505 do {
10506 header = (struct legacy_pci_rom_hdr *)cur_header;
10507 pcir_offset = le16_to_cpu(header->pcir_offset);
10508 pcir_header = (struct cxgb4_pcir_data *)(cur_header +
10509 pcir_offset);
10510
10511 /**
10512 * Only modify the Device ID if code type is Legacy or HP.
10513 * 0x00: Okay to modify
10514 * 0x01: FCODE. Do not modify
10515 * 0x03: Okay to modify
10516 * 0x04-0xFF: Do not modify
10517 */
10518 if (pcir_header->code_type == CXGB4_HDR_CODE1) {
10519 u8 csum = 0;
10520 int i;
10521
10522 /**
10523 * Modify Device ID to match current adatper
10524 */
10525 pcir_header->device_id = cpu_to_le16(device_id);
10526
10527 /**
10528 * Set checksum temporarily to 0.
10529 * We will recalculate it later.
10530 */
10531 header->cksum = 0x0;
10532
10533 /**
10534 * Calculate and update checksum
10535 */
10536 for (i = 0; i < (header->size512 * 512); i++)
10537 csum += cur_header[i];
10538
10539 /**
10540 * Invert summed value to create the checksum
10541 * Writing new checksum value directly to the boot data
10542 */
10543 cur_header[7] = -csum;
10544
10545 } else if (pcir_header->code_type == CXGB4_HDR_CODE2) {
10546 /**
10547 * Modify Device ID to match current adatper
10548 */
10549 pcir_header->device_id = cpu_to_le16(device_id);
10550 }
10551
10552 /**
10553 * Move header pointer up to the next image in the ROM.
10554 */
10555 cur_header += header->size512 * 512;
10556 } while (!(pcir_header->indicator & CXGB4_HDR_INDI));
10557 }
10558
10559 /**
10560 * t4_load_boot - download boot flash
10561 * @adap: the adapter
10562 * @boot_data: the boot image to write
10563 * @boot_addr: offset in flash to write boot_data
10564 * @size: image size
10565 *
10566 * Write the supplied boot image to the card's serial flash.
10567 * The boot image has the following sections: a 28-byte header and the
10568 * boot image.
10569 */
t4_load_boot(struct adapter * adap,u8 * boot_data,unsigned int boot_addr,unsigned int size)10570 int t4_load_boot(struct adapter *adap, u8 *boot_data,
10571 unsigned int boot_addr, unsigned int size)
10572 {
10573 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10574 unsigned int boot_sector = (boot_addr * 1024);
10575 struct cxgb4_pci_exp_rom_header *header;
10576 struct cxgb4_pcir_data *pcir_header;
10577 int pcir_offset;
10578 unsigned int i;
10579 u16 device_id;
10580 int ret, addr;
10581
10582 /**
10583 * Make sure the boot image does not encroach on the firmware region
10584 */
10585 if ((boot_sector + size) >> 16 > FLASH_FW_START_SEC) {
10586 dev_err(adap->pdev_dev, "boot image encroaching on firmware region\n");
10587 return -EFBIG;
10588 }
10589
10590 /* Get boot header */
10591 header = (struct cxgb4_pci_exp_rom_header *)boot_data;
10592 pcir_offset = le16_to_cpu(header->pcir_offset);
10593 /* PCIR Data Structure */
10594 pcir_header = (struct cxgb4_pcir_data *)&boot_data[pcir_offset];
10595
10596 /**
10597 * Perform some primitive sanity testing to avoid accidentally
10598 * writing garbage over the boot sectors. We ought to check for
10599 * more but it's not worth it for now ...
10600 */
10601 if (size < BOOT_MIN_SIZE || size > BOOT_MAX_SIZE) {
10602 dev_err(adap->pdev_dev, "boot image too small/large\n");
10603 return -EFBIG;
10604 }
10605
10606 if (le16_to_cpu(header->signature) != BOOT_SIGNATURE) {
10607 dev_err(adap->pdev_dev, "Boot image missing signature\n");
10608 return -EINVAL;
10609 }
10610
10611 /* Check PCI header signature */
10612 if (le32_to_cpu(pcir_header->signature) != PCIR_SIGNATURE) {
10613 dev_err(adap->pdev_dev, "PCI header missing signature\n");
10614 return -EINVAL;
10615 }
10616
10617 /* Check Vendor ID matches Chelsio ID*/
10618 if (le16_to_cpu(pcir_header->vendor_id) != PCI_VENDOR_ID_CHELSIO) {
10619 dev_err(adap->pdev_dev, "Vendor ID missing signature\n");
10620 return -EINVAL;
10621 }
10622
10623 /**
10624 * The boot sector is comprised of the Expansion-ROM boot, iSCSI boot,
10625 * and Boot configuration data sections. These 3 boot sections span
10626 * sectors 0 to 7 in flash and live right before the FW image location.
10627 */
10628 i = DIV_ROUND_UP(size ? size : FLASH_FW_START, sf_sec_size);
10629 ret = t4_flash_erase_sectors(adap, boot_sector >> 16,
10630 (boot_sector >> 16) + i - 1);
10631
10632 /**
10633 * If size == 0 then we're simply erasing the FLASH sectors associated
10634 * with the on-adapter option ROM file
10635 */
10636 if (ret || size == 0)
10637 goto out;
10638 /* Retrieve adapter's device ID */
10639 pci_read_config_word(adap->pdev, PCI_DEVICE_ID, &device_id);
10640 /* Want to deal with PF 0 so I strip off PF 4 indicator */
10641 device_id = device_id & 0xf0ff;
10642
10643 /* Check PCIE Device ID */
10644 if (le16_to_cpu(pcir_header->device_id) != device_id) {
10645 /**
10646 * Change the device ID in the Boot BIOS image to match
10647 * the Device ID of the current adapter.
10648 */
10649 modify_device_id(device_id, boot_data);
10650 }
10651
10652 /**
10653 * Skip over the first SF_PAGE_SIZE worth of data and write it after
10654 * we finish copying the rest of the boot image. This will ensure
10655 * that the BIOS boot header will only be written if the boot image
10656 * was written in full.
10657 */
10658 addr = boot_sector;
10659 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
10660 addr += SF_PAGE_SIZE;
10661 boot_data += SF_PAGE_SIZE;
10662 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, boot_data,
10663 false);
10664 if (ret)
10665 goto out;
10666 }
10667
10668 ret = t4_write_flash(adap, boot_sector, SF_PAGE_SIZE,
10669 (const u8 *)header, false);
10670
10671 out:
10672 if (ret)
10673 dev_err(adap->pdev_dev, "boot image load failed, error %d\n",
10674 ret);
10675 return ret;
10676 }
10677
10678 /**
10679 * t4_flash_bootcfg_addr - return the address of the flash
10680 * optionrom configuration
10681 * @adapter: the adapter
10682 *
10683 * Return the address within the flash where the OptionROM Configuration
10684 * is stored, or an error if the device FLASH is too small to contain
10685 * a OptionROM Configuration.
10686 */
t4_flash_bootcfg_addr(struct adapter * adapter)10687 static int t4_flash_bootcfg_addr(struct adapter *adapter)
10688 {
10689 /**
10690 * If the device FLASH isn't large enough to hold a Firmware
10691 * Configuration File, return an error.
10692 */
10693 if (adapter->params.sf_size <
10694 FLASH_BOOTCFG_START + FLASH_BOOTCFG_MAX_SIZE)
10695 return -ENOSPC;
10696
10697 return FLASH_BOOTCFG_START;
10698 }
10699
t4_load_bootcfg(struct adapter * adap,const u8 * cfg_data,unsigned int size)10700 int t4_load_bootcfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
10701 {
10702 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
10703 struct cxgb4_bootcfg_data *header;
10704 unsigned int flash_cfg_start_sec;
10705 unsigned int addr, npad;
10706 int ret, i, n, cfg_addr;
10707
10708 cfg_addr = t4_flash_bootcfg_addr(adap);
10709 if (cfg_addr < 0)
10710 return cfg_addr;
10711
10712 addr = cfg_addr;
10713 flash_cfg_start_sec = addr / SF_SEC_SIZE;
10714
10715 if (size > FLASH_BOOTCFG_MAX_SIZE) {
10716 dev_err(adap->pdev_dev, "bootcfg file too large, max is %u bytes\n",
10717 FLASH_BOOTCFG_MAX_SIZE);
10718 return -EFBIG;
10719 }
10720
10721 header = (struct cxgb4_bootcfg_data *)cfg_data;
10722 if (le16_to_cpu(header->signature) != BOOT_CFG_SIG) {
10723 dev_err(adap->pdev_dev, "Wrong bootcfg signature\n");
10724 ret = -EINVAL;
10725 goto out;
10726 }
10727
10728 i = DIV_ROUND_UP(FLASH_BOOTCFG_MAX_SIZE,
10729 sf_sec_size);
10730 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
10731 flash_cfg_start_sec + i - 1);
10732
10733 /**
10734 * If size == 0 then we're simply erasing the FLASH sectors associated
10735 * with the on-adapter OptionROM Configuration File.
10736 */
10737 if (ret || size == 0)
10738 goto out;
10739
10740 /* this will write to the flash up to SF_PAGE_SIZE at a time */
10741 for (i = 0; i < size; i += SF_PAGE_SIZE) {
10742 n = min_t(u32, size - i, SF_PAGE_SIZE);
10743
10744 ret = t4_write_flash(adap, addr, n, cfg_data, false);
10745 if (ret)
10746 goto out;
10747
10748 addr += SF_PAGE_SIZE;
10749 cfg_data += SF_PAGE_SIZE;
10750 }
10751
10752 npad = ((size + 4 - 1) & ~3) - size;
10753 for (i = 0; i < npad; i++) {
10754 u8 data = 0;
10755
10756 ret = t4_write_flash(adap, cfg_addr + size + i, 1, &data,
10757 false);
10758 if (ret)
10759 goto out;
10760 }
10761
10762 out:
10763 if (ret)
10764 dev_err(adap->pdev_dev, "boot config data %s failed %d\n",
10765 (size == 0 ? "clear" : "download"), ret);
10766 return ret;
10767 }
10768