1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
27
28 #define SMU_11_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
30
31 #include "amdgpu.h"
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v11_0.h"
37 #include "soc15_common.h"
38 #include "atom.h"
39 #include "amdgpu_ras.h"
40 #include "smu_cmn.h"
41
42 #include "asic_reg/thm/thm_11_0_2_offset.h"
43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_11_0_offset.h"
45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
48
49 /*
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
53 */
54 #undef pr_err
55 #undef pr_warn
56 #undef pr_info
57 #undef pr_debug
58
59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
66 MODULE_FIRMWARE("amdgpu/beige_goby_smc.bin");
67
68 #define SMU11_VOLTAGE_SCALE 4
69
70 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
71
72 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
73 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
74 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
75 #define smnPCIE_LC_SPEED_CNTL 0x11140290
76 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
77 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
78
79 #define mmTHM_BACO_CNTL_ARCT 0xA7
80 #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0
81
smu_v11_0_poll_baco_exit(struct smu_context * smu)82 static void smu_v11_0_poll_baco_exit(struct smu_context *smu)
83 {
84 struct amdgpu_device *adev = smu->adev;
85 uint32_t data, loop = 0;
86
87 do {
88 usleep_range(1000, 1100);
89 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
90 } while ((data & 0x100) && (++loop < 100));
91 }
92
smu_v11_0_init_microcode(struct smu_context * smu)93 int smu_v11_0_init_microcode(struct smu_context *smu)
94 {
95 struct amdgpu_device *adev = smu->adev;
96 char ucode_prefix[25];
97 int err = 0;
98 const struct smc_firmware_header_v1_0 *hdr;
99 const struct common_firmware_header *header;
100 struct amdgpu_firmware_info *ucode = NULL;
101
102 if (amdgpu_sriov_vf(adev) &&
103 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9)) ||
104 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 7))))
105 return 0;
106
107 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix));
108 err = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
109 "amdgpu/%s.bin", ucode_prefix);
110 if (err)
111 goto out;
112
113 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
114 amdgpu_ucode_print_smc_hdr(&hdr->header);
115 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
116
117 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
118 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
119 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
120 ucode->fw = adev->pm.fw;
121 header = (const struct common_firmware_header *)ucode->fw->data;
122 adev->firmware.fw_size +=
123 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
124 }
125
126 out:
127 if (err)
128 amdgpu_ucode_release(&adev->pm.fw);
129 return err;
130 }
131
smu_v11_0_fini_microcode(struct smu_context * smu)132 void smu_v11_0_fini_microcode(struct smu_context *smu)
133 {
134 struct amdgpu_device *adev = smu->adev;
135
136 amdgpu_ucode_release(&adev->pm.fw);
137 adev->pm.fw_version = 0;
138 }
139
smu_v11_0_load_microcode(struct smu_context * smu)140 int smu_v11_0_load_microcode(struct smu_context *smu)
141 {
142 struct amdgpu_device *adev = smu->adev;
143 const uint32_t *src;
144 const struct smc_firmware_header_v1_0 *hdr;
145 uint32_t addr_start = MP1_SRAM;
146 uint32_t i;
147 uint32_t smc_fw_size;
148 uint32_t mp1_fw_flags;
149
150 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
151 src = (const uint32_t *)(adev->pm.fw->data +
152 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
153 smc_fw_size = hdr->header.ucode_size_bytes;
154
155 for (i = 1; i < smc_fw_size/4 - 1; i++) {
156 WREG32_PCIE(addr_start, src[i]);
157 addr_start += 4;
158 }
159
160 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
161 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
162 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
163 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
164
165 for (i = 0; i < adev->usec_timeout; i++) {
166 mp1_fw_flags = RREG32_PCIE(MP1_Public |
167 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
168 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
169 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
170 break;
171 udelay(1);
172 }
173
174 if (i == adev->usec_timeout)
175 return -ETIME;
176
177 return 0;
178 }
179
smu_v11_0_check_fw_status(struct smu_context * smu)180 int smu_v11_0_check_fw_status(struct smu_context *smu)
181 {
182 struct amdgpu_device *adev = smu->adev;
183 uint32_t mp1_fw_flags;
184
185 mp1_fw_flags = RREG32_PCIE(MP1_Public |
186 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
187
188 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
189 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
190 return 0;
191
192 return -EIO;
193 }
194
smu_v11_0_check_fw_version(struct smu_context * smu)195 int smu_v11_0_check_fw_version(struct smu_context *smu)
196 {
197 struct amdgpu_device *adev = smu->adev;
198 uint32_t if_version = 0xff, smu_version = 0xff;
199 uint8_t smu_program, smu_major, smu_minor, smu_debug;
200 int ret = 0;
201
202 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
203 if (ret)
204 return ret;
205
206 smu_program = (smu_version >> 24) & 0xff;
207 smu_major = (smu_version >> 16) & 0xff;
208 smu_minor = (smu_version >> 8) & 0xff;
209 smu_debug = (smu_version >> 0) & 0xff;
210 if (smu->is_apu)
211 adev->pm.fw_version = smu_version;
212
213 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
214 case IP_VERSION(11, 0, 0):
215 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
216 break;
217 case IP_VERSION(11, 0, 9):
218 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
219 break;
220 case IP_VERSION(11, 0, 5):
221 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
222 break;
223 case IP_VERSION(11, 0, 7):
224 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
225 break;
226 case IP_VERSION(11, 0, 11):
227 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
228 break;
229 case IP_VERSION(11, 5, 0):
230 case IP_VERSION(11, 5, 2):
231 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
232 break;
233 case IP_VERSION(11, 0, 12):
234 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
235 break;
236 case IP_VERSION(11, 0, 13):
237 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Beige_Goby;
238 break;
239 case IP_VERSION(11, 0, 8):
240 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Cyan_Skillfish;
241 break;
242 case IP_VERSION(11, 0, 2):
243 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
244 break;
245 default:
246 dev_err(smu->adev->dev, "smu unsupported IP version: 0x%x.\n",
247 amdgpu_ip_version(adev, MP1_HWIP, 0));
248 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
249 break;
250 }
251
252 /*
253 * 1. if_version mismatch is not critical as our fw is designed
254 * to be backward compatible.
255 * 2. New fw usually brings some optimizations. But that's visible
256 * only on the paired driver.
257 * Considering above, we just leave user a verbal message instead
258 * of halt driver loading.
259 */
260 if (if_version != smu->smc_driver_if_version) {
261 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
262 "smu fw program = %d, version = 0x%08x (%d.%d.%d)\n",
263 smu->smc_driver_if_version, if_version,
264 smu_program, smu_version, smu_major, smu_minor, smu_debug);
265 dev_info(smu->adev->dev, "SMU driver if version not matched\n");
266 }
267
268 return ret;
269 }
270
smu_v11_0_set_pptable_v2_0(struct smu_context * smu,void ** table,uint32_t * size)271 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
272 {
273 struct amdgpu_device *adev = smu->adev;
274 uint32_t ppt_offset_bytes;
275 const struct smc_firmware_header_v2_0 *v2;
276
277 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
278
279 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
280 *size = le32_to_cpu(v2->ppt_size_bytes);
281 *table = (uint8_t *)v2 + ppt_offset_bytes;
282
283 return 0;
284 }
285
smu_v11_0_set_pptable_v2_1(struct smu_context * smu,void ** table,uint32_t * size,uint32_t pptable_id)286 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
287 uint32_t *size, uint32_t pptable_id)
288 {
289 struct amdgpu_device *adev = smu->adev;
290 const struct smc_firmware_header_v2_1 *v2_1;
291 struct smc_soft_pptable_entry *entries;
292 uint32_t pptable_count = 0;
293 int i = 0;
294
295 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
296 entries = (struct smc_soft_pptable_entry *)
297 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
298 pptable_count = le32_to_cpu(v2_1->pptable_count);
299 for (i = 0; i < pptable_count; i++) {
300 if (le32_to_cpu(entries[i].id) == pptable_id) {
301 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
302 *size = le32_to_cpu(entries[i].ppt_size_bytes);
303 break;
304 }
305 }
306
307 if (i == pptable_count)
308 return -EINVAL;
309
310 return 0;
311 }
312
smu_v11_0_setup_pptable(struct smu_context * smu)313 int smu_v11_0_setup_pptable(struct smu_context *smu)
314 {
315 struct amdgpu_device *adev = smu->adev;
316 const struct smc_firmware_header_v1_0 *hdr;
317 int ret, index;
318 uint32_t size = 0;
319 uint16_t atom_table_size;
320 uint8_t frev, crev;
321 void *table;
322 uint16_t version_major, version_minor;
323
324 if (!amdgpu_sriov_vf(adev)) {
325 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
326 version_major = le16_to_cpu(hdr->header.header_version_major);
327 version_minor = le16_to_cpu(hdr->header.header_version_minor);
328 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
329 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
330 switch (version_minor) {
331 case 0:
332 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
333 break;
334 case 1:
335 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
336 smu->smu_table.boot_values.pp_table_id);
337 break;
338 default:
339 ret = -EINVAL;
340 break;
341 }
342 if (ret)
343 return ret;
344 goto out;
345 }
346 }
347
348 dev_info(adev->dev, "use vbios provided pptable\n");
349 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
350 powerplayinfo);
351
352 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
353 (uint8_t **)&table);
354 if (ret)
355 return ret;
356 size = atom_table_size;
357
358 out:
359 if (!smu->smu_table.power_play_table)
360 smu->smu_table.power_play_table = table;
361 if (!smu->smu_table.power_play_table_size)
362 smu->smu_table.power_play_table_size = size;
363
364 return 0;
365 }
366
smu_v11_0_init_smc_tables(struct smu_context * smu)367 int smu_v11_0_init_smc_tables(struct smu_context *smu)
368 {
369 struct smu_table_context *smu_table = &smu->smu_table;
370 struct smu_table *tables = smu_table->tables;
371 int ret = 0;
372
373 smu_table->driver_pptable =
374 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
375 if (!smu_table->driver_pptable) {
376 ret = -ENOMEM;
377 goto err0_out;
378 }
379
380 smu_table->max_sustainable_clocks =
381 kzalloc_obj(struct smu_11_0_max_sustainable_clocks);
382 if (!smu_table->max_sustainable_clocks) {
383 ret = -ENOMEM;
384 goto err1_out;
385 }
386
387 /* Arcturus does not support OVERDRIVE */
388 if (tables[SMU_TABLE_OVERDRIVE].size) {
389 smu_table->overdrive_table =
390 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
391 if (!smu_table->overdrive_table) {
392 ret = -ENOMEM;
393 goto err2_out;
394 }
395
396 smu_table->boot_overdrive_table =
397 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
398 if (!smu_table->boot_overdrive_table) {
399 ret = -ENOMEM;
400 goto err3_out;
401 }
402
403 smu_table->user_overdrive_table =
404 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
405 if (!smu_table->user_overdrive_table) {
406 ret = -ENOMEM;
407 goto err4_out;
408 }
409
410 }
411
412 return 0;
413
414 err4_out:
415 kfree(smu_table->boot_overdrive_table);
416 err3_out:
417 kfree(smu_table->overdrive_table);
418 err2_out:
419 kfree(smu_table->max_sustainable_clocks);
420 err1_out:
421 kfree(smu_table->driver_pptable);
422 err0_out:
423 return ret;
424 }
425
smu_v11_0_fini_smc_tables(struct smu_context * smu)426 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
427 {
428 struct smu_table_context *smu_table = &smu->smu_table;
429 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
430
431 smu_driver_table_fini(smu, SMU_DRIVER_TABLE_GPU_METRICS);
432 kfree(smu_table->user_overdrive_table);
433 kfree(smu_table->boot_overdrive_table);
434 kfree(smu_table->overdrive_table);
435 kfree(smu_table->max_sustainable_clocks);
436 kfree(smu_table->driver_pptable);
437 kfree(smu_table->clocks_table);
438 smu_table->user_overdrive_table = NULL;
439 smu_table->boot_overdrive_table = NULL;
440 smu_table->overdrive_table = NULL;
441 smu_table->max_sustainable_clocks = NULL;
442 smu_table->driver_pptable = NULL;
443 smu_table->clocks_table = NULL;
444 kfree(smu_table->hardcode_pptable);
445 smu_table->hardcode_pptable = NULL;
446
447 kfree(smu_table->driver_smu_config_table);
448 kfree(smu_table->ecc_table);
449 kfree(smu_table->metrics_table);
450 kfree(smu_table->watermarks_table);
451 smu_table->driver_smu_config_table = NULL;
452 smu_table->ecc_table = NULL;
453 smu_table->metrics_table = NULL;
454 smu_table->watermarks_table = NULL;
455 smu_table->metrics_time = 0;
456
457 kfree(smu_dpm->dpm_context);
458 kfree(smu_dpm->golden_dpm_context);
459 kfree(smu_dpm->dpm_current_power_state);
460 kfree(smu_dpm->dpm_request_power_state);
461 smu_dpm->dpm_context = NULL;
462 smu_dpm->golden_dpm_context = NULL;
463 smu_dpm->dpm_context_size = 0;
464 smu_dpm->dpm_current_power_state = NULL;
465 smu_dpm->dpm_request_power_state = NULL;
466
467 return 0;
468 }
469
smu_v11_0_init_power(struct smu_context * smu)470 int smu_v11_0_init_power(struct smu_context *smu)
471 {
472 struct amdgpu_device *adev = smu->adev;
473 struct smu_power_context *smu_power = &smu->smu_power;
474 u32 ip_version = amdgpu_ip_version(adev, MP1_HWIP, 0);
475 size_t size = ((ip_version == IP_VERSION(11, 5, 0)) ||
476 (ip_version == IP_VERSION(11, 5, 2))) ?
477 sizeof(struct smu_11_5_power_context) :
478 sizeof(struct smu_11_0_power_context);
479
480 smu_power->power_context = kzalloc(size, GFP_KERNEL);
481 if (!smu_power->power_context)
482 return -ENOMEM;
483 smu_power->power_context_size = size;
484
485 return 0;
486 }
487
smu_v11_0_fini_power(struct smu_context * smu)488 int smu_v11_0_fini_power(struct smu_context *smu)
489 {
490 struct smu_power_context *smu_power = &smu->smu_power;
491
492 kfree(smu_power->power_context);
493 smu_power->power_context = NULL;
494 smu_power->power_context_size = 0;
495
496 return 0;
497 }
498
smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device * adev,uint8_t clk_id,uint8_t syspll_id,uint32_t * clk_freq)499 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
500 uint8_t clk_id,
501 uint8_t syspll_id,
502 uint32_t *clk_freq)
503 {
504 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
505 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
506 int ret, index;
507
508 input.clk_id = clk_id;
509 input.syspll_id = syspll_id;
510 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
511 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
512 getsmuclockinfo);
513
514 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
515 (uint32_t *)&input, sizeof(input));
516 if (ret)
517 return -EINVAL;
518
519 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
520 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
521
522 return 0;
523 }
524
smu_v11_0_get_vbios_bootup_values(struct smu_context * smu)525 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
526 {
527 int ret, index;
528 uint16_t size;
529 uint8_t frev, crev;
530 struct atom_common_table_header *header;
531 struct atom_firmware_info_v3_3 *v_3_3;
532 struct atom_firmware_info_v3_1 *v_3_1;
533
534 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
535 firmwareinfo);
536
537 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
538 (uint8_t **)&header);
539 if (ret)
540 return ret;
541
542 if (header->format_revision != 3) {
543 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
544 return -EINVAL;
545 }
546
547 switch (header->content_revision) {
548 case 0:
549 case 1:
550 case 2:
551 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
552 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
553 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
554 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
555 smu->smu_table.boot_values.socclk = 0;
556 smu->smu_table.boot_values.dcefclk = 0;
557 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
558 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
559 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
560 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
561 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
562 smu->smu_table.boot_values.pp_table_id = 0;
563 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
564 break;
565 case 3:
566 case 4:
567 default:
568 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
569 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
570 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
571 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
572 smu->smu_table.boot_values.socclk = 0;
573 smu->smu_table.boot_values.dcefclk = 0;
574 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
575 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
576 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
577 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
578 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
579 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
580 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
581 }
582
583 smu->smu_table.boot_values.format_revision = header->format_revision;
584 smu->smu_table.boot_values.content_revision = header->content_revision;
585
586 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
587 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
588 (uint8_t)0,
589 &smu->smu_table.boot_values.socclk);
590
591 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
592 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
593 (uint8_t)0,
594 &smu->smu_table.boot_values.dcefclk);
595
596 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
597 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
598 (uint8_t)0,
599 &smu->smu_table.boot_values.eclk);
600
601 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
602 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
603 (uint8_t)0,
604 &smu->smu_table.boot_values.vclk);
605
606 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
607 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
608 (uint8_t)0,
609 &smu->smu_table.boot_values.dclk);
610
611 if ((smu->smu_table.boot_values.format_revision == 3) &&
612 (smu->smu_table.boot_values.content_revision >= 2))
613 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
614 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
615 (uint8_t)SMU11_SYSPLL1_2_ID,
616 &smu->smu_table.boot_values.fclk);
617
618 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
619 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
620 (uint8_t)SMU11_SYSPLL3_1_ID,
621 &smu->smu_table.boot_values.lclk);
622
623 return 0;
624 }
625
smu_v11_0_notify_memory_pool_location(struct smu_context * smu)626 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
627 {
628 struct smu_table_context *smu_table = &smu->smu_table;
629 struct smu_table *memory_pool = &smu_table->memory_pool;
630 int ret = 0;
631 uint64_t address;
632 uint32_t address_low, address_high;
633
634 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
635 return ret;
636
637 address = (uintptr_t)memory_pool->cpu_addr;
638 address_high = (uint32_t)upper_32_bits(address);
639 address_low = (uint32_t)lower_32_bits(address);
640
641 ret = smu_cmn_send_smc_msg_with_param(smu,
642 SMU_MSG_SetSystemVirtualDramAddrHigh,
643 address_high,
644 NULL);
645 if (ret)
646 return ret;
647 ret = smu_cmn_send_smc_msg_with_param(smu,
648 SMU_MSG_SetSystemVirtualDramAddrLow,
649 address_low,
650 NULL);
651 if (ret)
652 return ret;
653
654 address = memory_pool->mc_address;
655 address_high = (uint32_t)upper_32_bits(address);
656 address_low = (uint32_t)lower_32_bits(address);
657
658 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
659 address_high, NULL);
660 if (ret)
661 return ret;
662 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
663 address_low, NULL);
664 if (ret)
665 return ret;
666 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
667 (uint32_t)memory_pool->size, NULL);
668 if (ret)
669 return ret;
670
671 return ret;
672 }
673
smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context * smu,uint32_t clk)674 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
675 {
676 int ret;
677
678 ret = smu_cmn_send_smc_msg_with_param(smu,
679 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
680 if (ret)
681 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
682
683 return ret;
684 }
685
smu_v11_0_set_driver_table_location(struct smu_context * smu)686 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
687 {
688 struct smu_table *driver_table = &smu->smu_table.driver_table;
689 int ret = 0;
690
691 if (driver_table->mc_address) {
692 ret = smu_cmn_send_smc_msg_with_param(smu,
693 SMU_MSG_SetDriverDramAddrHigh,
694 upper_32_bits(driver_table->mc_address),
695 NULL);
696 if (!ret)
697 ret = smu_cmn_send_smc_msg_with_param(smu,
698 SMU_MSG_SetDriverDramAddrLow,
699 lower_32_bits(driver_table->mc_address),
700 NULL);
701 }
702
703 return ret;
704 }
705
smu_v11_0_set_tool_table_location(struct smu_context * smu)706 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
707 {
708 int ret = 0;
709 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
710
711 if (tool_table->mc_address) {
712 ret = smu_cmn_send_smc_msg_with_param(smu,
713 SMU_MSG_SetToolsDramAddrHigh,
714 upper_32_bits(tool_table->mc_address),
715 NULL);
716 if (!ret)
717 ret = smu_cmn_send_smc_msg_with_param(smu,
718 SMU_MSG_SetToolsDramAddrLow,
719 lower_32_bits(tool_table->mc_address),
720 NULL);
721 }
722
723 return ret;
724 }
725
smu_v11_0_init_display_count(struct smu_context * smu,uint32_t count)726 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
727 {
728 struct amdgpu_device *adev = smu->adev;
729
730 /* Navy_Flounder/Dimgrey_Cavefish do not support to change
731 * display num currently
732 */
733 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 11) ||
734 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 0) ||
735 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 5, 2) ||
736 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 12) ||
737 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 13))
738 return 0;
739
740 return smu_cmn_send_smc_msg_with_param(smu,
741 SMU_MSG_NumOfDisplays,
742 count,
743 NULL);
744 }
745
746
smu_v11_0_set_allowed_mask(struct smu_context * smu)747 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
748 {
749 struct smu_feature *feature = &smu->smu_feature;
750 int ret = 0;
751 uint32_t feature_mask[2];
752
753 if (smu_feature_list_is_empty(smu, SMU_FEATURE_LIST_ALLOWED) ||
754 feature->feature_num < SMU_FEATURE_NUM_DEFAULT) {
755 ret = -EINVAL;
756 goto failed;
757 }
758
759 smu_feature_list_to_arr32(smu, SMU_FEATURE_LIST_ALLOWED, feature_mask);
760
761 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
762 feature_mask[1], NULL);
763 if (ret)
764 goto failed;
765
766 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
767 feature_mask[0], NULL);
768 if (ret)
769 goto failed;
770
771 failed:
772 return ret;
773 }
774
smu_v11_0_system_features_control(struct smu_context * smu,bool en)775 int smu_v11_0_system_features_control(struct smu_context *smu,
776 bool en)
777 {
778 return smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
779 SMU_MSG_DisableAllSmuFeatures), NULL);
780 }
781
smu_v11_0_notify_display_change(struct smu_context * smu)782 int smu_v11_0_notify_display_change(struct smu_context *smu)
783 {
784 int ret = 0;
785
786 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
787 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
788 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
789
790 return ret;
791 }
792
793 static int
smu_v11_0_get_max_sustainable_clock(struct smu_context * smu,uint32_t * clock,enum smu_clk_type clock_select)794 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
795 enum smu_clk_type clock_select)
796 {
797 int ret = 0;
798 int clk_id;
799
800 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
801 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
802 return 0;
803
804 clk_id = smu_cmn_to_asic_specific_index(smu,
805 CMN2ASIC_MAPPING_CLK,
806 clock_select);
807 if (clk_id < 0)
808 return -EINVAL;
809
810 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
811 clk_id << 16, clock);
812 if (ret) {
813 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
814 return ret;
815 }
816
817 if (*clock != 0)
818 return 0;
819
820 /* if DC limit is zero, return AC limit */
821 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
822 clk_id << 16, clock);
823 if (ret) {
824 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
825 return ret;
826 }
827
828 return 0;
829 }
830
smu_v11_0_init_max_sustainable_clocks(struct smu_context * smu)831 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
832 {
833 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
834 smu->smu_table.max_sustainable_clocks;
835 int ret = 0;
836
837 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
838 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
839 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
840 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
841 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
842 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
843
844 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
845 ret = smu_v11_0_get_max_sustainable_clock(smu,
846 &(max_sustainable_clocks->uclock),
847 SMU_UCLK);
848 if (ret) {
849 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
850 __func__);
851 return ret;
852 }
853 }
854
855 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
856 ret = smu_v11_0_get_max_sustainable_clock(smu,
857 &(max_sustainable_clocks->soc_clock),
858 SMU_SOCCLK);
859 if (ret) {
860 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
861 __func__);
862 return ret;
863 }
864 }
865
866 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
867 ret = smu_v11_0_get_max_sustainable_clock(smu,
868 &(max_sustainable_clocks->dcef_clock),
869 SMU_DCEFCLK);
870 if (ret) {
871 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
872 __func__);
873 return ret;
874 }
875
876 ret = smu_v11_0_get_max_sustainable_clock(smu,
877 &(max_sustainable_clocks->display_clock),
878 SMU_DISPCLK);
879 if (ret) {
880 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
881 __func__);
882 return ret;
883 }
884 ret = smu_v11_0_get_max_sustainable_clock(smu,
885 &(max_sustainable_clocks->phy_clock),
886 SMU_PHYCLK);
887 if (ret) {
888 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
889 __func__);
890 return ret;
891 }
892 ret = smu_v11_0_get_max_sustainable_clock(smu,
893 &(max_sustainable_clocks->pixel_clock),
894 SMU_PIXCLK);
895 if (ret) {
896 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
897 __func__);
898 return ret;
899 }
900 }
901
902 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
903 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
904
905 return 0;
906 }
907
smu_v11_0_get_current_power_limit(struct smu_context * smu,uint32_t * power_limit)908 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
909 uint32_t *power_limit)
910 {
911 int power_src;
912 int ret = 0;
913
914 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
915 return -EINVAL;
916
917 power_src = smu_cmn_to_asic_specific_index(smu,
918 CMN2ASIC_MAPPING_PWR,
919 smu->adev->pm.ac_power ?
920 SMU_POWER_SOURCE_AC :
921 SMU_POWER_SOURCE_DC);
922 if (power_src < 0)
923 return -EINVAL;
924
925 /*
926 * BIT 24-31: ControllerId (only PPT0 is supported for now)
927 * BIT 16-23: PowerSource
928 */
929 ret = smu_cmn_send_smc_msg_with_param(smu,
930 SMU_MSG_GetPptLimit,
931 (0 << 24) | (power_src << 16),
932 power_limit);
933 if (ret)
934 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
935
936 return ret;
937 }
938
smu_v11_0_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)939 int smu_v11_0_set_power_limit(struct smu_context *smu,
940 enum smu_ppt_limit_type limit_type,
941 uint32_t limit)
942 {
943 int power_src;
944 int ret = 0;
945 uint32_t limit_param;
946
947 if (limit_type != SMU_DEFAULT_PPT_LIMIT)
948 return -EINVAL;
949
950 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
951 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
952 return -EOPNOTSUPP;
953 }
954
955 power_src = smu_cmn_to_asic_specific_index(smu,
956 CMN2ASIC_MAPPING_PWR,
957 smu->adev->pm.ac_power ?
958 SMU_POWER_SOURCE_AC :
959 SMU_POWER_SOURCE_DC);
960 if (power_src < 0)
961 return -EINVAL;
962
963 /*
964 * BIT 24-31: ControllerId (only PPT0 is supported for now)
965 * BIT 16-23: PowerSource
966 * BIT 0-15: PowerLimit
967 */
968 limit_param = (limit & 0xFFFF);
969 limit_param |= 0 << 24;
970 limit_param |= (power_src) << 16;
971 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, limit_param, NULL);
972 if (ret) {
973 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
974 return ret;
975 }
976
977 smu->current_power_limit = limit;
978
979 return 0;
980 }
981
smu_v11_0_ack_ac_dc_interrupt(struct smu_context * smu)982 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
983 {
984 return smu_cmn_send_smc_msg(smu,
985 SMU_MSG_ReenableAcDcInterrupt,
986 NULL);
987 }
988
smu_v11_0_process_pending_interrupt(struct smu_context * smu)989 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
990 {
991 int ret = 0;
992
993 if (smu->dc_controlled_by_gpio &&
994 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
995 ret = smu_v11_0_ack_ac_dc_interrupt(smu);
996
997 return ret;
998 }
999
smu_v11_0_interrupt_work(struct smu_context * smu)1000 void smu_v11_0_interrupt_work(struct smu_context *smu)
1001 {
1002 if (smu_v11_0_ack_ac_dc_interrupt(smu))
1003 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
1004 }
1005
smu_v11_0_enable_thermal_alert(struct smu_context * smu)1006 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1007 {
1008 int ret = 0;
1009
1010 if (smu->smu_table.thermal_controller_type) {
1011 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1012 if (ret)
1013 return ret;
1014 }
1015
1016 /*
1017 * After init there might have been missed interrupts triggered
1018 * before driver registers for interrupt (Ex. AC/DC).
1019 */
1020 return smu_v11_0_process_pending_interrupt(smu);
1021 }
1022
smu_v11_0_disable_thermal_alert(struct smu_context * smu)1023 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1024 {
1025 int ret = 0;
1026
1027 if (smu->smu_table.thermal_controller_type)
1028 ret = amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1029
1030 return ret;
1031 }
1032
convert_to_vddc(uint8_t vid)1033 static uint16_t convert_to_vddc(uint8_t vid)
1034 {
1035 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1036 }
1037
smu_v11_0_get_gfx_vdd(struct smu_context * smu,uint32_t * value)1038 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1039 {
1040 struct amdgpu_device *adev = smu->adev;
1041 uint32_t vdd = 0, val_vid = 0;
1042
1043 if (!value)
1044 return -EINVAL;
1045 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1046 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1047 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1048
1049 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1050
1051 *value = vdd;
1052
1053 return 0;
1054
1055 }
1056
1057 int
smu_v11_0_display_clock_voltage_request(struct smu_context * smu,struct pp_display_clock_request * clock_req)1058 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1059 struct pp_display_clock_request
1060 *clock_req)
1061 {
1062 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1063 int ret = 0;
1064 enum smu_clk_type clk_select = 0;
1065 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1066
1067 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1068 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1069 switch (clk_type) {
1070 case amd_pp_dcef_clock:
1071 clk_select = SMU_DCEFCLK;
1072 break;
1073 case amd_pp_disp_clock:
1074 clk_select = SMU_DISPCLK;
1075 break;
1076 case amd_pp_pixel_clock:
1077 clk_select = SMU_PIXCLK;
1078 break;
1079 case amd_pp_phy_clock:
1080 clk_select = SMU_PHYCLK;
1081 break;
1082 case amd_pp_mem_clock:
1083 clk_select = SMU_UCLK;
1084 break;
1085 default:
1086 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1087 ret = -EINVAL;
1088 break;
1089 }
1090
1091 if (ret)
1092 goto failed;
1093
1094 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1095 return 0;
1096
1097 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1098
1099 if(clk_select == SMU_UCLK)
1100 smu->hard_min_uclk_req_from_dal = clk_freq;
1101 }
1102
1103 failed:
1104 return ret;
1105 }
1106
smu_v11_0_gfx_off_control(struct smu_context * smu,bool enable)1107 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1108 {
1109 int ret = 0;
1110 struct amdgpu_device *adev = smu->adev;
1111
1112 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1113 case IP_VERSION(11, 0, 0):
1114 case IP_VERSION(11, 0, 5):
1115 case IP_VERSION(11, 0, 9):
1116 case IP_VERSION(11, 0, 7):
1117 case IP_VERSION(11, 0, 11):
1118 case IP_VERSION(11, 0, 12):
1119 case IP_VERSION(11, 0, 13):
1120 case IP_VERSION(11, 5, 0):
1121 case IP_VERSION(11, 5, 2):
1122 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1123 return 0;
1124 if (enable)
1125 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1126 else
1127 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1128 break;
1129 default:
1130 break;
1131 }
1132
1133 return ret;
1134 }
1135
1136 uint32_t
smu_v11_0_get_fan_control_mode(struct smu_context * smu)1137 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1138 {
1139 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1140 return AMD_FAN_CTRL_AUTO;
1141 else
1142 return smu->user_dpm_profile.fan_mode;
1143 }
1144
1145 static int
smu_v11_0_auto_fan_control(struct smu_context * smu,bool auto_fan_control)1146 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1147 {
1148 int ret = 0;
1149
1150 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1151 return 0;
1152
1153 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1154 if (ret)
1155 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1156 __func__, (auto_fan_control ? "Start" : "Stop"));
1157
1158 return ret;
1159 }
1160
1161 static int
smu_v11_0_set_fan_static_mode(struct smu_context * smu,uint32_t mode)1162 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1163 {
1164 struct amdgpu_device *adev = smu->adev;
1165
1166 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1167 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1168 CG_FDO_CTRL2, TMIN, 0));
1169 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1170 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1171 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1172
1173 return 0;
1174 }
1175
1176 int
smu_v11_0_set_fan_speed_pwm(struct smu_context * smu,uint32_t speed)1177 smu_v11_0_set_fan_speed_pwm(struct smu_context *smu, uint32_t speed)
1178 {
1179 struct amdgpu_device *adev = smu->adev;
1180 uint32_t duty100, duty;
1181 uint64_t tmp64;
1182
1183 speed = min_t(uint32_t, speed, 255);
1184
1185 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1186 CG_FDO_CTRL1, FMAX_DUTY100);
1187 if (!duty100)
1188 return -EINVAL;
1189
1190 tmp64 = (uint64_t)speed * duty100;
1191 do_div(tmp64, 255);
1192 duty = (uint32_t)tmp64;
1193
1194 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1195 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1196 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1197
1198 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1199 }
1200
smu_v11_0_set_fan_speed_rpm(struct smu_context * smu,uint32_t speed)1201 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
1202 uint32_t speed)
1203 {
1204 struct amdgpu_device *adev = smu->adev;
1205 /*
1206 * crystal_clock_freq used for fan speed rpm calculation is
1207 * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1208 */
1209 uint32_t crystal_clock_freq = 2500;
1210 uint32_t tach_period;
1211
1212 if (!speed || speed > UINT_MAX/8)
1213 return -EINVAL;
1214 /*
1215 * To prevent from possible overheat, some ASICs may have requirement
1216 * for minimum fan speed:
1217 * - For some NV10 SKU, the fan speed cannot be set lower than
1218 * 700 RPM.
1219 * - For some Sienna Cichlid SKU, the fan speed cannot be set
1220 * lower than 500 RPM.
1221 */
1222 tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1223 WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
1224 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
1225 CG_TACH_CTRL, TARGET_PERIOD,
1226 tach_period));
1227
1228 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1229 }
1230
smu_v11_0_get_fan_speed_pwm(struct smu_context * smu,uint32_t * speed)1231 int smu_v11_0_get_fan_speed_pwm(struct smu_context *smu,
1232 uint32_t *speed)
1233 {
1234 struct amdgpu_device *adev = smu->adev;
1235 uint32_t duty100, duty;
1236 uint64_t tmp64;
1237
1238 /*
1239 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1240 * detected via register retrieving. To workaround this, we will
1241 * report the fan speed as 0 PWM if user just requested such.
1242 */
1243 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1244 && !smu->user_dpm_profile.fan_speed_pwm) {
1245 *speed = 0;
1246 return 0;
1247 }
1248
1249 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1250 CG_FDO_CTRL1, FMAX_DUTY100);
1251 duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
1252 CG_THERMAL_STATUS, FDO_PWM_DUTY);
1253 if (!duty100)
1254 return -EINVAL;
1255
1256 tmp64 = (uint64_t)duty * 255;
1257 do_div(tmp64, duty100);
1258 *speed = min_t(uint32_t, tmp64, 255);
1259
1260 return 0;
1261 }
1262
smu_v11_0_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1263 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
1264 uint32_t *speed)
1265 {
1266 struct amdgpu_device *adev = smu->adev;
1267 uint32_t crystal_clock_freq = 2500;
1268 uint32_t tach_status;
1269 uint64_t tmp64;
1270
1271 /*
1272 * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1273 * detected via register retrieving. To workaround this, we will
1274 * report the fan speed as 0 RPM if user just requested such.
1275 */
1276 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1277 && !smu->user_dpm_profile.fan_speed_rpm) {
1278 *speed = 0;
1279 return 0;
1280 }
1281
1282 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1283
1284 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS);
1285 if (tach_status) {
1286 do_div(tmp64, tach_status);
1287 *speed = (uint32_t)tmp64;
1288 } else {
1289 dev_warn_once(adev->dev, "Got zero output on CG_TACH_STATUS reading!\n");
1290 *speed = 0;
1291 }
1292
1293 return 0;
1294 }
1295
1296 int
smu_v11_0_set_fan_control_mode(struct smu_context * smu,uint32_t mode)1297 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1298 uint32_t mode)
1299 {
1300 int ret = 0;
1301
1302 switch (mode) {
1303 case AMD_FAN_CTRL_NONE:
1304 ret = smu_v11_0_auto_fan_control(smu, 0);
1305 if (!ret)
1306 ret = smu_v11_0_set_fan_speed_pwm(smu, 255);
1307 break;
1308 case AMD_FAN_CTRL_MANUAL:
1309 ret = smu_v11_0_auto_fan_control(smu, 0);
1310 break;
1311 case AMD_FAN_CTRL_AUTO:
1312 ret = smu_v11_0_auto_fan_control(smu, 1);
1313 break;
1314 default:
1315 break;
1316 }
1317
1318 if (ret) {
1319 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1320 return -EINVAL;
1321 }
1322
1323 return ret;
1324 }
1325
smu_v11_0_set_xgmi_pstate(struct smu_context * smu,uint32_t pstate)1326 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1327 uint32_t pstate)
1328 {
1329 return smu_cmn_send_smc_msg_with_param(smu,
1330 SMU_MSG_SetXgmiMode,
1331 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1332 NULL);
1333 }
1334
smu_v11_0_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1335 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1336 struct amdgpu_irq_src *source,
1337 unsigned tyep,
1338 enum amdgpu_interrupt_state state)
1339 {
1340 struct smu_context *smu = adev->powerplay.pp_handle;
1341 uint32_t low, high;
1342 uint32_t val = 0;
1343
1344 switch (state) {
1345 case AMDGPU_IRQ_STATE_DISABLE:
1346 /* For THM irqs */
1347 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1348 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1349 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1350 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1351
1352 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1353
1354 /* For MP1 SW irqs */
1355 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1356 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1357 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1358
1359 break;
1360 case AMDGPU_IRQ_STATE_ENABLE:
1361 /* For THM irqs */
1362 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1363 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1364 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1365 smu->thermal_range.software_shutdown_temp);
1366
1367 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1368 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1369 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1370 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1371 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1372 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1373 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1374 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1375 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1376
1377 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1378 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1379 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1380 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1381
1382 /* For MP1 SW irqs */
1383 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1384 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1385 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1386 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1387
1388 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1389 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1390 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1391
1392 break;
1393 default:
1394 break;
1395 }
1396
1397 return 0;
1398 }
1399
1400 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1401 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1402
1403 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1404
smu_v11_0_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1405 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1406 struct amdgpu_irq_src *source,
1407 struct amdgpu_iv_entry *entry)
1408 {
1409 struct smu_context *smu = adev->powerplay.pp_handle;
1410 uint32_t client_id = entry->client_id;
1411 uint32_t src_id = entry->src_id;
1412 /*
1413 * ctxid is used to distinguish different
1414 * events for SMCToHost interrupt.
1415 */
1416 uint32_t ctxid = entry->src_data[0];
1417 uint32_t data;
1418
1419 if (client_id == SOC15_IH_CLIENTID_THM) {
1420 switch (src_id) {
1421 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1422 schedule_delayed_work(&smu->swctf_delayed_work,
1423 msecs_to_jiffies(AMDGPU_SWCTF_EXTRA_DELAY));
1424 break;
1425 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1426 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1427 break;
1428 default:
1429 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1430 src_id);
1431 break;
1432 }
1433 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1434 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1435 /*
1436 * HW CTF just occurred. Shutdown to prevent further damage.
1437 */
1438 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1439 orderly_poweroff(true);
1440 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1441 if (src_id == SMU_IH_INTERRUPT_ID_TO_DRIVER) {
1442 /* ACK SMUToHost interrupt */
1443 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1444 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1445 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1446
1447 switch (ctxid) {
1448 case SMU_IH_INTERRUPT_CONTEXT_ID_AC:
1449 dev_dbg(adev->dev, "Switched to AC mode!\n");
1450 schedule_work(&smu->interrupt_work);
1451 adev->pm.ac_power = true;
1452 break;
1453 case SMU_IH_INTERRUPT_CONTEXT_ID_DC:
1454 dev_dbg(adev->dev, "Switched to DC mode!\n");
1455 schedule_work(&smu->interrupt_work);
1456 adev->pm.ac_power = false;
1457 break;
1458 case SMU_IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1459 /*
1460 * Increment the throttle interrupt counter
1461 */
1462 atomic64_inc(&smu->throttle_int_counter);
1463
1464 if (!atomic_read(&adev->throttling_logging_enabled))
1465 return 0;
1466
1467 if (__ratelimit(&adev->throttling_logging_rs))
1468 schedule_work(&smu->throttling_logging_work);
1469
1470 break;
1471 default:
1472 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1473 ctxid, client_id);
1474 break;
1475 }
1476 }
1477 }
1478
1479 return 0;
1480 }
1481
1482 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1483 {
1484 .set = smu_v11_0_set_irq_state,
1485 .process = smu_v11_0_irq_process,
1486 };
1487
smu_v11_0_register_irq_handler(struct smu_context * smu)1488 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1489 {
1490 struct amdgpu_device *adev = smu->adev;
1491 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1492 int ret = 0;
1493
1494 irq_src->num_types = 1;
1495 irq_src->funcs = &smu_v11_0_irq_funcs;
1496
1497 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1498 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1499 irq_src);
1500 if (ret)
1501 return ret;
1502
1503 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1504 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1505 irq_src);
1506 if (ret)
1507 return ret;
1508
1509 /* Register CTF(GPIO_19) interrupt */
1510 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1511 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1512 irq_src);
1513 if (ret)
1514 return ret;
1515
1516 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1517 SMU_IH_INTERRUPT_ID_TO_DRIVER,
1518 irq_src);
1519 if (ret)
1520 return ret;
1521
1522 return ret;
1523 }
1524
smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context * smu,struct pp_smu_nv_clock_table * max_clocks)1525 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1526 struct pp_smu_nv_clock_table *max_clocks)
1527 {
1528 struct smu_table_context *table_context = &smu->smu_table;
1529 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1530
1531 if (!max_clocks || !table_context->max_sustainable_clocks)
1532 return -EINVAL;
1533
1534 sustainable_clocks = table_context->max_sustainable_clocks;
1535
1536 max_clocks->dcfClockInKhz =
1537 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1538 max_clocks->displayClockInKhz =
1539 (unsigned int) sustainable_clocks->display_clock * 1000;
1540 max_clocks->phyClockInKhz =
1541 (unsigned int) sustainable_clocks->phy_clock * 1000;
1542 max_clocks->pixelClockInKhz =
1543 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1544 max_clocks->uClockInKhz =
1545 (unsigned int) sustainable_clocks->uclock * 1000;
1546 max_clocks->socClockInKhz =
1547 (unsigned int) sustainable_clocks->soc_clock * 1000;
1548 max_clocks->dscClockInKhz = 0;
1549 max_clocks->dppClockInKhz = 0;
1550 max_clocks->fabricClockInKhz = 0;
1551
1552 return 0;
1553 }
1554
smu_v11_0_set_azalia_d3_pme(struct smu_context * smu)1555 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1556 {
1557 return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1558 }
1559
smu_v11_0_baco_set_armd3_sequence(struct smu_context * smu,enum smu_baco_seq baco_seq)1560 int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu,
1561 enum smu_baco_seq baco_seq)
1562 {
1563 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1564 }
1565
smu_v11_0_get_bamaco_support(struct smu_context * smu)1566 int smu_v11_0_get_bamaco_support(struct smu_context *smu)
1567 {
1568 struct smu_baco_context *smu_baco = &smu->smu_baco;
1569 int bamaco_support = 0;
1570
1571 if (amdgpu_sriov_vf(smu->adev) || !smu_baco->platform_support)
1572 return 0;
1573
1574 if (smu_baco->maco_support)
1575 bamaco_support |= MACO_SUPPORT;
1576
1577 /* return true if ASIC is in BACO state already */
1578 if (smu_v11_0_baco_get_state(smu) == SMU_BACO_STATE_ENTER)
1579 return bamaco_support |= BACO_SUPPORT;
1580
1581 /* Arcturus does not support this bit mask */
1582 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1583 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1584 return 0;
1585
1586 return (bamaco_support |= BACO_SUPPORT);
1587 }
1588
smu_v11_0_baco_get_state(struct smu_context * smu)1589 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1590 {
1591 struct smu_baco_context *smu_baco = &smu->smu_baco;
1592
1593 return smu_baco->state;
1594 }
1595
1596 #define D3HOT_BACO_SEQUENCE 0
1597 #define D3HOT_BAMACO_SEQUENCE 2
1598
smu_v11_0_baco_set_state(struct smu_context * smu,enum smu_baco_state state)1599 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1600 {
1601 struct smu_baco_context *smu_baco = &smu->smu_baco;
1602 struct amdgpu_device *adev = smu->adev;
1603 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1604 uint32_t data;
1605 int ret = 0;
1606
1607 if (smu_v11_0_baco_get_state(smu) == state)
1608 return 0;
1609
1610 if (state == SMU_BACO_STATE_ENTER) {
1611 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1612 case IP_VERSION(11, 0, 7):
1613 case IP_VERSION(11, 0, 11):
1614 case IP_VERSION(11, 0, 12):
1615 case IP_VERSION(11, 0, 13):
1616 if (adev->pm.rpm_mode == AMDGPU_RUNPM_BAMACO)
1617 ret = smu_cmn_send_smc_msg_with_param(smu,
1618 SMU_MSG_EnterBaco,
1619 D3HOT_BAMACO_SEQUENCE,
1620 NULL);
1621 else
1622 ret = smu_cmn_send_smc_msg_with_param(smu,
1623 SMU_MSG_EnterBaco,
1624 D3HOT_BACO_SEQUENCE,
1625 NULL);
1626 break;
1627 default:
1628 if (!ras || !adev->ras_enabled ||
1629 (adev->init_lvl->level ==
1630 AMDGPU_INIT_LEVEL_MINIMAL_XGMI)) {
1631 if (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1632 IP_VERSION(11, 0, 2)) {
1633 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
1634 data |= 0x80000000;
1635 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
1636 } else {
1637 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1638 data |= 0x80000000;
1639 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1640 }
1641
1642 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1643 } else {
1644 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1645 }
1646 break;
1647 }
1648
1649 } else {
1650 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1651 if (ret)
1652 return ret;
1653
1654 /* clear vbios scratch 6 and 7 for coming asic reinit */
1655 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1656 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1657 }
1658
1659 if (!ret)
1660 smu_baco->state = state;
1661
1662 return ret;
1663 }
1664
smu_v11_0_baco_enter(struct smu_context * smu)1665 int smu_v11_0_baco_enter(struct smu_context *smu)
1666 {
1667 int ret = 0;
1668
1669 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1670 if (ret)
1671 return ret;
1672
1673 msleep(10);
1674
1675 return ret;
1676 }
1677
smu_v11_0_baco_exit(struct smu_context * smu)1678 int smu_v11_0_baco_exit(struct smu_context *smu)
1679 {
1680 int ret;
1681
1682 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1683 if (!ret) {
1684 /*
1685 * Poll BACO exit status to ensure FW has completed
1686 * BACO exit process to avoid timing issues.
1687 */
1688 smu_v11_0_poll_baco_exit(smu);
1689 }
1690
1691 return ret;
1692 }
1693
smu_v11_0_mode1_reset(struct smu_context * smu)1694 int smu_v11_0_mode1_reset(struct smu_context *smu)
1695 {
1696 int ret = 0;
1697
1698 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1699 if (!ret)
1700 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1701
1702 return ret;
1703 }
1704
smu_v11_0_handle_passthrough_sbr(struct smu_context * smu,bool enable)1705 int smu_v11_0_handle_passthrough_sbr(struct smu_context *smu, bool enable)
1706 {
1707 int ret = 0;
1708
1709 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LightSBR, enable ? 1 : 0, NULL);
1710
1711 return ret;
1712 }
1713
1714
smu_v11_0_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)1715 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1716 uint32_t *min, uint32_t *max)
1717 {
1718 int ret = 0, clk_id = 0;
1719 uint32_t param = 0;
1720 uint32_t clock_limit;
1721
1722 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1723 switch (clk_type) {
1724 case SMU_MCLK:
1725 case SMU_UCLK:
1726 clock_limit = smu->smu_table.boot_values.uclk;
1727 break;
1728 case SMU_GFXCLK:
1729 case SMU_SCLK:
1730 clock_limit = smu->smu_table.boot_values.gfxclk;
1731 break;
1732 case SMU_SOCCLK:
1733 clock_limit = smu->smu_table.boot_values.socclk;
1734 break;
1735 default:
1736 clock_limit = 0;
1737 break;
1738 }
1739
1740 /* clock in Mhz unit */
1741 if (min)
1742 *min = clock_limit / 100;
1743 if (max)
1744 *max = clock_limit / 100;
1745
1746 return 0;
1747 }
1748
1749 clk_id = smu_cmn_to_asic_specific_index(smu,
1750 CMN2ASIC_MAPPING_CLK,
1751 clk_type);
1752 if (clk_id < 0) {
1753 ret = -EINVAL;
1754 goto failed;
1755 }
1756 param = (clk_id & 0xffff) << 16;
1757
1758 if (max) {
1759 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1760 if (ret)
1761 goto failed;
1762 }
1763
1764 if (min) {
1765 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1766 if (ret)
1767 goto failed;
1768 }
1769
1770 failed:
1771 return ret;
1772 }
1773
smu_v11_0_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)1774 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1775 enum smu_clk_type clk_type,
1776 uint32_t min,
1777 uint32_t max,
1778 bool automatic)
1779 {
1780 int ret = 0, clk_id = 0;
1781 uint32_t param;
1782
1783 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1784 return 0;
1785
1786 clk_id = smu_cmn_to_asic_specific_index(smu,
1787 CMN2ASIC_MAPPING_CLK,
1788 clk_type);
1789 if (clk_id < 0)
1790 return clk_id;
1791
1792 if (max > 0) {
1793 if (automatic)
1794 param = (uint32_t)((clk_id << 16) | 0xffff);
1795 else
1796 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1797 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1798 param, NULL);
1799 if (ret)
1800 goto out;
1801 }
1802
1803 if (min > 0) {
1804 if (automatic)
1805 param = (uint32_t)((clk_id << 16) | 0);
1806 else
1807 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1808 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1809 param, NULL);
1810 if (ret)
1811 goto out;
1812 }
1813
1814 out:
1815 return ret;
1816 }
1817
smu_v11_0_set_hard_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max)1818 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1819 enum smu_clk_type clk_type,
1820 uint32_t min,
1821 uint32_t max)
1822 {
1823 int ret = 0, clk_id = 0;
1824 uint32_t param;
1825
1826 if (min <= 0 && max <= 0)
1827 return -EINVAL;
1828
1829 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1830 return 0;
1831
1832 clk_id = smu_cmn_to_asic_specific_index(smu,
1833 CMN2ASIC_MAPPING_CLK,
1834 clk_type);
1835 if (clk_id < 0)
1836 return clk_id;
1837
1838 if (max > 0) {
1839 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1840 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1841 param, NULL);
1842 if (ret)
1843 return ret;
1844 }
1845
1846 if (min > 0) {
1847 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1848 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1849 param, NULL);
1850 if (ret)
1851 return ret;
1852 }
1853
1854 return ret;
1855 }
1856
smu_v11_0_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1857 int smu_v11_0_set_performance_level(struct smu_context *smu,
1858 enum amd_dpm_forced_level level)
1859 {
1860 struct smu_11_0_dpm_context *dpm_context =
1861 smu->smu_dpm.dpm_context;
1862 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
1863 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
1864 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
1865 struct smu_umd_pstate_table *pstate_table =
1866 &smu->pstate_table;
1867 struct amdgpu_device *adev = smu->adev;
1868 uint32_t sclk_min = 0, sclk_max = 0;
1869 uint32_t mclk_min = 0, mclk_max = 0;
1870 uint32_t socclk_min = 0, socclk_max = 0;
1871 int ret = 0;
1872 bool auto_level = false;
1873
1874 switch (level) {
1875 case AMD_DPM_FORCED_LEVEL_HIGH:
1876 sclk_min = sclk_max = SMU_DPM_TABLE_MAX(gfx_table);
1877 mclk_min = mclk_max = SMU_DPM_TABLE_MAX(mem_table);
1878 socclk_min = socclk_max = SMU_DPM_TABLE_MAX(soc_table);
1879 break;
1880 case AMD_DPM_FORCED_LEVEL_LOW:
1881 sclk_min = sclk_max = SMU_DPM_TABLE_MIN(gfx_table);
1882 mclk_min = mclk_max = SMU_DPM_TABLE_MIN(mem_table);
1883 socclk_min = socclk_max = SMU_DPM_TABLE_MIN(soc_table);
1884 break;
1885 case AMD_DPM_FORCED_LEVEL_AUTO:
1886 sclk_min = SMU_DPM_TABLE_MIN(gfx_table);
1887 sclk_max = SMU_DPM_TABLE_MAX(gfx_table);
1888 mclk_min = SMU_DPM_TABLE_MIN(mem_table);
1889 mclk_max = SMU_DPM_TABLE_MAX(mem_table);
1890 socclk_min = SMU_DPM_TABLE_MIN(soc_table);
1891 socclk_max = SMU_DPM_TABLE_MAX(soc_table);
1892 auto_level = true;
1893 break;
1894 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1895 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1896 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1897 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1898 break;
1899 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1900 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1901 break;
1902 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1903 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1904 break;
1905 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1906 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1907 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1908 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1909 break;
1910 case AMD_DPM_FORCED_LEVEL_MANUAL:
1911 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1912 return 0;
1913 default:
1914 dev_err(adev->dev, "Invalid performance level %d\n", level);
1915 return -EINVAL;
1916 }
1917
1918 /*
1919 * Separate MCLK and SOCCLK soft min/max settings are not allowed
1920 * on Arcturus.
1921 */
1922 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) {
1923 mclk_min = mclk_max = 0;
1924 socclk_min = socclk_max = 0;
1925 auto_level = false;
1926 }
1927
1928 if (sclk_min && sclk_max) {
1929 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1930 SMU_GFXCLK,
1931 sclk_min,
1932 sclk_max,
1933 auto_level);
1934 if (ret)
1935 return ret;
1936 }
1937
1938 if (mclk_min && mclk_max) {
1939 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1940 SMU_MCLK,
1941 mclk_min,
1942 mclk_max,
1943 auto_level);
1944 if (ret)
1945 return ret;
1946 }
1947
1948 if (socclk_min && socclk_max) {
1949 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1950 SMU_SOCCLK,
1951 socclk_min,
1952 socclk_max,
1953 auto_level);
1954 if (ret)
1955 return ret;
1956 }
1957
1958 return ret;
1959 }
1960
smu_v11_0_set_power_source(struct smu_context * smu,enum smu_power_src_type power_src)1961 int smu_v11_0_set_power_source(struct smu_context *smu,
1962 enum smu_power_src_type power_src)
1963 {
1964 int pwr_source;
1965
1966 pwr_source = smu_cmn_to_asic_specific_index(smu,
1967 CMN2ASIC_MAPPING_PWR,
1968 (uint32_t)power_src);
1969 if (pwr_source < 0)
1970 return -EINVAL;
1971
1972 return smu_cmn_send_smc_msg_with_param(smu,
1973 SMU_MSG_NotifyPowerSource,
1974 pwr_source,
1975 NULL);
1976 }
1977
smu_v11_0_get_dpm_freq_by_index(struct smu_context * smu,enum smu_clk_type clk_type,uint16_t level,uint32_t * value)1978 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1979 enum smu_clk_type clk_type,
1980 uint16_t level,
1981 uint32_t *value)
1982 {
1983 int ret = 0, clk_id = 0;
1984 uint32_t param;
1985
1986 if (!value)
1987 return -EINVAL;
1988
1989 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1990 return 0;
1991
1992 clk_id = smu_cmn_to_asic_specific_index(smu,
1993 CMN2ASIC_MAPPING_CLK,
1994 clk_type);
1995 if (clk_id < 0)
1996 return clk_id;
1997
1998 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1999
2000 ret = smu_cmn_send_smc_msg_with_param(smu,
2001 SMU_MSG_GetDpmFreqByIndex,
2002 param,
2003 value);
2004 if (ret)
2005 return ret;
2006
2007 /*
2008 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
2009 * now, we un-support it
2010 */
2011 *value = *value & 0x7fffffff;
2012
2013 return ret;
2014 }
2015
smu_v11_0_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)2016 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
2017 enum smu_clk_type clk_type,
2018 uint32_t *value)
2019 {
2020 return smu_v11_0_get_dpm_freq_by_index(smu,
2021 clk_type,
2022 0xff,
2023 value);
2024 }
2025
smu_v11_0_set_single_dpm_table(struct smu_context * smu,enum smu_clk_type clk_type,struct smu_dpm_table * single_dpm_table)2026 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
2027 enum smu_clk_type clk_type,
2028 struct smu_dpm_table *single_dpm_table)
2029 {
2030 int ret = 0;
2031 uint32_t clk;
2032 int i;
2033
2034 ret = smu_v11_0_get_dpm_level_count(smu,
2035 clk_type,
2036 &single_dpm_table->count);
2037 if (ret) {
2038 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
2039 return ret;
2040 }
2041
2042 for (i = 0; i < single_dpm_table->count; i++) {
2043 ret = smu_v11_0_get_dpm_freq_by_index(smu,
2044 clk_type,
2045 i,
2046 &clk);
2047 if (ret) {
2048 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
2049 return ret;
2050 }
2051
2052 single_dpm_table->dpm_levels[i].value = clk;
2053 single_dpm_table->dpm_levels[i].enabled = true;
2054 }
2055
2056 return 0;
2057 }
2058
smu_v11_0_get_current_pcie_link_width_level(struct smu_context * smu)2059 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
2060 {
2061 struct amdgpu_device *adev = smu->adev;
2062
2063 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2064 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2065 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2066 }
2067
smu_v11_0_get_current_pcie_link_width(struct smu_context * smu)2068 uint16_t smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
2069 {
2070 uint32_t width_level;
2071
2072 width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
2073 if (width_level > LINK_WIDTH_MAX)
2074 width_level = 0;
2075
2076 return link_width[width_level];
2077 }
2078
smu_v11_0_get_current_pcie_link_speed_level(struct smu_context * smu)2079 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2080 {
2081 struct amdgpu_device *adev = smu->adev;
2082
2083 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2084 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2085 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2086 }
2087
smu_v11_0_get_current_pcie_link_speed(struct smu_context * smu)2088 uint16_t smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2089 {
2090 uint32_t speed_level;
2091
2092 speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2093 if (speed_level > LINK_SPEED_MAX)
2094 speed_level = 0;
2095
2096 return link_speed[speed_level];
2097 }
2098
smu_v11_0_gfx_ulv_control(struct smu_context * smu,bool enablement)2099 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2100 bool enablement)
2101 {
2102 int ret = 0;
2103
2104 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2105 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2106
2107 return ret;
2108 }
2109
smu_v11_0_deep_sleep_control(struct smu_context * smu,bool enablement)2110 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2111 bool enablement)
2112 {
2113 struct amdgpu_device *adev = smu->adev;
2114 int ret = 0;
2115
2116 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2117 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2118 if (ret) {
2119 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2120 return ret;
2121 }
2122 }
2123
2124 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2125 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2126 if (ret) {
2127 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2128 return ret;
2129 }
2130 }
2131
2132 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2133 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2134 if (ret) {
2135 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2136 return ret;
2137 }
2138 }
2139
2140 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2141 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2142 if (ret) {
2143 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2144 return ret;
2145 }
2146 }
2147
2148 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2149 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2150 if (ret) {
2151 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
2152 return ret;
2153 }
2154 }
2155
2156 return ret;
2157 }
2158
smu_v11_0_restore_user_od_settings(struct smu_context * smu)2159 int smu_v11_0_restore_user_od_settings(struct smu_context *smu)
2160 {
2161 struct smu_table_context *table_context = &smu->smu_table;
2162 void *user_od_table = table_context->user_overdrive_table;
2163 int ret = 0;
2164
2165 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)user_od_table, true);
2166 if (ret)
2167 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2168
2169 return ret;
2170 }
2171
smu_v11_0_init_msg_ctl(struct smu_context * smu,const struct cmn2asic_msg_mapping * message_map)2172 void smu_v11_0_init_msg_ctl(struct smu_context *smu,
2173 const struct cmn2asic_msg_mapping *message_map)
2174 {
2175 struct amdgpu_device *adev = smu->adev;
2176 struct smu_msg_ctl *ctl = &smu->msg_ctl;
2177
2178 ctl->smu = smu;
2179 mutex_init(&ctl->lock);
2180 ctl->config.msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
2181 ctl->config.resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
2182 ctl->config.arg_regs[0] = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
2183 ctl->config.num_arg_regs = 1;
2184 ctl->ops = &smu_msg_v1_ops;
2185 ctl->default_timeout = adev->usec_timeout * 20;
2186 ctl->message_map = message_map;
2187 }
2188