xref: /linux/arch/openrisc/include/asm/cacheflush.h (revision ec0c2d5359e2f288d75d98465829d31c6d26da47)
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * OpenRISC Linux
4  *
5  * Linux architectural port borrowing liberally from similar works of
6  * others.  All original copyrights apply as per the original source
7  * declaration.
8  *
9  * OpenRISC implementation:
10  * Copyright (C) Jan Henrik Weinstock <jan.weinstock@rwth-aachen.de>
11  * et al.
12  */
13 
14 #ifndef __ASM_CACHEFLUSH_H
15 #define __ASM_CACHEFLUSH_H
16 
17 #include <linux/mm.h>
18 
19 /*
20  * Helper function for flushing or invalidating entire pages from data
21  * and instruction caches. SMP needs a little extra work, since we need
22  * to flush the pages on all cpus.
23  */
24 extern void local_dcache_page_flush(struct page *page);
25 extern void local_icache_page_inv(struct page *page);
26 extern void local_dcache_range_flush(unsigned long start, unsigned long end);
27 extern void local_dcache_range_inv(unsigned long start, unsigned long end);
28 extern void local_icache_range_inv(unsigned long start, unsigned long end);
29 
30 /*
31  * Data cache flushing always happen on the local cpu. Instruction cache
32  * invalidations need to be broadcasted to all other cpu in the system in
33  * case of SMP configurations.
34  */
35 #ifndef CONFIG_SMP
36 #define dcache_page_flush(page)      local_dcache_page_flush(page)
37 #define icache_page_inv(page)        local_icache_page_inv(page)
38 #else  /* CONFIG_SMP */
39 #define dcache_page_flush(page)      local_dcache_page_flush(page)
40 #define icache_page_inv(page)        smp_icache_page_inv(page)
41 extern void smp_icache_page_inv(struct page *page);
42 #endif /* CONFIG_SMP */
43 
44 /*
45  * Even if the actual block size is larger than L1_CACHE_BYTES, paddr
46  * can be incremented by L1_CACHE_BYTES. When paddr is written to the
47  * invalidate register, the entire cache line encompassing this address
48  * is invalidated. Each subsequent reference to the same cache line will
49  * not affect the invalidation process.
50  */
51 #define local_dcache_block_flush(addr) \
52 	local_dcache_range_flush(addr, addr + L1_CACHE_BYTES)
53 #define local_dcache_block_inv(addr) \
54 	local_dcache_range_inv(addr, addr + L1_CACHE_BYTES)
55 #define local_icache_block_inv(addr) \
56 	local_icache_range_inv(addr, addr + L1_CACHE_BYTES)
57 
58 /*
59  * Synchronizes caches. Whenever a cpu writes executable code to memory, this
60  * should be called to make sure the processor sees the newly written code.
61  */
sync_icache_dcache(struct page * page)62 static inline void sync_icache_dcache(struct page *page)
63 {
64 	if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
65 		dcache_page_flush(page);
66 	icache_page_inv(page);
67 }
68 
69 /*
70  * Pages with this bit set need not be flushed/invalidated, since
71  * they have not changed since last flush. New pages start with
72  * PG_arch_1 not set and are therefore dirty by default.
73  */
74 #define PG_dc_clean                  PG_arch_1
75 
flush_dcache_folio(struct folio * folio)76 static inline void flush_dcache_folio(struct folio *folio)
77 {
78 	clear_bit(PG_dc_clean, &folio->flags);
79 }
80 #define flush_dcache_folio flush_dcache_folio
81 
82 #define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
flush_dcache_page(struct page * page)83 static inline void flush_dcache_page(struct page *page)
84 {
85 	flush_dcache_folio(page_folio(page));
86 }
87 
88 #define flush_icache_user_page(vma, page, addr, len)	\
89 do {							\
90 	if (vma->vm_flags & VM_EXEC)			\
91 		sync_icache_dcache(page);		\
92 } while (0)
93 
94 #include <asm-generic/cacheflush.h>
95 
96 #endif /* __ASM_CACHEFLUSH_H */
97