1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * mpc8xxx_wdt.c - MPC8xx/MPC83xx/MPC86xx watchdog userspace interface
4 *
5 * Authors: Dave Updegraff <dave@cray.org>
6 * Kumar Gala <galak@kernel.crashing.org>
7 * Attribution: from 83xx_wst: Florian Schirmer <jolt@tuxbox.org>
8 * ..and from sc520_wdt
9 * Copyright (c) 2008 MontaVista Software, Inc.
10 * Anton Vorontsov <avorontsov@ru.mvista.com>
11 *
12 * Note: it appears that you can only actually ENABLE or DISABLE the thing
13 * once after POR. Once enabled, you cannot disable, and vice versa.
14 */
15
16 #include <linux/fs.h>
17 #include <linux/init.h>
18 #include <linux/kernel.h>
19 #include <linux/of.h>
20 #include <linux/platform_device.h>
21 #include <linux/module.h>
22 #include <linux/watchdog.h>
23 #include <linux/io.h>
24 #include <linux/uaccess.h>
25 #include <sysdev/fsl_soc.h>
26
27 #define WATCHDOG_TIMEOUT 10
28
29 struct mpc8xxx_wdt {
30 __be32 res0;
31 __be32 swcrr; /* System watchdog control register */
32 #define SWCRR_SWTC 0xFFFF0000 /* Software Watchdog Time Count. */
33 #define SWCRR_SWF 0x00000008 /* Software Watchdog Freeze (mpc8xx). */
34 #define SWCRR_SWEN 0x00000004 /* Watchdog Enable bit. */
35 #define SWCRR_SWRI 0x00000002 /* Software Watchdog Reset/Interrupt Select bit.*/
36 #define SWCRR_SWPR 0x00000001 /* Software Watchdog Counter Prescale bit. */
37 __be32 swcnr; /* System watchdog count register */
38 u8 res1[2];
39 __be16 swsrr; /* System watchdog service register */
40 u8 res2[0xF0];
41 };
42
43 struct mpc8xxx_wdt_type {
44 int prescaler;
45 bool hw_enabled;
46 u32 rsr_mask;
47 };
48
49 struct mpc8xxx_wdt_ddata {
50 struct mpc8xxx_wdt __iomem *base;
51 struct watchdog_device wdd;
52 spinlock_t lock;
53 u16 swtc;
54 };
55
56 static u16 timeout;
57 module_param(timeout, ushort, 0);
58 MODULE_PARM_DESC(timeout,
59 "Watchdog timeout in seconds. (1<timeout<65535, default="
60 __MODULE_STRING(WATCHDOG_TIMEOUT) ")");
61
62 static bool reset = 1;
63 module_param(reset, bool, 0);
64 MODULE_PARM_DESC(reset,
65 "Watchdog Interrupt/Reset Mode. 0 = interrupt, 1 = reset");
66
67 static bool nowayout = WATCHDOG_NOWAYOUT;
68 module_param(nowayout, bool, 0);
69 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
70 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
71
mpc8xxx_wdt_keepalive(struct mpc8xxx_wdt_ddata * ddata)72 static void mpc8xxx_wdt_keepalive(struct mpc8xxx_wdt_ddata *ddata)
73 {
74 /* Ping the WDT */
75 spin_lock(&ddata->lock);
76 out_be16(&ddata->base->swsrr, 0x556c);
77 out_be16(&ddata->base->swsrr, 0xaa39);
78 spin_unlock(&ddata->lock);
79 }
80
mpc8xxx_wdt_start(struct watchdog_device * w)81 static int mpc8xxx_wdt_start(struct watchdog_device *w)
82 {
83 struct mpc8xxx_wdt_ddata *ddata =
84 container_of(w, struct mpc8xxx_wdt_ddata, wdd);
85 u32 tmp = in_be32(&ddata->base->swcrr);
86
87 /* Good, fire up the show */
88 tmp &= ~(SWCRR_SWTC | SWCRR_SWF | SWCRR_SWEN | SWCRR_SWRI | SWCRR_SWPR);
89 tmp |= SWCRR_SWEN | SWCRR_SWPR | (ddata->swtc << 16);
90
91 if (reset)
92 tmp |= SWCRR_SWRI;
93
94 out_be32(&ddata->base->swcrr, tmp);
95
96 tmp = in_be32(&ddata->base->swcrr);
97 if (!(tmp & SWCRR_SWEN))
98 return -EOPNOTSUPP;
99
100 ddata->swtc = tmp >> 16;
101 set_bit(WDOG_HW_RUNNING, &ddata->wdd.status);
102
103 mpc8xxx_wdt_keepalive(ddata);
104
105 return 0;
106 }
107
mpc8xxx_wdt_ping(struct watchdog_device * w)108 static int mpc8xxx_wdt_ping(struct watchdog_device *w)
109 {
110 struct mpc8xxx_wdt_ddata *ddata =
111 container_of(w, struct mpc8xxx_wdt_ddata, wdd);
112
113 mpc8xxx_wdt_keepalive(ddata);
114 return 0;
115 }
116
117 static struct watchdog_info mpc8xxx_wdt_info = {
118 .options = WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE | WDIOF_SETTIMEOUT,
119 .firmware_version = 1,
120 .identity = "MPC8xxx",
121 };
122
123 static const struct watchdog_ops mpc8xxx_wdt_ops = {
124 .owner = THIS_MODULE,
125 .start = mpc8xxx_wdt_start,
126 .ping = mpc8xxx_wdt_ping,
127 };
128
mpc8xxx_wdt_probe(struct platform_device * ofdev)129 static int mpc8xxx_wdt_probe(struct platform_device *ofdev)
130 {
131 int ret;
132 struct resource *res;
133 const struct mpc8xxx_wdt_type *wdt_type;
134 struct mpc8xxx_wdt_ddata *ddata;
135 u32 freq = fsl_get_sys_freq();
136 bool enabled;
137 struct device *dev = &ofdev->dev;
138
139 wdt_type = of_device_get_match_data(dev);
140 if (!wdt_type)
141 return -EINVAL;
142
143 if (!freq || freq == -1)
144 return -EINVAL;
145
146 ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL);
147 if (!ddata)
148 return -ENOMEM;
149
150 ddata->base = devm_platform_ioremap_resource(ofdev, 0);
151 if (IS_ERR(ddata->base))
152 return PTR_ERR(ddata->base);
153
154 enabled = in_be32(&ddata->base->swcrr) & SWCRR_SWEN;
155 if (!enabled && wdt_type->hw_enabled) {
156 dev_info(dev, "could not be enabled in software\n");
157 return -ENODEV;
158 }
159
160 res = platform_get_resource(ofdev, IORESOURCE_MEM, 1);
161 if (res) {
162 bool status;
163 u32 __iomem *rsr = ioremap(res->start, resource_size(res));
164
165 if (!rsr)
166 return -ENOMEM;
167
168 status = in_be32(rsr) & wdt_type->rsr_mask;
169 ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0;
170 /* clear reset status bits related to watchdog timer */
171 out_be32(rsr, wdt_type->rsr_mask);
172 iounmap(rsr);
173
174 dev_info(dev, "Last boot was %scaused by watchdog\n",
175 status ? "" : "not ");
176 }
177
178 spin_lock_init(&ddata->lock);
179
180 ddata->wdd.info = &mpc8xxx_wdt_info;
181 ddata->wdd.ops = &mpc8xxx_wdt_ops;
182
183 ddata->wdd.timeout = WATCHDOG_TIMEOUT;
184 watchdog_init_timeout(&ddata->wdd, timeout, dev);
185
186 watchdog_set_nowayout(&ddata->wdd, nowayout);
187
188 ddata->swtc = min(ddata->wdd.timeout * freq / wdt_type->prescaler,
189 0xffffU);
190
191 /*
192 * If the watchdog was previously enabled or we're running on
193 * MPC8xxx, we should ping the wdt from the kernel until the
194 * userspace handles it.
195 */
196 if (enabled)
197 mpc8xxx_wdt_start(&ddata->wdd);
198
199 ddata->wdd.max_hw_heartbeat_ms = (ddata->swtc * wdt_type->prescaler) /
200 (freq / 1000);
201 ddata->wdd.min_timeout = ddata->wdd.max_hw_heartbeat_ms / 1000;
202 if (ddata->wdd.timeout < ddata->wdd.min_timeout)
203 ddata->wdd.timeout = ddata->wdd.min_timeout;
204
205 ret = devm_watchdog_register_device(dev, &ddata->wdd);
206 if (ret)
207 return ret;
208
209 dev_info(dev,
210 "WDT driver for MPC8xxx initialized. mode:%s timeout=%d sec\n",
211 reset ? "reset" : "interrupt", ddata->wdd.timeout);
212
213 platform_set_drvdata(ofdev, ddata);
214 return 0;
215 }
216
217 static const struct of_device_id mpc8xxx_wdt_match[] = {
218 {
219 .compatible = "mpc83xx_wdt",
220 .data = &(struct mpc8xxx_wdt_type) {
221 .prescaler = 0x10000,
222 .rsr_mask = BIT(3), /* RSR Bit SWRS */
223 },
224 },
225 {
226 .compatible = "fsl,mpc8610-wdt",
227 .data = &(struct mpc8xxx_wdt_type) {
228 .prescaler = 0x10000,
229 .hw_enabled = true,
230 .rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */
231 },
232 },
233 {
234 .compatible = "fsl,mpc823-wdt",
235 .data = &(struct mpc8xxx_wdt_type) {
236 .prescaler = 0x800,
237 .hw_enabled = true,
238 .rsr_mask = BIT(28), /* RSR Bit SWRS */
239 },
240 },
241 {},
242 };
243 MODULE_DEVICE_TABLE(of, mpc8xxx_wdt_match);
244
245 static struct platform_driver mpc8xxx_wdt_driver = {
246 .probe = mpc8xxx_wdt_probe,
247 .driver = {
248 .name = "mpc8xxx_wdt",
249 .of_match_table = mpc8xxx_wdt_match,
250 },
251 };
252
mpc8xxx_wdt_init(void)253 static int __init mpc8xxx_wdt_init(void)
254 {
255 return platform_driver_register(&mpc8xxx_wdt_driver);
256 }
257 arch_initcall(mpc8xxx_wdt_init);
258
mpc8xxx_wdt_exit(void)259 static void __exit mpc8xxx_wdt_exit(void)
260 {
261 platform_driver_unregister(&mpc8xxx_wdt_driver);
262 }
263 module_exit(mpc8xxx_wdt_exit);
264
265 MODULE_AUTHOR("Dave Updegraff, Kumar Gala");
266 MODULE_DESCRIPTION("Driver for watchdog timer in MPC8xx/MPC83xx/MPC86xx "
267 "uProcessors");
268 MODULE_LICENSE("GPL");
269