1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
3
4 #ifndef _WX_TYPE_H_
5 #define _WX_TYPE_H_
6
7 #include <linux/ptp_clock_kernel.h>
8 #include <linux/timecounter.h>
9 #include <linux/bitfield.h>
10 #include <linux/netdevice.h>
11 #include <linux/if_vlan.h>
12 #include <linux/phylink.h>
13 #include <linux/dim.h>
14 #include <net/ip.h>
15
16 #define WX_NCSI_SUP 0x8000
17 #define WX_NCSI_MASK 0x8000
18 #define WX_WOL_SUP 0x4000
19 #define WX_WOL_MASK 0x4000
20
21 /* MSI-X capability fields masks */
22 #define WX_PCIE_MSIX_TBL_SZ_MASK 0x7FF
23 #define WX_PCI_LINK_STATUS 0xB2
24 #define WX_MAX_PF_MACVLANS 15
25 #define WX_MAX_VF_MC_ENTRIES 30
26
27 /**************** Global Registers ****************************/
28 #define WX_VF_REG_OFFSET(_v) FIELD_GET(GENMASK(15, 5), (_v))
29 #define WX_VF_IND_SHIFT(_v) FIELD_GET(GENMASK(4, 0), (_v))
30
31 /* chip control Registers */
32 #define WX_MIS_PWR 0x10000
33 #define WX_MIS_RST 0x1000C
34 #define WX_MIS_RST_LAN_RST(_i) BIT((_i) + 1)
35 #define WX_MIS_RST_SW_RST BIT(0)
36 #define WX_MIS_ST 0x10028
37 #define WX_MIS_ST_MNG_INIT_DN BIT(0)
38 #define WX_MIS_SWSM 0x1002C
39 #define WX_MIS_SWSM_SMBI BIT(0)
40 #define WX_MIS_RST_ST 0x10030
41 #define WX_MIS_RST_ST_RST_INI_SHIFT 8
42 #define WX_MIS_RST_ST_RST_INIT (0xFF << WX_MIS_RST_ST_RST_INI_SHIFT)
43
44 /* FMGR Registers */
45 #define WX_SPI_CMD 0x10104
46 #define WX_SPI_CMD_READ_DWORD 0x1
47 #define WX_SPI_CLK_DIV 0x3
48 #define WX_SPI_CMD_CMD(_v) FIELD_PREP(GENMASK(30, 28), _v)
49 #define WX_SPI_CMD_CLK(_v) FIELD_PREP(GENMASK(27, 25), _v)
50 #define WX_SPI_CMD_ADDR(_v) FIELD_PREP(GENMASK(23, 0), _v)
51 #define WX_SPI_DATA 0x10108
52 #define WX_SPI_DATA_BYPASS BIT(31)
53 #define WX_SPI_DATA_OP_DONE BIT(0)
54 #define WX_SPI_STATUS 0x1010C
55 #define WX_SPI_STATUS_OPDONE BIT(0)
56 #define WX_SPI_STATUS_FLASH_BYPASS BIT(31)
57 #define WX_SPI_ILDR_STATUS 0x10120
58
59 /* Sensors for PVT(Process Voltage Temperature) */
60 #define WX_TS_EN 0x10304
61 #define WX_TS_EN_ENA BIT(0)
62 #define WX_TS_ALARM_THRE 0x1030C
63 #define WX_TS_DALARM_THRE 0x10310
64 #define WX_TS_INT_EN 0x10314
65 #define WX_TS_INT_EN_DALARM_INT_EN BIT(1)
66 #define WX_TS_INT_EN_ALARM_INT_EN BIT(0)
67 #define WX_TS_ALARM_ST 0x10318
68 #define WX_TS_ALARM_ST_DALARM BIT(1)
69 #define WX_TS_ALARM_ST_ALARM BIT(0)
70
71 /* statistic */
72 #define WX_TX_FRAME_CNT_GOOD_BAD_L 0x1181C
73 #define WX_TX_BC_FRAMES_GOOD_L 0x11824
74 #define WX_TX_MC_FRAMES_GOOD_L 0x1182C
75 #define WX_RX_FRAME_CNT_GOOD_BAD_L 0x11900
76 #define WX_RX_BC_FRAMES_GOOD_L 0x11918
77 #define WX_RX_MC_FRAMES_GOOD_L 0x11920
78 #define WX_RX_CRC_ERROR_FRAMES_L 0x11928
79 #define WX_RX_LEN_ERROR_FRAMES_L 0x11978
80 #define WX_RX_UNDERSIZE_FRAMES_GOOD 0x11938
81 #define WX_RX_OVERSIZE_FRAMES_GOOD 0x1193C
82 #define WX_MAC_LXONOFFRXC 0x11E0C
83
84 /*********************** Receive DMA registers **************************/
85 #define WX_RDM_VF_RE(_i) (0x12004 + ((_i) * 4))
86 #define WX_RDM_RSC_CTL 0x1200C
87 #define WX_RDM_RSC_CTL_FREE_CNT_DIS BIT(8)
88 #define WX_RDM_RSC_CTL_FREE_CTL BIT(7)
89 #define WX_RDM_PF_QDE(_i) (0x12080 + ((_i) * 4))
90 #define WX_RDM_VFRE_CLR(_i) (0x120A0 + ((_i) * 4))
91 #define WX_RDM_DCACHE_CTL 0x120A8
92 #define WX_RDM_DCACHE_CTL_EN BIT(0)
93 #define WX_RDM_DRP_PKT 0x12500
94 #define WX_RDM_PKT_CNT 0x12504
95 #define WX_RDM_BYTE_CNT_LSB 0x12508
96 #define WX_RDM_BMC2OS_CNT 0x12510
97
98 /************************* Port Registers ************************************/
99 /* port cfg Registers */
100 #define WX_CFG_PORT_CTL 0x14400
101 #define WX_CFG_PORT_CTL_PFRSTD BIT(14)
102 #define WX_CFG_PORT_CTL_DRV_LOAD BIT(3)
103 #define WX_CFG_PORT_CTL_QINQ BIT(2)
104 #define WX_CFG_PORT_CTL_D_VLAN BIT(0) /* double vlan*/
105 #define WX_CFG_PORT_ST 0x14404
106 #define WX_CFG_PORT_ST_LANID GENMASK(9, 8)
107 #define WX_CFG_TAG_TPID(_i) (0x14430 + ((_i) * 4))
108 #define WX_CFG_PORT_CTL_NUM_VT_MASK GENMASK(13, 12) /* number of TVs */
109
110 #define WX_CFG_PORT_CTL_NUM_VT_NONE 0
111 #define WX_CFG_PORT_CTL_NUM_VT_8 FIELD_PREP(GENMASK(13, 12), 1)
112 #define WX_CFG_PORT_CTL_NUM_VT_32 FIELD_PREP(GENMASK(13, 12), 2)
113 #define WX_CFG_PORT_CTL_NUM_VT_64 FIELD_PREP(GENMASK(13, 12), 3)
114
115 /* GPIO Registers */
116 #define WX_GPIO_DR 0x14800
117 #define WX_GPIO_DR_0 BIT(0) /* SDP0 Data Value */
118 #define WX_GPIO_DR_1 BIT(1) /* SDP1 Data Value */
119 #define WX_GPIO_DDR 0x14804
120 #define WX_GPIO_DDR_0 BIT(0) /* SDP0 IO direction */
121 #define WX_GPIO_DDR_1 BIT(1) /* SDP1 IO direction */
122 #define WX_GPIO_CTL 0x14808
123 #define WX_GPIO_INTEN 0x14830
124 #define WX_GPIO_INTEN_0 BIT(0)
125 #define WX_GPIO_INTEN_1 BIT(1)
126 #define WX_GPIO_INTMASK 0x14834
127 #define WX_GPIO_INTTYPE_LEVEL 0x14838
128 #define WX_GPIO_POLARITY 0x1483C
129 #define WX_GPIO_INTSTATUS 0x14844
130 #define WX_GPIO_EOI 0x1484C
131 #define WX_GPIO_EXT 0x14850
132
133 /*********************** Transmit DMA registers **************************/
134 /* transmit global control */
135 #define WX_TDM_CTL 0x18000
136 #define WX_TDM_VF_TE(_i) (0x18004 + ((_i) * 4))
137 #define WX_TDM_MAC_AS(_i) (0x18060 + ((_i) * 4))
138 #define WX_TDM_VLAN_AS(_i) (0x18070 + ((_i) * 4))
139 #define WX_TDM_VFTE_CLR(_i) (0x180A0 + ((_i) * 4))
140
141 /* TDM CTL BIT */
142 #define WX_TDM_CTL_TE BIT(0) /* Transmit Enable */
143 #define WX_TDM_PB_THRE(_i) (0x18020 + ((_i) * 4))
144 #define WX_TDM_RP_IDX 0x1820C
145 #define WX_TDM_PKT_CNT 0x18308
146 #define WX_TDM_BYTE_CNT_LSB 0x1830C
147 #define WX_TDM_OS2BMC_CNT 0x18314
148 #define WX_TDM_RP_RATE 0x18404
149
150 /***************************** RDB registers *********************************/
151 /* receive packet buffer */
152 #define WX_RDB_PB_CTL 0x19000
153 #define WX_RDB_PB_CTL_RXEN BIT(31) /* Enable Receiver */
154 #define WX_RDB_PB_CTL_DISABLED BIT(0)
155 #define WX_RDB_PB_SZ(_i) (0x19020 + ((_i) * 4))
156 #define WX_RDB_PB_SZ_SHIFT 10
157 /* statistic */
158 #define WX_RDB_PFCMACDAL 0x19210
159 #define WX_RDB_PFCMACDAH 0x19214
160 #define WX_RDB_LXOFFTXC 0x19218
161 #define WX_RDB_LXONTXC 0x1921C
162 /* Flow Control Registers */
163 #define WX_RDB_RFCV 0x19200
164 #define WX_RDB_RFCL 0x19220
165 #define WX_RDB_RFCL_XONE BIT(31)
166 #define WX_RDB_RFCH 0x19260
167 #define WX_RDB_RFCH_XOFFE BIT(31)
168 #define WX_RDB_RFCRT 0x192A0
169 #define WX_RDB_RFCC 0x192A4
170 #define WX_RDB_RFCC_RFCE_802_3X BIT(3)
171 /* ring assignment */
172 #define WX_RDB_PL_CFG(_i) (0x19300 + ((_i) * 4))
173 #define WX_RDB_PL_CFG_L4HDR BIT(1)
174 #define WX_RDB_PL_CFG_L3HDR BIT(2)
175 #define WX_RDB_PL_CFG_L2HDR BIT(3)
176 #define WX_RDB_PL_CFG_TUN_TUNHDR BIT(4)
177 #define WX_RDB_PL_CFG_TUN_OUTL2HDR BIT(5)
178 #define WX_RDB_PL_CFG_RSS_EN BIT(24)
179 #define WX_RDB_PL_CFG_RSS_MASK GENMASK(23, 16)
180 #define WX_RDB_RSSTBL(_i) (0x19400 + ((_i) * 4))
181 #define WX_RDB_RSSRK(_i) (0x19480 + ((_i) * 4))
182 #define WX_RDB_RA_CTL 0x194F4
183 #define WX_RDB_RA_CTL_MULTI_RSS BIT(0)
184 #define WX_RDB_RA_CTL_RSS_EN BIT(2) /* RSS Enable */
185 #define WX_RDB_RA_CTL_RSS_IPV4_TCP BIT(16)
186 #define WX_RDB_RA_CTL_RSS_IPV4 BIT(17)
187 #define WX_RDB_RA_CTL_RSS_IPV6 BIT(20)
188 #define WX_RDB_RA_CTL_RSS_IPV6_TCP BIT(21)
189 #define WX_RDB_RA_CTL_RSS_IPV4_UDP BIT(22)
190 #define WX_RDB_RA_CTL_RSS_IPV6_UDP BIT(23)
191 #define WX_RDB_RA_CTL_RSS_MASK GENMASK(23, 16)
192 #define WX_RDB_FDIR_MATCH 0x19558
193 #define WX_RDB_FDIR_MISS 0x1955C
194 /* VM RSS */
195 #define WX_RDB_VMRSSRK(_i, _p) (0x1A000 + ((_i) * 4) + ((_p) * 0x40))
196 #define WX_RDB_VMRSSTBL(_i, _p) (0x1B000 + ((_i) * 4) + ((_p) * 0x40))
197
198 /******************************* PSR Registers *******************************/
199 /* psr control */
200 #define WX_PSR_CTL 0x15000
201 #define WX_PSR_VM_CTL 0x151B0
202 /* Header split receive */
203 #define WX_PSR_CTL_SW_EN BIT(18)
204 #define WX_PSR_CTL_RSC_ACK BIT(17)
205 #define WX_PSR_CTL_RSC_DIS BIT(16)
206 #define WX_PSR_CTL_PCSD BIT(13)
207 #define WX_PSR_CTL_IPPCSE BIT(12)
208 #define WX_PSR_CTL_BAM BIT(10)
209 #define WX_PSR_CTL_UPE BIT(9)
210 #define WX_PSR_CTL_MPE BIT(8)
211 #define WX_PSR_CTL_MFE BIT(7)
212 #define WX_PSR_CTL_MO_SHIFT 5
213 #define WX_PSR_CTL_MO (0x3 << WX_PSR_CTL_MO_SHIFT)
214 #define WX_PSR_CTL_TPE BIT(4)
215 #define WX_PSR_MAX_SZ 0x15020
216 #define WX_PSR_VLAN_CTL 0x15088
217 #define WX_PSR_VLAN_CTL_CFIEN BIT(29) /* bit 29 */
218 #define WX_PSR_VLAN_CTL_VFE BIT(30) /* bit 30 */
219 /* EType Queue Filter */
220 #define WX_PSR_ETYPE_SWC(_i) (0x15128 + ((_i) * 4))
221 #define WX_PSR_ETYPE_SWC_FILTER_1588 3
222 #define WX_PSR_ETYPE_SWC_FILTER_EN BIT(31)
223 #define WX_PSR_ETYPE_SWC_1588 BIT(30)
224 /* 1588 */
225 #define WX_PSR_1588_MSG 0x15120
226 #define WX_PSR_1588_MSG_V1_SYNC FIELD_PREP(GENMASK(7, 0), 0)
227 #define WX_PSR_1588_MSG_V1_DELAY_REQ FIELD_PREP(GENMASK(7, 0), 1)
228 #define WX_PSR_1588_STMPL 0x151E8
229 #define WX_PSR_1588_STMPH 0x151A4
230 #define WX_PSR_1588_CTL 0x15188
231 #define WX_PSR_1588_CTL_ENABLED BIT(4)
232 #define WX_PSR_1588_CTL_TYPE_MASK GENMASK(3, 1)
233 #define WX_PSR_1588_CTL_TYPE_L4_V1 FIELD_PREP(GENMASK(3, 1), 1)
234 #define WX_PSR_1588_CTL_TYPE_EVENT_V2 FIELD_PREP(GENMASK(3, 1), 5)
235 #define WX_PSR_1588_CTL_VALID BIT(0)
236 /* mcasst/ucast overflow tbl */
237 #define WX_PSR_MC_TBL(_i) (0x15200 + ((_i) * 4))
238 #define WX_PSR_MC_TBL_REG(_i) FIELD_GET(GENMASK(11, 5), (_i))
239 #define WX_PSR_MC_TBL_BIT(_i) FIELD_GET(GENMASK(4, 0), (_i))
240 #define WX_PSR_UC_TBL(_i) (0x15400 + ((_i) * 4))
241 #define WX_PSR_VM_CTL_REPLEN BIT(30) /* replication enabled */
242 #define WX_PSR_VM_CTL_POOL_MASK GENMASK(12, 7)
243
244 /* VM L2 contorl */
245 #define WX_PSR_VM_L2CTL(_i) (0x15600 + ((_i) * 4))
246 #define WX_PSR_VM_L2CTL_UPE BIT(4) /* unicast promiscuous */
247 #define WX_PSR_VM_L2CTL_VACC BIT(6) /* accept nomatched vlan */
248 #define WX_PSR_VM_L2CTL_VPE BIT(7) /* vlan promiscuous mode */
249 #define WX_PSR_VM_L2CTL_AUPE BIT(8) /* accept untagged packets */
250 #define WX_PSR_VM_L2CTL_ROMPE BIT(9) /* accept packets in MTA tbl */
251 #define WX_PSR_VM_L2CTL_ROPE BIT(10) /* accept packets in UC tbl */
252 #define WX_PSR_VM_L2CTL_BAM BIT(11) /* accept broadcast packets */
253 #define WX_PSR_VM_L2CTL_MPE BIT(12) /* multicast promiscuous */
254
255 /* Management */
256 #define WX_PSR_MNG_FLEX_SEL 0x1582C
257 #define WX_PSR_MNG_FLEX_DW_L(_i) (0x15A00 + ((_i) * 16))
258 #define WX_PSR_MNG_FLEX_DW_H(_i) (0x15A04 + ((_i) * 16))
259 #define WX_PSR_MNG_FLEX_MSK(_i) (0x15A08 + ((_i) * 16))
260 #define WX_PSR_LAN_FLEX_SEL 0x15B8C
261 #define WX_PSR_LAN_FLEX_DW_L(_i) (0x15C00 + ((_i) * 16))
262 #define WX_PSR_LAN_FLEX_DW_H(_i) (0x15C04 + ((_i) * 16))
263 #define WX_PSR_LAN_FLEX_MSK(_i) (0x15C08 + ((_i) * 16))
264
265 #define WX_PSR_WKUP_CTL 0x15B80
266 /* Wake Up Filter Control Bit */
267 #define WX_PSR_WKUP_CTL_MAG BIT(1) /* Magic Packet Wakeup Enable */
268
269 /* vlan tbl */
270 #define WX_PSR_VLAN_TBL(_i) (0x16000 + ((_i) * 4))
271
272 /* mac switcher */
273 #define WX_PSR_MAC_SWC_AD_L 0x16200
274 #define WX_PSR_MAC_SWC_AD_H 0x16204
275 #define WX_PSR_MAC_SWC_AD_H_AD(v) FIELD_PREP(U16_MAX, v)
276 #define WX_PSR_MAC_SWC_AD_H_ADTYPE(v) FIELD_PREP(BIT(30), v)
277 #define WX_PSR_MAC_SWC_AD_H_AV BIT(31)
278 #define WX_PSR_MAC_SWC_VM_L 0x16208
279 #define WX_PSR_MAC_SWC_VM_H 0x1620C
280 #define WX_PSR_MAC_SWC_IDX 0x16210
281 #define WX_CLEAR_VMDQ_ALL 0xFFFFFFFFU
282
283 /* vlan switch */
284 #define WX_PSR_VLAN_SWC 0x16220
285 #define WX_PSR_VLAN_SWC_VM_L 0x16224
286 #define WX_PSR_VLAN_SWC_VM_H 0x16228
287 #define WX_PSR_VLAN_SWC_VM(_i) (0x16224 + ((_i) * 4))
288 #define WX_PSR_VLAN_SWC_IDX 0x16230 /* 64 vlan entries */
289 /* VLAN pool filtering masks */
290 #define WX_PSR_VLAN_SWC_VIEN BIT(31) /* filter is valid */
291 #define WX_PSR_VLAN_SWC_ENTRIES 64
292 #define WX_PSR_VLAN_SWC_VLANID_MASK GENMASK(11, 0)
293
294 /********************************* RSEC **************************************/
295 /* general rsec */
296 #define WX_RSC_CTL 0x17000
297 #define WX_RSC_CTL_SAVE_MAC_ERR BIT(6)
298 #define WX_RSC_CTL_CRC_STRIP BIT(2)
299 #define WX_RSC_CTL_RX_DIS BIT(1)
300 #define WX_RSC_ST 0x17004
301 #define WX_RSC_ST_RSEC_RDY BIT(0)
302
303 /*********************** Transmit DMA registers **************************/
304 /* transmit global control */
305 #define WX_TDM_ETYPE_AS(_i) (0x18058 + ((_i) * 4))
306 #define WX_TDM_VLAN_INS(_i) (0x18100 + ((_i) * 4))
307 /* Per VF Port VLAN insertion rules */
308 #define WX_TDM_VLAN_INS_VLANA_DEFAULT BIT(30) /* Always use default VLAN*/
309
310 /****************************** TDB ******************************************/
311 #define WX_TDB_PB_SZ(_i) (0x1CC00 + ((_i) * 4))
312 #define WX_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */
313
314 /****************************** TSEC *****************************************/
315 /* Security Control Registers */
316 #define WX_TSC_CTL 0x1D000
317 #define WX_TSC_CTL_TX_DIS BIT(1)
318 #define WX_TSC_CTL_TSEC_DIS BIT(0)
319 #define WX_TSC_ST 0x1D004
320 #define WX_TSC_ST_SECTX_RDY BIT(0)
321 #define WX_TSC_BUF_AE 0x1D00C
322 #define WX_TSC_BUF_AE_THR GENMASK(9, 0)
323 /* 1588 */
324 #define WX_TSC_1588_CTL 0x11F00
325 #define WX_TSC_1588_CTL_ENABLED BIT(4)
326 #define WX_TSC_1588_CTL_VALID BIT(0)
327 #define WX_TSC_1588_STMPL 0x11F04
328 #define WX_TSC_1588_STMPH 0x11F08
329 #define WX_TSC_1588_SYSTIML 0x11F0C
330 #define WX_TSC_1588_SYSTIMH 0x11F10
331 #define WX_TSC_1588_INC 0x11F14
332 #define WX_TSC_1588_INT_ST 0x11F20
333 #define WX_TSC_1588_INT_ST_TT1 BIT(5)
334 #define WX_TSC_1588_INT_EN 0x11F24
335 #define WX_TSC_1588_INT_EN_TT1 BIT(5)
336 #define WX_TSC_1588_AUX_CTL 0x11F28
337 #define WX_TSC_1588_AUX_CTL_EN_TS0 BIT(8)
338 #define WX_TSC_1588_AUX_CTL_EN_TT1 BIT(2)
339 #define WX_TSC_1588_AUX_CTL_PLSG BIT(1)
340 #define WX_TSC_1588_AUX_CTL_EN_TT0 BIT(0)
341 #define WX_TSC_1588_TRGT_L(i) (0x11F2C + ((i) * 8)) /* [0,1] */
342 #define WX_TSC_1588_TRGT_H(i) (0x11F30 + ((i) * 8)) /* [0,1] */
343 #define WX_TSC_1588_SDP(i) (0x11F5C + ((i) * 4)) /* [0,3] */
344 #define WX_TSC_1588_SDP_OUT_LEVEL_H FIELD_PREP(BIT(4), 0)
345 #define WX_TSC_1588_SDP_OUT_LEVEL_L FIELD_PREP(BIT(4), 1)
346 #define WX_TSC_1588_SDP_FUN_SEL_MASK GENMASK(2, 0)
347 #define WX_TSC_1588_SDP_FUN_SEL_TT0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 1)
348 #define WX_TSC_1588_SDP_FUN_SEL_TS0 FIELD_PREP(WX_TSC_1588_SDP_FUN_SEL_MASK, 5)
349
350 /************************************** MNG ********************************/
351 #define WX_MNG_SWFW_SYNC 0x1E008
352 #define WX_MNG_SWFW_SYNC_SW_MB BIT(2)
353 #define WX_MNG_SWFW_SYNC_SW_FLASH BIT(3)
354 #define WX_MNG_MBOX 0x1E100
355 #define WX_MNG_MBOX_CTL 0x1E044
356 #define WX_MNG_MBOX_CTL_SWRDY BIT(0)
357 #define WX_MNG_MBOX_CTL_FWRDY BIT(2)
358 #define WX_MNG_BMC2OS_CNT 0x1E090
359 #define WX_MNG_OS2BMC_CNT 0x1E094
360 #define WX_SW2FW_MBOX_CMD 0x1E0A0
361 #define WX_SW2FW_MBOX_CMD_VLD BIT(31)
362 #define WX_SW2FW_MBOX 0x1E200
363 #define WX_FW2SW_MBOX 0x1E300
364
365 /************************************* ETH MAC *****************************/
366 #define WX_MAC_TX_CFG 0x11000
367 #define WX_MAC_TX_CFG_TE BIT(0)
368 #define WX_MAC_TX_CFG_SPEED_MASK GENMASK(30, 29)
369 #define WX_MAC_TX_CFG_SPEED_10G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 0)
370 #define WX_MAC_TX_CFG_SPEED_1G FIELD_PREP(WX_MAC_TX_CFG_SPEED_MASK, 3)
371 #define WX_MAC_RX_CFG 0x11004
372 #define WX_MAC_RX_CFG_RE BIT(0)
373 #define WX_MAC_RX_CFG_JE BIT(8)
374 #define WX_MAC_PKT_FLT 0x11008
375 #define WX_MAC_PKT_FLT_PR BIT(0) /* promiscuous mode */
376 #define WX_MAC_WDG_TIMEOUT 0x1100C
377 #define WX_MAC_RX_FLOW_CTRL 0x11090
378 #define WX_MAC_RX_FLOW_CTRL_RFE BIT(0) /* receive fc enable */
379
380 #define WX_MAC_WDG_TIMEOUT_WTO_MASK GENMASK(3, 0)
381 #define WX_MAC_WDG_TIMEOUT_WTO_DELTA 2
382 /* MDIO Registers */
383 #define WX_MSCA 0x11200
384 #define WX_MSCA_RA(v) FIELD_PREP(U16_MAX, v)
385 #define WX_MSCA_PA(v) FIELD_PREP(GENMASK(20, 16), v)
386 #define WX_MSCA_DA(v) FIELD_PREP(GENMASK(25, 21), v)
387 #define WX_MSCC 0x11204
388 #define WX_MSCC_CMD(v) FIELD_PREP(GENMASK(17, 16), v)
389
390 enum WX_MSCA_CMD_value {
391 WX_MSCA_CMD_RSV = 0,
392 WX_MSCA_CMD_WRITE,
393 WX_MSCA_CMD_POST_READ,
394 WX_MSCA_CMD_READ,
395 };
396
397 #define WX_MSCC_SADDR BIT(18)
398 #define WX_MSCC_BUSY BIT(22)
399 #define WX_MDIO_CLK(v) FIELD_PREP(GENMASK(21, 19), v)
400 #define WX_MDIO_CLAUSE_SELECT 0x11220
401 #define WX_MMC_CONTROL 0x11800
402 #define WX_MMC_CONTROL_RSTONRD BIT(2) /* reset on read */
403
404 /********************************* BAR registers ***************************/
405 /* Interrupt Registers */
406 #define WX_BME_CTL 0x12020
407 #define WX_PX_MISC_IC 0x100
408 #define WX_PX_MISC_ICS 0x104
409 #define WX_PX_MISC_IEN 0x108
410 #define WX_PX_INTA 0x110
411 #define WX_PX_GPIE 0x118
412 #define WX_PX_GPIE_MODEL BIT(0)
413 #define WX_PX_IC(_i) (0x120 + (_i) * 4)
414 #define WX_PX_IMS(_i) (0x140 + (_i) * 4)
415 #define WX_PX_IMC(_i) (0x150 + (_i) * 4)
416 #define WX_PX_ISB_ADDR_L 0x160
417 #define WX_PX_ISB_ADDR_H 0x164
418 #define WX_PX_TRANSACTION_PENDING 0x168
419 #define WX_PX_ITRSEL 0x180
420 #define WX_PX_ITR(_i) (0x200 + (_i) * 4)
421 #define WX_PX_ITR_CNT_WDIS BIT(31)
422 #define WX_PX_MISC_IVAR 0x4FC
423 #define WX_PX_IVAR(_i) (0x500 + (_i) * 4)
424
425 #define WX_PX_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
426 #define WX_7K_ITR 595
427 #define WX_12K_ITR 336
428 #define WX_20K_ITR 200
429 #define WX_MIN_RSC_ITR 24
430 #define WX_SP_MAX_EITR 0x00000FF8U
431 #define WX_AML_MAX_EITR 0x00000FFFU
432 #define WX_EM_MAX_EITR 0x00007FFCU
433
434 /* transmit DMA Registers */
435 #define WX_PX_TR_BAL(_i) (0x03000 + ((_i) * 0x40))
436 #define WX_PX_TR_BAH(_i) (0x03004 + ((_i) * 0x40))
437 #define WX_PX_TR_WP(_i) (0x03008 + ((_i) * 0x40))
438 #define WX_PX_TR_RP(_i) (0x0300C + ((_i) * 0x40))
439 #define WX_PX_TR_CFG(_i) (0x03010 + ((_i) * 0x40))
440 #define WX_PX_TR_HEAD_ADDRL(_i) (0x03028 + ((_i) * 0x40))
441 #define WX_PX_TR_HEAD_ADDRH(_i) (0x0302C + ((_i) * 0x40))
442 /* Transmit Config masks */
443 #define WX_PX_TR_CFG_ENABLE BIT(0) /* Ena specific Tx Queue */
444 #define WX_PX_TR_CFG_TR_SIZE_SHIFT 1 /* tx desc number per ring */
445 #define WX_PX_TR_CFG_SWFLSH BIT(26) /* Tx Desc. wr-bk flushing */
446 #define WX_PX_TR_CFG_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */
447 #define WX_PX_TR_CFG_THRE_SHIFT 8
448 #define WX_PX_TR_CFG_HEAD_WB BIT(27)
449
450 /* Receive DMA Registers */
451 #define WX_PX_RR_BAL(_i) (0x01000 + ((_i) * 0x40))
452 #define WX_PX_RR_BAH(_i) (0x01004 + ((_i) * 0x40))
453 #define WX_PX_RR_WP(_i) (0x01008 + ((_i) * 0x40))
454 #define WX_PX_RR_RP(_i) (0x0100C + ((_i) * 0x40))
455 #define WX_PX_RR_CFG(_i) (0x01010 + ((_i) * 0x40))
456 #define WX_PX_MPRC(_i) (0x01020 + ((_i) * 0x40))
457 /* PX_RR_CFG bit definitions */
458 #define WX_PX_RR_CFG_VLAN BIT(31)
459 #define WX_PX_RR_CFG_DROP_EN BIT(30)
460 #define WX_PX_RR_CFG_RSC BIT(29)
461 #define WX_PX_RR_CFG_SPLIT_MODE BIT(26)
462 #define WX_PX_RR_CFG_MAX_RSCBUF_16 FIELD_PREP(GENMASK(24, 23), 3)
463 #define WX_PX_RR_CFG_DESC_MERGE BIT(19)
464 #define WX_PX_RR_CFG_RR_THER_SHIFT 16
465 #define WX_PX_RR_CFG_RR_HDR_SZ GENMASK(15, 12)
466 #define WX_PX_RR_CFG_RR_BUF_SZ GENMASK(11, 8)
467 #define WX_PX_RR_CFG_BHDRSIZE_SHIFT 6 /* 64byte resolution (>> 6)
468 * + at bit 8 offset (<< 12)
469 * = (<< 6)
470 */
471 #define WX_PX_RR_CFG_BSIZEPKT_SHIFT 2 /* so many KBs */
472 #define WX_PX_RR_CFG_RR_SIZE_SHIFT 1
473 #define WX_PX_RR_CFG_RR_EN BIT(0)
474
475 /* Number of 80 microseconds we wait for PCI Express master disable */
476 #define WX_PCI_MASTER_DISABLE_TIMEOUT 80000
477
478 #define WX_RSS_64Q_MASK 0x3F
479 #define WX_RSS_8Q_MASK 0x7
480 #define WX_RSS_4Q_MASK 0x3
481 #define WX_RSS_2Q_MASK 0x1
482 #define WX_RSS_DISABLED_MASK 0x0
483
484 #define WX_VMDQ_4Q_MASK 0x7C
485 #define WX_VMDQ_2Q_MASK 0x7E
486
487 /****************** Manageablility Host Interface defines ********************/
488 #define WX_HI_MAX_BLOCK_BYTE_LENGTH 256 /* Num of bytes in range */
489 #define WX_HI_COMMAND_TIMEOUT 1000 /* Process HI command limit */
490 #define WX_HIC_HDR_INDEX_MAX 255
491
492 #define FW_READ_SHADOW_RAM_CMD 0x31
493 #define FW_READ_SHADOW_RAM_LEN 0x6
494 #define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */
495 #define FW_NVM_DATA_OFFSET 3
496 #define FW_MAX_READ_BUFFER_SIZE 244
497 #define FW_RESET_CMD 0xDF
498 #define FW_RESET_LEN 0x2
499 #define FW_CEM_HDR_LEN 0x4
500 #define FW_CEM_CMD_RESERVED 0X0
501 #define FW_CEM_MAX_RETRIES 3
502 #define FW_CEM_RESP_STATUS_SUCCESS 0x1
503 #define FW_PPS_SET_CMD 0xF6
504 #define FW_PPS_SET_LEN 0x14
505
506 #define WX_SW_REGION_PTR 0x1C
507
508 #define WX_MAC_STATE_DEFAULT 0x1
509 #define WX_MAC_STATE_MODIFIED 0x2
510 #define WX_MAC_STATE_IN_USE 0x4
511
512 /* BitTimes (BT) conversion */
513 #define WX_BT2KB(BT) (((BT) + (8 * 1024 - 1)) / (8 * 1024))
514 #define WX_B2BT(BT) ((BT) * 8)
515
516 /* Calculate Delay to respond to PFC */
517 #define WX_PFC_D 672
518 /* Calculate Cable Delay */
519 #define WX_CABLE_DC 5556 /* Delay Copper */
520 /* Calculate Delay incurred from higher layer */
521 #define WX_HD 6144
522
523 /* Calculate Interface Delay */
524 #define WX_PHY_D 12800
525 #define WX_MAC_D 4096
526 #define WX_XAUI_D (2 * 1024)
527 #define WX_ID (WX_MAC_D + WX_XAUI_D + WX_PHY_D)
528 /* Calculate PCI Bus delay for low thresholds */
529 #define WX_PCI_DELAY 10000
530
531 /* Calculate delay value in bit times */
532 #define WX_DV(_max_frame_link, _max_frame_tc) \
533 ((36 * (WX_B2BT(_max_frame_link) + WX_PFC_D + \
534 (2 * WX_CABLE_DC) + (2 * WX_ID) + WX_HD) / 25 + 1) + \
535 2 * WX_B2BT(_max_frame_tc))
536
537 /* Calculate low threshold delay values */
538 #define WX_LOW_DV(_max_frame_tc) \
539 (2 * (2 * WX_B2BT(_max_frame_tc) + (36 * WX_PCI_DELAY / 25) + 1))
540
541 /* flow control */
542 #define WX_DEFAULT_FCPAUSE 0xFFFF
543
544 #define WX_MAX_RXD 8192
545 #define WX_MAX_TXD 8192
546 #define WX_MIN_RXD 128
547 #define WX_MIN_TXD 128
548
549 /* Number of Transmit and Receive Descriptors must be a multiple of 128 */
550 #define WX_REQ_RX_DESCRIPTOR_MULTIPLE 128
551 #define WX_REQ_TX_DESCRIPTOR_MULTIPLE 128
552
553 #define WX_MAX_JUMBO_FRAME_SIZE 9432 /* max payload 9414 */
554 #define VMDQ_P(p) ((p) + wx->ring_feature[RING_F_VMDQ].offset)
555
556 /* Supported Rx Buffer Sizes */
557 #define WX_RXBUFFER_256 256 /* Used for skb receive header */
558 #define WX_RXBUFFER_2K 2048
559 #define WX_RXBUFFER_3K 3072
560 #define WX_MAX_RXBUFFER 16384 /* largest size for single descriptor */
561
562 #define WX_RX_BUFFER_WRITE 16 /* Must be power of 2 */
563
564 #define WX_MAX_DATA_PER_TXD BIT(14)
565 /* Tx Descriptors needed, worst case */
566 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), WX_MAX_DATA_PER_TXD)
567 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
568
569 /******************* Receive Descriptor bit definitions **********************/
570 #define WX_RXD_STAT_DD BIT(0) /* Done */
571 #define WX_RXD_STAT_EOP BIT(1) /* End of Packet */
572 #define WX_RXD_STAT_VP BIT(5) /* IEEE VLAN Pkt */
573 #define WX_RXD_STAT_L4CS BIT(7) /* L4 xsum calculated */
574 #define WX_RXD_STAT_IPCS BIT(8) /* IP xsum calculated */
575 #define WX_RXD_STAT_OUTERIPCS BIT(10) /* Cloud IP xsum calculated*/
576 #define WX_RXD_STAT_IPV6EX BIT(12) /* IPv6 Dest Header */
577 #define WX_RXD_STAT_TS BIT(14) /* IEEE1588 Time Stamp */
578
579 #define WX_RXD_ERR_OUTERIPER BIT(26) /* CRC IP Header error */
580 #define WX_RXD_ERR_RXE BIT(29) /* Any MAC Error */
581 #define WX_RXD_ERR_TCPE BIT(30) /* TCP/UDP Checksum Error */
582 #define WX_RXD_ERR_IPE BIT(31) /* IP Checksum Error */
583
584 /* RSS Hash results */
585 #define WX_RXD_RSSTYPE_MASK GENMASK(3, 0)
586 #define WX_RXD_RSSTYPE_IPV4_TCP 0x00000001U
587 #define WX_RXD_RSSTYPE_IPV6_TCP 0x00000003U
588 #define WX_RXD_RSSTYPE_IPV4_SCTP 0x00000004U
589 #define WX_RXD_RSSTYPE_IPV6_SCTP 0x00000006U
590 #define WX_RXD_RSSTYPE_IPV4_UDP 0x00000007U
591 #define WX_RXD_RSSTYPE_IPV6_UDP 0x00000008U
592
593 #define WX_RSS_L4_TYPES_MASK \
594 ((1ul << WX_RXD_RSSTYPE_IPV4_TCP) | \
595 (1ul << WX_RXD_RSSTYPE_IPV4_UDP) | \
596 (1ul << WX_RXD_RSSTYPE_IPV4_SCTP) | \
597 (1ul << WX_RXD_RSSTYPE_IPV6_TCP) | \
598 (1ul << WX_RXD_RSSTYPE_IPV6_UDP) | \
599 (1ul << WX_RXD_RSSTYPE_IPV6_SCTP))
600 /* TUN */
601 #define WX_PTYPE_TUN_IPV4 0x80
602 #define WX_PTYPE_TUN_IPV6 0xC0
603
604 /* PKT for TUN */
605 #define WX_PTYPE_PKT_IPIP 0x00 /* IP+IP */
606 #define WX_PTYPE_PKT_IG 0x10 /* IP+GRE */
607 #define WX_PTYPE_PKT_IGM 0x20 /* IP+GRE+MAC */
608 #define WX_PTYPE_PKT_IGMV 0x30 /* IP+GRE+MAC+VLAN */
609 /* PKT for !TUN */
610 #define WX_PTYPE_PKT_MAC 0x10
611 #define WX_PTYPE_PKT_IP 0x20
612
613 /* TYP for PKT=mac */
614 #define WX_PTYPE_TYP_MAC 0x01
615 /* TYP for PKT=ip */
616 #define WX_PTYPE_PKT_IPV6 0x08
617 #define WX_PTYPE_TYP_IPFRAG 0x01
618 #define WX_PTYPE_TYP_IP 0x02
619 #define WX_PTYPE_TYP_UDP 0x03
620 #define WX_PTYPE_TYP_TCP 0x04
621 #define WX_PTYPE_TYP_SCTP 0x05
622
623 /* Packet type non-ip values */
624 enum wx_l2_ptypes {
625 WX_PTYPE_L2_ABORTED = (WX_PTYPE_PKT_MAC),
626 WX_PTYPE_L2_MAC = (WX_PTYPE_PKT_MAC | WX_PTYPE_TYP_MAC),
627
628 WX_PTYPE_L2_IPV4_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IPFRAG),
629 WX_PTYPE_L2_IPV4 = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_IP),
630 WX_PTYPE_L2_IPV4_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_UDP),
631 WX_PTYPE_L2_IPV4_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_TCP),
632 WX_PTYPE_L2_IPV4_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_TYP_SCTP),
633 WX_PTYPE_L2_IPV6_FRAG = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
634 WX_PTYPE_TYP_IPFRAG),
635 WX_PTYPE_L2_IPV6 = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
636 WX_PTYPE_TYP_IP),
637 WX_PTYPE_L2_IPV6_UDP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
638 WX_PTYPE_TYP_UDP),
639 WX_PTYPE_L2_IPV6_TCP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
640 WX_PTYPE_TYP_TCP),
641 WX_PTYPE_L2_IPV6_SCTP = (WX_PTYPE_PKT_IP | WX_PTYPE_PKT_IPV6 |
642 WX_PTYPE_TYP_SCTP),
643
644 WX_PTYPE_L2_TUN4_MAC = (WX_PTYPE_TUN_IPV4 | WX_PTYPE_PKT_IGM),
645 WX_PTYPE_L2_TUN6_MAC = (WX_PTYPE_TUN_IPV6 | WX_PTYPE_PKT_IGM),
646 };
647
648 #define WX_PTYPE_PKT(_pt) ((_pt) & 0x30)
649 #define WX_PTYPE_TYPL4(_pt) ((_pt) & 0x07)
650
651 #define WX_RXD_PKTTYPE(_rxd) \
652 ((le32_to_cpu((_rxd)->wb.lower.lo_dword.data) >> 9) & 0xFF)
653
654 #define WX_RXD_RSCCNT_MASK GENMASK(20, 17)
655 #define WX_RXD_RSCCNT_SHIFT 17
656 #define WX_RXD_NEXTP_MASK GENMASK(19, 4)
657 #define WX_RXD_NEXTP_SHIFT 4
658
659 /*********************** Transmit Descriptor Config Masks ****************/
660 #define WX_TXD_STAT_DD BIT(0) /* Descriptor Done */
661 #define WX_TXD_DTYP_DATA 0 /* Adv Data Descriptor */
662 #define WX_TXD_PAYLEN_SHIFT 13 /* Desc PAYLEN shift */
663 #define WX_TXD_EOP BIT(24) /* End of Packet */
664 #define WX_TXD_IFCS BIT(25) /* Insert FCS */
665 #define WX_TXD_RS BIT(27) /* Report Status */
666
667 /*********************** Adv Transmit Descriptor Config Masks ****************/
668 #define WX_TXD_MAC_TSTAMP BIT(19) /* IEEE1588 time stamp */
669 #define WX_TXD_DTYP_CTXT BIT(20) /* Adv Context Desc */
670 #define WX_TXD_LINKSEC BIT(26) /* enable linksec */
671 #define WX_TXD_VLE BIT(30) /* VLAN pkt enable */
672 #define WX_TXD_TSE BIT(31) /* TCP Seg enable */
673 #define WX_TXD_CC BIT(7) /* Check Context */
674 #define WX_TXD_IPSEC BIT(8) /* enable ipsec esp */
675 #define WX_TXD_L4CS BIT(9)
676 #define WX_TXD_IIPCS BIT(10)
677 #define WX_TXD_EIPCS BIT(11)
678 #define WX_TXD_PAYLEN_SHIFT 13 /* Adv desc PAYLEN shift */
679 #define WX_TXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
680 #define WX_TXD_TAG_TPID_SEL_SHIFT 11
681
682 #define WX_TXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
683 #define WX_TXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
684
685 #define WX_TXD_OUTER_IPLEN_SHIFT 12 /* Adv ctxt OUTERIPLEN shift */
686 #define WX_TXD_TUNNEL_LEN_SHIFT 21 /* Adv ctxt TUNNELLEN shift */
687 #define WX_TXD_TUNNEL_TYPE_SHIFT 11 /* Adv Tx Desc Tunnel Type shift */
688 #define WX_TXD_TUNNEL_UDP FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 0)
689 #define WX_TXD_TUNNEL_GRE FIELD_PREP(BIT(WX_TXD_TUNNEL_TYPE_SHIFT), 1)
690
691 enum wx_tx_flags {
692 /* cmd_type flags */
693 WX_TX_FLAGS_HW_VLAN = 0x01,
694 WX_TX_FLAGS_TSO = 0x02,
695 WX_TX_FLAGS_TSTAMP = 0x04,
696
697 /* olinfo flags */
698 WX_TX_FLAGS_CC = 0x08,
699 WX_TX_FLAGS_IPV4 = 0x10,
700 WX_TX_FLAGS_CSUM = 0x20,
701 WX_TX_FLAGS_OUTER_IPV4 = 0x100,
702 WX_TX_FLAGS_LINKSEC = 0x200,
703 WX_TX_FLAGS_IPSEC = 0x400,
704
705 /* software defined flags */
706 WX_TX_FLAGS_SW_VLAN = 0x40,
707 };
708
709 /* VLAN info */
710 #define WX_TX_FLAGS_VLAN_MASK GENMASK(31, 16)
711 #define WX_TX_FLAGS_VLAN_SHIFT 16
712
713 /* wx_dec_ptype.mac: outer mac */
714 enum wx_dec_ptype_mac {
715 WX_DEC_PTYPE_MAC_IP = 0,
716 WX_DEC_PTYPE_MAC_L2 = 2,
717 WX_DEC_PTYPE_MAC_FCOE = 3,
718 };
719
720 /* wx_dec_ptype.[e]ip: outer&encaped ip */
721 #define WX_DEC_PTYPE_IP_FRAG 0x4
722 enum wx_dec_ptype_ip {
723 WX_DEC_PTYPE_IP_NONE = 0,
724 WX_DEC_PTYPE_IP_IPV4 = 1,
725 WX_DEC_PTYPE_IP_IPV6 = 2,
726 WX_DEC_PTYPE_IP_FGV4 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV4,
727 WX_DEC_PTYPE_IP_FGV6 = WX_DEC_PTYPE_IP_FRAG | WX_DEC_PTYPE_IP_IPV6,
728 };
729
730 /* wx_dec_ptype.etype: encaped type */
731 enum wx_dec_ptype_etype {
732 WX_DEC_PTYPE_ETYPE_NONE = 0,
733 WX_DEC_PTYPE_ETYPE_IPIP = 1, /* IP+IP */
734 WX_DEC_PTYPE_ETYPE_IG = 2, /* IP+GRE */
735 WX_DEC_PTYPE_ETYPE_IGM = 3, /* IP+GRE+MAC */
736 WX_DEC_PTYPE_ETYPE_IGMV = 4, /* IP+GRE+MAC+VLAN */
737 };
738
739 /* wx_dec_ptype.proto: payload proto */
740 enum wx_dec_ptype_prot {
741 WX_DEC_PTYPE_PROT_NONE = 0,
742 WX_DEC_PTYPE_PROT_UDP = 1,
743 WX_DEC_PTYPE_PROT_TCP = 2,
744 WX_DEC_PTYPE_PROT_SCTP = 3,
745 WX_DEC_PTYPE_PROT_ICMP = 4,
746 WX_DEC_PTYPE_PROT_TS = 5, /* time sync */
747 };
748
749 /* wx_dec_ptype.layer: payload layer */
750 enum wx_dec_ptype_layer {
751 WX_DEC_PTYPE_LAYER_NONE = 0,
752 WX_DEC_PTYPE_LAYER_PAY2 = 1,
753 WX_DEC_PTYPE_LAYER_PAY3 = 2,
754 WX_DEC_PTYPE_LAYER_PAY4 = 3,
755 };
756
757 struct wx_dec_ptype {
758 u32 known:1;
759 u32 mac:2; /* outer mac */
760 u32 ip:3; /* outer ip*/
761 u32 etype:3; /* encaped type */
762 u32 eip:3; /* encaped ip */
763 u32 prot:4; /* payload proto */
764 u32 layer:3; /* payload layer */
765 };
766
767 /* macro to make the table lines short */
768 #define WX_PTT(mac, ip, etype, eip, proto, layer)\
769 {1, \
770 WX_DEC_PTYPE_MAC_##mac, /* mac */\
771 WX_DEC_PTYPE_IP_##ip, /* ip */ \
772 WX_DEC_PTYPE_ETYPE_##etype, /* etype */\
773 WX_DEC_PTYPE_IP_##eip, /* eip */\
774 WX_DEC_PTYPE_PROT_##proto, /* proto */\
775 WX_DEC_PTYPE_LAYER_##layer /* layer */}
776
777 /* Host Interface Command Structures */
778 struct wx_hic_hdr {
779 u8 cmd;
780 u8 buf_len;
781 union {
782 u8 cmd_resv;
783 u8 ret_status;
784 } cmd_or_resp;
785 union {
786 u8 checksum;
787 u8 index;
788 };
789 };
790
791 struct wx_hic_hdr2_req {
792 u8 cmd;
793 u8 buf_lenh;
794 u8 buf_lenl;
795 union {
796 u8 checksum;
797 u8 index;
798 };
799 };
800
801 struct wx_hic_hdr2_rsp {
802 u8 cmd;
803 u8 buf_lenl;
804 u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */
805 union {
806 u8 checksum;
807 u8 index;
808 };
809 };
810
811 union wx_hic_hdr2 {
812 struct wx_hic_hdr2_req req;
813 struct wx_hic_hdr2_rsp rsp;
814 };
815
816 /* These need to be dword aligned */
817 struct wx_hic_read_shadow_ram {
818 union wx_hic_hdr2 hdr;
819 u32 address;
820 u16 length;
821 u16 pad2;
822 u16 data;
823 u16 pad3;
824 };
825
826 struct wx_hic_reset {
827 struct wx_hic_hdr hdr;
828 u16 lan_id;
829 u16 reset_type;
830 };
831
832 struct wx_hic_set_pps {
833 struct wx_hic_hdr hdr;
834 u8 lan_id;
835 u8 enable;
836 u16 pad2;
837 u64 nsec;
838 u64 cycles;
839 };
840
841 /* Bus parameters */
842 struct wx_bus_info {
843 u8 func;
844 u16 device;
845 };
846
847 struct wx_mbx_info {
848 u16 size;
849 u32 mailbox;
850 u32 udelay;
851 u32 timeout;
852 /* lock mbx access */
853 spinlock_t mbx_lock;
854 };
855
856 struct wx_thermal_sensor_data {
857 s16 temp;
858 s16 alarm_thresh;
859 s16 dalarm_thresh;
860 };
861
862 enum wx_mac_type {
863 wx_mac_unknown = 0,
864 wx_mac_sp,
865 wx_mac_em,
866 wx_mac_aml,
867 wx_mac_aml40,
868 };
869
870 enum wx_media_type {
871 wx_media_unknown = 0,
872 wx_media_fiber,
873 wx_media_copper,
874 wx_media_backplane
875 };
876
877 enum em_mac_type {
878 em_mac_type_unknown = 0,
879 em_mac_type_mdi,
880 em_mac_type_rgmii
881 };
882
883 struct wx_mac_info {
884 enum wx_mac_type type;
885 bool set_lben;
886 u8 addr[ETH_ALEN];
887 u8 perm_addr[ETH_ALEN];
888 u32 mta_shadow[128];
889 s32 mc_filter_type;
890 u32 mcft_size;
891 u32 vft_shadow[128];
892 u32 vft_size;
893 u32 num_rar_entries;
894 u32 rx_pb_size;
895 u32 tx_pb_size;
896 u32 max_tx_queues;
897 u32 max_rx_queues;
898
899 u16 max_msix_vectors;
900 struct wx_thermal_sensor_data sensor;
901 };
902
903 enum wx_eeprom_type {
904 wx_eeprom_uninitialized = 0,
905 wx_eeprom_spi,
906 wx_flash,
907 wx_eeprom_none /* No NVM support */
908 };
909
910 struct wx_eeprom_info {
911 enum wx_eeprom_type type;
912 u32 semaphore_delay;
913 u16 word_size;
914 u16 sw_region_offset;
915 };
916
917 struct wx_addr_filter_info {
918 u32 num_mc_addrs;
919 u32 mta_in_use;
920 bool user_set_promisc;
921 };
922
923 struct wx_mac_addr {
924 u8 addr[ETH_ALEN];
925 u16 state; /* bitmask */
926 u64 pools;
927 };
928
929 enum wx_reset_type {
930 WX_LAN_RESET = 0,
931 WX_SW_RESET,
932 WX_GLOBAL_RESET
933 };
934
935 struct wx_cb {
936 dma_addr_t dma;
937 u16 append_cnt; /* number of skb's appended */
938 bool dma_released;
939 };
940
941 #define WX_CB(skb) ((struct wx_cb *)(skb)->cb)
942
943 /* Transmit Descriptor */
944 union wx_tx_desc {
945 struct {
946 __le64 buffer_addr; /* Address of descriptor's data buf */
947 __le32 cmd_type_len;
948 __le32 olinfo_status;
949 } read;
950 struct {
951 __le64 rsvd; /* Reserved */
952 __le32 nxtseq_seed;
953 __le32 status;
954 } wb;
955 };
956
957 /* Receive Descriptor */
958 union wx_rx_desc {
959 struct {
960 __le64 pkt_addr; /* Packet buffer address */
961 __le64 hdr_addr; /* Header buffer address */
962 } read;
963 struct {
964 struct {
965 union {
966 __le32 data;
967 struct {
968 __le16 pkt_info; /* RSS, Pkt type */
969 __le16 hdr_info; /* Splithdr, hdrlen */
970 } hs_rss;
971 } lo_dword;
972 union {
973 __le32 rss; /* RSS Hash */
974 struct {
975 __le16 ip_id; /* IP id */
976 __le16 csum; /* Packet Checksum */
977 } csum_ip;
978 } hi_dword;
979 } lower;
980 struct {
981 __le32 status_error; /* ext status/error */
982 __le16 length; /* Packet length */
983 __le16 vlan; /* VLAN tag */
984 } upper;
985 } wb; /* writeback */
986 };
987
988 struct wx_tx_context_desc {
989 __le32 vlan_macip_lens;
990 __le32 seqnum_seed;
991 __le32 type_tucmd_mlhl;
992 __le32 mss_l4len_idx;
993 };
994
995 /* if _flag is in _input, return _result */
996 #define WX_SET_FLAG(_input, _flag, _result) \
997 (((_flag) <= (_result)) ? \
998 ((u32)((_input) & (_flag)) * ((_result) / (_flag))) : \
999 ((u32)((_input) & (_flag)) / ((_flag) / (_result))))
1000
1001 #define WX_RX_DESC(R, i) \
1002 (&(((union wx_rx_desc *)((R)->desc))[i]))
1003 #define WX_TX_DESC(R, i) \
1004 (&(((union wx_tx_desc *)((R)->desc))[i]))
1005 #define WX_TX_CTXTDESC(R, i) \
1006 (&(((struct wx_tx_context_desc *)((R)->desc))[i]))
1007
1008 /* wrapper around a pointer to a socket buffer,
1009 * so a DMA handle can be stored along with the buffer
1010 */
1011 struct wx_tx_buffer {
1012 union wx_tx_desc *next_to_watch;
1013 unsigned long time_stamp;
1014 struct sk_buff *skb;
1015 unsigned int bytecount;
1016 unsigned short gso_segs;
1017 DEFINE_DMA_UNMAP_ADDR(dma);
1018 DEFINE_DMA_UNMAP_LEN(len);
1019 __be16 protocol;
1020 u32 tx_flags;
1021 u32 next_eop;
1022 };
1023
1024 struct wx_rx_buffer {
1025 struct sk_buff *skb;
1026 dma_addr_t dma;
1027 struct page *page;
1028 unsigned int page_offset;
1029 };
1030
1031 struct wx_queue_stats {
1032 u64 packets;
1033 u64 bytes;
1034 };
1035
1036 struct wx_tx_queue_stats {
1037 u64 restart_queue;
1038 u64 tx_busy;
1039 };
1040
1041 struct wx_rx_queue_stats {
1042 u64 non_eop_descs;
1043 u64 csum_good_cnt;
1044 u64 csum_err;
1045 u64 alloc_rx_buff_failed;
1046 u64 rsc_count;
1047 u64 rsc_flush;
1048 };
1049
1050 /* iterator for handling rings in ring container */
1051 #define wx_for_each_ring(posm, headm) \
1052 for (posm = (headm).ring; posm; posm = posm->next)
1053
1054 struct wx_ring_container {
1055 struct wx_ring *ring; /* pointer to linked list of rings */
1056 unsigned int total_bytes; /* total bytes processed this int */
1057 unsigned int total_packets; /* total packets processed this int */
1058 u8 count; /* total number of rings in vector */
1059 u8 itr; /* current ITR setting for ring */
1060 struct dim dim; /* data for net_dim algorithm */
1061 };
1062 struct wx_ring {
1063 struct wx_ring *next; /* pointer to next ring in q_vector */
1064 struct wx_q_vector *q_vector; /* backpointer to host q_vector */
1065 struct net_device *netdev; /* netdev ring belongs to */
1066 struct device *dev; /* device for DMA mapping */
1067 struct page_pool *page_pool;
1068 void *desc; /* descriptor ring memory */
1069 union {
1070 struct wx_tx_buffer *tx_buffer_info;
1071 struct wx_rx_buffer *rx_buffer_info;
1072 };
1073 u8 __iomem *tail;
1074 dma_addr_t dma; /* phys. address of descriptor ring */
1075 dma_addr_t headwb_dma;
1076 u32 *headwb_mem;
1077 unsigned int size; /* length in bytes */
1078
1079 u16 count; /* amount of descriptors */
1080 unsigned long last_rx_timestamp;
1081
1082 u8 queue_index; /* needed for multiqueue queue management */
1083 u8 reg_idx; /* holds the special value that gets
1084 * the hardware register offset
1085 * associated with this ring, which is
1086 * different for DCB and RSS modes
1087 */
1088 u16 next_to_use;
1089 u16 next_to_clean;
1090 u16 rx_buf_len;
1091 union {
1092 u16 next_to_alloc;
1093 struct {
1094 u8 atr_sample_rate;
1095 u8 atr_count;
1096 };
1097 };
1098
1099 struct wx_queue_stats stats;
1100 struct u64_stats_sync syncp;
1101 union {
1102 struct wx_tx_queue_stats tx_stats;
1103 struct wx_rx_queue_stats rx_stats;
1104 };
1105 } ____cacheline_internodealigned_in_smp;
1106
1107 struct wx_q_vector {
1108 struct wx *wx;
1109 int cpu; /* CPU for DCA */
1110 int numa_node;
1111 u16 v_idx; /* index of q_vector within array, also used for
1112 * finding the bit in EICR and friends that
1113 * represents the vector for this ring
1114 */
1115 u16 itr; /* Interrupt throttle rate written to EITR */
1116 struct wx_ring_container rx, tx;
1117 struct napi_struct napi;
1118 struct rcu_head rcu; /* to avoid race with update stats on free */
1119
1120 u16 total_events; /* number of interrupts processed */
1121
1122 char name[IFNAMSIZ + 17];
1123
1124 /* for dynamic allocation of rings associated with this q_vector */
1125 struct wx_ring ring[] ____cacheline_internodealigned_in_smp;
1126 };
1127
1128 struct wx_ring_feature {
1129 u16 limit; /* upper limit on feature indices */
1130 u16 indices; /* current value of indices */
1131 u16 mask; /* Mask used for feature to ring mapping */
1132 u16 offset; /* offset to start of feature */
1133 };
1134
1135 enum wx_ring_f_enum {
1136 RING_F_NONE = 0,
1137 RING_F_VMDQ,
1138 RING_F_RSS,
1139 RING_F_FDIR,
1140 RING_F_ARRAY_SIZE /* must be last in enum set */
1141 };
1142
1143 enum wx_isb_idx {
1144 WX_ISB_HEADER,
1145 WX_ISB_MISC,
1146 WX_ISB_VEC0,
1147 WX_ISB_VEC1,
1148 WX_ISB_MAX
1149 };
1150
1151 struct wx_fc_info {
1152 u32 high_water; /* Flow Ctrl High-water */
1153 u32 low_water; /* Flow Ctrl Low-water */
1154 };
1155
1156 /* Statistics counters collected by the MAC */
1157 struct wx_hw_stats {
1158 u64 gprc;
1159 u64 gptc;
1160 u64 gorc;
1161 u64 gotc;
1162 u64 tpr;
1163 u64 tpt;
1164 u64 bprc;
1165 u64 bptc;
1166 u64 mprc;
1167 u64 mptc;
1168 u64 roc;
1169 u64 ruc;
1170 u64 lxonoffrxc;
1171 u64 lxontxc;
1172 u64 lxofftxc;
1173 u64 o2bgptc;
1174 u64 b2ospc;
1175 u64 o2bspc;
1176 u64 b2ogprc;
1177 u64 rdmdrop;
1178 u64 crcerrs;
1179 u64 rlec;
1180 u64 qmprc;
1181 u64 fdirmatch;
1182 u64 fdirmiss;
1183 };
1184
1185 enum wx_state {
1186 WX_STATE_RESETTING,
1187 WX_STATE_SWFW_BUSY,
1188 WX_STATE_PTP_RUNNING,
1189 WX_STATE_PTP_TX_IN_PROGRESS,
1190 WX_STATE_SERVICE_SCHED,
1191 WX_STATE_NBITS /* must be last */
1192 };
1193
1194 struct vf_data_storage {
1195 struct pci_dev *vfdev;
1196 unsigned char vf_mac_addr[ETH_ALEN];
1197 bool spoofchk_enabled;
1198 bool link_enable;
1199 bool trusted;
1200 int xcast_mode;
1201 unsigned int vf_api;
1202 bool clear_to_send;
1203 u16 pf_vlan; /* When set, guest VLAN config not allowed. */
1204 u16 pf_qos;
1205 bool pf_set_mac;
1206
1207 u16 vf_mc_hashes[WX_MAX_VF_MC_ENTRIES];
1208 u16 num_vf_mc_hashes;
1209 u16 vlan_count;
1210 int link_state;
1211 };
1212
1213 struct vf_macvlans {
1214 struct list_head mvlist;
1215 int vf;
1216 bool free;
1217 bool is_macvlan;
1218 u8 vf_macvlan[ETH_ALEN];
1219 };
1220
1221 #define WX_RSS_FIELD_IPV4_TCP BIT(0)
1222 #define WX_RSS_FIELD_IPV4 BIT(1)
1223 #define WX_RSS_FIELD_IPV4_SCTP BIT(2)
1224 #define WX_RSS_FIELD_IPV6_SCTP BIT(3)
1225 #define WX_RSS_FIELD_IPV6_TCP BIT(4)
1226 #define WX_RSS_FIELD_IPV6 BIT(5)
1227 #define WX_RSS_FIELD_IPV4_UDP BIT(6)
1228 #define WX_RSS_FIELD_IPV6_UDP BIT(7)
1229
1230 struct wx_rss_flow_map {
1231 u8 flow_type;
1232 u32 data;
1233 u8 flag;
1234 };
1235
1236 enum wx_pf_flags {
1237 WX_FLAG_MULTI_64_FUNC,
1238 WX_FLAG_SWFW_RING,
1239 WX_FLAG_VMDQ_ENABLED,
1240 WX_FLAG_VLAN_PROMISC,
1241 WX_FLAG_SRIOV_ENABLED,
1242 WX_FLAG_IRQ_VECTOR_SHARED,
1243 WX_FLAG_FDIR_CAPABLE,
1244 WX_FLAG_FDIR_HASH,
1245 WX_FLAG_FDIR_PERFECT,
1246 WX_FLAG_RSC_CAPABLE,
1247 WX_FLAG_RSC_ENABLED,
1248 WX_FLAG_RX_HWTSTAMP_ENABLED,
1249 WX_FLAG_RX_HWTSTAMP_IN_REGISTER,
1250 WX_FLAG_PTP_PPS_ENABLED,
1251 WX_FLAG_NEED_LINK_CONFIG,
1252 WX_FLAG_NEED_MODULE_RESET,
1253 WX_FLAG_NEED_UPDATE_LINK,
1254 WX_FLAG_NEED_DO_RESET,
1255 WX_FLAG_RX_MERGE_ENABLED,
1256 WX_FLAG_TXHEAD_WB_ENABLED,
1257 WX_PF_FLAGS_NBITS /* must be last */
1258 };
1259
1260 struct wx {
1261 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
1262 DECLARE_BITMAP(state, WX_STATE_NBITS);
1263 DECLARE_BITMAP(flags, WX_PF_FLAGS_NBITS);
1264
1265 void *priv;
1266 u8 __iomem *hw_addr;
1267 u8 __iomem *b4_addr; /* vf only */
1268 struct pci_dev *pdev;
1269 struct net_device *netdev;
1270 struct wx_bus_info bus;
1271 struct wx_mbx_info mbx;
1272 struct wx_mac_info mac;
1273 enum em_mac_type mac_type;
1274 enum wx_media_type media_type;
1275 struct wx_eeprom_info eeprom;
1276 struct wx_addr_filter_info addr_ctrl;
1277 struct wx_fc_info fc;
1278 struct wx_mac_addr *mac_table;
1279 u16 device_id;
1280 u16 vendor_id;
1281 u16 subsystem_device_id;
1282 u16 subsystem_vendor_id;
1283 u8 revision_id;
1284 u16 oem_ssid;
1285 u16 oem_svid;
1286 u16 msg_enable;
1287 bool adapter_stopped;
1288 u16 tpid[8];
1289 char eeprom_id[32];
1290 char *driver_name;
1291 enum wx_reset_type reset_type;
1292 u8 swfw_index;
1293
1294 /* PHY stuff */
1295 bool notify_down;
1296 unsigned int link;
1297 int speed;
1298 int duplex;
1299 struct phy_device *phydev;
1300 struct phylink *phylink;
1301 struct phylink_config phylink_config;
1302
1303 bool wol_hw_supported;
1304 bool ncsi_enabled;
1305 bool gpio_ctrl;
1306 raw_spinlock_t gpio_lock;
1307
1308 /* Tx fast path data */
1309 int num_tx_queues;
1310 u16 tx_itr_setting;
1311 u16 tx_work_limit;
1312
1313 /* Rx fast path data */
1314 int num_rx_queues;
1315 u16 rx_itr_setting;
1316 u16 rx_work_limit;
1317 bool adaptive_itr;
1318
1319 int num_q_vectors; /* current number of q_vectors for device */
1320 int max_q_vectors; /* upper limit of q_vectors for device */
1321
1322 u32 tx_ring_count;
1323 u32 rx_ring_count;
1324
1325 struct wx_ring *tx_ring[64] ____cacheline_aligned_in_smp;
1326 struct wx_ring *rx_ring[64];
1327 struct wx_q_vector *q_vector[64];
1328 int num_rx_pools;
1329 int num_rx_queues_per_pool;
1330
1331 unsigned int queues_per_pool;
1332 struct msix_entry *msix_q_entries;
1333 struct msix_entry *msix_entry;
1334 struct wx_ring_feature ring_feature[RING_F_ARRAY_SIZE];
1335
1336 /* misc interrupt status block */
1337 dma_addr_t isb_dma;
1338 u32 *isb_mem;
1339 u32 isb_tag[WX_ISB_MAX];
1340 bool misc_irq_domain;
1341 u32 eims_other;
1342 u32 eims_enable_mask;
1343
1344 #define WX_MAX_RETA_ENTRIES 128
1345 #define WX_RSS_INDIR_TBL_MAX 64
1346 u8 rss_indir_tbl[WX_MAX_RETA_ENTRIES];
1347 u8 rss_flags;
1348 bool rss_enabled;
1349 #define WX_RSS_KEY_SIZE 40 /* size of RSS Hash Key in bytes */
1350 u32 *rss_key;
1351 u32 wol;
1352
1353 u16 bd_number;
1354 bool default_up;
1355
1356 struct wx_hw_stats stats;
1357 u64 tx_busy;
1358 u64 non_eop_descs;
1359 u64 restart_queue;
1360 u64 hw_csum_rx_good;
1361 u64 hw_csum_rx_error;
1362 u64 alloc_rx_buff_failed;
1363 u64 rsc_count;
1364 u64 rsc_flush;
1365 unsigned int num_vfs;
1366 struct vf_data_storage *vfinfo;
1367 struct vf_macvlans vf_mvs;
1368 struct vf_macvlans *mv_list;
1369 unsigned long fwd_bitmask;
1370
1371 u32 atr_sample_rate;
1372 void (*atr)(struct wx_ring *ring, struct wx_tx_buffer *first, u8 ptype);
1373 void (*configure_fdir)(struct wx *wx);
1374 int (*setup_tc)(struct net_device *netdev, u8 tc);
1375 void (*do_reset)(struct net_device *netdev);
1376 int (*ptp_setup_sdp)(struct wx *wx);
1377 void (*set_num_queues)(struct wx *wx);
1378
1379 bool pps_enabled;
1380 u64 pps_width;
1381 u64 pps_edge_start;
1382 u64 pps_edge_end;
1383 u64 sec_to_cc;
1384 u32 base_incval;
1385 u32 tx_hwtstamp_pkts;
1386 u32 tx_hwtstamp_timeouts;
1387 u32 tx_hwtstamp_skipped;
1388 u32 tx_hwtstamp_errors;
1389 u32 rx_hwtstamp_cleared;
1390 unsigned long last_overflow_check;
1391 unsigned long last_rx_ptp_check;
1392 unsigned long ptp_tx_start;
1393 seqlock_t hw_tc_lock; /* seqlock for ptp */
1394 struct cyclecounter hw_cc;
1395 struct timecounter hw_tc;
1396 struct ptp_clock *ptp_clock;
1397 struct ptp_clock_info ptp_caps;
1398 struct kernel_hwtstamp_config tstamp_config;
1399 struct sk_buff *ptp_tx_skb;
1400
1401 struct timer_list service_timer;
1402 struct work_struct service_task;
1403 };
1404
1405 #define WX_INTR_ALL (~0ULL)
1406 #define WX_INTR_Q(i) BIT((i))
1407
1408 /* register operations */
1409 #define wr32(a, reg, value) writel((value), ((a)->hw_addr + (reg)))
1410 #define rd32(a, reg) readl((a)->hw_addr + (reg))
1411 #define rd32a(a, reg, offset) ( \
1412 rd32((a), (reg) + ((offset) << 2)))
1413 #define wr32a(a, reg, off, val) \
1414 wr32((a), (reg) + ((off) << 2), (val))
1415
1416 static inline u32
rd32m(struct wx * wx,u32 reg,u32 mask)1417 rd32m(struct wx *wx, u32 reg, u32 mask)
1418 {
1419 u32 val;
1420
1421 val = rd32(wx, reg);
1422 return val & mask;
1423 }
1424
1425 static inline void
wr32m(struct wx * wx,u32 reg,u32 mask,u32 field)1426 wr32m(struct wx *wx, u32 reg, u32 mask, u32 field)
1427 {
1428 u32 val;
1429
1430 val = rd32(wx, reg);
1431 val = ((val & ~mask) | (field & mask));
1432
1433 wr32(wx, reg, val);
1434 }
1435
1436 static inline u64
rd64(struct wx * wx,u32 reg)1437 rd64(struct wx *wx, u32 reg)
1438 {
1439 u64 lsb, msb;
1440
1441 lsb = rd32(wx, reg);
1442 msb = rd32(wx, reg + 4);
1443
1444 return (lsb | msb << 32);
1445 }
1446
1447 static inline u32
rd32ptp(struct wx * wx,u32 reg)1448 rd32ptp(struct wx *wx, u32 reg)
1449 {
1450 if (wx->mac.type == wx_mac_em)
1451 return rd32(wx, reg);
1452
1453 return rd32(wx, reg + 0xB500);
1454 }
1455
1456 static inline void
wr32ptp(struct wx * wx,u32 reg,u32 value)1457 wr32ptp(struct wx *wx, u32 reg, u32 value)
1458 {
1459 if (wx->mac.type == wx_mac_em)
1460 return wr32(wx, reg, value);
1461
1462 return wr32(wx, reg + 0xB500, value);
1463 }
1464
1465 /* On some domestic CPU platforms, sometimes IO is not synchronized with
1466 * flushing memory, here use readl() to flush PCI read and write.
1467 */
1468 #define WX_WRITE_FLUSH(H) rd32(H, WX_MIS_PWR)
1469
1470 #define wx_err(wx, fmt, arg...) \
1471 dev_err(&(wx)->pdev->dev, fmt, ##arg)
1472
1473 #define wx_dbg(wx, fmt, arg...) \
1474 dev_dbg(&(wx)->pdev->dev, fmt, ##arg)
1475
phylink_to_wx(struct phylink_config * config)1476 static inline struct wx *phylink_to_wx(struct phylink_config *config)
1477 {
1478 return container_of(config, struct wx, phylink_config);
1479 }
1480
wx_set_state_reset(struct wx * wx)1481 static inline int wx_set_state_reset(struct wx *wx)
1482 {
1483 u8 timeout = 50;
1484
1485 while (test_and_set_bit(WX_STATE_RESETTING, wx->state)) {
1486 timeout--;
1487 if (!timeout)
1488 return -EBUSY;
1489
1490 usleep_range(1000, 2000);
1491 }
1492
1493 return 0;
1494 }
1495
wx_rx_pg_order(struct wx_ring * ring)1496 static inline unsigned int wx_rx_pg_order(struct wx_ring *ring)
1497 {
1498 #if (PAGE_SIZE < 8192)
1499 if (ring->rx_buf_len == WX_RXBUFFER_3K)
1500 return 1;
1501 #endif
1502 return 0;
1503 }
1504
1505 #define wx_rx_pg_size(_ring) (PAGE_SIZE << wx_rx_pg_order(_ring))
1506
1507 #endif /* _WX_TYPE_H_ */
1508