1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2024 Collabora Ltd.
5 *
6 * Author: Algea Cao <algea.cao@rock-chips.com>
7 * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
8 */
9 #include <linux/completion.h>
10 #include <linux/hdmi.h>
11 #include <linux/export.h>
12 #include <linux/i2c.h>
13 #include <linux/irq.h>
14 #include <linux/module.h>
15 #include <linux/mutex.h>
16 #include <linux/of.h>
17 #include <linux/workqueue.h>
18
19 #include <drm/bridge/dw_hdmi_qp.h>
20 #include <drm/display/drm_hdmi_helper.h>
21 #include <drm/display/drm_hdmi_cec_helper.h>
22 #include <drm/display/drm_hdmi_state_helper.h>
23 #include <drm/drm_atomic.h>
24 #include <drm/drm_atomic_helper.h>
25 #include <drm/drm_bridge.h>
26 #include <drm/drm_connector.h>
27 #include <drm/drm_edid.h>
28 #include <drm/drm_modes.h>
29
30 #include <media/cec.h>
31
32 #include <sound/hdmi-codec.h>
33
34 #include "dw-hdmi-qp.h"
35
36 #define DDC_CI_ADDR 0x37
37 #define DDC_SEGMENT_ADDR 0x30
38
39 #define HDMI14_MAX_TMDSCLK 340000000
40
41 #define SCRAMB_POLL_DELAY_MS 3000
42
43 /*
44 * Unless otherwise noted, entries in this table are 100% optimization.
45 * Values can be obtained from dw_hdmi_qp_compute_n() but that function is
46 * slow so we pre-compute values we expect to see.
47 *
48 * The values for TMDS 25175, 25200, 27000, 54000, 74250 and 148500 kHz are
49 * the recommended N values specified in the Audio chapter of the HDMI
50 * specification.
51 */
52 static const struct dw_hdmi_audio_tmds_n {
53 unsigned long tmds;
54 unsigned int n_32k;
55 unsigned int n_44k1;
56 unsigned int n_48k;
57 } common_tmds_n_table[] = {
58 { .tmds = 25175000, .n_32k = 4576, .n_44k1 = 7007, .n_48k = 6864, },
59 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
60 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
61 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, },
62 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, },
63 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
64 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
65 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
66 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
67 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, },
68 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
69 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
70 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
71 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
72 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, },
73 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
74 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, },
75 { .tmds = 73250000, .n_32k = 11648, .n_44k1 = 14112, .n_48k = 6144, },
76 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
77 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, },
78 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, },
79 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, },
80 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
81 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
82 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
83 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
84 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, },
85 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, },
86 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, },
87 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
88 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, },
89 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
90 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, },
91 { .tmds = 146250000, .n_32k = 11648, .n_44k1 = 6272, .n_48k = 6144, },
92 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, },
93 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, },
94 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, },
95
96 /* For 297 MHz+ HDMI spec have some other rule for setting N */
97 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, },
98 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240,},
99
100 /* End of table */
101 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, },
102 };
103
104 /*
105 * These are the CTS values as recommended in the Audio chapter of the HDMI
106 * specification.
107 */
108 static const struct dw_hdmi_audio_tmds_cts {
109 unsigned long tmds;
110 unsigned int cts_32k;
111 unsigned int cts_44k1;
112 unsigned int cts_48k;
113 } common_tmds_cts_table[] = {
114 { .tmds = 25175000, .cts_32k = 28125, .cts_44k1 = 31250, .cts_48k = 28125, },
115 { .tmds = 25200000, .cts_32k = 25200, .cts_44k1 = 28000, .cts_48k = 25200, },
116 { .tmds = 27000000, .cts_32k = 27000, .cts_44k1 = 30000, .cts_48k = 27000, },
117 { .tmds = 54000000, .cts_32k = 54000, .cts_44k1 = 60000, .cts_48k = 54000, },
118 { .tmds = 74250000, .cts_32k = 74250, .cts_44k1 = 82500, .cts_48k = 74250, },
119 { .tmds = 148500000, .cts_32k = 148500, .cts_44k1 = 165000, .cts_48k = 148500, },
120
121 /* End of table */
122 { .tmds = 0, .cts_32k = 0, .cts_44k1 = 0, .cts_48k = 0, },
123 };
124
125 struct dw_hdmi_qp_i2c {
126 struct i2c_adapter adap;
127
128 struct mutex lock; /* used to serialize data transfers */
129 struct completion cmp;
130 u8 stat;
131
132 u8 slave_reg;
133 bool is_regaddr;
134 bool is_segment;
135 };
136
137 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC
138 struct dw_hdmi_qp_cec {
139 struct drm_connector *connector;
140 int irq;
141 u32 addresses;
142 struct cec_msg rx_msg;
143 u8 tx_status;
144 bool tx_done;
145 bool rx_done;
146 };
147 #endif
148
149 struct dw_hdmi_qp {
150 struct drm_bridge bridge;
151
152 struct device *dev;
153 struct dw_hdmi_qp_i2c *i2c;
154
155 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC
156 struct dw_hdmi_qp_cec *cec;
157 #endif
158
159 struct {
160 const struct dw_hdmi_qp_phy_ops *ops;
161 void *data;
162 } phy;
163
164 unsigned long ref_clk_rate;
165 struct regmap *regm;
166
167 unsigned long tmds_char_rate;
168 };
169
dw_hdmi_qp_write(struct dw_hdmi_qp * hdmi,unsigned int val,int offset)170 static void dw_hdmi_qp_write(struct dw_hdmi_qp *hdmi, unsigned int val,
171 int offset)
172 {
173 regmap_write(hdmi->regm, offset, val);
174 }
175
dw_hdmi_qp_read(struct dw_hdmi_qp * hdmi,int offset)176 static unsigned int dw_hdmi_qp_read(struct dw_hdmi_qp *hdmi, int offset)
177 {
178 unsigned int val = 0;
179
180 regmap_read(hdmi->regm, offset, &val);
181
182 return val;
183 }
184
dw_hdmi_qp_mod(struct dw_hdmi_qp * hdmi,unsigned int data,unsigned int mask,unsigned int reg)185 static void dw_hdmi_qp_mod(struct dw_hdmi_qp *hdmi, unsigned int data,
186 unsigned int mask, unsigned int reg)
187 {
188 regmap_update_bits(hdmi->regm, reg, mask, data);
189 }
190
dw_hdmi_qp_from_bridge(struct drm_bridge * bridge)191 static struct dw_hdmi_qp *dw_hdmi_qp_from_bridge(struct drm_bridge *bridge)
192 {
193 return container_of(bridge, struct dw_hdmi_qp, bridge);
194 }
195
dw_hdmi_qp_set_cts_n(struct dw_hdmi_qp * hdmi,unsigned int cts,unsigned int n)196 static void dw_hdmi_qp_set_cts_n(struct dw_hdmi_qp *hdmi, unsigned int cts,
197 unsigned int n)
198 {
199 /* Set N */
200 dw_hdmi_qp_mod(hdmi, n, AUDPKT_ACR_N_VALUE, AUDPKT_ACR_CONTROL0);
201
202 /* Set CTS */
203 if (cts)
204 dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_EN, AUDPKT_ACR_CTS_OVR_EN_MSK,
205 AUDPKT_ACR_CONTROL1);
206 else
207 dw_hdmi_qp_mod(hdmi, 0, AUDPKT_ACR_CTS_OVR_EN_MSK,
208 AUDPKT_ACR_CONTROL1);
209
210 dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_VAL(cts), AUDPKT_ACR_CTS_OVR_VAL_MSK,
211 AUDPKT_ACR_CONTROL1);
212 }
213
dw_hdmi_qp_match_tmds_n_table(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long freq)214 static int dw_hdmi_qp_match_tmds_n_table(struct dw_hdmi_qp *hdmi,
215 unsigned long pixel_clk,
216 unsigned long freq)
217 {
218 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL;
219 int i;
220
221 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) {
222 if (pixel_clk == common_tmds_n_table[i].tmds) {
223 tmds_n = &common_tmds_n_table[i];
224 break;
225 }
226 }
227
228 if (!tmds_n)
229 return -ENOENT;
230
231 switch (freq) {
232 case 32000:
233 return tmds_n->n_32k;
234 case 44100:
235 case 88200:
236 case 176400:
237 return (freq / 44100) * tmds_n->n_44k1;
238 case 48000:
239 case 96000:
240 case 192000:
241 return (freq / 48000) * tmds_n->n_48k;
242 default:
243 return -ENOENT;
244 }
245 }
246
dw_hdmi_qp_audio_math_diff(unsigned int freq,unsigned int n,unsigned int pixel_clk)247 static u32 dw_hdmi_qp_audio_math_diff(unsigned int freq, unsigned int n,
248 unsigned int pixel_clk)
249 {
250 u64 cts = mul_u32_u32(pixel_clk, n);
251
252 return do_div(cts, 128 * freq);
253 }
254
dw_hdmi_qp_compute_n(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long freq)255 static unsigned int dw_hdmi_qp_compute_n(struct dw_hdmi_qp *hdmi,
256 unsigned long pixel_clk,
257 unsigned long freq)
258 {
259 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500);
260 unsigned int max_n = (128 * freq) / 300;
261 unsigned int ideal_n = (128 * freq) / 1000;
262 unsigned int best_n_distance = ideal_n;
263 unsigned int best_n = 0;
264 u64 best_diff = U64_MAX;
265 int n;
266
267 /* If the ideal N could satisfy the audio math, then just take it */
268 if (dw_hdmi_qp_audio_math_diff(freq, ideal_n, pixel_clk) == 0)
269 return ideal_n;
270
271 for (n = min_n; n <= max_n; n++) {
272 u64 diff = dw_hdmi_qp_audio_math_diff(freq, n, pixel_clk);
273
274 if (diff < best_diff ||
275 (diff == best_diff && abs(n - ideal_n) < best_n_distance)) {
276 best_n = n;
277 best_diff = diff;
278 best_n_distance = abs(best_n - ideal_n);
279 }
280
281 /*
282 * The best N already satisfy the audio math, and also be
283 * the closest value to ideal N, so just cut the loop.
284 */
285 if (best_diff == 0 && (abs(n - ideal_n) > best_n_distance))
286 break;
287 }
288
289 return best_n;
290 }
291
dw_hdmi_qp_find_n(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long sample_rate)292 static unsigned int dw_hdmi_qp_find_n(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk,
293 unsigned long sample_rate)
294 {
295 int n = dw_hdmi_qp_match_tmds_n_table(hdmi, pixel_clk, sample_rate);
296
297 if (n > 0)
298 return n;
299
300 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n",
301 pixel_clk);
302
303 return dw_hdmi_qp_compute_n(hdmi, pixel_clk, sample_rate);
304 }
305
dw_hdmi_qp_find_cts(struct dw_hdmi_qp * hdmi,unsigned long pixel_clk,unsigned long sample_rate)306 static unsigned int dw_hdmi_qp_find_cts(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk,
307 unsigned long sample_rate)
308 {
309 const struct dw_hdmi_audio_tmds_cts *tmds_cts = NULL;
310 int i;
311
312 for (i = 0; common_tmds_cts_table[i].tmds != 0; i++) {
313 if (pixel_clk == common_tmds_cts_table[i].tmds) {
314 tmds_cts = &common_tmds_cts_table[i];
315 break;
316 }
317 }
318
319 if (!tmds_cts)
320 return 0;
321
322 switch (sample_rate) {
323 case 32000:
324 return tmds_cts->cts_32k;
325 case 44100:
326 case 88200:
327 case 176400:
328 return tmds_cts->cts_44k1;
329 case 48000:
330 case 96000:
331 case 192000:
332 return tmds_cts->cts_48k;
333 default:
334 return -ENOENT;
335 }
336 }
337
dw_hdmi_qp_set_audio_interface(struct dw_hdmi_qp * hdmi,struct hdmi_codec_daifmt * fmt,struct hdmi_codec_params * hparms)338 static void dw_hdmi_qp_set_audio_interface(struct dw_hdmi_qp *hdmi,
339 struct hdmi_codec_daifmt *fmt,
340 struct hdmi_codec_params *hparms)
341 {
342 u32 conf0 = 0;
343
344 /* Reset the audio data path of the AVP */
345 dw_hdmi_qp_write(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWINIT_P, GLOBAL_SWRESET_REQUEST);
346
347 /* Disable AUDS, ACR, AUDI */
348 dw_hdmi_qp_mod(hdmi, 0,
349 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDS_TX_EN | PKTSCHED_AUDI_TX_EN,
350 PKTSCHED_PKT_EN);
351
352 /* Clear the audio FIFO */
353 dw_hdmi_qp_write(hdmi, AUDIO_FIFO_CLR_P, AUDIO_INTERFACE_CONTROL0);
354
355 /* Select I2S interface as the audio source */
356 dw_hdmi_qp_mod(hdmi, AUD_IF_I2S, AUD_IF_SEL_MSK, AUDIO_INTERFACE_CONFIG0);
357
358 /* Enable the active i2s lanes */
359 switch (hparms->channels) {
360 case 7 ... 8:
361 conf0 |= I2S_LINES_EN(3);
362 fallthrough;
363 case 5 ... 6:
364 conf0 |= I2S_LINES_EN(2);
365 fallthrough;
366 case 3 ... 4:
367 conf0 |= I2S_LINES_EN(1);
368 fallthrough;
369 default:
370 conf0 |= I2S_LINES_EN(0);
371 break;
372 }
373
374 dw_hdmi_qp_mod(hdmi, conf0, I2S_LINES_EN_MSK, AUDIO_INTERFACE_CONFIG0);
375
376 /*
377 * Enable bpcuv generated internally for L-PCM, or received
378 * from stream for NLPCM/HBR.
379 */
380 switch (fmt->bit_fmt) {
381 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
382 conf0 = (hparms->channels == 8) ? AUD_HBR : AUD_ASP;
383 conf0 |= I2S_BPCUV_RCV_EN;
384 break;
385 default:
386 conf0 = AUD_ASP | I2S_BPCUV_RCV_DIS;
387 break;
388 }
389
390 dw_hdmi_qp_mod(hdmi, conf0, I2S_BPCUV_RCV_MSK | AUD_FORMAT_MSK,
391 AUDIO_INTERFACE_CONFIG0);
392
393 /* Enable audio FIFO auto clear when overflow */
394 dw_hdmi_qp_mod(hdmi, AUD_FIFO_INIT_ON_OVF_EN, AUD_FIFO_INIT_ON_OVF_MSK,
395 AUDIO_INTERFACE_CONFIG0);
396 }
397
398 /*
399 * When transmitting IEC60958 linear PCM audio, these registers allow to
400 * configure the channel status information of all the channel status
401 * bits in the IEC60958 frame. For the moment this configuration is only
402 * used when the I2S audio interface, General Purpose Audio (GPA),
403 * or AHB audio DMA (AHBAUDDMA) interface is active
404 * (for S/PDIF interface this information comes from the stream).
405 */
dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp * hdmi,u8 * channel_status,bool ref2stream)406 static void dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp *hdmi,
407 u8 *channel_status, bool ref2stream)
408 {
409 /*
410 * AUDPKT_CHSTATUS_OVR0: { RSV, RSV, CS1, CS0 }
411 * AUDPKT_CHSTATUS_OVR1: { CS6, CS5, CS4, CS3 }
412 *
413 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
414 * CS0: | Mode | d | c | b | a |
415 * CS1: | Category Code |
416 * CS2: | Channel Number | Source Number |
417 * CS3: | Clock Accuracy | Sample Freq |
418 * CS4: | Ori Sample Freq | Word Length |
419 * CS5: | | CGMS-A |
420 * CS6~CS23: Reserved
421 *
422 * a: use of channel status block
423 * b: linear PCM identification: 0 for lpcm, 1 for nlpcm
424 * c: copyright information
425 * d: additional format information
426 */
427
428 if (ref2stream)
429 channel_status[0] |= IEC958_AES0_NONAUDIO;
430
431 if ((dw_hdmi_qp_read(hdmi, AUDIO_INTERFACE_CONFIG0) & GENMASK(25, 24)) == AUD_HBR) {
432 /* fixup cs for HBR */
433 channel_status[3] = (channel_status[3] & 0xf0) | IEC958_AES3_CON_FS_768000;
434 channel_status[4] = (channel_status[4] & 0x0f) | IEC958_AES4_CON_ORIGFS_NOTID;
435 }
436
437 dw_hdmi_qp_write(hdmi, channel_status[0] | (channel_status[1] << 8),
438 AUDPKT_CHSTATUS_OVR0);
439
440 regmap_bulk_write(hdmi->regm, AUDPKT_CHSTATUS_OVR1, &channel_status[3], 1);
441
442 if (ref2stream)
443 dw_hdmi_qp_mod(hdmi, 0,
444 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK,
445 AUDPKT_CONTROL0);
446 else
447 dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN,
448 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK,
449 AUDPKT_CONTROL0);
450 }
451
dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp * hdmi,unsigned long long tmds_char_rate,unsigned int sample_rate)452 static void dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp *hdmi, unsigned long long tmds_char_rate,
453 unsigned int sample_rate)
454 {
455 unsigned int n, cts;
456
457 n = dw_hdmi_qp_find_n(hdmi, tmds_char_rate, sample_rate);
458 cts = dw_hdmi_qp_find_cts(hdmi, tmds_char_rate, sample_rate);
459
460 dw_hdmi_qp_set_cts_n(hdmi, cts, n);
461 }
462
dw_hdmi_qp_audio_enable(struct drm_bridge * bridge,struct drm_connector * connector)463 static int dw_hdmi_qp_audio_enable(struct drm_bridge *bridge,
464 struct drm_connector *connector)
465 {
466 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
467
468 if (hdmi->tmds_char_rate)
469 dw_hdmi_qp_mod(hdmi, 0, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE);
470
471 return 0;
472 }
473
dw_hdmi_qp_audio_prepare(struct drm_bridge * bridge,struct drm_connector * connector,struct hdmi_codec_daifmt * fmt,struct hdmi_codec_params * hparms)474 static int dw_hdmi_qp_audio_prepare(struct drm_bridge *bridge,
475 struct drm_connector *connector,
476 struct hdmi_codec_daifmt *fmt,
477 struct hdmi_codec_params *hparms)
478 {
479 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
480 bool ref2stream = false;
481
482 if (!hdmi->tmds_char_rate)
483 return -ENODEV;
484
485 if (fmt->bit_clk_provider | fmt->frame_clk_provider) {
486 dev_err(hdmi->dev, "unsupported clock settings\n");
487 return -EINVAL;
488 }
489
490 if (fmt->bit_fmt == SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE)
491 ref2stream = true;
492
493 dw_hdmi_qp_set_audio_interface(hdmi, fmt, hparms);
494 dw_hdmi_qp_set_sample_rate(hdmi, hdmi->tmds_char_rate, hparms->sample_rate);
495 dw_hdmi_qp_set_channel_status(hdmi, hparms->iec.status, ref2stream);
496 drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, &hparms->cea);
497
498 return 0;
499 }
500
dw_hdmi_qp_audio_disable_regs(struct dw_hdmi_qp * hdmi)501 static void dw_hdmi_qp_audio_disable_regs(struct dw_hdmi_qp *hdmi)
502 {
503 /*
504 * Keep ACR, AUDI, AUDS packet always on to make SINK device
505 * active for better compatibility and user experience.
506 *
507 * This also fix POP sound on some SINK devices which wakeup
508 * from suspend to active.
509 */
510 dw_hdmi_qp_mod(hdmi, I2S_BPCUV_RCV_DIS, I2S_BPCUV_RCV_MSK,
511 AUDIO_INTERFACE_CONFIG0);
512 dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN,
513 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK,
514 AUDPKT_CONTROL0);
515
516 dw_hdmi_qp_mod(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE,
517 AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE);
518 }
519
dw_hdmi_qp_audio_disable(struct drm_bridge * bridge,struct drm_connector * connector)520 static void dw_hdmi_qp_audio_disable(struct drm_bridge *bridge,
521 struct drm_connector *connector)
522 {
523 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
524
525 drm_atomic_helper_connector_hdmi_clear_audio_infoframe(connector);
526
527 if (hdmi->tmds_char_rate)
528 dw_hdmi_qp_audio_disable_regs(hdmi);
529 }
530
dw_hdmi_qp_i2c_read(struct dw_hdmi_qp * hdmi,unsigned char * buf,unsigned int length)531 static int dw_hdmi_qp_i2c_read(struct dw_hdmi_qp *hdmi,
532 unsigned char *buf, unsigned int length)
533 {
534 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
535 int stat;
536
537 if (!i2c->is_regaddr) {
538 dev_dbg(hdmi->dev, "set read register address to 0\n");
539 i2c->slave_reg = 0x00;
540 i2c->is_regaddr = true;
541 }
542
543 while (length--) {
544 reinit_completion(&i2c->cmp);
545
546 dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
547 I2CM_INTERFACE_CONTROL0);
548
549 if (i2c->is_segment)
550 dw_hdmi_qp_mod(hdmi, I2CM_EXT_READ, I2CM_WR_MASK,
551 I2CM_INTERFACE_CONTROL0);
552 else
553 dw_hdmi_qp_mod(hdmi, I2CM_FM_READ, I2CM_WR_MASK,
554 I2CM_INTERFACE_CONTROL0);
555
556 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
557 if (!stat) {
558 dev_err(hdmi->dev, "i2c read timed out\n");
559 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
560 return -EAGAIN;
561 }
562
563 /* Check for error condition on the bus */
564 if (i2c->stat & I2CM_NACK_RCVD_IRQ) {
565 dev_err(hdmi->dev, "i2c read error\n");
566 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
567 return -EIO;
568 }
569
570 *buf++ = dw_hdmi_qp_read(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff;
571 dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
572 }
573
574 i2c->is_segment = false;
575
576 return 0;
577 }
578
dw_hdmi_qp_i2c_write(struct dw_hdmi_qp * hdmi,unsigned char * buf,unsigned int length)579 static int dw_hdmi_qp_i2c_write(struct dw_hdmi_qp *hdmi,
580 unsigned char *buf, unsigned int length)
581 {
582 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
583 int stat;
584
585 if (!i2c->is_regaddr) {
586 /* Use the first write byte as register address */
587 i2c->slave_reg = buf[0];
588 length--;
589 buf++;
590 i2c->is_regaddr = true;
591 }
592
593 while (length--) {
594 reinit_completion(&i2c->cmp);
595
596 dw_hdmi_qp_write(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3);
597 dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR,
598 I2CM_INTERFACE_CONTROL0);
599 dw_hdmi_qp_mod(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK,
600 I2CM_INTERFACE_CONTROL0);
601
602 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10);
603 if (!stat) {
604 dev_err(hdmi->dev, "i2c write time out!\n");
605 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
606 return -EAGAIN;
607 }
608
609 /* Check for error condition on the bus */
610 if (i2c->stat & I2CM_NACK_RCVD_IRQ) {
611 dev_err(hdmi->dev, "i2c write nack!\n");
612 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
613 return -EIO;
614 }
615
616 dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0);
617 }
618
619 return 0;
620 }
621
dw_hdmi_qp_i2c_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)622 static int dw_hdmi_qp_i2c_xfer(struct i2c_adapter *adap,
623 struct i2c_msg *msgs, int num)
624 {
625 struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap);
626 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
627 u8 addr = msgs[0].addr;
628 int i, ret = 0;
629
630 if (addr == DDC_CI_ADDR)
631 /*
632 * The internal I2C controller does not support the multi-byte
633 * read and write operations needed for DDC/CI.
634 * FIXME: Blacklist the DDC/CI address until we filter out
635 * unsupported I2C operations.
636 */
637 return -EOPNOTSUPP;
638
639 for (i = 0; i < num; i++) {
640 if (msgs[i].len == 0) {
641 dev_err(hdmi->dev,
642 "unsupported transfer %d/%d, no data\n",
643 i + 1, num);
644 return -EOPNOTSUPP;
645 }
646 }
647
648 guard(mutex)(&i2c->lock);
649
650 /* Unmute DONE and ERROR interrupts */
651 dw_hdmi_qp_mod(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
652 I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N,
653 MAINUNIT_1_INT_MASK_N);
654
655 /* Set slave device address taken from the first I2C message */
656 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1)
657 addr = DDC_ADDR;
658
659 dw_hdmi_qp_mod(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0);
660
661 /* Set slave device register address on transfer */
662 i2c->is_regaddr = false;
663
664 /* Set segment pointer for I2C extended read mode operation */
665 i2c->is_segment = false;
666
667 for (i = 0; i < num; i++) {
668 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) {
669 i2c->is_segment = true;
670 dw_hdmi_qp_mod(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR,
671 I2CM_INTERFACE_CONTROL1);
672 dw_hdmi_qp_mod(hdmi, *msgs[i].buf << 7, I2CM_SEG_PTR,
673 I2CM_INTERFACE_CONTROL1);
674 } else {
675 if (msgs[i].flags & I2C_M_RD)
676 ret = dw_hdmi_qp_i2c_read(hdmi, msgs[i].buf,
677 msgs[i].len);
678 else
679 ret = dw_hdmi_qp_i2c_write(hdmi, msgs[i].buf,
680 msgs[i].len);
681 }
682 if (ret < 0)
683 break;
684 }
685
686 if (!ret)
687 ret = num;
688
689 /* Mute DONE and ERROR interrupts */
690 dw_hdmi_qp_mod(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N,
691 MAINUNIT_1_INT_MASK_N);
692
693 return ret;
694 }
695
dw_hdmi_qp_i2c_func(struct i2c_adapter * adapter)696 static u32 dw_hdmi_qp_i2c_func(struct i2c_adapter *adapter)
697 {
698 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
699 }
700
701 static const struct i2c_algorithm dw_hdmi_qp_algorithm = {
702 .master_xfer = dw_hdmi_qp_i2c_xfer,
703 .functionality = dw_hdmi_qp_i2c_func,
704 };
705
dw_hdmi_qp_i2c_adapter(struct dw_hdmi_qp * hdmi)706 static struct i2c_adapter *dw_hdmi_qp_i2c_adapter(struct dw_hdmi_qp *hdmi)
707 {
708 struct dw_hdmi_qp_i2c *i2c;
709 struct i2c_adapter *adap;
710 int ret;
711
712 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL);
713 if (!i2c)
714 return ERR_PTR(-ENOMEM);
715
716 mutex_init(&i2c->lock);
717 init_completion(&i2c->cmp);
718
719 adap = &i2c->adap;
720 adap->owner = THIS_MODULE;
721 adap->dev.parent = hdmi->dev;
722 adap->algo = &dw_hdmi_qp_algorithm;
723 strscpy(adap->name, "DesignWare HDMI QP", sizeof(adap->name));
724
725 i2c_set_adapdata(adap, hdmi);
726
727 ret = devm_i2c_add_adapter(hdmi->dev, adap);
728 if (ret) {
729 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name);
730 devm_kfree(hdmi->dev, i2c);
731 return ERR_PTR(ret);
732 }
733
734 hdmi->i2c = i2c;
735 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name);
736
737 return adap;
738 }
739
dw_hdmi_qp_config_avi_infoframe(struct dw_hdmi_qp * hdmi,const u8 * buffer,size_t len)740 static int dw_hdmi_qp_config_avi_infoframe(struct dw_hdmi_qp *hdmi,
741 const u8 *buffer, size_t len)
742 {
743 u32 val, i, j;
744
745 if (len != HDMI_INFOFRAME_SIZE(AVI)) {
746 dev_err(hdmi->dev, "failed to configure avi infoframe\n");
747 return -EINVAL;
748 }
749
750 /*
751 * DW HDMI QP IP uses a different byte format from standard AVI info
752 * frames, though generally the bits are in the correct bytes.
753 */
754 val = buffer[1] << 8 | buffer[2] << 16;
755 dw_hdmi_qp_write(hdmi, val, PKT_AVI_CONTENTS0);
756
757 for (i = 0; i < 4; i++) {
758 for (j = 0; j < 4; j++) {
759 if (i * 4 + j >= 14)
760 break;
761 if (!j)
762 val = buffer[i * 4 + j + 3];
763 val |= buffer[i * 4 + j + 3] << (8 * j);
764 }
765
766 dw_hdmi_qp_write(hdmi, val, PKT_AVI_CONTENTS1 + i * 4);
767 }
768
769 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1);
770
771 dw_hdmi_qp_mod(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN,
772 PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, PKTSCHED_PKT_EN);
773
774 return 0;
775 }
776
dw_hdmi_qp_config_drm_infoframe(struct dw_hdmi_qp * hdmi,const u8 * buffer,size_t len)777 static int dw_hdmi_qp_config_drm_infoframe(struct dw_hdmi_qp *hdmi,
778 const u8 *buffer, size_t len)
779 {
780 u32 val, i;
781
782 if (len != HDMI_INFOFRAME_SIZE(DRM)) {
783 dev_err(hdmi->dev, "failed to configure drm infoframe\n");
784 return -EINVAL;
785 }
786
787 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
788
789 val = buffer[1] << 8 | buffer[2] << 16;
790 dw_hdmi_qp_write(hdmi, val, PKT_DRMI_CONTENTS0);
791
792 for (i = 0; i <= buffer[2]; i++) {
793 if (i % 4 == 0)
794 val = buffer[3 + i];
795 val |= buffer[3 + i] << ((i % 4) * 8);
796
797 if ((i % 4 == 3) || i == buffer[2])
798 dw_hdmi_qp_write(hdmi, val,
799 PKT_DRMI_CONTENTS1 + ((i / 4) * 4));
800 }
801
802 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_FIELDRATE, PKTSCHED_PKT_CONFIG1);
803 dw_hdmi_qp_mod(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN,
804 PKTSCHED_PKT_EN);
805
806 return 0;
807 }
808
809 /*
810 * Static values documented in the TRM
811 * Different values are only used for debug purposes
812 */
813 #define DW_HDMI_QP_AUDIO_INFOFRAME_HB1 0x1
814 #define DW_HDMI_QP_AUDIO_INFOFRAME_HB2 0xa
815
dw_hdmi_qp_config_audio_infoframe(struct dw_hdmi_qp * hdmi,const u8 * buffer,size_t len)816 static int dw_hdmi_qp_config_audio_infoframe(struct dw_hdmi_qp *hdmi,
817 const u8 *buffer, size_t len)
818 {
819 /*
820 * AUDI_CONTENTS0: { RSV, HB2, HB1, RSV }
821 * AUDI_CONTENTS1: { PB3, PB2, PB1, PB0 }
822 * AUDI_CONTENTS2: { PB7, PB6, PB5, PB4 }
823 *
824 * PB0: CheckSum
825 * PB1: | CT3 | CT2 | CT1 | CT0 | F13 | CC2 | CC1 | CC0 |
826 * PB2: | F27 | F26 | F25 | SF2 | SF1 | SF0 | SS1 | SS0 |
827 * PB3: | F37 | F36 | F35 | F34 | F33 | F32 | F31 | F30 |
828 * PB4: | CA7 | CA6 | CA5 | CA4 | CA3 | CA2 | CA1 | CA0 |
829 * PB5: | DM_INH | LSV3 | LSV2 | LSV1 | LSV0 | F52 | F51 | F50 |
830 * PB6~PB10: Reserved
831 *
832 * AUDI_CONTENTS0 default value defined by HDMI specification,
833 * and shall only be changed for debug purposes.
834 */
835 u32 header_bytes = (DW_HDMI_QP_AUDIO_INFOFRAME_HB1 << 8) |
836 (DW_HDMI_QP_AUDIO_INFOFRAME_HB2 << 16);
837
838 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS0, &header_bytes, 1);
839 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS1, &buffer[3], 1);
840 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS2, &buffer[4], 1);
841
842 /* Enable ACR, AUDI, AMD */
843 dw_hdmi_qp_mod(hdmi,
844 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN,
845 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN,
846 PKTSCHED_PKT_EN);
847
848 /* Enable AUDS */
849 dw_hdmi_qp_mod(hdmi, PKTSCHED_AUDS_TX_EN, PKTSCHED_AUDS_TX_EN, PKTSCHED_PKT_EN);
850
851 return 0;
852 }
853
dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)854 static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge,
855 struct drm_atomic_state *state)
856 {
857 struct dw_hdmi_qp *hdmi = bridge->driver_private;
858 struct drm_connector_state *conn_state;
859 struct drm_connector *connector;
860 unsigned int op_mode;
861
862 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder);
863 if (WARN_ON(!connector))
864 return;
865
866 conn_state = drm_atomic_get_new_connector_state(state, connector);
867 if (WARN_ON(!conn_state))
868 return;
869
870 if (connector->display_info.is_hdmi) {
871 dev_dbg(hdmi->dev, "%s mode=HDMI %s rate=%llu bpc=%u\n", __func__,
872 drm_hdmi_connector_get_output_format_name(conn_state->hdmi.output_format),
873 conn_state->hdmi.tmds_char_rate, conn_state->hdmi.output_bpc);
874 op_mode = 0;
875 hdmi->tmds_char_rate = conn_state->hdmi.tmds_char_rate;
876 } else {
877 dev_dbg(hdmi->dev, "%s mode=DVI\n", __func__);
878 op_mode = OPMODE_DVI;
879 }
880
881 hdmi->phy.ops->init(hdmi, hdmi->phy.data);
882
883 dw_hdmi_qp_mod(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0);
884 dw_hdmi_qp_mod(hdmi, op_mode, OPMODE_DVI, LINK_CONFIG0);
885
886 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state);
887 }
888
dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)889 static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge,
890 struct drm_atomic_state *state)
891 {
892 struct dw_hdmi_qp *hdmi = bridge->driver_private;
893
894 hdmi->tmds_char_rate = 0;
895
896 hdmi->phy.ops->disable(hdmi, hdmi->phy.data);
897 }
898
899 static enum drm_connector_status
dw_hdmi_qp_bridge_detect(struct drm_bridge * bridge,struct drm_connector * connector)900 dw_hdmi_qp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector)
901 {
902 struct dw_hdmi_qp *hdmi = bridge->driver_private;
903
904 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
905 }
906
907 static const struct drm_edid *
dw_hdmi_qp_bridge_edid_read(struct drm_bridge * bridge,struct drm_connector * connector)908 dw_hdmi_qp_bridge_edid_read(struct drm_bridge *bridge,
909 struct drm_connector *connector)
910 {
911 struct dw_hdmi_qp *hdmi = bridge->driver_private;
912 const struct drm_edid *drm_edid;
913
914 drm_edid = drm_edid_read_ddc(connector, bridge->ddc);
915 if (!drm_edid)
916 dev_dbg(hdmi->dev, "failed to get edid\n");
917
918 return drm_edid;
919 }
920
921 static enum drm_mode_status
dw_hdmi_qp_bridge_tmds_char_rate_valid(const struct drm_bridge * bridge,const struct drm_display_mode * mode,unsigned long long rate)922 dw_hdmi_qp_bridge_tmds_char_rate_valid(const struct drm_bridge *bridge,
923 const struct drm_display_mode *mode,
924 unsigned long long rate)
925 {
926 struct dw_hdmi_qp *hdmi = bridge->driver_private;
927
928 if (rate > HDMI14_MAX_TMDSCLK) {
929 dev_dbg(hdmi->dev, "Unsupported TMDS char rate: %lld\n", rate);
930 return MODE_CLOCK_HIGH;
931 }
932
933 return MODE_OK;
934 }
935
dw_hdmi_qp_bridge_clear_infoframe(struct drm_bridge * bridge,enum hdmi_infoframe_type type)936 static int dw_hdmi_qp_bridge_clear_infoframe(struct drm_bridge *bridge,
937 enum hdmi_infoframe_type type)
938 {
939 struct dw_hdmi_qp *hdmi = bridge->driver_private;
940
941 switch (type) {
942 case HDMI_INFOFRAME_TYPE_AVI:
943 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN,
944 PKTSCHED_PKT_EN);
945 break;
946
947 case HDMI_INFOFRAME_TYPE_DRM:
948 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN);
949 break;
950
951 case HDMI_INFOFRAME_TYPE_AUDIO:
952 dw_hdmi_qp_mod(hdmi, 0,
953 PKTSCHED_ACR_TX_EN |
954 PKTSCHED_AUDS_TX_EN |
955 PKTSCHED_AUDI_TX_EN,
956 PKTSCHED_PKT_EN);
957 break;
958 default:
959 dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type);
960 }
961
962 return 0;
963 }
964
dw_hdmi_qp_bridge_write_infoframe(struct drm_bridge * bridge,enum hdmi_infoframe_type type,const u8 * buffer,size_t len)965 static int dw_hdmi_qp_bridge_write_infoframe(struct drm_bridge *bridge,
966 enum hdmi_infoframe_type type,
967 const u8 *buffer, size_t len)
968 {
969 struct dw_hdmi_qp *hdmi = bridge->driver_private;
970
971 dw_hdmi_qp_bridge_clear_infoframe(bridge, type);
972
973 switch (type) {
974 case HDMI_INFOFRAME_TYPE_AVI:
975 return dw_hdmi_qp_config_avi_infoframe(hdmi, buffer, len);
976
977 case HDMI_INFOFRAME_TYPE_DRM:
978 return dw_hdmi_qp_config_drm_infoframe(hdmi, buffer, len);
979
980 case HDMI_INFOFRAME_TYPE_AUDIO:
981 return dw_hdmi_qp_config_audio_infoframe(hdmi, buffer, len);
982
983 default:
984 dev_dbg(hdmi->dev, "Unsupported infoframe type %x\n", type);
985 return 0;
986 }
987 }
988
989 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC
dw_hdmi_qp_cec_hardirq(int irq,void * dev_id)990 static irqreturn_t dw_hdmi_qp_cec_hardirq(int irq, void *dev_id)
991 {
992 struct dw_hdmi_qp *hdmi = dev_id;
993 struct dw_hdmi_qp_cec *cec = hdmi->cec;
994 irqreturn_t ret = IRQ_HANDLED;
995 u32 stat;
996
997 stat = dw_hdmi_qp_read(hdmi, CEC_INT_STATUS);
998 if (stat == 0)
999 return IRQ_NONE;
1000
1001 dw_hdmi_qp_write(hdmi, stat, CEC_INT_CLEAR);
1002
1003 if (stat & CEC_STAT_LINE_ERR) {
1004 cec->tx_status = CEC_TX_STATUS_ERROR;
1005 cec->tx_done = true;
1006 ret = IRQ_WAKE_THREAD;
1007 } else if (stat & CEC_STAT_DONE) {
1008 cec->tx_status = CEC_TX_STATUS_OK;
1009 cec->tx_done = true;
1010 ret = IRQ_WAKE_THREAD;
1011 } else if (stat & CEC_STAT_NACK) {
1012 cec->tx_status = CEC_TX_STATUS_NACK;
1013 cec->tx_done = true;
1014 ret = IRQ_WAKE_THREAD;
1015 }
1016
1017 if (stat & CEC_STAT_EOM) {
1018 unsigned int len, i, val;
1019
1020 val = dw_hdmi_qp_read(hdmi, CEC_RX_COUNT_STATUS);
1021 len = (val & 0xf) + 1;
1022
1023 if (len > sizeof(cec->rx_msg.msg))
1024 len = sizeof(cec->rx_msg.msg);
1025
1026 for (i = 0; i < 4; i++) {
1027 val = dw_hdmi_qp_read(hdmi, CEC_RX_DATA3_0 + i * 4);
1028 cec->rx_msg.msg[i * 4] = val & 0xff;
1029 cec->rx_msg.msg[i * 4 + 1] = (val >> 8) & 0xff;
1030 cec->rx_msg.msg[i * 4 + 2] = (val >> 16) & 0xff;
1031 cec->rx_msg.msg[i * 4 + 3] = (val >> 24) & 0xff;
1032 }
1033
1034 dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL);
1035
1036 cec->rx_msg.len = len;
1037 cec->rx_done = true;
1038
1039 ret = IRQ_WAKE_THREAD;
1040 }
1041
1042 return ret;
1043 }
1044
dw_hdmi_qp_cec_thread(int irq,void * dev_id)1045 static irqreturn_t dw_hdmi_qp_cec_thread(int irq, void *dev_id)
1046 {
1047 struct dw_hdmi_qp *hdmi = dev_id;
1048 struct dw_hdmi_qp_cec *cec = hdmi->cec;
1049
1050 if (cec->tx_done) {
1051 cec->tx_done = false;
1052 drm_connector_hdmi_cec_transmit_attempt_done(cec->connector,
1053 cec->tx_status);
1054 }
1055
1056 if (cec->rx_done) {
1057 cec->rx_done = false;
1058 drm_connector_hdmi_cec_received_msg(cec->connector, &cec->rx_msg);
1059 }
1060
1061 return IRQ_HANDLED;
1062 }
1063
dw_hdmi_qp_cec_init(struct drm_bridge * bridge,struct drm_connector * connector)1064 static int dw_hdmi_qp_cec_init(struct drm_bridge *bridge,
1065 struct drm_connector *connector)
1066 {
1067 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
1068 struct dw_hdmi_qp_cec *cec = hdmi->cec;
1069
1070 cec->connector = connector;
1071
1072 dw_hdmi_qp_write(hdmi, 0, CEC_TX_COUNT);
1073 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR);
1074 dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N);
1075
1076 return devm_request_threaded_irq(hdmi->dev, cec->irq,
1077 dw_hdmi_qp_cec_hardirq,
1078 dw_hdmi_qp_cec_thread, IRQF_SHARED,
1079 dev_name(hdmi->dev), hdmi);
1080 }
1081
dw_hdmi_qp_cec_log_addr(struct drm_bridge * bridge,u8 logical_addr)1082 static int dw_hdmi_qp_cec_log_addr(struct drm_bridge *bridge, u8 logical_addr)
1083 {
1084 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
1085 struct dw_hdmi_qp_cec *cec = hdmi->cec;
1086
1087 if (logical_addr == CEC_LOG_ADDR_INVALID)
1088 cec->addresses = 0;
1089 else
1090 cec->addresses |= BIT(logical_addr) | CEC_ADDR_BROADCAST;
1091
1092 dw_hdmi_qp_write(hdmi, cec->addresses, CEC_ADDR);
1093
1094 return 0;
1095 }
1096
dw_hdmi_qp_cec_enable(struct drm_bridge * bridge,bool enable)1097 static int dw_hdmi_qp_cec_enable(struct drm_bridge *bridge, bool enable)
1098 {
1099 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
1100 unsigned int irqs;
1101 u32 swdisable;
1102
1103 if (!enable) {
1104 dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N);
1105 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR);
1106
1107 swdisable = dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE);
1108 swdisable = swdisable | CEC_SWDISABLE;
1109 dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE);
1110 } else {
1111 swdisable = dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE);
1112 swdisable = swdisable & ~CEC_SWDISABLE;
1113 dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE);
1114
1115 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR);
1116 dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL);
1117
1118 dw_hdmi_qp_cec_log_addr(bridge, CEC_LOG_ADDR_INVALID);
1119
1120 irqs = CEC_STAT_LINE_ERR | CEC_STAT_NACK | CEC_STAT_EOM |
1121 CEC_STAT_DONE;
1122 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR);
1123 dw_hdmi_qp_write(hdmi, irqs, CEC_INT_MASK_N);
1124 }
1125
1126 return 0;
1127 }
1128
dw_hdmi_qp_cec_transmit(struct drm_bridge * bridge,u8 attempts,u32 signal_free_time,struct cec_msg * msg)1129 static int dw_hdmi_qp_cec_transmit(struct drm_bridge *bridge, u8 attempts,
1130 u32 signal_free_time, struct cec_msg *msg)
1131 {
1132 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge);
1133 unsigned int i;
1134 u32 val;
1135
1136 for (i = 0; i < msg->len; i++) {
1137 if (!(i % 4))
1138 val = msg->msg[i];
1139 if ((i % 4) == 1)
1140 val |= msg->msg[i] << 8;
1141 if ((i % 4) == 2)
1142 val |= msg->msg[i] << 16;
1143 if ((i % 4) == 3)
1144 val |= msg->msg[i] << 24;
1145
1146 if (i == (msg->len - 1) || (i % 4) == 3)
1147 dw_hdmi_qp_write(hdmi, val, CEC_TX_DATA3_0 + (i / 4) * 4);
1148 }
1149
1150 dw_hdmi_qp_write(hdmi, msg->len - 1, CEC_TX_COUNT);
1151 dw_hdmi_qp_write(hdmi, CEC_CTRL_START, CEC_TX_CONTROL);
1152
1153 return 0;
1154 }
1155 #else
1156 #define dw_hdmi_qp_cec_init NULL
1157 #define dw_hdmi_qp_cec_enable NULL
1158 #define dw_hdmi_qp_cec_log_addr NULL
1159 #define dw_hdmi_qp_cec_transmit NULL
1160 #endif /* CONFIG_DRM_DW_HDMI_QP_CEC */
1161
1162 static const struct drm_bridge_funcs dw_hdmi_qp_bridge_funcs = {
1163 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1164 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1165 .atomic_reset = drm_atomic_helper_bridge_reset,
1166 .atomic_enable = dw_hdmi_qp_bridge_atomic_enable,
1167 .atomic_disable = dw_hdmi_qp_bridge_atomic_disable,
1168 .detect = dw_hdmi_qp_bridge_detect,
1169 .edid_read = dw_hdmi_qp_bridge_edid_read,
1170 .hdmi_tmds_char_rate_valid = dw_hdmi_qp_bridge_tmds_char_rate_valid,
1171 .hdmi_clear_infoframe = dw_hdmi_qp_bridge_clear_infoframe,
1172 .hdmi_write_infoframe = dw_hdmi_qp_bridge_write_infoframe,
1173 .hdmi_audio_startup = dw_hdmi_qp_audio_enable,
1174 .hdmi_audio_shutdown = dw_hdmi_qp_audio_disable,
1175 .hdmi_audio_prepare = dw_hdmi_qp_audio_prepare,
1176 .hdmi_cec_init = dw_hdmi_qp_cec_init,
1177 .hdmi_cec_enable = dw_hdmi_qp_cec_enable,
1178 .hdmi_cec_log_addr = dw_hdmi_qp_cec_log_addr,
1179 .hdmi_cec_transmit = dw_hdmi_qp_cec_transmit,
1180 };
1181
dw_hdmi_qp_main_hardirq(int irq,void * dev_id)1182 static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id)
1183 {
1184 struct dw_hdmi_qp *hdmi = dev_id;
1185 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c;
1186 u32 stat;
1187
1188 stat = dw_hdmi_qp_read(hdmi, MAINUNIT_1_INT_STATUS);
1189
1190 i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ |
1191 I2CM_NACK_RCVD_IRQ);
1192
1193 if (i2c->stat) {
1194 dw_hdmi_qp_write(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR);
1195 complete(&i2c->cmp);
1196 }
1197
1198 if (stat)
1199 return IRQ_HANDLED;
1200
1201 return IRQ_NONE;
1202 }
1203
1204 static const struct regmap_config dw_hdmi_qp_regmap_config = {
1205 .reg_bits = 32,
1206 .val_bits = 32,
1207 .reg_stride = 4,
1208 .max_register = EARCRX_1_INT_FORCE,
1209 };
1210
dw_hdmi_qp_init_hw(struct dw_hdmi_qp * hdmi)1211 static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *hdmi)
1212 {
1213 dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N);
1214 dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N);
1215 dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0);
1216
1217 /* Software reset */
1218 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0);
1219 dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0);
1220 dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0);
1221
1222 /* Clear DONE and ERROR interrupts */
1223 dw_hdmi_qp_write(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR,
1224 MAINUNIT_1_INT_CLEAR);
1225
1226 if (hdmi->phy.ops->setup_hpd)
1227 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data);
1228 }
1229
dw_hdmi_qp_bind(struct platform_device * pdev,struct drm_encoder * encoder,const struct dw_hdmi_qp_plat_data * plat_data)1230 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev,
1231 struct drm_encoder *encoder,
1232 const struct dw_hdmi_qp_plat_data *plat_data)
1233 {
1234 struct device *dev = &pdev->dev;
1235 struct dw_hdmi_qp *hdmi;
1236 void __iomem *regs;
1237 int ret;
1238
1239 if (!plat_data->phy_ops || !plat_data->phy_ops->init ||
1240 !plat_data->phy_ops->disable || !plat_data->phy_ops->read_hpd) {
1241 dev_err(dev, "Missing platform PHY ops\n");
1242 return ERR_PTR(-ENODEV);
1243 }
1244
1245 hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi_qp, bridge,
1246 &dw_hdmi_qp_bridge_funcs);
1247 if (IS_ERR(hdmi))
1248 return ERR_CAST(hdmi);
1249
1250 hdmi->dev = dev;
1251
1252 regs = devm_platform_ioremap_resource(pdev, 0);
1253 if (IS_ERR(regs))
1254 return ERR_CAST(regs);
1255
1256 hdmi->regm = devm_regmap_init_mmio(dev, regs, &dw_hdmi_qp_regmap_config);
1257 if (IS_ERR(hdmi->regm)) {
1258 dev_err(dev, "Failed to configure regmap\n");
1259 return ERR_CAST(hdmi->regm);
1260 }
1261
1262 hdmi->phy.ops = plat_data->phy_ops;
1263 hdmi->phy.data = plat_data->phy_data;
1264
1265 if (plat_data->ref_clk_rate) {
1266 hdmi->ref_clk_rate = plat_data->ref_clk_rate;
1267 } else {
1268 hdmi->ref_clk_rate = 428571429;
1269 dev_warn(dev, "Set ref_clk_rate to vendor default\n");
1270 }
1271
1272 dw_hdmi_qp_init_hw(hdmi);
1273
1274 ret = devm_request_threaded_irq(dev, plat_data->main_irq,
1275 dw_hdmi_qp_main_hardirq, NULL,
1276 IRQF_SHARED, dev_name(dev), hdmi);
1277 if (ret)
1278 return ERR_PTR(ret);
1279
1280 hdmi->bridge.driver_private = hdmi;
1281 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT |
1282 DRM_BRIDGE_OP_EDID |
1283 DRM_BRIDGE_OP_HDMI |
1284 DRM_BRIDGE_OP_HDMI_AUDIO |
1285 DRM_BRIDGE_OP_HPD;
1286 hdmi->bridge.of_node = pdev->dev.of_node;
1287 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1288 hdmi->bridge.vendor = "Synopsys";
1289 hdmi->bridge.product = "DW HDMI QP TX";
1290
1291 if (plat_data->supported_formats)
1292 hdmi->bridge.supported_formats = plat_data->supported_formats;
1293
1294 if (plat_data->max_bpc)
1295 hdmi->bridge.max_bpc = plat_data->max_bpc;
1296
1297 hdmi->bridge.ddc = dw_hdmi_qp_i2c_adapter(hdmi);
1298 if (IS_ERR(hdmi->bridge.ddc))
1299 return ERR_CAST(hdmi->bridge.ddc);
1300
1301 hdmi->bridge.hdmi_audio_max_i2s_playback_channels = 8;
1302 hdmi->bridge.hdmi_audio_dev = dev;
1303 hdmi->bridge.hdmi_audio_dai_port = 1;
1304
1305 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC
1306 if (plat_data->cec_irq) {
1307 hdmi->bridge.ops |= DRM_BRIDGE_OP_HDMI_CEC_ADAPTER;
1308 hdmi->bridge.hdmi_cec_dev = dev;
1309 hdmi->bridge.hdmi_cec_adapter_name = dev_name(dev);
1310
1311 hdmi->cec = devm_kzalloc(hdmi->dev, sizeof(*hdmi->cec), GFP_KERNEL);
1312 if (!hdmi->cec)
1313 return ERR_PTR(-ENOMEM);
1314
1315 hdmi->cec->irq = plat_data->cec_irq;
1316 } else {
1317 dev_warn(dev, "Disabled CEC support due to missing IRQ\n");
1318 }
1319 #endif
1320
1321 ret = devm_drm_bridge_add(dev, &hdmi->bridge);
1322 if (ret)
1323 return ERR_PTR(ret);
1324
1325 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL,
1326 DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1327 if (ret)
1328 return ERR_PTR(ret);
1329
1330 return hdmi;
1331 }
1332 EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind);
1333
dw_hdmi_qp_resume(struct device * dev,struct dw_hdmi_qp * hdmi)1334 void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi)
1335 {
1336 dw_hdmi_qp_init_hw(hdmi);
1337 }
1338 EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume);
1339
1340 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>");
1341 MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>");
1342 MODULE_DESCRIPTION("DW HDMI QP transmitter library");
1343 MODULE_LICENSE("GPL");
1344