1 /*
2 * Common utility functions for VGA-based graphics cards.
3 *
4 * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive for
8 * more details.
9 *
10 * Some parts are based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
11 */
12
13 #include <linux/export.h>
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/string.h>
17 #include <linux/fb.h>
18 #include <linux/math.h>
19 #include <linux/svga.h>
20 #include <asm/types.h>
21 #include <asm/io.h>
22
23 /* Write a CRT register value spread across multiple registers */
svga_wcrt_multi(void __iomem * regbase,const struct vga_regset * regset,u32 value)24 void svga_wcrt_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value)
25 {
26 u8 regval, bitval, bitnum;
27
28 while (regset->regnum != VGA_REGSET_END_VAL) {
29 regval = vga_rcrt(regbase, regset->regnum);
30 bitnum = regset->lowbit;
31 while (bitnum <= regset->highbit) {
32 bitval = 1 << bitnum;
33 regval = regval & ~bitval;
34 if (value & 1)
35 regval = regval | bitval;
36 bitnum++;
37 value = value >> 1;
38 }
39 vga_wcrt(regbase, regset->regnum, regval);
40 regset++;
41 }
42 }
43
44 /* Write a sequencer register value spread across multiple registers */
svga_wseq_multi(void __iomem * regbase,const struct vga_regset * regset,u32 value)45 void svga_wseq_multi(void __iomem *regbase, const struct vga_regset *regset, u32 value)
46 {
47 u8 regval, bitval, bitnum;
48
49 while (regset->regnum != VGA_REGSET_END_VAL) {
50 regval = vga_rseq(regbase, regset->regnum);
51 bitnum = regset->lowbit;
52 while (bitnum <= regset->highbit) {
53 bitval = 1 << bitnum;
54 regval = regval & ~bitval;
55 if (value & 1)
56 regval = regval | bitval;
57 bitnum++;
58 value = value >> 1;
59 }
60 vga_wseq(regbase, regset->regnum, regval);
61 regset++;
62 }
63 }
64
svga_regset_size(const struct vga_regset * regset)65 static unsigned int svga_regset_size(const struct vga_regset *regset)
66 {
67 u8 count = 0;
68
69 while (regset->regnum != VGA_REGSET_END_VAL) {
70 count += regset->highbit - regset->lowbit + 1;
71 regset++;
72 }
73 return 1 << count;
74 }
75
76 /* ------------------------------------------------------------------------- */
77
78 /* Set graphics controller registers to sane values */
svga_set_default_gfx_regs(void __iomem * regbase)79 void svga_set_default_gfx_regs(void __iomem *regbase)
80 {
81 /* All standard GFX registers (GR00 - GR08) */
82 vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0x00);
83 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0x00);
84 vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0x00);
85 vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0x00);
86 vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0x00);
87 vga_wgfx(regbase, VGA_GFX_MODE, 0x00);
88 /* vga_wgfx(regbase, VGA_GFX_MODE, 0x20); */
89 /* vga_wgfx(regbase, VGA_GFX_MODE, 0x40); */
90 vga_wgfx(regbase, VGA_GFX_MISC, 0x05);
91 /* vga_wgfx(regbase, VGA_GFX_MISC, 0x01); */
92 vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x0F);
93 vga_wgfx(regbase, VGA_GFX_BIT_MASK, 0xFF);
94 }
95
96 /* Set attribute controller registers to sane values */
svga_set_default_atc_regs(void __iomem * regbase)97 void svga_set_default_atc_regs(void __iomem *regbase)
98 {
99 u8 count;
100
101 vga_r(regbase, 0x3DA);
102 vga_w(regbase, VGA_ATT_W, 0x00);
103
104 /* All standard ATC registers (AR00 - AR14) */
105 for (count = 0; count <= 0xF; count++)
106 svga_wattr(regbase, count, count);
107
108 svga_wattr(regbase, VGA_ATC_MODE, 0x01);
109 /* svga_wattr(regbase, VGA_ATC_MODE, 0x41); */
110 svga_wattr(regbase, VGA_ATC_OVERSCAN, 0x00);
111 svga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 0x0F);
112 svga_wattr(regbase, VGA_ATC_PEL, 0x00);
113 svga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0x00);
114
115 vga_r(regbase, 0x3DA);
116 vga_w(regbase, VGA_ATT_W, 0x20);
117 }
118
119 /* Set sequencer registers to sane values */
svga_set_default_seq_regs(void __iomem * regbase)120 void svga_set_default_seq_regs(void __iomem *regbase)
121 {
122 /* Standard sequencer registers (SR01 - SR04), SR00 is not set */
123 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, VGA_SR01_CHAR_CLK_8DOTS);
124 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, VGA_SR02_ALL_PLANES);
125 vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
126 /* vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE | VGA_SR04_CHN_4M); */
127 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM | VGA_SR04_SEQ_MODE);
128 }
129
130 /* Set CRTC registers to sane values */
svga_set_default_crt_regs(void __iomem * regbase)131 void svga_set_default_crt_regs(void __iomem *regbase)
132 {
133 /* Standard CRT registers CR03 CR08 CR09 CR14 CR17 */
134 svga_wcrt_mask(regbase, 0x03, 0x80, 0x80); /* Enable vertical retrace EVRA */
135 vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
136 svga_wcrt_mask(regbase, VGA_CRTC_MAX_SCAN, 0, 0x1F);
137 vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
138 vga_wcrt(regbase, VGA_CRTC_MODE, 0xE3);
139 }
140
svga_set_textmode_vga_regs(void __iomem * regbase)141 void svga_set_textmode_vga_regs(void __iomem *regbase)
142 {
143 /* svga_wseq_mask(regbase, 0x1, 0x00, 0x01); */ /* Switch 8/9 pixel per char */
144 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, VGA_SR04_EXT_MEM);
145 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x03);
146
147 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, 0x0f); /* 0x4f */
148 vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0x1f);
149 svga_wcrt_mask(regbase, VGA_CRTC_MODE, 0x23, 0x7f);
150
151 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0x0d);
152 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 0x0e);
153 vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0x00);
154 vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0x00);
155
156 vga_wgfx(regbase, VGA_GFX_MODE, 0x10); /* Odd/even memory mode */
157 vga_wgfx(regbase, VGA_GFX_MISC, 0x0E); /* Misc graphics register - text mode enable */
158 vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 0x00);
159
160 vga_r(regbase, 0x3DA);
161 vga_w(regbase, VGA_ATT_W, 0x00);
162
163 svga_wattr(regbase, 0x10, 0x0C); /* Attribute Mode Control Register - text mode, blinking and line graphics */
164 svga_wattr(regbase, 0x13, 0x08); /* Horizontal Pixel Panning Register */
165
166 vga_r(regbase, 0x3DA);
167 vga_w(regbase, VGA_ATT_W, 0x20);
168 }
169
170 #if 0
171 void svga_dump_var(struct fb_var_screeninfo *var, int node)
172 {
173 pr_debug("fb%d: var.vmode : 0x%X\n", node, var->vmode);
174 pr_debug("fb%d: var.xres : %d\n", node, var->xres);
175 pr_debug("fb%d: var.yres : %d\n", node, var->yres);
176 pr_debug("fb%d: var.bits_per_pixel: %d\n", node, var->bits_per_pixel);
177 pr_debug("fb%d: var.xres_virtual : %d\n", node, var->xres_virtual);
178 pr_debug("fb%d: var.yres_virtual : %d\n", node, var->yres_virtual);
179 pr_debug("fb%d: var.left_margin : %d\n", node, var->left_margin);
180 pr_debug("fb%d: var.right_margin : %d\n", node, var->right_margin);
181 pr_debug("fb%d: var.upper_margin : %d\n", node, var->upper_margin);
182 pr_debug("fb%d: var.lower_margin : %d\n", node, var->lower_margin);
183 pr_debug("fb%d: var.hsync_len : %d\n", node, var->hsync_len);
184 pr_debug("fb%d: var.vsync_len : %d\n", node, var->vsync_len);
185 pr_debug("fb%d: var.sync : 0x%X\n", node, var->sync);
186 pr_debug("fb%d: var.pixclock : %d\n\n", node, var->pixclock);
187 }
188 #endif /* 0 */
189
190 /* ------------------------------------------------------------------------- */
191
svga_settile(struct fb_info * info,struct fb_tilemap * map)192 void svga_settile(struct fb_info *info, struct fb_tilemap *map)
193 {
194 const u8 *font = map->data;
195 u8 __iomem *fb = (u8 __iomem *)info->screen_base;
196 int i, c;
197
198 if ((map->width != 8) || (map->height != 16) ||
199 (map->depth != 1) || (map->length != 256)) {
200 fb_err(info, "unsupported font parameters: width %d, height %d, depth %d, length %d\n",
201 map->width, map->height, map->depth, map->length);
202 return;
203 }
204
205 fb += 2;
206 for (c = 0; c < map->length; c++) {
207 for (i = 0; i < map->height; i++) {
208 fb_writeb(font[i], fb + i * 4);
209 // fb[i * 4] = font[i];
210 }
211 fb += 128;
212 font += map->height;
213 }
214 }
215
216 /* Copy area in text (tileblit) mode */
svga_tilecopy(struct fb_info * info,struct fb_tilearea * area)217 void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area)
218 {
219 int dx, dy;
220 /* colstride is halved in this function because u16 are used */
221 int colstride = 1 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
222 int rowstride = colstride * (info->var.xres_virtual / 8);
223 u16 __iomem *fb = (u16 __iomem *) info->screen_base;
224 u16 __iomem *src, *dst;
225
226 if ((area->sy > area->dy) ||
227 ((area->sy == area->dy) && (area->sx > area->dx))) {
228 src = fb + area->sx * colstride + area->sy * rowstride;
229 dst = fb + area->dx * colstride + area->dy * rowstride;
230 } else {
231 src = fb + (area->sx + area->width - 1) * colstride
232 + (area->sy + area->height - 1) * rowstride;
233 dst = fb + (area->dx + area->width - 1) * colstride
234 + (area->dy + area->height - 1) * rowstride;
235
236 colstride = -colstride;
237 rowstride = -rowstride;
238 }
239
240 for (dy = 0; dy < area->height; dy++) {
241 u16 __iomem *src2 = src;
242 u16 __iomem *dst2 = dst;
243 for (dx = 0; dx < area->width; dx++) {
244 fb_writew(fb_readw(src2), dst2);
245 // *dst2 = *src2;
246 src2 += colstride;
247 dst2 += colstride;
248 }
249 src += rowstride;
250 dst += rowstride;
251 }
252 }
253
254 /* Fill area in text (tileblit) mode */
svga_tilefill(struct fb_info * info,struct fb_tilerect * rect)255 void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect)
256 {
257 int dx, dy;
258 int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
259 int rowstride = colstride * (info->var.xres_virtual / 8);
260 int attr = (0x0F & rect->bg) << 4 | (0x0F & rect->fg);
261 u8 __iomem *fb = (u8 __iomem *)info->screen_base;
262 fb += rect->sx * colstride + rect->sy * rowstride;
263
264 for (dy = 0; dy < rect->height; dy++) {
265 u8 __iomem *fb2 = fb;
266 for (dx = 0; dx < rect->width; dx++) {
267 fb_writeb(rect->index, fb2);
268 fb_writeb(attr, fb2 + 1);
269 fb2 += colstride;
270 }
271 fb += rowstride;
272 }
273 }
274
275 /* Write text in text (tileblit) mode */
svga_tileblit(struct fb_info * info,struct fb_tileblit * blit)276 void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit)
277 {
278 int dx, dy, i;
279 int colstride = 2 << (info->fix.type_aux & FB_AUX_TEXT_SVGA_MASK);
280 int rowstride = colstride * (info->var.xres_virtual / 8);
281 int attr = (0x0F & blit->bg) << 4 | (0x0F & blit->fg);
282 u8 __iomem *fb = (u8 __iomem *)info->screen_base;
283 fb += blit->sx * colstride + blit->sy * rowstride;
284
285 i = 0;
286 for (dy = 0; dy < blit->height; dy++) {
287 u8 __iomem *fb2 = fb;
288 for (dx = 0; dx < blit->width; dx++) {
289 fb_writeb(blit->indices[i], fb2);
290 fb_writeb(attr, fb2 + 1);
291 fb2 += colstride;
292 i++;
293 if (i == blit->length)
294 return;
295 }
296 fb += rowstride;
297 }
298 }
299
300 /* Set cursor in text (tileblit) mode */
svga_tilecursor(void __iomem * regbase,struct fb_info * info,struct fb_tilecursor * cursor)301 void svga_tilecursor(void __iomem *regbase, struct fb_info *info, struct fb_tilecursor *cursor)
302 {
303 u8 cs = 0x0d;
304 u8 ce = 0x0e;
305 u16 pos = cursor->sx + (info->var.xoffset / 8)
306 + (cursor->sy + (info->var.yoffset / 16))
307 * (info->var.xres_virtual / 8);
308
309 if (!cursor->mode)
310 return;
311
312 svga_wcrt_mask(regbase, 0x0A, 0x20, 0x20); /* disable cursor */
313
314 if (cursor->shape == FB_TILE_CURSOR_NONE)
315 return;
316
317 switch (cursor->shape) {
318 case FB_TILE_CURSOR_UNDERLINE:
319 cs = 0x0d;
320 break;
321 case FB_TILE_CURSOR_LOWER_THIRD:
322 cs = 0x09;
323 break;
324 case FB_TILE_CURSOR_LOWER_HALF:
325 cs = 0x07;
326 break;
327 case FB_TILE_CURSOR_TWO_THIRDS:
328 cs = 0x05;
329 break;
330 case FB_TILE_CURSOR_BLOCK:
331 cs = 0x01;
332 break;
333 }
334
335 /* set cursor position */
336 vga_wcrt(regbase, 0x0E, pos >> 8);
337 vga_wcrt(regbase, 0x0F, pos & 0xFF);
338
339 vga_wcrt(regbase, 0x0B, ce); /* set cursor end */
340 vga_wcrt(regbase, 0x0A, cs); /* set cursor start and enable it */
341 }
342
svga_get_tilemax(struct fb_info * info)343 int svga_get_tilemax(struct fb_info *info)
344 {
345 return 256;
346 }
347
348 /* Get capabilities of accelerator based on the mode */
349
svga_get_caps(struct fb_info * info,struct fb_blit_caps * caps,struct fb_var_screeninfo * var)350 void svga_get_caps(struct fb_info *info, struct fb_blit_caps *caps,
351 struct fb_var_screeninfo *var)
352 {
353 if (var->bits_per_pixel == 0) {
354 /* can only support 256 8x16 bitmap */
355 bitmap_zero(caps->x, FB_MAX_BLIT_WIDTH);
356 set_bit(8 - 1, caps->x);
357 bitmap_zero(caps->y, FB_MAX_BLIT_HEIGHT);
358 set_bit(16 - 1, caps->y);
359 caps->len = 256;
360 } else {
361 if (var->bits_per_pixel == 4) {
362 bitmap_zero(caps->x, FB_MAX_BLIT_WIDTH);
363 set_bit(8 - 1, caps->x);
364 } else {
365 bitmap_fill(caps->x, FB_MAX_BLIT_WIDTH);
366 }
367 bitmap_fill(caps->y, FB_MAX_BLIT_HEIGHT);
368 caps->len = ~(u32)0;
369 }
370 }
371 EXPORT_SYMBOL(svga_get_caps);
372
373 /* ------------------------------------------------------------------------- */
374
375 /*
376 * Compute PLL settings (M, N, R)
377 * F_VCO = (F_BASE * M) / N
378 * F_OUT = F_VCO / (2^R)
379 */
svga_compute_pll(const struct svga_pll * pll,u32 f_wanted,u16 * m,u16 * n,u16 * r,int node)380 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node)
381 {
382 u16 am, an, ar;
383 u32 f_vco, f_current, delta_current, delta_best;
384
385 pr_debug("fb%d: ideal frequency: %d kHz\n", node, (unsigned int)f_wanted);
386
387 ar = pll->r_max;
388 f_vco = f_wanted << ar;
389
390 /* overflow check */
391 if ((f_vco >> ar) != f_wanted)
392 return -EINVAL;
393
394 /* It is usually better to have greater VCO clock
395 because of better frequency stability.
396 So first try r_max, then r smaller. */
397 while ((ar > pll->r_min) && (f_vco > pll->f_vco_max)) {
398 ar--;
399 f_vco = f_vco >> 1;
400 }
401
402 /* VCO bounds check */
403 if ((f_vco < pll->f_vco_min) || (f_vco > pll->f_vco_max))
404 return -EINVAL;
405
406 delta_best = 0xFFFFFFFF;
407 *m = 0;
408 *n = 0;
409 *r = ar;
410
411 am = pll->m_min;
412 an = pll->n_min;
413
414 while ((am <= pll->m_max) && (an <= pll->n_max)) {
415 f_current = (pll->f_base * am) / an;
416 delta_current = abs_diff(f_current, f_vco);
417
418 if (delta_current < delta_best) {
419 delta_best = delta_current;
420 *m = am;
421 *n = an;
422 }
423
424 if (f_current <= f_vco)
425 am++;
426 else
427 an++;
428 }
429
430 f_current = (pll->f_base * *m) / *n;
431 pr_debug("fb%d: found frequency: %d kHz (VCO %d kHz)\n", node, (int)(f_current >> ar), (int)f_current);
432 pr_debug("fb%d: m = %d n = %d r = %d\n", node, (unsigned int)*m, (unsigned int)*n, (unsigned int)*r);
433 return 0;
434 }
435
436 /* ------------------------------------------------------------------------- */
437
438 /* Check CRT timing values */
svga_check_timings(const struct svga_timing_regs * tm,struct fb_var_screeninfo * var,int node)439 int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node)
440 {
441 u32 value;
442
443 var->xres = (var->xres + 7) & ~7;
444 var->left_margin = (var->left_margin + 7) & ~7;
445 var->right_margin = (var->right_margin + 7) & ~7;
446 var->hsync_len = (var->hsync_len + 7) & ~7;
447
448 /* Check horizontal total */
449 value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
450 if (((value / 8) - 5) >= svga_regset_size(tm->h_total_regs))
451 return -EINVAL;
452
453 /* Check horizontal display and blank start */
454 value = var->xres;
455 if (((value / 8) - 1) >= svga_regset_size(tm->h_display_regs))
456 return -EINVAL;
457 if (((value / 8) - 1) >= svga_regset_size(tm->h_blank_start_regs))
458 return -EINVAL;
459
460 /* Check horizontal sync start */
461 value = var->xres + var->right_margin;
462 if (((value / 8) - 1) >= svga_regset_size(tm->h_sync_start_regs))
463 return -EINVAL;
464
465 /* Check horizontal blank end (or length) */
466 value = var->left_margin + var->right_margin + var->hsync_len;
467 if ((value == 0) || ((value / 8) >= svga_regset_size(tm->h_blank_end_regs)))
468 return -EINVAL;
469
470 /* Check horizontal sync end (or length) */
471 value = var->hsync_len;
472 if ((value == 0) || ((value / 8) >= svga_regset_size(tm->h_sync_end_regs)))
473 return -EINVAL;
474
475 /* Check vertical total */
476 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
477 if ((value - 1) >= svga_regset_size(tm->v_total_regs))
478 return -EINVAL;
479
480 /* Check vertical display and blank start */
481 value = var->yres;
482 if ((value - 1) >= svga_regset_size(tm->v_display_regs))
483 return -EINVAL;
484 if ((value - 1) >= svga_regset_size(tm->v_blank_start_regs))
485 return -EINVAL;
486
487 /* Check vertical sync start */
488 value = var->yres + var->lower_margin;
489 if ((value - 1) >= svga_regset_size(tm->v_sync_start_regs))
490 return -EINVAL;
491
492 /* Check vertical blank end (or length) */
493 value = var->upper_margin + var->lower_margin + var->vsync_len;
494 if ((value == 0) || (value >= svga_regset_size(tm->v_blank_end_regs)))
495 return -EINVAL;
496
497 /* Check vertical sync end (or length) */
498 value = var->vsync_len;
499 if ((value == 0) || (value >= svga_regset_size(tm->v_sync_end_regs)))
500 return -EINVAL;
501
502 return 0;
503 }
504
505 /* Set CRT timing registers */
svga_set_timings(void __iomem * regbase,const struct svga_timing_regs * tm,struct fb_var_screeninfo * var,u32 hmul,u32 hdiv,u32 vmul,u32 vdiv,u32 hborder,int node)506 void svga_set_timings(void __iomem *regbase, const struct svga_timing_regs *tm,
507 struct fb_var_screeninfo *var,
508 u32 hmul, u32 hdiv, u32 vmul, u32 vdiv, u32 hborder, int node)
509 {
510 u8 regval;
511 u32 value;
512
513 value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
514 value = (value * hmul) / hdiv;
515 pr_debug("fb%d: horizontal total : %d\n", node, value);
516 svga_wcrt_multi(regbase, tm->h_total_regs, (value / 8) - 5);
517
518 value = var->xres;
519 value = (value * hmul) / hdiv;
520 pr_debug("fb%d: horizontal display : %d\n", node, value);
521 svga_wcrt_multi(regbase, tm->h_display_regs, (value / 8) - 1);
522
523 value = var->xres;
524 value = (value * hmul) / hdiv;
525 pr_debug("fb%d: horizontal blank start: %d\n", node, value);
526 svga_wcrt_multi(regbase, tm->h_blank_start_regs, (value / 8) - 1 + hborder);
527
528 value = var->xres + var->left_margin + var->right_margin + var->hsync_len;
529 value = (value * hmul) / hdiv;
530 pr_debug("fb%d: horizontal blank end : %d\n", node, value);
531 svga_wcrt_multi(regbase, tm->h_blank_end_regs, (value / 8) - 1 - hborder);
532
533 value = var->xres + var->right_margin;
534 value = (value * hmul) / hdiv;
535 pr_debug("fb%d: horizontal sync start : %d\n", node, value);
536 svga_wcrt_multi(regbase, tm->h_sync_start_regs, (value / 8));
537
538 value = var->xres + var->right_margin + var->hsync_len;
539 value = (value * hmul) / hdiv;
540 pr_debug("fb%d: horizontal sync end : %d\n", node, value);
541 svga_wcrt_multi(regbase, tm->h_sync_end_regs, (value / 8));
542
543 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
544 value = (value * vmul) / vdiv;
545 pr_debug("fb%d: vertical total : %d\n", node, value);
546 svga_wcrt_multi(regbase, tm->v_total_regs, value - 2);
547
548 value = var->yres;
549 value = (value * vmul) / vdiv;
550 pr_debug("fb%d: vertical display : %d\n", node, value);
551 svga_wcrt_multi(regbase, tm->v_display_regs, value - 1);
552
553 value = var->yres;
554 value = (value * vmul) / vdiv;
555 pr_debug("fb%d: vertical blank start : %d\n", node, value);
556 svga_wcrt_multi(regbase, tm->v_blank_start_regs, value);
557
558 value = var->yres + var->upper_margin + var->lower_margin + var->vsync_len;
559 value = (value * vmul) / vdiv;
560 pr_debug("fb%d: vertical blank end : %d\n", node, value);
561 svga_wcrt_multi(regbase, tm->v_blank_end_regs, value - 2);
562
563 value = var->yres + var->lower_margin;
564 value = (value * vmul) / vdiv;
565 pr_debug("fb%d: vertical sync start : %d\n", node, value);
566 svga_wcrt_multi(regbase, tm->v_sync_start_regs, value);
567
568 value = var->yres + var->lower_margin + var->vsync_len;
569 value = (value * vmul) / vdiv;
570 pr_debug("fb%d: vertical sync end : %d\n", node, value);
571 svga_wcrt_multi(regbase, tm->v_sync_end_regs, value);
572
573 /* Set horizontal and vertical sync pulse polarity in misc register */
574
575 regval = vga_r(regbase, VGA_MIS_R);
576 if (var->sync & FB_SYNC_HOR_HIGH_ACT) {
577 pr_debug("fb%d: positive horizontal sync\n", node);
578 regval = regval & ~0x80;
579 } else {
580 pr_debug("fb%d: negative horizontal sync\n", node);
581 regval = regval | 0x80;
582 }
583 if (var->sync & FB_SYNC_VERT_HIGH_ACT) {
584 pr_debug("fb%d: positive vertical sync\n", node);
585 regval = regval & ~0x40;
586 } else {
587 pr_debug("fb%d: negative vertical sync\n\n", node);
588 regval = regval | 0x40;
589 }
590 vga_w(regbase, VGA_MIS_W, regval);
591 }
592
593 /* ------------------------------------------------------------------------- */
594
match_format(const struct svga_fb_format * frm,struct fb_var_screeninfo * var)595 static inline int match_format(const struct svga_fb_format *frm,
596 struct fb_var_screeninfo *var)
597 {
598 int i = 0;
599 int stored = -EINVAL;
600
601 while (frm->bits_per_pixel != SVGA_FORMAT_END_VAL) {
602 if ((var->bits_per_pixel == frm->bits_per_pixel) &&
603 (var->red.length <= frm->red.length) &&
604 (var->green.length <= frm->green.length) &&
605 (var->blue.length <= frm->blue.length) &&
606 (var->transp.length <= frm->transp.length) &&
607 (var->nonstd == frm->nonstd))
608 return i;
609 if (var->bits_per_pixel == frm->bits_per_pixel)
610 stored = i;
611 i++;
612 frm++;
613 }
614 return stored;
615 }
616
svga_match_format(const struct svga_fb_format * frm,struct fb_var_screeninfo * var,struct fb_fix_screeninfo * fix)617 int svga_match_format(const struct svga_fb_format *frm,
618 struct fb_var_screeninfo *var,
619 struct fb_fix_screeninfo *fix)
620 {
621 int i = match_format(frm, var);
622
623 if (i >= 0) {
624 var->bits_per_pixel = frm[i].bits_per_pixel;
625 var->red = frm[i].red;
626 var->green = frm[i].green;
627 var->blue = frm[i].blue;
628 var->transp = frm[i].transp;
629 var->nonstd = frm[i].nonstd;
630 if (fix != NULL) {
631 fix->type = frm[i].type;
632 fix->type_aux = frm[i].type_aux;
633 fix->visual = frm[i].visual;
634 fix->xpanstep = frm[i].xpanstep;
635 }
636 }
637
638 return i;
639 }
640
641 EXPORT_SYMBOL(svga_wcrt_multi);
642 EXPORT_SYMBOL(svga_wseq_multi);
643
644 EXPORT_SYMBOL(svga_set_default_gfx_regs);
645 EXPORT_SYMBOL(svga_set_default_atc_regs);
646 EXPORT_SYMBOL(svga_set_default_seq_regs);
647 EXPORT_SYMBOL(svga_set_default_crt_regs);
648 EXPORT_SYMBOL(svga_set_textmode_vga_regs);
649
650 EXPORT_SYMBOL(svga_settile);
651 EXPORT_SYMBOL(svga_tilecopy);
652 EXPORT_SYMBOL(svga_tilefill);
653 EXPORT_SYMBOL(svga_tileblit);
654 EXPORT_SYMBOL(svga_tilecursor);
655 EXPORT_SYMBOL(svga_get_tilemax);
656
657 EXPORT_SYMBOL(svga_compute_pll);
658 EXPORT_SYMBOL(svga_check_timings);
659 EXPORT_SYMBOL(svga_set_timings);
660 EXPORT_SYMBOL(svga_match_format);
661
662 MODULE_AUTHOR("Ondrej Zajicek <santiago@crfreenet.org>");
663 MODULE_DESCRIPTION("Common utility functions for VGA-based graphics cards");
664 MODULE_LICENSE("GPL");
665