1 // SPDX-License-Identifier: GPL-2.0 2 // Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. 3 // Copyright (c) 2018, Linaro Limited 4 5 #include <dt-bindings/sound/qcom,q6afe.h> 6 #include <linux/slab.h> 7 #include <linux/kernel.h> 8 #include <linux/uaccess.h> 9 #include <linux/wait.h> 10 #include <linux/jiffies.h> 11 #include <linux/sched.h> 12 #include <linux/module.h> 13 #include <linux/kref.h> 14 #include <linux/of.h> 15 #include <linux/of_platform.h> 16 #include <linux/spinlock.h> 17 #include <linux/delay.h> 18 #include <linux/soc/qcom/apr.h> 19 #include <sound/soc.h> 20 #include <sound/soc-dai.h> 21 #include <sound/pcm.h> 22 #include <sound/pcm_params.h> 23 #include "q6dsp-errno.h" 24 #include "q6core.h" 25 #include "q6afe.h" 26 27 /* AFE CMDs */ 28 #define AFE_PORT_CMD_DEVICE_START 0x000100E5 29 #define AFE_PORT_CMD_DEVICE_STOP 0x000100E6 30 #define AFE_PORT_CMD_SET_PARAM_V2 0x000100EF 31 #define AFE_SVC_CMD_SET_PARAM 0x000100f3 32 #define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106 33 #define AFE_PARAM_ID_HDMI_CONFIG 0x00010210 34 #define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C 35 #define AFE_MODULE_TDM 0x0001028A 36 37 #define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG 0x00010235 38 #define AFE_PARAM_ID_USB_AUDIO_DEV_PARAMS 0x000102A5 39 #define AFE_PARAM_ID_USB_AUDIO_DEV_LPCM_FMT 0x000102AA 40 41 #define AFE_PARAM_ID_LPAIF_CLK_CONFIG 0x00010238 42 #define AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG 0x00010239 43 44 #define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212 45 #define AFE_PARAM_ID_I2S_CONFIG 0x0001020D 46 #define AFE_PARAM_ID_TDM_CONFIG 0x0001029D 47 #define AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG 0x00010297 48 #define AFE_PARAM_ID_CODEC_DMA_CONFIG 0x000102B8 49 #define AFE_PARAM_ID_USB_AUDIO_CONFIG 0x000102A4 50 #define AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f4 51 #define AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST 0x000100f5 52 #define AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST 0x000100f6 53 54 /* I2S config specific */ 55 #define AFE_API_VERSION_I2S_CONFIG 0x1 56 #define AFE_PORT_I2S_SD0 0x1 57 #define AFE_PORT_I2S_SD1 0x2 58 #define AFE_PORT_I2S_SD2 0x3 59 #define AFE_PORT_I2S_SD3 0x4 60 #define AFE_PORT_I2S_SD0_MASK BIT(0x0) 61 #define AFE_PORT_I2S_SD1_MASK BIT(0x1) 62 #define AFE_PORT_I2S_SD2_MASK BIT(0x2) 63 #define AFE_PORT_I2S_SD3_MASK BIT(0x3) 64 #define AFE_PORT_I2S_SD0_1_MASK GENMASK(1, 0) 65 #define AFE_PORT_I2S_SD2_3_MASK GENMASK(3, 2) 66 #define AFE_PORT_I2S_SD0_1_2_MASK GENMASK(2, 0) 67 #define AFE_PORT_I2S_SD0_1_2_3_MASK GENMASK(3, 0) 68 #define AFE_PORT_I2S_QUAD01 0x5 69 #define AFE_PORT_I2S_QUAD23 0x6 70 #define AFE_PORT_I2S_6CHS 0x7 71 #define AFE_PORT_I2S_8CHS 0x8 72 #define AFE_PORT_I2S_MONO 0x0 73 #define AFE_PORT_I2S_STEREO 0x1 74 #define AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL 0x0 75 #define AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL 0x1 76 #define AFE_LINEAR_PCM_DATA 0x0 77 78 #define AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 0x1 79 80 /* Port IDs */ 81 #define AFE_API_VERSION_HDMI_CONFIG 0x1 82 #define AFE_PORT_ID_MULTICHAN_HDMI_RX 0x100E 83 #define AFE_PORT_ID_HDMI_OVER_DP_RX 0x6020 84 85 /* USB AFE port */ 86 #define AFE_PORT_ID_USB_RX 0x7000 87 88 #define AFE_API_VERSION_SLIMBUS_CONFIG 0x1 89 /* Clock set API version */ 90 #define AFE_API_VERSION_CLOCK_SET 1 91 #define Q6AFE_LPASS_CLK_CONFIG_API_VERSION 0x1 92 #define AFE_MODULE_CLOCK_SET 0x0001028F 93 #define AFE_PARAM_ID_CLOCK_SET 0x00010290 94 95 /* SLIMbus Rx port on channel 0. */ 96 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX 0x4000 97 /* SLIMbus Tx port on channel 0. */ 98 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX 0x4001 99 /* SLIMbus Rx port on channel 1. */ 100 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX 0x4002 101 /* SLIMbus Tx port on channel 1. */ 102 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX 0x4003 103 /* SLIMbus Rx port on channel 2. */ 104 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX 0x4004 105 /* SLIMbus Tx port on channel 2. */ 106 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX 0x4005 107 /* SLIMbus Rx port on channel 3. */ 108 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX 0x4006 109 /* SLIMbus Tx port on channel 3. */ 110 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX 0x4007 111 /* SLIMbus Rx port on channel 4. */ 112 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX 0x4008 113 /* SLIMbus Tx port on channel 4. */ 114 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX 0x4009 115 /* SLIMbus Rx port on channel 5. */ 116 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX 0x400a 117 /* SLIMbus Tx port on channel 5. */ 118 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX 0x400b 119 /* SLIMbus Rx port on channel 6. */ 120 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX 0x400c 121 /* SLIMbus Tx port on channel 6. */ 122 #define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX 0x400d 123 #define AFE_PORT_ID_PRIMARY_MI2S_RX 0x1000 124 #define AFE_PORT_ID_PRIMARY_MI2S_TX 0x1001 125 #define AFE_PORT_ID_SECONDARY_MI2S_RX 0x1002 126 #define AFE_PORT_ID_SECONDARY_MI2S_TX 0x1003 127 #define AFE_PORT_ID_TERTIARY_MI2S_RX 0x1004 128 #define AFE_PORT_ID_TERTIARY_MI2S_TX 0x1005 129 #define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006 130 #define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007 131 #define AFE_PORT_ID_QUINARY_MI2S_RX 0x1016 132 #define AFE_PORT_ID_QUINARY_MI2S_TX 0x1017 133 134 /* Start of the range of port IDs for TDM devices. */ 135 #define AFE_PORT_ID_TDM_PORT_RANGE_START 0x9000 136 137 /* End of the range of port IDs for TDM devices. */ 138 #define AFE_PORT_ID_TDM_PORT_RANGE_END \ 139 (AFE_PORT_ID_TDM_PORT_RANGE_START+0x50-1) 140 141 /* Size of the range of port IDs for TDM ports. */ 142 #define AFE_PORT_ID_TDM_PORT_RANGE_SIZE \ 143 (AFE_PORT_ID_TDM_PORT_RANGE_END - \ 144 AFE_PORT_ID_TDM_PORT_RANGE_START+1) 145 146 #define AFE_PORT_ID_PRIMARY_TDM_RX \ 147 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x00) 148 #define AFE_PORT_ID_PRIMARY_TDM_RX_1 \ 149 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x02) 150 #define AFE_PORT_ID_PRIMARY_TDM_RX_2 \ 151 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x04) 152 #define AFE_PORT_ID_PRIMARY_TDM_RX_3 \ 153 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x06) 154 #define AFE_PORT_ID_PRIMARY_TDM_RX_4 \ 155 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x08) 156 #define AFE_PORT_ID_PRIMARY_TDM_RX_5 \ 157 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0A) 158 #define AFE_PORT_ID_PRIMARY_TDM_RX_6 \ 159 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0C) 160 #define AFE_PORT_ID_PRIMARY_TDM_RX_7 \ 161 (AFE_PORT_ID_PRIMARY_TDM_RX + 0x0E) 162 163 #define AFE_PORT_ID_PRIMARY_TDM_TX \ 164 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x01) 165 #define AFE_PORT_ID_PRIMARY_TDM_TX_1 \ 166 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x02) 167 #define AFE_PORT_ID_PRIMARY_TDM_TX_2 \ 168 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x04) 169 #define AFE_PORT_ID_PRIMARY_TDM_TX_3 \ 170 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x06) 171 #define AFE_PORT_ID_PRIMARY_TDM_TX_4 \ 172 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x08) 173 #define AFE_PORT_ID_PRIMARY_TDM_TX_5 \ 174 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0A) 175 #define AFE_PORT_ID_PRIMARY_TDM_TX_6 \ 176 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0C) 177 #define AFE_PORT_ID_PRIMARY_TDM_TX_7 \ 178 (AFE_PORT_ID_PRIMARY_TDM_TX + 0x0E) 179 180 #define AFE_PORT_ID_SECONDARY_TDM_RX \ 181 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x10) 182 #define AFE_PORT_ID_SECONDARY_TDM_RX_1 \ 183 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x02) 184 #define AFE_PORT_ID_SECONDARY_TDM_RX_2 \ 185 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x04) 186 #define AFE_PORT_ID_SECONDARY_TDM_RX_3 \ 187 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x06) 188 #define AFE_PORT_ID_SECONDARY_TDM_RX_4 \ 189 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x08) 190 #define AFE_PORT_ID_SECONDARY_TDM_RX_5 \ 191 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0A) 192 #define AFE_PORT_ID_SECONDARY_TDM_RX_6 \ 193 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0C) 194 #define AFE_PORT_ID_SECONDARY_TDM_RX_7 \ 195 (AFE_PORT_ID_SECONDARY_TDM_RX + 0x0E) 196 197 #define AFE_PORT_ID_SECONDARY_TDM_TX \ 198 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x11) 199 #define AFE_PORT_ID_SECONDARY_TDM_TX_1 \ 200 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x02) 201 #define AFE_PORT_ID_SECONDARY_TDM_TX_2 \ 202 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x04) 203 #define AFE_PORT_ID_SECONDARY_TDM_TX_3 \ 204 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x06) 205 #define AFE_PORT_ID_SECONDARY_TDM_TX_4 \ 206 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x08) 207 #define AFE_PORT_ID_SECONDARY_TDM_TX_5 \ 208 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0A) 209 #define AFE_PORT_ID_SECONDARY_TDM_TX_6 \ 210 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0C) 211 #define AFE_PORT_ID_SECONDARY_TDM_TX_7 \ 212 (AFE_PORT_ID_SECONDARY_TDM_TX + 0x0E) 213 214 #define AFE_PORT_ID_TERTIARY_TDM_RX \ 215 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x20) 216 #define AFE_PORT_ID_TERTIARY_TDM_RX_1 \ 217 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x02) 218 #define AFE_PORT_ID_TERTIARY_TDM_RX_2 \ 219 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x04) 220 #define AFE_PORT_ID_TERTIARY_TDM_RX_3 \ 221 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x06) 222 #define AFE_PORT_ID_TERTIARY_TDM_RX_4 \ 223 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x08) 224 #define AFE_PORT_ID_TERTIARY_TDM_RX_5 \ 225 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0A) 226 #define AFE_PORT_ID_TERTIARY_TDM_RX_6 \ 227 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0C) 228 #define AFE_PORT_ID_TERTIARY_TDM_RX_7 \ 229 (AFE_PORT_ID_TERTIARY_TDM_RX + 0x0E) 230 231 #define AFE_PORT_ID_TERTIARY_TDM_TX \ 232 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x21) 233 #define AFE_PORT_ID_TERTIARY_TDM_TX_1 \ 234 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x02) 235 #define AFE_PORT_ID_TERTIARY_TDM_TX_2 \ 236 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x04) 237 #define AFE_PORT_ID_TERTIARY_TDM_TX_3 \ 238 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x06) 239 #define AFE_PORT_ID_TERTIARY_TDM_TX_4 \ 240 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x08) 241 #define AFE_PORT_ID_TERTIARY_TDM_TX_5 \ 242 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0A) 243 #define AFE_PORT_ID_TERTIARY_TDM_TX_6 \ 244 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0C) 245 #define AFE_PORT_ID_TERTIARY_TDM_TX_7 \ 246 (AFE_PORT_ID_TERTIARY_TDM_TX + 0x0E) 247 248 #define AFE_PORT_ID_QUATERNARY_TDM_RX \ 249 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x30) 250 #define AFE_PORT_ID_QUATERNARY_TDM_RX_1 \ 251 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x02) 252 #define AFE_PORT_ID_QUATERNARY_TDM_RX_2 \ 253 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x04) 254 #define AFE_PORT_ID_QUATERNARY_TDM_RX_3 \ 255 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x06) 256 #define AFE_PORT_ID_QUATERNARY_TDM_RX_4 \ 257 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x08) 258 #define AFE_PORT_ID_QUATERNARY_TDM_RX_5 \ 259 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0A) 260 #define AFE_PORT_ID_QUATERNARY_TDM_RX_6 \ 261 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0C) 262 #define AFE_PORT_ID_QUATERNARY_TDM_RX_7 \ 263 (AFE_PORT_ID_QUATERNARY_TDM_RX + 0x0E) 264 265 #define AFE_PORT_ID_QUATERNARY_TDM_TX \ 266 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x31) 267 #define AFE_PORT_ID_QUATERNARY_TDM_TX_1 \ 268 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x02) 269 #define AFE_PORT_ID_QUATERNARY_TDM_TX_2 \ 270 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x04) 271 #define AFE_PORT_ID_QUATERNARY_TDM_TX_3 \ 272 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x06) 273 #define AFE_PORT_ID_QUATERNARY_TDM_TX_4 \ 274 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x08) 275 #define AFE_PORT_ID_QUATERNARY_TDM_TX_5 \ 276 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0A) 277 #define AFE_PORT_ID_QUATERNARY_TDM_TX_6 \ 278 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0C) 279 #define AFE_PORT_ID_QUATERNARY_TDM_TX_7 \ 280 (AFE_PORT_ID_QUATERNARY_TDM_TX + 0x0E) 281 282 #define AFE_PORT_ID_QUINARY_TDM_RX \ 283 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x40) 284 #define AFE_PORT_ID_QUINARY_TDM_RX_1 \ 285 (AFE_PORT_ID_QUINARY_TDM_RX + 0x02) 286 #define AFE_PORT_ID_QUINARY_TDM_RX_2 \ 287 (AFE_PORT_ID_QUINARY_TDM_RX + 0x04) 288 #define AFE_PORT_ID_QUINARY_TDM_RX_3 \ 289 (AFE_PORT_ID_QUINARY_TDM_RX + 0x06) 290 #define AFE_PORT_ID_QUINARY_TDM_RX_4 \ 291 (AFE_PORT_ID_QUINARY_TDM_RX + 0x08) 292 #define AFE_PORT_ID_QUINARY_TDM_RX_5 \ 293 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0A) 294 #define AFE_PORT_ID_QUINARY_TDM_RX_6 \ 295 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0C) 296 #define AFE_PORT_ID_QUINARY_TDM_RX_7 \ 297 (AFE_PORT_ID_QUINARY_TDM_RX + 0x0E) 298 299 #define AFE_PORT_ID_QUINARY_TDM_TX \ 300 (AFE_PORT_ID_TDM_PORT_RANGE_START + 0x41) 301 #define AFE_PORT_ID_QUINARY_TDM_TX_1 \ 302 (AFE_PORT_ID_QUINARY_TDM_TX + 0x02) 303 #define AFE_PORT_ID_QUINARY_TDM_TX_2 \ 304 (AFE_PORT_ID_QUINARY_TDM_TX + 0x04) 305 #define AFE_PORT_ID_QUINARY_TDM_TX_3 \ 306 (AFE_PORT_ID_QUINARY_TDM_TX + 0x06) 307 #define AFE_PORT_ID_QUINARY_TDM_TX_4 \ 308 (AFE_PORT_ID_QUINARY_TDM_TX + 0x08) 309 #define AFE_PORT_ID_QUINARY_TDM_TX_5 \ 310 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0A) 311 #define AFE_PORT_ID_QUINARY_TDM_TX_6 \ 312 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0C) 313 #define AFE_PORT_ID_QUINARY_TDM_TX_7 \ 314 (AFE_PORT_ID_QUINARY_TDM_TX + 0x0E) 315 316 /* AFE WSA Codec DMA Rx port 0 */ 317 #define AFE_PORT_ID_WSA_CODEC_DMA_RX_0 0xB000 318 /* AFE WSA Codec DMA Tx port 0 */ 319 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_0 0xB001 320 /* AFE WSA Codec DMA Rx port 1 */ 321 #define AFE_PORT_ID_WSA_CODEC_DMA_RX_1 0xB002 322 /* AFE WSA Codec DMA Tx port 1 */ 323 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_1 0xB003 324 /* AFE WSA Codec DMA Tx port 2 */ 325 #define AFE_PORT_ID_WSA_CODEC_DMA_TX_2 0xB005 326 /* AFE VA Codec DMA Tx port 0 */ 327 #define AFE_PORT_ID_VA_CODEC_DMA_TX_0 0xB021 328 /* AFE VA Codec DMA Tx port 1 */ 329 #define AFE_PORT_ID_VA_CODEC_DMA_TX_1 0xB023 330 /* AFE VA Codec DMA Tx port 2 */ 331 #define AFE_PORT_ID_VA_CODEC_DMA_TX_2 0xB025 332 /* AFE Rx Codec DMA Rx port 0 */ 333 #define AFE_PORT_ID_RX_CODEC_DMA_RX_0 0xB030 334 /* AFE Tx Codec DMA Tx port 0 */ 335 #define AFE_PORT_ID_TX_CODEC_DMA_TX_0 0xB031 336 /* AFE Rx Codec DMA Rx port 1 */ 337 #define AFE_PORT_ID_RX_CODEC_DMA_RX_1 0xB032 338 /* AFE Tx Codec DMA Tx port 1 */ 339 #define AFE_PORT_ID_TX_CODEC_DMA_TX_1 0xB033 340 /* AFE Rx Codec DMA Rx port 2 */ 341 #define AFE_PORT_ID_RX_CODEC_DMA_RX_2 0xB034 342 /* AFE Tx Codec DMA Tx port 2 */ 343 #define AFE_PORT_ID_TX_CODEC_DMA_TX_2 0xB035 344 /* AFE Rx Codec DMA Rx port 3 */ 345 #define AFE_PORT_ID_RX_CODEC_DMA_RX_3 0xB036 346 /* AFE Tx Codec DMA Tx port 3 */ 347 #define AFE_PORT_ID_TX_CODEC_DMA_TX_3 0xB037 348 /* AFE Rx Codec DMA Rx port 4 */ 349 #define AFE_PORT_ID_RX_CODEC_DMA_RX_4 0xB038 350 /* AFE Tx Codec DMA Tx port 4 */ 351 #define AFE_PORT_ID_TX_CODEC_DMA_TX_4 0xB039 352 /* AFE Rx Codec DMA Rx port 5 */ 353 #define AFE_PORT_ID_RX_CODEC_DMA_RX_5 0xB03A 354 /* AFE Tx Codec DMA Tx port 5 */ 355 #define AFE_PORT_ID_TX_CODEC_DMA_TX_5 0xB03B 356 /* AFE Rx Codec DMA Rx port 6 */ 357 #define AFE_PORT_ID_RX_CODEC_DMA_RX_6 0xB03C 358 /* AFE Rx Codec DMA Rx port 7 */ 359 #define AFE_PORT_ID_RX_CODEC_DMA_RX_7 0xB03E 360 361 #define Q6AFE_LPASS_MODE_CLK1_VALID 1 362 #define Q6AFE_LPASS_MODE_CLK2_VALID 2 363 #define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 364 #define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 365 #define AFE_API_VERSION_TDM_CONFIG 1 366 #define AFE_API_VERSION_SLOT_MAPPING_CONFIG 1 367 #define AFE_API_VERSION_CODEC_DMA_CONFIG 1 368 369 #define TIMEOUT_MS 3000 370 #define AFE_CMD_RESP_AVAIL 0 371 #define AFE_CMD_RESP_NONE 1 372 #define AFE_CLK_TOKEN 1024 373 374 struct q6afe { 375 struct apr_device *apr; 376 struct device *dev; 377 struct q6core_svc_api_info ainfo; 378 struct mutex lock; 379 struct aprv2_ibasic_rsp_result_t result; 380 wait_queue_head_t wait; 381 struct list_head port_list; 382 spinlock_t port_list_lock; 383 }; 384 385 struct afe_port_cmd_device_start { 386 u16 port_id; 387 u16 reserved; 388 } __packed; 389 390 struct afe_port_cmd_device_stop { 391 u16 port_id; 392 u16 reserved; 393 /* Reserved for 32-bit alignment. This field must be set to 0.*/ 394 } __packed; 395 396 struct afe_port_param_data_v2 { 397 u32 module_id; 398 u32 param_id; 399 u16 param_size; 400 u16 reserved; 401 } __packed; 402 403 struct afe_svc_cmd_set_param { 404 uint32_t payload_size; 405 uint32_t payload_address_lsw; 406 uint32_t payload_address_msw; 407 uint32_t mem_map_handle; 408 } __packed; 409 410 struct afe_port_cmd_set_param_v2 { 411 u16 port_id; 412 u16 payload_size; 413 u32 payload_address_lsw; 414 u32 payload_address_msw; 415 u32 mem_map_handle; 416 } __packed; 417 418 struct afe_param_id_hdmi_multi_chan_audio_cfg { 419 u32 hdmi_cfg_minor_version; 420 u16 datatype; 421 u16 channel_allocation; 422 u32 sample_rate; 423 u16 bit_width; 424 u16 reserved; 425 } __packed; 426 427 struct afe_param_id_slimbus_cfg { 428 u32 sb_cfg_minor_version; 429 /* Minor version used for tracking the version of the SLIMBUS 430 * configuration interface. 431 * Supported values: #AFE_API_VERSION_SLIMBUS_CONFIG 432 */ 433 434 u16 slimbus_dev_id; 435 /* SLIMbus hardware device ID, which is required to handle 436 * multiple SLIMbus hardware blocks. 437 * Supported values: - #AFE_SLIMBUS_DEVICE_1 - #AFE_SLIMBUS_DEVICE_2 438 */ 439 u16 bit_width; 440 /* Bit width of the sample. 441 * Supported values: 16, 24 442 */ 443 u16 data_format; 444 /* Data format supported by the SLIMbus hardware. The default is 445 * 0 (#AFE_SB_DATA_FORMAT_NOT_INDICATED), which indicates the 446 * hardware does not perform any format conversions before the data 447 * transfer. 448 */ 449 u16 num_channels; 450 /* Number of channels. 451 * Supported values: 1 to #AFE_PORT_MAX_AUDIO_CHAN_CNT 452 */ 453 u8 shared_ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; 454 /* Mapping of shared channel IDs (128 to 255) to which the 455 * master port is to be connected. 456 * Shared_channel_mapping[i] represents the shared channel assigned 457 * for audio channel i in multichannel audio data. 458 */ 459 u32 sample_rate; 460 /* Sampling rate of the port. 461 * Supported values: 462 * - #AFE_PORT_SAMPLE_RATE_8K 463 * - #AFE_PORT_SAMPLE_RATE_16K 464 * - #AFE_PORT_SAMPLE_RATE_48K 465 * - #AFE_PORT_SAMPLE_RATE_96K 466 * - #AFE_PORT_SAMPLE_RATE_192K 467 */ 468 } __packed; 469 470 struct afe_clk_cfg { 471 u32 i2s_cfg_minor_version; 472 u32 clk_val1; 473 u32 clk_val2; 474 u16 clk_src; 475 u16 clk_root; 476 u16 clk_set_mode; 477 u16 reserved; 478 } __packed; 479 480 struct afe_digital_clk_cfg { 481 u32 i2s_cfg_minor_version; 482 u32 clk_val; 483 u16 clk_root; 484 u16 reserved; 485 } __packed; 486 487 struct afe_param_id_i2s_cfg { 488 u32 i2s_cfg_minor_version; 489 u16 bit_width; 490 u16 channel_mode; 491 u16 mono_stereo; 492 u16 ws_src; 493 u32 sample_rate; 494 u16 data_format; 495 u16 reserved; 496 } __packed; 497 498 struct afe_param_id_tdm_cfg { 499 u32 tdm_cfg_minor_version; 500 u32 num_channels; 501 u32 sample_rate; 502 u32 bit_width; 503 u16 data_format; 504 u16 sync_mode; 505 u16 sync_src; 506 u16 nslots_per_frame; 507 u16 ctrl_data_out_enable; 508 u16 ctrl_invert_sync_pulse; 509 u16 ctrl_sync_data_delay; 510 u16 slot_width; 511 u32 slot_mask; 512 } __packed; 513 514 struct afe_param_id_cdc_dma_cfg { 515 u32 cdc_dma_cfg_minor_version; 516 u32 sample_rate; 517 u16 bit_width; 518 u16 data_format; 519 u16 num_channels; 520 u16 active_channels_mask; 521 } __packed; 522 523 struct afe_param_id_usb_cfg { 524 /* Minor version used for tracking USB audio device configuration. 525 * Supported values: AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 526 */ 527 u32 cfg_minor_version; 528 /* Sampling rate of the port. 529 * Supported values: 530 * - AFE_PORT_SAMPLE_RATE_8K 531 * - AFE_PORT_SAMPLE_RATE_11025 532 * - AFE_PORT_SAMPLE_RATE_12K 533 * - AFE_PORT_SAMPLE_RATE_16K 534 * - AFE_PORT_SAMPLE_RATE_22050 535 * - AFE_PORT_SAMPLE_RATE_24K 536 * - AFE_PORT_SAMPLE_RATE_32K 537 * - AFE_PORT_SAMPLE_RATE_44P1K 538 * - AFE_PORT_SAMPLE_RATE_48K 539 * - AFE_PORT_SAMPLE_RATE_96K 540 * - AFE_PORT_SAMPLE_RATE_192K 541 */ 542 u32 sample_rate; 543 /* Bit width of the sample. 544 * Supported values: 16, 24 545 */ 546 u16 bit_width; 547 /* Number of channels. 548 * Supported values: 1 and 2 549 */ 550 u16 num_channels; 551 /* Data format supported by the USB. The supported value is 552 * 0 (#AFE_USB_AUDIO_DATA_FORMAT_LINEAR_PCM). 553 */ 554 u16 data_format; 555 /* this field must be 0 */ 556 u16 reserved; 557 /* device token of actual end USB audio device */ 558 u32 dev_token; 559 /* endianness of this interface */ 560 u32 endian; 561 /* service interval */ 562 u32 service_interval; 563 } __packed; 564 565 /** 566 * struct afe_param_id_usb_audio_dev_params 567 * @cfg_minor_version: Minor version used for tracking USB audio device 568 * configuration. 569 * Supported values: 570 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 571 * @dev_token: device token of actual end USB audio device 572 **/ 573 struct afe_param_id_usb_audio_dev_params { 574 u32 cfg_minor_version; 575 u32 dev_token; 576 } __packed; 577 578 /** 579 * struct afe_param_id_usb_audio_dev_lpcm_fmt 580 * @cfg_minor_version: Minor version used for tracking USB audio device 581 * configuration. 582 * Supported values: 583 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 584 * @endian: endianness of this interface 585 **/ 586 struct afe_param_id_usb_audio_dev_lpcm_fmt { 587 u32 cfg_minor_version; 588 u32 endian; 589 } __packed; 590 591 #define AFE_PARAM_ID_USB_AUDIO_SVC_INTERVAL 0x000102B7 592 593 /** 594 * struct afe_param_id_usb_audio_svc_interval 595 * @cfg_minor_version: Minor version used for tracking USB audio device 596 * configuration. 597 * Supported values: 598 * AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG 599 * @svc_interval: service interval 600 **/ 601 struct afe_param_id_usb_audio_svc_interval { 602 u32 cfg_minor_version; 603 u32 svc_interval; 604 } __packed; 605 606 union afe_port_config { 607 struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch; 608 struct afe_param_id_slimbus_cfg slim_cfg; 609 struct afe_param_id_i2s_cfg i2s_cfg; 610 struct afe_param_id_tdm_cfg tdm_cfg; 611 struct afe_param_id_cdc_dma_cfg dma_cfg; 612 struct afe_param_id_usb_cfg usb_cfg; 613 } __packed; 614 615 616 struct afe_clk_set { 617 uint32_t clk_set_minor_version; 618 uint32_t clk_id; 619 uint32_t clk_freq_in_hz; 620 uint16_t clk_attri; 621 uint16_t clk_root; 622 uint32_t enable; 623 }; 624 625 struct afe_param_id_slot_mapping_cfg { 626 u32 minor_version; 627 u16 num_channels; 628 u16 bitwidth; 629 u32 data_align_type; 630 u16 ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; 631 } __packed; 632 633 struct q6afe_port { 634 wait_queue_head_t wait; 635 union afe_port_config port_cfg; 636 struct afe_param_id_slot_mapping_cfg *scfg; 637 struct aprv2_ibasic_rsp_result_t result; 638 int token; 639 int id; 640 int cfg_type; 641 struct q6afe *afe; 642 struct kref refcount; 643 struct list_head node; 644 }; 645 646 struct afe_cmd_remote_lpass_core_hw_vote_request { 647 uint32_t hw_block_id; 648 char client_name[8]; 649 } __packed; 650 651 struct afe_cmd_remote_lpass_core_hw_devote_request { 652 uint32_t hw_block_id; 653 uint32_t client_handle; 654 } __packed; 655 656 657 658 struct afe_port_map { 659 int port_id; 660 int token; 661 int is_rx; 662 int is_dig_pcm; 663 }; 664 665 /* 666 * Mapping between Virtual Port IDs to DSP AFE Port ID 667 * On B Family SoCs DSP Port IDs are consistent across multiple SoCs 668 * on A Family SoCs DSP port IDs are same as virtual Port IDs. 669 */ 670 671 static struct afe_port_map port_maps[AFE_PORT_MAX] = { 672 [HDMI_RX] = { AFE_PORT_ID_MULTICHAN_HDMI_RX, HDMI_RX, 1, 1}, 673 [SLIMBUS_0_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX, 674 SLIMBUS_0_RX, 1, 1}, 675 [SLIMBUS_1_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX, 676 SLIMBUS_1_RX, 1, 1}, 677 [SLIMBUS_2_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX, 678 SLIMBUS_2_RX, 1, 1}, 679 [SLIMBUS_3_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX, 680 SLIMBUS_3_RX, 1, 1}, 681 [SLIMBUS_4_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX, 682 SLIMBUS_4_RX, 1, 1}, 683 [SLIMBUS_5_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX, 684 SLIMBUS_5_RX, 1, 1}, 685 [SLIMBUS_6_RX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX, 686 SLIMBUS_6_RX, 1, 1}, 687 [SLIMBUS_0_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX, 688 SLIMBUS_0_TX, 0, 1}, 689 [SLIMBUS_1_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX, 690 SLIMBUS_1_TX, 0, 1}, 691 [SLIMBUS_2_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX, 692 SLIMBUS_2_TX, 0, 1}, 693 [SLIMBUS_3_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX, 694 SLIMBUS_3_TX, 0, 1}, 695 [SLIMBUS_4_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX, 696 SLIMBUS_4_TX, 0, 1}, 697 [SLIMBUS_5_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX, 698 SLIMBUS_5_TX, 0, 1}, 699 [SLIMBUS_6_TX] = { AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX, 700 SLIMBUS_6_TX, 0, 1}, 701 [PRIMARY_MI2S_RX] = { AFE_PORT_ID_PRIMARY_MI2S_RX, 702 PRIMARY_MI2S_RX, 1, 1}, 703 [PRIMARY_MI2S_TX] = { AFE_PORT_ID_PRIMARY_MI2S_TX, 704 PRIMARY_MI2S_RX, 0, 1}, 705 [SECONDARY_MI2S_RX] = { AFE_PORT_ID_SECONDARY_MI2S_RX, 706 SECONDARY_MI2S_RX, 1, 1}, 707 [SECONDARY_MI2S_TX] = { AFE_PORT_ID_SECONDARY_MI2S_TX, 708 SECONDARY_MI2S_TX, 0, 1}, 709 [TERTIARY_MI2S_RX] = { AFE_PORT_ID_TERTIARY_MI2S_RX, 710 TERTIARY_MI2S_RX, 1, 1}, 711 [TERTIARY_MI2S_TX] = { AFE_PORT_ID_TERTIARY_MI2S_TX, 712 TERTIARY_MI2S_TX, 0, 1}, 713 [QUATERNARY_MI2S_RX] = { AFE_PORT_ID_QUATERNARY_MI2S_RX, 714 QUATERNARY_MI2S_RX, 1, 1}, 715 [QUATERNARY_MI2S_TX] = { AFE_PORT_ID_QUATERNARY_MI2S_TX, 716 QUATERNARY_MI2S_TX, 0, 1}, 717 [QUINARY_MI2S_RX] = { AFE_PORT_ID_QUINARY_MI2S_RX, 718 QUINARY_MI2S_RX, 1, 1}, 719 [QUINARY_MI2S_TX] = { AFE_PORT_ID_QUINARY_MI2S_TX, 720 QUINARY_MI2S_TX, 0, 1}, 721 [PRIMARY_TDM_RX_0] = { AFE_PORT_ID_PRIMARY_TDM_RX, 722 PRIMARY_TDM_RX_0, 1, 1}, 723 [PRIMARY_TDM_TX_0] = { AFE_PORT_ID_PRIMARY_TDM_TX, 724 PRIMARY_TDM_TX_0, 0, 1}, 725 [PRIMARY_TDM_RX_1] = { AFE_PORT_ID_PRIMARY_TDM_RX_1, 726 PRIMARY_TDM_RX_1, 1, 1}, 727 [PRIMARY_TDM_TX_1] = { AFE_PORT_ID_PRIMARY_TDM_TX_1, 728 PRIMARY_TDM_TX_1, 0, 1}, 729 [PRIMARY_TDM_RX_2] = { AFE_PORT_ID_PRIMARY_TDM_RX_2, 730 PRIMARY_TDM_RX_2, 1, 1}, 731 [PRIMARY_TDM_TX_2] = { AFE_PORT_ID_PRIMARY_TDM_TX_2, 732 PRIMARY_TDM_TX_2, 0, 1}, 733 [PRIMARY_TDM_RX_3] = { AFE_PORT_ID_PRIMARY_TDM_RX_3, 734 PRIMARY_TDM_RX_3, 1, 1}, 735 [PRIMARY_TDM_TX_3] = { AFE_PORT_ID_PRIMARY_TDM_TX_3, 736 PRIMARY_TDM_TX_3, 0, 1}, 737 [PRIMARY_TDM_RX_4] = { AFE_PORT_ID_PRIMARY_TDM_RX_4, 738 PRIMARY_TDM_RX_4, 1, 1}, 739 [PRIMARY_TDM_TX_4] = { AFE_PORT_ID_PRIMARY_TDM_TX_4, 740 PRIMARY_TDM_TX_4, 0, 1}, 741 [PRIMARY_TDM_RX_5] = { AFE_PORT_ID_PRIMARY_TDM_RX_5, 742 PRIMARY_TDM_RX_5, 1, 1}, 743 [PRIMARY_TDM_TX_5] = { AFE_PORT_ID_PRIMARY_TDM_TX_5, 744 PRIMARY_TDM_TX_5, 0, 1}, 745 [PRIMARY_TDM_RX_6] = { AFE_PORT_ID_PRIMARY_TDM_RX_6, 746 PRIMARY_TDM_RX_6, 1, 1}, 747 [PRIMARY_TDM_TX_6] = { AFE_PORT_ID_PRIMARY_TDM_TX_6, 748 PRIMARY_TDM_TX_6, 0, 1}, 749 [PRIMARY_TDM_RX_7] = { AFE_PORT_ID_PRIMARY_TDM_RX_7, 750 PRIMARY_TDM_RX_7, 1, 1}, 751 [PRIMARY_TDM_TX_7] = { AFE_PORT_ID_PRIMARY_TDM_TX_7, 752 PRIMARY_TDM_TX_7, 0, 1}, 753 [SECONDARY_TDM_RX_0] = { AFE_PORT_ID_SECONDARY_TDM_RX, 754 SECONDARY_TDM_RX_0, 1, 1}, 755 [SECONDARY_TDM_TX_0] = { AFE_PORT_ID_SECONDARY_TDM_TX, 756 SECONDARY_TDM_TX_0, 0, 1}, 757 [SECONDARY_TDM_RX_1] = { AFE_PORT_ID_SECONDARY_TDM_RX_1, 758 SECONDARY_TDM_RX_1, 1, 1}, 759 [SECONDARY_TDM_TX_1] = { AFE_PORT_ID_SECONDARY_TDM_TX_1, 760 SECONDARY_TDM_TX_1, 0, 1}, 761 [SECONDARY_TDM_RX_2] = { AFE_PORT_ID_SECONDARY_TDM_RX_2, 762 SECONDARY_TDM_RX_2, 1, 1}, 763 [SECONDARY_TDM_TX_2] = { AFE_PORT_ID_SECONDARY_TDM_TX_2, 764 SECONDARY_TDM_TX_2, 0, 1}, 765 [SECONDARY_TDM_RX_3] = { AFE_PORT_ID_SECONDARY_TDM_RX_3, 766 SECONDARY_TDM_RX_3, 1, 1}, 767 [SECONDARY_TDM_TX_3] = { AFE_PORT_ID_SECONDARY_TDM_TX_3, 768 SECONDARY_TDM_TX_3, 0, 1}, 769 [SECONDARY_TDM_RX_4] = { AFE_PORT_ID_SECONDARY_TDM_RX_4, 770 SECONDARY_TDM_RX_4, 1, 1}, 771 [SECONDARY_TDM_TX_4] = { AFE_PORT_ID_SECONDARY_TDM_TX_4, 772 SECONDARY_TDM_TX_4, 0, 1}, 773 [SECONDARY_TDM_RX_5] = { AFE_PORT_ID_SECONDARY_TDM_RX_5, 774 SECONDARY_TDM_RX_5, 1, 1}, 775 [SECONDARY_TDM_TX_5] = { AFE_PORT_ID_SECONDARY_TDM_TX_5, 776 SECONDARY_TDM_TX_5, 0, 1}, 777 [SECONDARY_TDM_RX_6] = { AFE_PORT_ID_SECONDARY_TDM_RX_6, 778 SECONDARY_TDM_RX_6, 1, 1}, 779 [SECONDARY_TDM_TX_6] = { AFE_PORT_ID_SECONDARY_TDM_TX_6, 780 SECONDARY_TDM_TX_6, 0, 1}, 781 [SECONDARY_TDM_RX_7] = { AFE_PORT_ID_SECONDARY_TDM_RX_7, 782 SECONDARY_TDM_RX_7, 1, 1}, 783 [SECONDARY_TDM_TX_7] = { AFE_PORT_ID_SECONDARY_TDM_TX_7, 784 SECONDARY_TDM_TX_7, 0, 1}, 785 [TERTIARY_TDM_RX_0] = { AFE_PORT_ID_TERTIARY_TDM_RX, 786 TERTIARY_TDM_RX_0, 1, 1}, 787 [TERTIARY_TDM_TX_0] = { AFE_PORT_ID_TERTIARY_TDM_TX, 788 TERTIARY_TDM_TX_0, 0, 1}, 789 [TERTIARY_TDM_RX_1] = { AFE_PORT_ID_TERTIARY_TDM_RX_1, 790 TERTIARY_TDM_RX_1, 1, 1}, 791 [TERTIARY_TDM_TX_1] = { AFE_PORT_ID_TERTIARY_TDM_TX_1, 792 TERTIARY_TDM_TX_1, 0, 1}, 793 [TERTIARY_TDM_RX_2] = { AFE_PORT_ID_TERTIARY_TDM_RX_2, 794 TERTIARY_TDM_RX_2, 1, 1}, 795 [TERTIARY_TDM_TX_2] = { AFE_PORT_ID_TERTIARY_TDM_TX_2, 796 TERTIARY_TDM_TX_2, 0, 1}, 797 [TERTIARY_TDM_RX_3] = { AFE_PORT_ID_TERTIARY_TDM_RX_3, 798 TERTIARY_TDM_RX_3, 1, 1}, 799 [TERTIARY_TDM_TX_3] = { AFE_PORT_ID_TERTIARY_TDM_TX_3, 800 TERTIARY_TDM_TX_3, 0, 1}, 801 [TERTIARY_TDM_RX_4] = { AFE_PORT_ID_TERTIARY_TDM_RX_4, 802 TERTIARY_TDM_RX_4, 1, 1}, 803 [TERTIARY_TDM_TX_4] = { AFE_PORT_ID_TERTIARY_TDM_TX_4, 804 TERTIARY_TDM_TX_4, 0, 1}, 805 [TERTIARY_TDM_RX_5] = { AFE_PORT_ID_TERTIARY_TDM_RX_5, 806 TERTIARY_TDM_RX_5, 1, 1}, 807 [TERTIARY_TDM_TX_5] = { AFE_PORT_ID_TERTIARY_TDM_TX_5, 808 TERTIARY_TDM_TX_5, 0, 1}, 809 [TERTIARY_TDM_RX_6] = { AFE_PORT_ID_TERTIARY_TDM_RX_6, 810 TERTIARY_TDM_RX_6, 1, 1}, 811 [TERTIARY_TDM_TX_6] = { AFE_PORT_ID_TERTIARY_TDM_TX_6, 812 TERTIARY_TDM_TX_6, 0, 1}, 813 [TERTIARY_TDM_RX_7] = { AFE_PORT_ID_TERTIARY_TDM_RX_7, 814 TERTIARY_TDM_RX_7, 1, 1}, 815 [TERTIARY_TDM_TX_7] = { AFE_PORT_ID_TERTIARY_TDM_TX_7, 816 TERTIARY_TDM_TX_7, 0, 1}, 817 [QUATERNARY_TDM_RX_0] = { AFE_PORT_ID_QUATERNARY_TDM_RX, 818 QUATERNARY_TDM_RX_0, 1, 1}, 819 [QUATERNARY_TDM_TX_0] = { AFE_PORT_ID_QUATERNARY_TDM_TX, 820 QUATERNARY_TDM_TX_0, 0, 1}, 821 [QUATERNARY_TDM_RX_1] = { AFE_PORT_ID_QUATERNARY_TDM_RX_1, 822 QUATERNARY_TDM_RX_1, 1, 1}, 823 [QUATERNARY_TDM_TX_1] = { AFE_PORT_ID_QUATERNARY_TDM_TX_1, 824 QUATERNARY_TDM_TX_1, 0, 1}, 825 [QUATERNARY_TDM_RX_2] = { AFE_PORT_ID_QUATERNARY_TDM_RX_2, 826 QUATERNARY_TDM_RX_2, 1, 1}, 827 [QUATERNARY_TDM_TX_2] = { AFE_PORT_ID_QUATERNARY_TDM_TX_2, 828 QUATERNARY_TDM_TX_2, 0, 1}, 829 [QUATERNARY_TDM_RX_3] = { AFE_PORT_ID_QUATERNARY_TDM_RX_3, 830 QUATERNARY_TDM_RX_3, 1, 1}, 831 [QUATERNARY_TDM_TX_3] = { AFE_PORT_ID_QUATERNARY_TDM_TX_3, 832 QUATERNARY_TDM_TX_3, 0, 1}, 833 [QUATERNARY_TDM_RX_4] = { AFE_PORT_ID_QUATERNARY_TDM_RX_4, 834 QUATERNARY_TDM_RX_4, 1, 1}, 835 [QUATERNARY_TDM_TX_4] = { AFE_PORT_ID_QUATERNARY_TDM_TX_4, 836 QUATERNARY_TDM_TX_4, 0, 1}, 837 [QUATERNARY_TDM_RX_5] = { AFE_PORT_ID_QUATERNARY_TDM_RX_5, 838 QUATERNARY_TDM_RX_5, 1, 1}, 839 [QUATERNARY_TDM_TX_5] = { AFE_PORT_ID_QUATERNARY_TDM_TX_5, 840 QUATERNARY_TDM_TX_5, 0, 1}, 841 [QUATERNARY_TDM_RX_6] = { AFE_PORT_ID_QUATERNARY_TDM_RX_6, 842 QUATERNARY_TDM_RX_6, 1, 1}, 843 [QUATERNARY_TDM_TX_6] = { AFE_PORT_ID_QUATERNARY_TDM_TX_6, 844 QUATERNARY_TDM_TX_6, 0, 1}, 845 [QUATERNARY_TDM_RX_7] = { AFE_PORT_ID_QUATERNARY_TDM_RX_7, 846 QUATERNARY_TDM_RX_7, 1, 1}, 847 [QUATERNARY_TDM_TX_7] = { AFE_PORT_ID_QUATERNARY_TDM_TX_7, 848 QUATERNARY_TDM_TX_7, 0, 1}, 849 [QUINARY_TDM_RX_0] = { AFE_PORT_ID_QUINARY_TDM_RX, 850 QUINARY_TDM_RX_0, 1, 1}, 851 [QUINARY_TDM_TX_0] = { AFE_PORT_ID_QUINARY_TDM_TX, 852 QUINARY_TDM_TX_0, 0, 1}, 853 [QUINARY_TDM_RX_1] = { AFE_PORT_ID_QUINARY_TDM_RX_1, 854 QUINARY_TDM_RX_1, 1, 1}, 855 [QUINARY_TDM_TX_1] = { AFE_PORT_ID_QUINARY_TDM_TX_1, 856 QUINARY_TDM_TX_1, 0, 1}, 857 [QUINARY_TDM_RX_2] = { AFE_PORT_ID_QUINARY_TDM_RX_2, 858 QUINARY_TDM_RX_2, 1, 1}, 859 [QUINARY_TDM_TX_2] = { AFE_PORT_ID_QUINARY_TDM_TX_2, 860 QUINARY_TDM_TX_2, 0, 1}, 861 [QUINARY_TDM_RX_3] = { AFE_PORT_ID_QUINARY_TDM_RX_3, 862 QUINARY_TDM_RX_3, 1, 1}, 863 [QUINARY_TDM_TX_3] = { AFE_PORT_ID_QUINARY_TDM_TX_3, 864 QUINARY_TDM_TX_3, 0, 1}, 865 [QUINARY_TDM_RX_4] = { AFE_PORT_ID_QUINARY_TDM_RX_4, 866 QUINARY_TDM_RX_4, 1, 1}, 867 [QUINARY_TDM_TX_4] = { AFE_PORT_ID_QUINARY_TDM_TX_4, 868 QUINARY_TDM_TX_4, 0, 1}, 869 [QUINARY_TDM_RX_5] = { AFE_PORT_ID_QUINARY_TDM_RX_5, 870 QUINARY_TDM_RX_5, 1, 1}, 871 [QUINARY_TDM_TX_5] = { AFE_PORT_ID_QUINARY_TDM_TX_5, 872 QUINARY_TDM_TX_5, 0, 1}, 873 [QUINARY_TDM_RX_6] = { AFE_PORT_ID_QUINARY_TDM_RX_6, 874 QUINARY_TDM_RX_6, 1, 1}, 875 [QUINARY_TDM_TX_6] = { AFE_PORT_ID_QUINARY_TDM_TX_6, 876 QUINARY_TDM_TX_6, 0, 1}, 877 [QUINARY_TDM_RX_7] = { AFE_PORT_ID_QUINARY_TDM_RX_7, 878 QUINARY_TDM_RX_7, 1, 1}, 879 [QUINARY_TDM_TX_7] = { AFE_PORT_ID_QUINARY_TDM_TX_7, 880 QUINARY_TDM_TX_7, 0, 1}, 881 [DISPLAY_PORT_RX] = { AFE_PORT_ID_HDMI_OVER_DP_RX, 882 DISPLAY_PORT_RX, 1, 1}, 883 [WSA_CODEC_DMA_RX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_0, 884 WSA_CODEC_DMA_RX_0, 1, 1}, 885 [WSA_CODEC_DMA_TX_0] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_0, 886 WSA_CODEC_DMA_TX_0, 0, 1}, 887 [WSA_CODEC_DMA_RX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_RX_1, 888 WSA_CODEC_DMA_RX_1, 1, 1}, 889 [WSA_CODEC_DMA_TX_1] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_1, 890 WSA_CODEC_DMA_TX_1, 0, 1}, 891 [WSA_CODEC_DMA_TX_2] = { AFE_PORT_ID_WSA_CODEC_DMA_TX_2, 892 WSA_CODEC_DMA_TX_2, 0, 1}, 893 [VA_CODEC_DMA_TX_0] = { AFE_PORT_ID_VA_CODEC_DMA_TX_0, 894 VA_CODEC_DMA_TX_0, 0, 1}, 895 [VA_CODEC_DMA_TX_1] = { AFE_PORT_ID_VA_CODEC_DMA_TX_1, 896 VA_CODEC_DMA_TX_1, 0, 1}, 897 [VA_CODEC_DMA_TX_2] = { AFE_PORT_ID_VA_CODEC_DMA_TX_2, 898 VA_CODEC_DMA_TX_2, 0, 1}, 899 [RX_CODEC_DMA_RX_0] = { AFE_PORT_ID_RX_CODEC_DMA_RX_0, 900 RX_CODEC_DMA_RX_0, 1, 1}, 901 [TX_CODEC_DMA_TX_0] = { AFE_PORT_ID_TX_CODEC_DMA_TX_0, 902 TX_CODEC_DMA_TX_0, 0, 1}, 903 [RX_CODEC_DMA_RX_1] = { AFE_PORT_ID_RX_CODEC_DMA_RX_1, 904 RX_CODEC_DMA_RX_1, 1, 1}, 905 [TX_CODEC_DMA_TX_1] = { AFE_PORT_ID_TX_CODEC_DMA_TX_1, 906 TX_CODEC_DMA_TX_1, 0, 1}, 907 [RX_CODEC_DMA_RX_2] = { AFE_PORT_ID_RX_CODEC_DMA_RX_2, 908 RX_CODEC_DMA_RX_2, 1, 1}, 909 [TX_CODEC_DMA_TX_2] = { AFE_PORT_ID_TX_CODEC_DMA_TX_2, 910 TX_CODEC_DMA_TX_2, 0, 1}, 911 [RX_CODEC_DMA_RX_3] = { AFE_PORT_ID_RX_CODEC_DMA_RX_3, 912 RX_CODEC_DMA_RX_3, 1, 1}, 913 [TX_CODEC_DMA_TX_3] = { AFE_PORT_ID_TX_CODEC_DMA_TX_3, 914 TX_CODEC_DMA_TX_3, 0, 1}, 915 [RX_CODEC_DMA_RX_4] = { AFE_PORT_ID_RX_CODEC_DMA_RX_4, 916 RX_CODEC_DMA_RX_4, 1, 1}, 917 [TX_CODEC_DMA_TX_4] = { AFE_PORT_ID_TX_CODEC_DMA_TX_4, 918 TX_CODEC_DMA_TX_4, 0, 1}, 919 [RX_CODEC_DMA_RX_5] = { AFE_PORT_ID_RX_CODEC_DMA_RX_5, 920 RX_CODEC_DMA_RX_5, 1, 1}, 921 [TX_CODEC_DMA_TX_5] = { AFE_PORT_ID_TX_CODEC_DMA_TX_5, 922 TX_CODEC_DMA_TX_5, 0, 1}, 923 [RX_CODEC_DMA_RX_6] = { AFE_PORT_ID_RX_CODEC_DMA_RX_6, 924 RX_CODEC_DMA_RX_6, 1, 1}, 925 [RX_CODEC_DMA_RX_7] = { AFE_PORT_ID_RX_CODEC_DMA_RX_7, 926 RX_CODEC_DMA_RX_7, 1, 1}, 927 [USB_RX] = { AFE_PORT_ID_USB_RX, USB_RX, 1, 1}, 928 }; 929 930 static void q6afe_port_free(struct kref *ref) 931 { 932 struct q6afe_port *port; 933 struct q6afe *afe; 934 unsigned long flags; 935 936 port = container_of(ref, struct q6afe_port, refcount); 937 afe = port->afe; 938 spin_lock_irqsave(&afe->port_list_lock, flags); 939 list_del(&port->node); 940 spin_unlock_irqrestore(&afe->port_list_lock, flags); 941 kfree(port->scfg); 942 kfree(port); 943 } 944 945 static struct q6afe_port *q6afe_find_port(struct q6afe *afe, int token) 946 { 947 struct q6afe_port *p; 948 struct q6afe_port *ret = NULL; 949 950 guard(spinlock)(&afe->port_list_lock); 951 list_for_each_entry(p, &afe->port_list, node) 952 if (p->token == token) { 953 ret = p; 954 kref_get(&p->refcount); 955 break; 956 } 957 958 return ret; 959 } 960 961 static int q6afe_callback(struct apr_device *adev, struct apr_resp_pkt *data) 962 { 963 struct q6afe *afe = dev_get_drvdata(&adev->dev); 964 struct aprv2_ibasic_rsp_result_t *res; 965 struct apr_hdr *hdr = &data->hdr; 966 struct q6afe_port *port; 967 968 if (!data->payload_size) 969 return 0; 970 971 res = data->payload; 972 switch (hdr->opcode) { 973 case APR_BASIC_RSP_RESULT: { 974 if (res->status) { 975 dev_err(afe->dev, "cmd = 0x%x returned error = 0x%x\n", 976 res->opcode, res->status); 977 } 978 switch (res->opcode) { 979 case AFE_PORT_CMD_SET_PARAM_V2: 980 case AFE_PORT_CMD_DEVICE_STOP: 981 case AFE_PORT_CMD_DEVICE_START: 982 case AFE_SVC_CMD_SET_PARAM: 983 port = q6afe_find_port(afe, hdr->token); 984 if (port) { 985 port->result = *res; 986 wake_up(&port->wait); 987 kref_put(&port->refcount, q6afe_port_free); 988 } else if (hdr->token == AFE_CLK_TOKEN) { 989 afe->result = *res; 990 wake_up(&afe->wait); 991 } 992 break; 993 default: 994 dev_err(afe->dev, "Unknown cmd 0x%x\n", res->opcode); 995 break; 996 } 997 } 998 break; 999 case AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST: 1000 afe->result.opcode = hdr->opcode; 1001 afe->result.status = res->status; 1002 wake_up(&afe->wait); 1003 break; 1004 default: 1005 break; 1006 } 1007 1008 return 0; 1009 } 1010 1011 /** 1012 * q6afe_get_port_id() - Get port id from a given port index 1013 * 1014 * @index: port index 1015 * 1016 * Return: Will be an negative on error or valid port_id on success 1017 */ 1018 int q6afe_get_port_id(int index) 1019 { 1020 if (index < 0 || index >= AFE_PORT_MAX) 1021 return -EINVAL; 1022 1023 return port_maps[index].port_id; 1024 } 1025 EXPORT_SYMBOL_GPL(q6afe_get_port_id); 1026 1027 static int afe_apr_send_pkt(struct q6afe *afe, struct apr_pkt *pkt, 1028 struct q6afe_port *port, uint32_t rsp_opcode) 1029 { 1030 wait_queue_head_t *wait; 1031 struct aprv2_ibasic_rsp_result_t *result; 1032 int ret; 1033 1034 mutex_lock(&afe->lock); 1035 if (port) { 1036 wait = &port->wait; 1037 result = &port->result; 1038 } else { 1039 result = &afe->result; 1040 wait = &afe->wait; 1041 } 1042 1043 result->opcode = 0; 1044 result->status = 0; 1045 1046 ret = apr_send_pkt(afe->apr, pkt); 1047 if (ret < 0) { 1048 dev_err(afe->dev, "packet not transmitted (%d)\n", ret); 1049 ret = -EINVAL; 1050 goto err; 1051 } 1052 1053 ret = wait_event_timeout(*wait, (result->opcode == rsp_opcode), 1054 msecs_to_jiffies(TIMEOUT_MS)); 1055 if (!ret) { 1056 ret = -ETIMEDOUT; 1057 } else if (result->status > 0) { 1058 dev_err(afe->dev, "DSP returned error[%x]\n", 1059 result->status); 1060 ret = -EINVAL; 1061 } else { 1062 ret = 0; 1063 } 1064 1065 err: 1066 mutex_unlock(&afe->lock); 1067 1068 return ret; 1069 } 1070 1071 static int q6afe_set_param(struct q6afe *afe, struct q6afe_port *port, 1072 void *data, int param_id, int module_id, int psize, 1073 int token) 1074 { 1075 struct afe_svc_cmd_set_param *param; 1076 struct afe_port_param_data_v2 *pdata; 1077 struct apr_pkt *pkt; 1078 int ret, pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; 1079 void *pl; 1080 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1081 if (!p) 1082 return -ENOMEM; 1083 1084 pkt = p; 1085 param = p + APR_HDR_SIZE; 1086 pdata = p + APR_HDR_SIZE + sizeof(*param); 1087 pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); 1088 memcpy(pl, data, psize); 1089 1090 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1091 APR_HDR_LEN(APR_HDR_SIZE), 1092 APR_PKT_VER); 1093 pkt->hdr.pkt_size = pkt_size; 1094 pkt->hdr.src_port = 0; 1095 pkt->hdr.dest_port = 0; 1096 pkt->hdr.token = token; 1097 pkt->hdr.opcode = AFE_SVC_CMD_SET_PARAM; 1098 1099 param->payload_size = sizeof(*pdata) + psize; 1100 param->payload_address_lsw = 0x00; 1101 param->payload_address_msw = 0x00; 1102 param->mem_map_handle = 0x00; 1103 pdata->module_id = module_id; 1104 pdata->param_id = param_id; 1105 pdata->param_size = psize; 1106 1107 ret = afe_apr_send_pkt(afe, pkt, port, AFE_SVC_CMD_SET_PARAM); 1108 if (ret) 1109 dev_err(afe->dev, "AFE set params failed %d\n", ret); 1110 1111 return ret; 1112 } 1113 1114 static int q6afe_port_set_param(struct q6afe_port *port, void *data, 1115 int param_id, int module_id, int psize) 1116 { 1117 return q6afe_set_param(port->afe, port, data, param_id, module_id, 1118 psize, port->token); 1119 } 1120 1121 static int q6afe_port_set_param_v2(struct q6afe_port *port, void *data, 1122 int param_id, int module_id, int psize) 1123 { 1124 struct afe_port_cmd_set_param_v2 *param; 1125 struct afe_port_param_data_v2 *pdata; 1126 struct q6afe *afe = port->afe; 1127 struct apr_pkt *pkt; 1128 u16 port_id = port->id; 1129 int ret, pkt_size = APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata) + psize; 1130 void *pl; 1131 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1132 if (!p) 1133 return -ENOMEM; 1134 1135 pkt = p; 1136 param = p + APR_HDR_SIZE; 1137 pdata = p + APR_HDR_SIZE + sizeof(*param); 1138 pl = p + APR_HDR_SIZE + sizeof(*param) + sizeof(*pdata); 1139 memcpy(pl, data, psize); 1140 1141 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1142 APR_HDR_LEN(APR_HDR_SIZE), 1143 APR_PKT_VER); 1144 pkt->hdr.pkt_size = pkt_size; 1145 pkt->hdr.src_port = 0; 1146 pkt->hdr.dest_port = 0; 1147 pkt->hdr.token = port->token; 1148 pkt->hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2; 1149 1150 param->port_id = port_id; 1151 param->payload_size = sizeof(*pdata) + psize; 1152 param->payload_address_lsw = 0x00; 1153 param->payload_address_msw = 0x00; 1154 param->mem_map_handle = 0x00; 1155 pdata->module_id = module_id; 1156 pdata->param_id = param_id; 1157 pdata->param_size = psize; 1158 1159 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_SET_PARAM_V2); 1160 if (ret) 1161 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1162 port_id, ret); 1163 1164 return ret; 1165 } 1166 1167 static int q6afe_port_set_lpass_clock(struct q6afe_port *port, 1168 struct afe_clk_cfg *cfg) 1169 { 1170 return q6afe_port_set_param_v2(port, cfg, 1171 AFE_PARAM_ID_LPAIF_CLK_CONFIG, 1172 AFE_MODULE_AUDIO_DEV_INTERFACE, 1173 sizeof(*cfg)); 1174 } 1175 1176 static int q6afe_set_lpass_clock_v2(struct q6afe_port *port, 1177 struct afe_clk_set *cfg) 1178 { 1179 return q6afe_port_set_param(port, cfg, AFE_PARAM_ID_CLOCK_SET, 1180 AFE_MODULE_CLOCK_SET, sizeof(*cfg)); 1181 } 1182 1183 static int q6afe_set_digital_codec_core_clock(struct q6afe_port *port, 1184 struct afe_digital_clk_cfg *cfg) 1185 { 1186 return q6afe_port_set_param_v2(port, cfg, 1187 AFE_PARAM_ID_INT_DIGITAL_CDC_CLK_CONFIG, 1188 AFE_MODULE_AUDIO_DEV_INTERFACE, 1189 sizeof(*cfg)); 1190 } 1191 1192 int q6afe_set_lpass_clock(struct device *dev, int clk_id, int attri, 1193 int clk_root, unsigned int freq) 1194 { 1195 struct q6afe *afe = dev_get_drvdata(dev->parent); 1196 struct afe_clk_set cset = {0,}; 1197 1198 cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; 1199 cset.clk_id = clk_id; 1200 cset.clk_freq_in_hz = freq; 1201 cset.clk_attri = attri; 1202 cset.clk_root = clk_root; 1203 cset.enable = !!freq; 1204 1205 return q6afe_set_param(afe, NULL, &cset, AFE_PARAM_ID_CLOCK_SET, 1206 AFE_MODULE_CLOCK_SET, sizeof(cset), 1207 AFE_CLK_TOKEN); 1208 } 1209 EXPORT_SYMBOL_GPL(q6afe_set_lpass_clock); 1210 1211 int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, 1212 int clk_src, int clk_root, 1213 unsigned int freq, int dir) 1214 { 1215 struct afe_clk_cfg ccfg = {0,}; 1216 struct afe_clk_set cset = {0,}; 1217 struct afe_digital_clk_cfg dcfg = {0,}; 1218 int ret; 1219 1220 switch (clk_id) { 1221 case LPAIF_DIG_CLK: 1222 dcfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1223 dcfg.clk_val = freq; 1224 dcfg.clk_root = clk_root; 1225 ret = q6afe_set_digital_codec_core_clock(port, &dcfg); 1226 break; 1227 case LPAIF_BIT_CLK: 1228 ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1229 ccfg.clk_val1 = freq; 1230 ccfg.clk_src = clk_src; 1231 ccfg.clk_root = clk_root; 1232 ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK1_VALID; 1233 ret = q6afe_port_set_lpass_clock(port, &ccfg); 1234 break; 1235 1236 case LPAIF_OSR_CLK: 1237 ccfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1238 ccfg.clk_val2 = freq; 1239 ccfg.clk_src = clk_src; 1240 ccfg.clk_root = clk_root; 1241 ccfg.clk_set_mode = Q6AFE_LPASS_MODE_CLK2_VALID; 1242 ret = q6afe_port_set_lpass_clock(port, &ccfg); 1243 break; 1244 case Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT ... Q6AFE_LPASS_CLK_ID_QUI_MI2S_OSR: 1245 case Q6AFE_LPASS_CLK_ID_MCLK_1 ... Q6AFE_LPASS_CLK_ID_INT_MCLK_1: 1246 case Q6AFE_LPASS_CLK_ID_PRI_TDM_IBIT ... Q6AFE_LPASS_CLK_ID_QUIN_TDM_EBIT: 1247 case Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK ... Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK: 1248 cset.clk_set_minor_version = AFE_API_VERSION_CLOCK_SET; 1249 cset.clk_id = clk_id; 1250 cset.clk_freq_in_hz = freq; 1251 cset.clk_attri = clk_src; 1252 cset.clk_root = clk_root; 1253 cset.enable = !!freq; 1254 ret = q6afe_set_lpass_clock_v2(port, &cset); 1255 break; 1256 default: 1257 ret = -EINVAL; 1258 break; 1259 } 1260 1261 return ret; 1262 } 1263 EXPORT_SYMBOL_GPL(q6afe_port_set_sysclk); 1264 1265 /** 1266 * q6afe_port_stop() - Stop a afe port 1267 * 1268 * @port: Instance of port to stop 1269 * 1270 * Return: Will be an negative on packet size on success. 1271 */ 1272 int q6afe_port_stop(struct q6afe_port *port) 1273 { 1274 struct afe_port_cmd_device_stop *stop; 1275 struct q6afe *afe = port->afe; 1276 struct apr_pkt *pkt; 1277 int port_id = port->id; 1278 int ret = 0; 1279 int index, pkt_size; 1280 void *p __free(kfree) = NULL; 1281 1282 index = port->token; 1283 if (index < 0 || index >= AFE_PORT_MAX) { 1284 dev_err(afe->dev, "AFE port index[%d] invalid!\n", index); 1285 return -EINVAL; 1286 } 1287 1288 pkt_size = APR_HDR_SIZE + sizeof(*stop); 1289 p = kzalloc(pkt_size, GFP_KERNEL); 1290 if (!p) 1291 return -ENOMEM; 1292 1293 pkt = p; 1294 stop = p + APR_HDR_SIZE; 1295 1296 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1297 APR_HDR_LEN(APR_HDR_SIZE), 1298 APR_PKT_VER); 1299 pkt->hdr.pkt_size = pkt_size; 1300 pkt->hdr.src_port = 0; 1301 pkt->hdr.dest_port = 0; 1302 pkt->hdr.token = index; 1303 pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_STOP; 1304 stop->port_id = port_id; 1305 stop->reserved = 0; 1306 1307 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_STOP); 1308 if (ret) 1309 dev_err(afe->dev, "AFE close failed %d\n", ret); 1310 1311 return ret; 1312 } 1313 EXPORT_SYMBOL_GPL(q6afe_port_stop); 1314 1315 /** 1316 * q6afe_slim_port_prepare() - Prepare slim afe port. 1317 * 1318 * @port: Instance of afe port 1319 * @cfg: SLIM configuration for the afe port 1320 * 1321 */ 1322 void q6afe_slim_port_prepare(struct q6afe_port *port, 1323 struct q6afe_slim_cfg *cfg) 1324 { 1325 union afe_port_config *pcfg = &port->port_cfg; 1326 1327 pcfg->slim_cfg.sb_cfg_minor_version = AFE_API_VERSION_SLIMBUS_CONFIG; 1328 pcfg->slim_cfg.sample_rate = cfg->sample_rate; 1329 pcfg->slim_cfg.bit_width = cfg->bit_width; 1330 pcfg->slim_cfg.num_channels = cfg->num_channels; 1331 pcfg->slim_cfg.data_format = cfg->data_format; 1332 pcfg->slim_cfg.shared_ch_mapping[0] = cfg->ch_mapping[0]; 1333 pcfg->slim_cfg.shared_ch_mapping[1] = cfg->ch_mapping[1]; 1334 pcfg->slim_cfg.shared_ch_mapping[2] = cfg->ch_mapping[2]; 1335 pcfg->slim_cfg.shared_ch_mapping[3] = cfg->ch_mapping[3]; 1336 1337 } 1338 EXPORT_SYMBOL_GPL(q6afe_slim_port_prepare); 1339 1340 /** 1341 * q6afe_tdm_port_prepare() - Prepare tdm afe port. 1342 * 1343 * @port: Instance of afe port 1344 * @cfg: TDM configuration for the afe port 1345 * 1346 */ 1347 void q6afe_tdm_port_prepare(struct q6afe_port *port, 1348 struct q6afe_tdm_cfg *cfg) 1349 { 1350 union afe_port_config *pcfg = &port->port_cfg; 1351 1352 pcfg->tdm_cfg.tdm_cfg_minor_version = AFE_API_VERSION_TDM_CONFIG; 1353 pcfg->tdm_cfg.num_channels = cfg->num_channels; 1354 pcfg->tdm_cfg.sample_rate = cfg->sample_rate; 1355 pcfg->tdm_cfg.bit_width = cfg->bit_width; 1356 pcfg->tdm_cfg.data_format = cfg->data_format; 1357 pcfg->tdm_cfg.sync_mode = cfg->sync_mode; 1358 pcfg->tdm_cfg.sync_src = cfg->sync_src; 1359 pcfg->tdm_cfg.nslots_per_frame = cfg->nslots_per_frame; 1360 1361 pcfg->tdm_cfg.slot_width = cfg->slot_width; 1362 pcfg->tdm_cfg.slot_mask = cfg->slot_mask; 1363 port->scfg = kzalloc(sizeof(*port->scfg), GFP_KERNEL); 1364 if (!port->scfg) 1365 return; 1366 1367 port->scfg->minor_version = AFE_API_VERSION_SLOT_MAPPING_CONFIG; 1368 port->scfg->num_channels = cfg->num_channels; 1369 port->scfg->bitwidth = cfg->bit_width; 1370 port->scfg->data_align_type = cfg->data_align_type; 1371 memcpy(port->scfg->ch_mapping, cfg->ch_mapping, 1372 sizeof(u16) * AFE_PORT_MAX_AUDIO_CHAN_CNT); 1373 } 1374 EXPORT_SYMBOL_GPL(q6afe_tdm_port_prepare); 1375 1376 /** 1377 * afe_port_send_usb_dev_param() - Send USB dev token 1378 * 1379 * @port: Instance of afe port 1380 * @cardidx: USB SND card index to reference 1381 * @pcmidx: USB SND PCM device index to reference 1382 * 1383 * The USB dev token carries information about which USB SND card instance and 1384 * PCM device to execute the offload on. This information is carried through 1385 * to the stream enable QMI request, which is handled by the offload class 1386 * driver. The information is parsed to determine which USB device to query 1387 * the required resources for. 1388 */ 1389 int afe_port_send_usb_dev_param(struct q6afe_port *port, int cardidx, int pcmidx) 1390 { 1391 struct afe_param_id_usb_audio_dev_params usb_dev; 1392 int ret; 1393 1394 memset(&usb_dev, 0, sizeof(usb_dev)); 1395 1396 usb_dev.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1397 usb_dev.dev_token = (cardidx << 16) | (pcmidx << 8); 1398 ret = q6afe_port_set_param_v2(port, &usb_dev, 1399 AFE_PARAM_ID_USB_AUDIO_DEV_PARAMS, 1400 AFE_MODULE_AUDIO_DEV_INTERFACE, 1401 sizeof(usb_dev)); 1402 if (ret) 1403 dev_err(port->afe->dev, "%s: AFE device param cmd failed %d\n", 1404 __func__, ret); 1405 1406 return ret; 1407 } 1408 EXPORT_SYMBOL_GPL(afe_port_send_usb_dev_param); 1409 1410 static int afe_port_send_usb_params(struct q6afe_port *port, struct q6afe_usb_cfg *cfg) 1411 { 1412 union afe_port_config *pcfg = &port->port_cfg; 1413 struct afe_param_id_usb_audio_dev_lpcm_fmt lpcm_fmt; 1414 struct afe_param_id_usb_audio_svc_interval svc_int; 1415 int ret; 1416 1417 if (!pcfg) { 1418 dev_err(port->afe->dev, "%s: Error, no configuration data\n", __func__); 1419 return -EINVAL; 1420 } 1421 1422 memset(&lpcm_fmt, 0, sizeof(lpcm_fmt)); 1423 memset(&svc_int, 0, sizeof(svc_int)); 1424 1425 lpcm_fmt.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1426 lpcm_fmt.endian = pcfg->usb_cfg.endian; 1427 ret = q6afe_port_set_param_v2(port, &lpcm_fmt, 1428 AFE_PARAM_ID_USB_AUDIO_DEV_LPCM_FMT, 1429 AFE_MODULE_AUDIO_DEV_INTERFACE, sizeof(lpcm_fmt)); 1430 if (ret) { 1431 dev_err(port->afe->dev, "%s: AFE device param cmd LPCM_FMT failed %d\n", 1432 __func__, ret); 1433 return ret; 1434 } 1435 1436 svc_int.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1437 svc_int.svc_interval = pcfg->usb_cfg.service_interval; 1438 ret = q6afe_port_set_param_v2(port, &svc_int, 1439 AFE_PARAM_ID_USB_AUDIO_SVC_INTERVAL, 1440 AFE_MODULE_AUDIO_DEV_INTERFACE, sizeof(svc_int)); 1441 if (ret) 1442 dev_err(port->afe->dev, "%s: AFE device param cmd svc_interval failed %d\n", 1443 __func__, ret); 1444 1445 return ret; 1446 } 1447 1448 /** 1449 * q6afe_usb_port_prepare() - Prepare usb afe port. 1450 * 1451 * @port: Instance of afe port 1452 * @cfg: USB configuration for the afe port 1453 * 1454 */ 1455 void q6afe_usb_port_prepare(struct q6afe_port *port, 1456 struct q6afe_usb_cfg *cfg) 1457 { 1458 union afe_port_config *pcfg = &port->port_cfg; 1459 1460 pcfg->usb_cfg.cfg_minor_version = AFE_API_MINOR_VERSION_USB_AUDIO_CONFIG; 1461 pcfg->usb_cfg.sample_rate = cfg->sample_rate; 1462 pcfg->usb_cfg.num_channels = cfg->num_channels; 1463 pcfg->usb_cfg.bit_width = cfg->bit_width; 1464 1465 afe_port_send_usb_params(port, cfg); 1466 } 1467 EXPORT_SYMBOL_GPL(q6afe_usb_port_prepare); 1468 1469 /** 1470 * q6afe_hdmi_port_prepare() - Prepare hdmi afe port. 1471 * 1472 * @port: Instance of afe port 1473 * @cfg: HDMI configuration for the afe port 1474 * 1475 */ 1476 void q6afe_hdmi_port_prepare(struct q6afe_port *port, 1477 struct q6afe_hdmi_cfg *cfg) 1478 { 1479 union afe_port_config *pcfg = &port->port_cfg; 1480 1481 pcfg->hdmi_multi_ch.hdmi_cfg_minor_version = 1482 AFE_API_VERSION_HDMI_CONFIG; 1483 pcfg->hdmi_multi_ch.datatype = cfg->datatype; 1484 pcfg->hdmi_multi_ch.channel_allocation = cfg->channel_allocation; 1485 pcfg->hdmi_multi_ch.sample_rate = cfg->sample_rate; 1486 pcfg->hdmi_multi_ch.bit_width = cfg->bit_width; 1487 } 1488 EXPORT_SYMBOL_GPL(q6afe_hdmi_port_prepare); 1489 1490 /** 1491 * q6afe_i2s_port_prepare() - Prepare i2s afe port. 1492 * 1493 * @port: Instance of afe port 1494 * @cfg: I2S configuration for the afe port 1495 * Return: Will be an negative on error and zero on success. 1496 */ 1497 int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg) 1498 { 1499 union afe_port_config *pcfg = &port->port_cfg; 1500 struct device *dev = port->afe->dev; 1501 int num_sd_lines; 1502 1503 pcfg->i2s_cfg.i2s_cfg_minor_version = AFE_API_VERSION_I2S_CONFIG; 1504 pcfg->i2s_cfg.sample_rate = cfg->sample_rate; 1505 pcfg->i2s_cfg.bit_width = cfg->bit_width; 1506 pcfg->i2s_cfg.data_format = AFE_LINEAR_PCM_DATA; 1507 1508 switch (cfg->fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) { 1509 case SND_SOC_DAIFMT_BP_FP: 1510 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL; 1511 break; 1512 case SND_SOC_DAIFMT_BC_FC: 1513 /* CPU is slave */ 1514 pcfg->i2s_cfg.ws_src = AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL; 1515 break; 1516 default: 1517 break; 1518 } 1519 1520 num_sd_lines = hweight_long(cfg->sd_line_mask); 1521 1522 switch (num_sd_lines) { 1523 case 0: 1524 dev_err(dev, "no line is assigned\n"); 1525 return -EINVAL; 1526 case 1: 1527 switch (cfg->sd_line_mask) { 1528 case AFE_PORT_I2S_SD0_MASK: 1529 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; 1530 break; 1531 case AFE_PORT_I2S_SD1_MASK: 1532 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD1; 1533 break; 1534 case AFE_PORT_I2S_SD2_MASK: 1535 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; 1536 break; 1537 case AFE_PORT_I2S_SD3_MASK: 1538 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD3; 1539 break; 1540 default: 1541 dev_err(dev, "Invalid SD lines\n"); 1542 return -EINVAL; 1543 } 1544 break; 1545 case 2: 1546 switch (cfg->sd_line_mask) { 1547 case AFE_PORT_I2S_SD0_1_MASK: 1548 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD01; 1549 break; 1550 case AFE_PORT_I2S_SD2_3_MASK: 1551 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_QUAD23; 1552 break; 1553 default: 1554 dev_err(dev, "Invalid SD lines\n"); 1555 return -EINVAL; 1556 } 1557 break; 1558 case 3: 1559 switch (cfg->sd_line_mask) { 1560 case AFE_PORT_I2S_SD0_1_2_MASK: 1561 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_6CHS; 1562 break; 1563 default: 1564 dev_err(dev, "Invalid SD lines\n"); 1565 return -EINVAL; 1566 } 1567 break; 1568 case 4: 1569 switch (cfg->sd_line_mask) { 1570 case AFE_PORT_I2S_SD0_1_2_3_MASK: 1571 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_8CHS; 1572 1573 break; 1574 default: 1575 dev_err(dev, "Invalid SD lines\n"); 1576 return -EINVAL; 1577 } 1578 break; 1579 default: 1580 dev_err(dev, "Invalid SD lines\n"); 1581 return -EINVAL; 1582 } 1583 1584 switch (cfg->num_channels) { 1585 case 1: 1586 case 2: 1587 switch (pcfg->i2s_cfg.channel_mode) { 1588 case AFE_PORT_I2S_QUAD01: 1589 case AFE_PORT_I2S_6CHS: 1590 case AFE_PORT_I2S_8CHS: 1591 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD0; 1592 break; 1593 case AFE_PORT_I2S_QUAD23: 1594 pcfg->i2s_cfg.channel_mode = AFE_PORT_I2S_SD2; 1595 break; 1596 } 1597 1598 if (cfg->num_channels == 2) 1599 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_STEREO; 1600 else 1601 pcfg->i2s_cfg.mono_stereo = AFE_PORT_I2S_MONO; 1602 1603 break; 1604 case 3: 1605 case 4: 1606 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_QUAD01) { 1607 dev_err(dev, "Invalid Channel mode\n"); 1608 return -EINVAL; 1609 } 1610 break; 1611 case 5: 1612 case 6: 1613 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_6CHS) { 1614 dev_err(dev, "Invalid Channel mode\n"); 1615 return -EINVAL; 1616 } 1617 break; 1618 case 7: 1619 case 8: 1620 if (pcfg->i2s_cfg.channel_mode < AFE_PORT_I2S_8CHS) { 1621 dev_err(dev, "Invalid Channel mode\n"); 1622 return -EINVAL; 1623 } 1624 break; 1625 default: 1626 break; 1627 } 1628 1629 return 0; 1630 } 1631 EXPORT_SYMBOL_GPL(q6afe_i2s_port_prepare); 1632 1633 /** 1634 * q6afe_cdc_dma_port_prepare() - Prepare dma afe port. 1635 * 1636 * @port: Instance of afe port 1637 * @cfg: DMA configuration for the afe port 1638 * 1639 */ 1640 void q6afe_cdc_dma_port_prepare(struct q6afe_port *port, 1641 struct q6afe_cdc_dma_cfg *cfg) 1642 { 1643 union afe_port_config *pcfg = &port->port_cfg; 1644 struct afe_param_id_cdc_dma_cfg *dma_cfg = &pcfg->dma_cfg; 1645 1646 dma_cfg->cdc_dma_cfg_minor_version = AFE_API_VERSION_CODEC_DMA_CONFIG; 1647 dma_cfg->sample_rate = cfg->sample_rate; 1648 dma_cfg->bit_width = cfg->bit_width; 1649 dma_cfg->data_format = cfg->data_format; 1650 dma_cfg->num_channels = cfg->num_channels; 1651 if (!cfg->active_channels_mask) 1652 dma_cfg->active_channels_mask = (1 << cfg->num_channels) - 1; 1653 } 1654 EXPORT_SYMBOL_GPL(q6afe_cdc_dma_port_prepare); 1655 /** 1656 * q6afe_port_start() - Start a afe port 1657 * 1658 * @port: Instance of port to start 1659 * 1660 * Return: Will be an negative on packet size on success. 1661 */ 1662 int q6afe_port_start(struct q6afe_port *port) 1663 { 1664 struct afe_port_cmd_device_start *start; 1665 struct q6afe *afe = port->afe; 1666 int port_id = port->id; 1667 int ret, param_id = port->cfg_type; 1668 struct apr_pkt *pkt; 1669 int pkt_size; 1670 void *p __free(kfree) = NULL; 1671 1672 ret = q6afe_port_set_param_v2(port, &port->port_cfg, param_id, 1673 AFE_MODULE_AUDIO_DEV_INTERFACE, 1674 sizeof(port->port_cfg)); 1675 if (ret) { 1676 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1677 port_id, ret); 1678 return ret; 1679 } 1680 1681 if (port->scfg) { 1682 ret = q6afe_port_set_param_v2(port, port->scfg, 1683 AFE_PARAM_ID_PORT_SLOT_MAPPING_CONFIG, 1684 AFE_MODULE_TDM, sizeof(*port->scfg)); 1685 if (ret) { 1686 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1687 port_id, ret); 1688 return ret; 1689 } 1690 } 1691 1692 pkt_size = APR_HDR_SIZE + sizeof(*start); 1693 p = kzalloc(pkt_size, GFP_KERNEL); 1694 if (!p) 1695 return -ENOMEM; 1696 1697 pkt = p; 1698 start = p + APR_HDR_SIZE; 1699 1700 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1701 APR_HDR_LEN(APR_HDR_SIZE), 1702 APR_PKT_VER); 1703 pkt->hdr.pkt_size = pkt_size; 1704 pkt->hdr.src_port = 0; 1705 pkt->hdr.dest_port = 0; 1706 pkt->hdr.token = port->token; 1707 pkt->hdr.opcode = AFE_PORT_CMD_DEVICE_START; 1708 1709 start->port_id = port_id; 1710 1711 ret = afe_apr_send_pkt(afe, pkt, port, AFE_PORT_CMD_DEVICE_START); 1712 if (ret) 1713 dev_err(afe->dev, "AFE enable for port 0x%x failed %d\n", 1714 port_id, ret); 1715 1716 return ret; 1717 } 1718 EXPORT_SYMBOL_GPL(q6afe_port_start); 1719 1720 /** 1721 * q6afe_port_get_from_id() - Get port instance from a port id 1722 * 1723 * @dev: Pointer to afe child device. 1724 * @id: port id 1725 * 1726 * Return: Will be an error pointer on error or a valid afe port 1727 * on success. 1728 */ 1729 struct q6afe_port *q6afe_port_get_from_id(struct device *dev, int id) 1730 { 1731 int port_id; 1732 struct q6afe *afe = dev_get_drvdata(dev->parent); 1733 struct q6afe_port *port; 1734 int cfg_type; 1735 1736 if (id < 0 || id >= AFE_PORT_MAX) { 1737 dev_err(dev, "AFE port token[%d] invalid!\n", id); 1738 return ERR_PTR(-EINVAL); 1739 } 1740 1741 /* if port is multiple times bind/unbind before callback finishes */ 1742 port = q6afe_find_port(afe, id); 1743 if (port) { 1744 dev_err(dev, "AFE Port already open\n"); 1745 return port; 1746 } 1747 1748 port_id = port_maps[id].port_id; 1749 1750 switch (port_id) { 1751 case AFE_PORT_ID_MULTICHAN_HDMI_RX: 1752 case AFE_PORT_ID_HDMI_OVER_DP_RX: 1753 cfg_type = AFE_PARAM_ID_HDMI_CONFIG; 1754 break; 1755 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX: 1756 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX: 1757 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX: 1758 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX: 1759 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX: 1760 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX: 1761 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX: 1762 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX: 1763 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX: 1764 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX: 1765 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX: 1766 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX: 1767 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX: 1768 case AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX: 1769 cfg_type = AFE_PARAM_ID_SLIMBUS_CONFIG; 1770 break; 1771 1772 case AFE_PORT_ID_PRIMARY_MI2S_RX: 1773 case AFE_PORT_ID_PRIMARY_MI2S_TX: 1774 case AFE_PORT_ID_SECONDARY_MI2S_RX: 1775 case AFE_PORT_ID_SECONDARY_MI2S_TX: 1776 case AFE_PORT_ID_TERTIARY_MI2S_RX: 1777 case AFE_PORT_ID_TERTIARY_MI2S_TX: 1778 case AFE_PORT_ID_QUATERNARY_MI2S_RX: 1779 case AFE_PORT_ID_QUATERNARY_MI2S_TX: 1780 case AFE_PORT_ID_QUINARY_MI2S_RX: 1781 case AFE_PORT_ID_QUINARY_MI2S_TX: 1782 cfg_type = AFE_PARAM_ID_I2S_CONFIG; 1783 break; 1784 case AFE_PORT_ID_PRIMARY_TDM_RX ... AFE_PORT_ID_QUINARY_TDM_TX_7: 1785 cfg_type = AFE_PARAM_ID_TDM_CONFIG; 1786 break; 1787 case AFE_PORT_ID_WSA_CODEC_DMA_RX_0 ... AFE_PORT_ID_RX_CODEC_DMA_RX_7: 1788 cfg_type = AFE_PARAM_ID_CODEC_DMA_CONFIG; 1789 break; 1790 case AFE_PORT_ID_USB_RX: 1791 cfg_type = AFE_PARAM_ID_USB_AUDIO_CONFIG; 1792 break; 1793 default: 1794 dev_err(dev, "Invalid port id 0x%x\n", port_id); 1795 return ERR_PTR(-EINVAL); 1796 } 1797 1798 port = kzalloc(sizeof(*port), GFP_KERNEL); 1799 if (!port) 1800 return ERR_PTR(-ENOMEM); 1801 1802 init_waitqueue_head(&port->wait); 1803 1804 port->token = id; 1805 port->id = port_id; 1806 port->afe = afe; 1807 port->cfg_type = cfg_type; 1808 kref_init(&port->refcount); 1809 1810 guard(spinlock)(&afe->port_list_lock); 1811 list_add_tail(&port->node, &afe->port_list); 1812 1813 return port; 1814 1815 } 1816 EXPORT_SYMBOL_GPL(q6afe_port_get_from_id); 1817 1818 /** 1819 * q6afe_port_put() - Release port reference 1820 * 1821 * @port: Instance of port to put 1822 */ 1823 void q6afe_port_put(struct q6afe_port *port) 1824 { 1825 kref_put(&port->refcount, q6afe_port_free); 1826 } 1827 EXPORT_SYMBOL_GPL(q6afe_port_put); 1828 1829 int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 1830 uint32_t client_handle) 1831 { 1832 struct q6afe *afe = dev_get_drvdata(dev->parent); 1833 struct afe_cmd_remote_lpass_core_hw_devote_request *vote_cfg; 1834 struct apr_pkt *pkt; 1835 int ret = 0; 1836 int pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg); 1837 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1838 if (!p) 1839 return -ENOMEM; 1840 1841 pkt = p; 1842 vote_cfg = p + APR_HDR_SIZE; 1843 1844 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1845 APR_HDR_LEN(APR_HDR_SIZE), 1846 APR_PKT_VER); 1847 pkt->hdr.pkt_size = pkt_size; 1848 pkt->hdr.src_port = 0; 1849 pkt->hdr.dest_port = 0; 1850 pkt->hdr.token = hw_block_id; 1851 pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_DEVOTE_REQUEST; 1852 vote_cfg->hw_block_id = hw_block_id; 1853 vote_cfg->client_handle = client_handle; 1854 1855 ret = apr_send_pkt(afe->apr, pkt); 1856 if (ret < 0) 1857 dev_err(afe->dev, "AFE failed to unvote (%d)\n", hw_block_id); 1858 1859 return ret; 1860 } 1861 EXPORT_SYMBOL(q6afe_unvote_lpass_core_hw); 1862 1863 int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, 1864 const char *client_name, uint32_t *client_handle) 1865 { 1866 struct q6afe *afe = dev_get_drvdata(dev->parent); 1867 struct afe_cmd_remote_lpass_core_hw_vote_request *vote_cfg; 1868 struct apr_pkt *pkt; 1869 int ret = 0; 1870 int pkt_size = APR_HDR_SIZE + sizeof(*vote_cfg); 1871 void *p __free(kfree) = kzalloc(pkt_size, GFP_KERNEL); 1872 if (!p) 1873 return -ENOMEM; 1874 1875 pkt = p; 1876 vote_cfg = p + APR_HDR_SIZE; 1877 1878 pkt->hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, 1879 APR_HDR_LEN(APR_HDR_SIZE), 1880 APR_PKT_VER); 1881 pkt->hdr.pkt_size = pkt_size; 1882 pkt->hdr.src_port = 0; 1883 pkt->hdr.dest_port = 0; 1884 pkt->hdr.token = hw_block_id; 1885 pkt->hdr.opcode = AFE_CMD_REMOTE_LPASS_CORE_HW_VOTE_REQUEST; 1886 vote_cfg->hw_block_id = hw_block_id; 1887 strscpy(vote_cfg->client_name, client_name, 1888 sizeof(vote_cfg->client_name)); 1889 1890 ret = afe_apr_send_pkt(afe, pkt, NULL, 1891 AFE_CMD_RSP_REMOTE_LPASS_CORE_HW_VOTE_REQUEST); 1892 if (ret) 1893 dev_err(afe->dev, "AFE failed to vote (%d)\n", hw_block_id); 1894 1895 return ret; 1896 } 1897 EXPORT_SYMBOL(q6afe_vote_lpass_core_hw); 1898 1899 static int q6afe_probe(struct apr_device *adev) 1900 { 1901 struct q6afe *afe; 1902 struct device *dev = &adev->dev; 1903 1904 afe = devm_kzalloc(dev, sizeof(*afe), GFP_KERNEL); 1905 if (!afe) 1906 return -ENOMEM; 1907 1908 q6core_get_svc_api_info(adev->svc_id, &afe->ainfo); 1909 afe->apr = adev; 1910 mutex_init(&afe->lock); 1911 init_waitqueue_head(&afe->wait); 1912 afe->dev = dev; 1913 INIT_LIST_HEAD(&afe->port_list); 1914 spin_lock_init(&afe->port_list_lock); 1915 1916 dev_set_drvdata(dev, afe); 1917 1918 return devm_of_platform_populate(dev); 1919 } 1920 1921 #ifdef CONFIG_OF 1922 static const struct of_device_id q6afe_device_id[] = { 1923 { .compatible = "qcom,q6afe" }, 1924 {}, 1925 }; 1926 MODULE_DEVICE_TABLE(of, q6afe_device_id); 1927 #endif 1928 1929 static struct apr_driver qcom_q6afe_driver = { 1930 .probe = q6afe_probe, 1931 .callback = q6afe_callback, 1932 .driver = { 1933 .name = "qcom-q6afe", 1934 .of_match_table = of_match_ptr(q6afe_device_id), 1935 1936 }, 1937 }; 1938 1939 module_apr_driver(qcom_q6afe_driver); 1940 MODULE_DESCRIPTION("Q6 Audio Front End"); 1941 MODULE_LICENSE("GPL v2"); 1942