1 /* 2 * Allwinner A1X SoCs pinctrl driver. 3 * 4 * Copyright (C) 2012 Maxime Ripard 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/clk.h> 14 #include <linux/export.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/irqchip/chained_irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/of.h> 21 #include <linux/of_clk.h> 22 #include <linux/platform_device.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/slab.h> 25 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/pinctrl/machine.h> 28 #include <linux/pinctrl/pinconf-generic.h> 29 #include <linux/pinctrl/pinconf.h> 30 #include <linux/pinctrl/pinctrl.h> 31 #include <linux/pinctrl/pinmux.h> 32 33 #include <dt-bindings/pinctrl/sun4i-a10.h> 34 35 #include "../core.h" 36 #include "pinctrl-sunxi.h" 37 38 /* 39 * These lock classes tell lockdep that GPIO IRQs are in a different 40 * category than their parents, so it won't report false recursion. 41 */ 42 static struct lock_class_key sunxi_pinctrl_irq_lock_class; 43 static struct lock_class_key sunxi_pinctrl_irq_request_class; 44 45 static struct irq_chip sunxi_pinctrl_edge_irq_chip; 46 static struct irq_chip sunxi_pinctrl_level_irq_chip; 47 48 /* 49 * The sunXi PIO registers are organized as a series of banks, with registers 50 * for each bank in the following order: 51 * - Mux config 52 * - Data value 53 * - Drive level 54 * - Pull direction 55 * 56 * Multiple consecutive registers are used for fields wider than one bit. 57 * 58 * The following functions calculate the register and the bit offset to access. 59 * They take a pin number which is relative to the start of the current device. 60 */ 61 62 /* 63 * When using the extended register layout, Bank K does not fit into the 64 * space used for the other banks. Instead it lives at offset 0x500. 65 */ 66 static u32 sunxi_bank_offset(const struct sunxi_pinctrl *pctl, u32 pin) 67 { 68 u32 offset = 0; 69 70 if (pin >= PK_BASE) { 71 pin -= PK_BASE; 72 offset = PIO_BANK_K_OFFSET; 73 } 74 75 return offset + (pin / PINS_PER_BANK) * pctl->bank_mem_size; 76 } 77 78 static void sunxi_mux_reg(const struct sunxi_pinctrl *pctl, 79 u32 pin, u32 *reg, u32 *shift, u32 *mask) 80 { 81 u32 offset = pin % PINS_PER_BANK * MUX_FIELD_WIDTH; 82 83 *reg = sunxi_bank_offset(pctl, pin) + MUX_REGS_OFFSET + 84 offset / BITS_PER_TYPE(u32) * sizeof(u32); 85 *shift = offset % BITS_PER_TYPE(u32); 86 *mask = (BIT(MUX_FIELD_WIDTH) - 1) << *shift; 87 } 88 89 static void sunxi_data_reg(const struct sunxi_pinctrl *pctl, 90 u32 pin, u32 *reg, u32 *shift, u32 *mask) 91 { 92 u32 offset = pin % PINS_PER_BANK * DATA_FIELD_WIDTH; 93 94 *reg = sunxi_bank_offset(pctl, pin) + DATA_REGS_OFFSET + 95 offset / BITS_PER_TYPE(u32) * sizeof(u32); 96 *shift = offset % BITS_PER_TYPE(u32); 97 *mask = (BIT(DATA_FIELD_WIDTH) - 1) << *shift; 98 } 99 100 static void sunxi_dlevel_reg(const struct sunxi_pinctrl *pctl, 101 u32 pin, u32 *reg, u32 *shift, u32 *mask) 102 { 103 u32 offset = pin % PINS_PER_BANK * pctl->dlevel_field_width; 104 105 *reg = sunxi_bank_offset(pctl, pin) + DLEVEL_REGS_OFFSET + 106 offset / BITS_PER_TYPE(u32) * sizeof(u32); 107 *shift = offset % BITS_PER_TYPE(u32); 108 *mask = (BIT(pctl->dlevel_field_width) - 1) << *shift; 109 } 110 111 static void sunxi_pull_reg(const struct sunxi_pinctrl *pctl, 112 u32 pin, u32 *reg, u32 *shift, u32 *mask) 113 { 114 u32 offset = pin % PINS_PER_BANK * PULL_FIELD_WIDTH; 115 116 *reg = sunxi_bank_offset(pctl, pin) + pctl->pull_regs_offset + 117 offset / BITS_PER_TYPE(u32) * sizeof(u32); 118 *shift = offset % BITS_PER_TYPE(u32); 119 *mask = (BIT(PULL_FIELD_WIDTH) - 1) << *shift; 120 } 121 122 static struct sunxi_pinctrl_group * 123 sunxi_pinctrl_find_group_by_name(struct sunxi_pinctrl *pctl, const char *group) 124 { 125 int i; 126 127 for (i = 0; i < pctl->ngroups; i++) { 128 struct sunxi_pinctrl_group *grp = pctl->groups + i; 129 130 if (!strcmp(grp->name, group)) 131 return grp; 132 } 133 134 return NULL; 135 } 136 137 static struct sunxi_pinctrl_function * 138 sunxi_pinctrl_find_function_by_name(struct sunxi_pinctrl *pctl, 139 const char *name) 140 { 141 struct sunxi_pinctrl_function *func = pctl->functions; 142 int i; 143 144 for (i = 0; i < pctl->nfunctions; i++) { 145 if (!func[i].name) 146 break; 147 148 if (!strcmp(func[i].name, name)) 149 return func + i; 150 } 151 152 return NULL; 153 } 154 155 static struct sunxi_desc_function * 156 sunxi_pinctrl_desc_find_function_by_name(struct sunxi_pinctrl *pctl, 157 const char *pin_name, 158 const char *func_name) 159 { 160 unsigned long variant = pctl->flags & SUNXI_PINCTRL_VARIANT_MASK; 161 int i; 162 163 for (i = 0; i < pctl->desc->npins; i++) { 164 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 165 166 if (!strcmp(pin->pin.name, pin_name)) { 167 struct sunxi_desc_function *func = pin->functions; 168 169 while (func->name) { 170 if (!strcmp(func->name, func_name) && 171 (!func->variant || 172 func->variant & variant)) 173 return func; 174 175 func++; 176 } 177 } 178 } 179 180 return NULL; 181 } 182 183 static struct sunxi_desc_function * 184 sunxi_pinctrl_desc_find_function_by_pin(struct sunxi_pinctrl *pctl, 185 const u16 pin_num, 186 const char *func_name) 187 { 188 int i; 189 190 for (i = 0; i < pctl->desc->npins; i++) { 191 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 192 193 if (pin->pin.number == pin_num) { 194 struct sunxi_desc_function *func = pin->functions; 195 196 while (func->name) { 197 if (!strcmp(func->name, func_name)) 198 return func; 199 200 func++; 201 } 202 } 203 } 204 205 return NULL; 206 } 207 208 static struct sunxi_desc_function * 209 sunxi_pinctrl_desc_find_function_by_pin_and_mux(struct sunxi_pinctrl *pctl, 210 const u16 pin_num, 211 const u8 muxval) 212 { 213 unsigned long variant = pctl->flags & SUNXI_PINCTRL_VARIANT_MASK; 214 215 for (unsigned int i = 0; i < pctl->desc->npins; i++) { 216 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 217 struct sunxi_desc_function *func = pin->functions; 218 219 if (pin->pin.number != pin_num) 220 continue; 221 222 if (pin->variant && !(variant & pin->variant)) 223 continue; 224 225 while (func->name) { 226 if (func->muxval == muxval) 227 return func; 228 229 func++; 230 } 231 } 232 233 return NULL; 234 } 235 236 static int sunxi_pctrl_get_groups_count(struct pinctrl_dev *pctldev) 237 { 238 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 239 240 return pctl->ngroups; 241 } 242 243 static const char *sunxi_pctrl_get_group_name(struct pinctrl_dev *pctldev, 244 unsigned group) 245 { 246 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 247 248 return pctl->groups[group].name; 249 } 250 251 static int sunxi_pctrl_get_group_pins(struct pinctrl_dev *pctldev, 252 unsigned group, 253 const unsigned **pins, 254 unsigned *num_pins) 255 { 256 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 257 258 *pins = (unsigned *)&pctl->groups[group].pin; 259 *num_pins = 1; 260 261 return 0; 262 } 263 264 static bool sunxi_pctrl_has_bias_prop(struct device_node *node) 265 { 266 return of_property_present(node, "bias-pull-up") || 267 of_property_present(node, "bias-pull-down") || 268 of_property_present(node, "bias-disable") || 269 of_property_present(node, "allwinner,pull"); 270 } 271 272 static bool sunxi_pctrl_has_drive_prop(struct device_node *node) 273 { 274 return of_property_present(node, "drive-strength") || 275 of_property_present(node, "allwinner,drive"); 276 } 277 278 static int sunxi_pctrl_parse_bias_prop(struct device_node *node) 279 { 280 u32 val; 281 282 /* Try the new style binding */ 283 if (of_property_present(node, "bias-pull-up")) 284 return PIN_CONFIG_BIAS_PULL_UP; 285 286 if (of_property_present(node, "bias-pull-down")) 287 return PIN_CONFIG_BIAS_PULL_DOWN; 288 289 if (of_property_present(node, "bias-disable")) 290 return PIN_CONFIG_BIAS_DISABLE; 291 292 /* And fall back to the old binding */ 293 if (of_property_read_u32(node, "allwinner,pull", &val)) 294 return -EINVAL; 295 296 switch (val) { 297 case SUN4I_PINCTRL_NO_PULL: 298 return PIN_CONFIG_BIAS_DISABLE; 299 case SUN4I_PINCTRL_PULL_UP: 300 return PIN_CONFIG_BIAS_PULL_UP; 301 case SUN4I_PINCTRL_PULL_DOWN: 302 return PIN_CONFIG_BIAS_PULL_DOWN; 303 } 304 305 return -EINVAL; 306 } 307 308 static int sunxi_pctrl_parse_drive_prop(struct device_node *node) 309 { 310 u32 val; 311 312 /* Try the new style binding */ 313 if (!of_property_read_u32(node, "drive-strength", &val)) { 314 /* We can't go below 10mA ... */ 315 if (val < 10) 316 return -EINVAL; 317 318 /* ... and only up to 40 mA ... */ 319 if (val > 40) 320 val = 40; 321 322 /* by steps of 10 mA */ 323 return rounddown(val, 10); 324 } 325 326 /* And then fall back to the old binding */ 327 if (of_property_read_u32(node, "allwinner,drive", &val)) 328 return -EINVAL; 329 330 return (val + 1) * 10; 331 } 332 333 static const char *sunxi_pctrl_parse_function_prop(struct device_node *node) 334 { 335 const char *function; 336 int ret; 337 338 /* Try the generic binding */ 339 ret = of_property_read_string(node, "function", &function); 340 if (!ret) 341 return function; 342 343 /* And fall back to our legacy one */ 344 ret = of_property_read_string(node, "allwinner,function", &function); 345 if (!ret) 346 return function; 347 348 return NULL; 349 } 350 351 static const char *sunxi_pctrl_find_pins_prop(struct device_node *node, 352 int *npins) 353 { 354 int count; 355 356 /* Try the generic binding */ 357 count = of_property_count_strings(node, "pins"); 358 if (count > 0) { 359 *npins = count; 360 return "pins"; 361 } 362 363 /* And fall back to our legacy one */ 364 count = of_property_count_strings(node, "allwinner,pins"); 365 if (count > 0) { 366 *npins = count; 367 return "allwinner,pins"; 368 } 369 370 return NULL; 371 } 372 373 static unsigned long *sunxi_pctrl_build_pin_config(struct device_node *node, 374 unsigned int *len) 375 { 376 unsigned long *pinconfig; 377 unsigned int configlen = 0, idx = 0; 378 int ret; 379 380 if (sunxi_pctrl_has_drive_prop(node)) 381 configlen++; 382 if (sunxi_pctrl_has_bias_prop(node)) 383 configlen++; 384 385 /* 386 * If we don't have any configuration, bail out 387 */ 388 if (!configlen) 389 return NULL; 390 391 pinconfig = kcalloc(configlen, sizeof(*pinconfig), GFP_KERNEL); 392 if (!pinconfig) 393 return ERR_PTR(-ENOMEM); 394 395 if (sunxi_pctrl_has_drive_prop(node)) { 396 int drive = sunxi_pctrl_parse_drive_prop(node); 397 if (drive < 0) { 398 ret = drive; 399 goto err_free; 400 } 401 402 pinconfig[idx++] = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 403 drive); 404 } 405 406 if (sunxi_pctrl_has_bias_prop(node)) { 407 int pull = sunxi_pctrl_parse_bias_prop(node); 408 int arg = 0; 409 if (pull < 0) { 410 ret = pull; 411 goto err_free; 412 } 413 414 if (pull != PIN_CONFIG_BIAS_DISABLE) 415 arg = 1; /* hardware uses weak pull resistors */ 416 417 pinconfig[idx++] = pinconf_to_config_packed(pull, arg); 418 } 419 420 421 *len = configlen; 422 return pinconfig; 423 424 err_free: 425 kfree(pinconfig); 426 return ERR_PTR(ret); 427 } 428 429 static int sunxi_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev, 430 struct device_node *node, 431 struct pinctrl_map **map, 432 unsigned *num_maps) 433 { 434 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 435 unsigned long *pinconfig; 436 struct property *prop; 437 const char *function, *pin_prop; 438 const char *group; 439 int ret, npins, nmaps, configlen = 0, i = 0; 440 struct pinctrl_map *new_map; 441 442 *map = NULL; 443 *num_maps = 0; 444 445 function = sunxi_pctrl_parse_function_prop(node); 446 if (!function) { 447 dev_err(pctl->dev, "missing function property in node %pOFn\n", 448 node); 449 return -EINVAL; 450 } 451 452 pin_prop = sunxi_pctrl_find_pins_prop(node, &npins); 453 if (!pin_prop) { 454 dev_err(pctl->dev, "missing pins property in node %pOFn\n", 455 node); 456 return -EINVAL; 457 } 458 459 /* 460 * We have two maps for each pin: one for the function, one 461 * for the configuration (bias, strength, etc). 462 * 463 * We might be slightly overshooting, since we might not have 464 * any configuration. 465 */ 466 nmaps = npins * 2; 467 *map = kmalloc_objs(struct pinctrl_map, nmaps); 468 if (!*map) 469 return -ENOMEM; 470 471 pinconfig = sunxi_pctrl_build_pin_config(node, &configlen); 472 if (IS_ERR(pinconfig)) { 473 ret = PTR_ERR(pinconfig); 474 goto err_free_map; 475 } 476 477 of_property_for_each_string(node, pin_prop, prop, group) { 478 struct sunxi_pinctrl_group *grp = 479 sunxi_pinctrl_find_group_by_name(pctl, group); 480 481 if (!grp) { 482 dev_err(pctl->dev, "unknown pin %s", group); 483 continue; 484 } 485 486 if (!sunxi_pinctrl_desc_find_function_by_name(pctl, 487 grp->name, 488 function)) { 489 dev_err(pctl->dev, "unsupported function %s on pin %s", 490 function, group); 491 continue; 492 } 493 494 (*map)[i].type = PIN_MAP_TYPE_MUX_GROUP; 495 (*map)[i].data.mux.group = group; 496 (*map)[i].data.mux.function = function; 497 498 i++; 499 500 if (pinconfig) { 501 (*map)[i].type = PIN_MAP_TYPE_CONFIGS_GROUP; 502 (*map)[i].data.configs.group_or_pin = group; 503 (*map)[i].data.configs.configs = pinconfig; 504 (*map)[i].data.configs.num_configs = configlen; 505 i++; 506 } 507 } 508 509 *num_maps = i; 510 511 /* 512 * We know have the number of maps we need, we can resize our 513 * map array 514 */ 515 new_map = krealloc(*map, i * sizeof(struct pinctrl_map), GFP_KERNEL); 516 if (!new_map) { 517 ret = -ENOMEM; 518 goto err_free_map; 519 } 520 521 *map = new_map; 522 523 return 0; 524 525 err_free_map: 526 kfree(*map); 527 *map = NULL; 528 return ret; 529 } 530 531 static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev, 532 struct pinctrl_map *map, 533 unsigned num_maps) 534 { 535 int i; 536 537 /* pin config is never in the first map */ 538 for (i = 1; i < num_maps; i++) { 539 if (map[i].type != PIN_MAP_TYPE_CONFIGS_GROUP) 540 continue; 541 542 /* 543 * All the maps share the same pin config, 544 * free only the first one we find. 545 */ 546 kfree(map[i].data.configs.configs); 547 break; 548 } 549 550 kfree(map); 551 } 552 553 static const struct pinctrl_ops sunxi_pctrl_ops = { 554 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 555 .dt_free_map = sunxi_pctrl_dt_free_map, 556 .get_groups_count = sunxi_pctrl_get_groups_count, 557 .get_group_name = sunxi_pctrl_get_group_name, 558 .get_group_pins = sunxi_pctrl_get_group_pins, 559 }; 560 561 static int sunxi_pconf_reg(const struct sunxi_pinctrl *pctl, 562 u32 pin, enum pin_config_param param, 563 u32 *reg, u32 *shift, u32 *mask) 564 { 565 switch (param) { 566 case PIN_CONFIG_DRIVE_STRENGTH: 567 sunxi_dlevel_reg(pctl, pin, reg, shift, mask); 568 break; 569 570 case PIN_CONFIG_BIAS_PULL_UP: 571 case PIN_CONFIG_BIAS_PULL_DOWN: 572 case PIN_CONFIG_BIAS_DISABLE: 573 sunxi_pull_reg(pctl, pin, reg, shift, mask); 574 break; 575 576 default: 577 return -ENOTSUPP; 578 } 579 580 return 0; 581 } 582 583 static int sunxi_pconf_get(struct pinctrl_dev *pctldev, unsigned pin, 584 unsigned long *config) 585 { 586 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 587 enum pin_config_param param = pinconf_to_config_param(*config); 588 u32 reg, shift, mask, val; 589 u16 arg; 590 int ret; 591 592 pin -= pctl->desc->pin_base; 593 594 ret = sunxi_pconf_reg(pctl, pin, param, ®, &shift, &mask); 595 if (ret < 0) 596 return ret; 597 598 val = (readl(pctl->membase + reg) & mask) >> shift; 599 600 switch (pinconf_to_config_param(*config)) { 601 case PIN_CONFIG_DRIVE_STRENGTH: 602 arg = (val + 1) * 10; 603 break; 604 605 case PIN_CONFIG_BIAS_PULL_UP: 606 if (val != SUN4I_PINCTRL_PULL_UP) 607 return -EINVAL; 608 arg = 1; /* hardware is weak pull-up */ 609 break; 610 611 case PIN_CONFIG_BIAS_PULL_DOWN: 612 if (val != SUN4I_PINCTRL_PULL_DOWN) 613 return -EINVAL; 614 arg = 1; /* hardware is weak pull-down */ 615 break; 616 617 case PIN_CONFIG_BIAS_DISABLE: 618 if (val != SUN4I_PINCTRL_NO_PULL) 619 return -EINVAL; 620 arg = 0; 621 break; 622 623 default: 624 /* sunxi_pconf_reg should catch anything unsupported */ 625 WARN_ON(1); 626 return -ENOTSUPP; 627 } 628 629 *config = pinconf_to_config_packed(param, arg); 630 631 return 0; 632 } 633 634 static int sunxi_pconf_group_get(struct pinctrl_dev *pctldev, 635 unsigned group, 636 unsigned long *config) 637 { 638 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 639 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 640 641 /* We only support 1 pin per group. Chain it to the pin callback */ 642 return sunxi_pconf_get(pctldev, g->pin, config); 643 } 644 645 static int sunxi_pconf_set(struct pinctrl_dev *pctldev, unsigned pin, 646 unsigned long *configs, unsigned num_configs) 647 { 648 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 649 int i; 650 651 pin -= pctl->desc->pin_base; 652 653 for (i = 0; i < num_configs; i++) { 654 u32 arg, reg, shift, mask, val; 655 enum pin_config_param param; 656 unsigned long flags; 657 int ret; 658 659 param = pinconf_to_config_param(configs[i]); 660 arg = pinconf_to_config_argument(configs[i]); 661 662 ret = sunxi_pconf_reg(pctl, pin, param, ®, &shift, &mask); 663 if (ret < 0) 664 return ret; 665 666 switch (param) { 667 case PIN_CONFIG_DRIVE_STRENGTH: 668 if (arg < 10 || arg > 40) 669 return -EINVAL; 670 /* 671 * We convert from mA to what the register expects: 672 * 0: 10mA 673 * 1: 20mA 674 * 2: 30mA 675 * 3: 40mA 676 */ 677 val = arg / 10 - 1; 678 break; 679 case PIN_CONFIG_BIAS_DISABLE: 680 val = 0; 681 break; 682 case PIN_CONFIG_BIAS_PULL_UP: 683 if (arg == 0) 684 return -EINVAL; 685 val = 1; 686 break; 687 case PIN_CONFIG_BIAS_PULL_DOWN: 688 if (arg == 0) 689 return -EINVAL; 690 val = 2; 691 break; 692 default: 693 /* sunxi_pconf_reg should catch anything unsupported */ 694 WARN_ON(1); 695 return -ENOTSUPP; 696 } 697 698 raw_spin_lock_irqsave(&pctl->lock, flags); 699 writel((readl(pctl->membase + reg) & ~mask) | val << shift, 700 pctl->membase + reg); 701 raw_spin_unlock_irqrestore(&pctl->lock, flags); 702 } /* for each config */ 703 704 return 0; 705 } 706 707 static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group, 708 unsigned long *configs, unsigned num_configs) 709 { 710 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 711 struct sunxi_pinctrl_group *g = &pctl->groups[group]; 712 713 /* We only support 1 pin per group. Chain it to the pin callback */ 714 return sunxi_pconf_set(pctldev, g->pin, configs, num_configs); 715 } 716 717 static const struct pinconf_ops sunxi_pconf_ops = { 718 .is_generic = true, 719 .pin_config_get = sunxi_pconf_get, 720 .pin_config_set = sunxi_pconf_set, 721 .pin_config_group_get = sunxi_pconf_group_get, 722 .pin_config_group_set = sunxi_pconf_group_set, 723 }; 724 725 static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, 726 unsigned pin, 727 struct regulator *supply) 728 { 729 unsigned short bank; 730 unsigned long flags; 731 u32 val, reg; 732 int uV; 733 734 if (!pctl->desc->io_bias_cfg_variant) 735 return 0; 736 737 uV = regulator_get_voltage(supply); 738 if (uV < 0) 739 return uV; 740 741 /* Might be dummy regulator with no voltage set */ 742 if (uV == 0) 743 return 0; 744 745 pin -= pctl->desc->pin_base; 746 bank = pin / PINS_PER_BANK; 747 748 switch (pctl->desc->io_bias_cfg_variant) { 749 case BIAS_VOLTAGE_GRP_CONFIG: 750 /* 751 * Configured value must be equal or greater to actual 752 * voltage. 753 */ 754 if (uV <= 1800000) 755 val = 0x0; /* 1.8V */ 756 else if (uV <= 2500000) 757 val = 0x6; /* 2.5V */ 758 else if (uV <= 2800000) 759 val = 0x9; /* 2.8V */ 760 else if (uV <= 3000000) 761 val = 0xA; /* 3.0V */ 762 else 763 val = 0xD; /* 3.3V */ 764 765 reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); 766 reg &= ~IO_BIAS_MASK; 767 writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); 768 return 0; 769 case BIAS_VOLTAGE_PIO_POW_MODE_CTL: 770 val = uV > 1800000 && uV <= 2500000 ? BIT(bank) : 0; 771 772 raw_spin_lock_irqsave(&pctl->lock, flags); 773 reg = readl(pctl->membase + pctl->pow_mod_sel_offset + 774 PIO_POW_MOD_CTL_OFS); 775 reg &= ~BIT(bank); 776 writel(reg | val, pctl->membase + pctl->pow_mod_sel_offset + 777 PIO_POW_MOD_CTL_OFS); 778 raw_spin_unlock_irqrestore(&pctl->lock, flags); 779 780 fallthrough; 781 case BIAS_VOLTAGE_PIO_POW_MODE_SEL: 782 val = uV <= 1800000 ? 1 : 0; 783 784 raw_spin_lock_irqsave(&pctl->lock, flags); 785 reg = readl(pctl->membase + pctl->pow_mod_sel_offset); 786 reg &= ~(1 << bank); 787 writel(reg | val << bank, 788 pctl->membase + pctl->pow_mod_sel_offset); 789 raw_spin_unlock_irqrestore(&pctl->lock, flags); 790 return 0; 791 default: 792 return -EINVAL; 793 } 794 } 795 796 static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) 797 { 798 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 799 800 return pctl->nfunctions; 801 } 802 803 static const char *sunxi_pmx_get_func_name(struct pinctrl_dev *pctldev, 804 unsigned function) 805 { 806 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 807 808 return pctl->functions[function].name; 809 } 810 811 static int sunxi_pmx_get_func_groups(struct pinctrl_dev *pctldev, 812 unsigned function, 813 const char * const **groups, 814 unsigned * const num_groups) 815 { 816 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 817 818 *groups = pctl->functions[function].groups; 819 *num_groups = pctl->functions[function].ngroups; 820 821 return 0; 822 } 823 824 static void sunxi_pmx_set(struct pinctrl_dev *pctldev, 825 unsigned pin, 826 u8 config) 827 { 828 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 829 u32 reg, shift, mask; 830 unsigned long flags; 831 832 pin -= pctl->desc->pin_base; 833 sunxi_mux_reg(pctl, pin, ®, &shift, &mask); 834 835 raw_spin_lock_irqsave(&pctl->lock, flags); 836 837 writel((readl(pctl->membase + reg) & ~mask) | config << shift, 838 pctl->membase + reg); 839 840 raw_spin_unlock_irqrestore(&pctl->lock, flags); 841 } 842 843 static int sunxi_pmx_set_mux(struct pinctrl_dev *pctldev, 844 unsigned function, 845 unsigned group) 846 { 847 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 848 struct sunxi_pinctrl_group *g = pctl->groups + group; 849 struct sunxi_pinctrl_function *func = pctl->functions + function; 850 struct sunxi_desc_function *desc = 851 sunxi_pinctrl_desc_find_function_by_name(pctl, 852 g->name, 853 func->name); 854 855 if (!desc) 856 return -EINVAL; 857 858 sunxi_pmx_set(pctldev, g->pin, desc->muxval); 859 860 return 0; 861 } 862 863 static int 864 sunxi_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 865 struct pinctrl_gpio_range *range, 866 unsigned offset, 867 bool input) 868 { 869 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 870 struct sunxi_desc_function *desc; 871 const char *func; 872 873 if (input) 874 func = "gpio_in"; 875 else 876 func = "gpio_out"; 877 878 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, offset, func); 879 if (!desc) 880 return -EINVAL; 881 882 sunxi_pmx_set(pctldev, offset, desc->muxval); 883 884 return 0; 885 } 886 887 static int sunxi_pmx_request(struct pinctrl_dev *pctldev, unsigned offset) 888 { 889 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 890 unsigned short bank = offset / PINS_PER_BANK; 891 unsigned short bank_offset = bank - pctl->desc->pin_base / 892 PINS_PER_BANK; 893 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; 894 struct regulator *reg = s_reg->regulator; 895 char supply[16]; 896 int ret; 897 898 if (WARN_ON_ONCE(bank_offset >= ARRAY_SIZE(pctl->regulators))) 899 return -EINVAL; 900 901 if (reg) { 902 refcount_inc(&s_reg->refcount); 903 return 0; 904 } 905 906 snprintf(supply, sizeof(supply), "vcc-p%c", 'a' + bank); 907 reg = regulator_get(pctl->dev, supply); 908 if (IS_ERR(reg)) 909 return dev_err_probe(pctl->dev, PTR_ERR(reg), 910 "Couldn't get bank P%c regulator\n", 911 'A' + bank); 912 913 ret = regulator_enable(reg); 914 if (ret) { 915 dev_err(pctl->dev, 916 "Couldn't enable bank P%c regulator\n", 'A' + bank); 917 goto out; 918 } 919 920 sunxi_pinctrl_set_io_bias_cfg(pctl, offset, reg); 921 922 s_reg->regulator = reg; 923 refcount_set(&s_reg->refcount, 1); 924 925 return 0; 926 927 out: 928 regulator_put(s_reg->regulator); 929 930 return ret; 931 } 932 933 static int sunxi_pmx_free(struct pinctrl_dev *pctldev, unsigned offset) 934 { 935 struct sunxi_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 936 unsigned short bank = offset / PINS_PER_BANK; 937 unsigned short bank_offset = bank - pctl->desc->pin_base / 938 PINS_PER_BANK; 939 struct sunxi_pinctrl_regulator *s_reg = &pctl->regulators[bank_offset]; 940 941 if (!refcount_dec_and_test(&s_reg->refcount)) 942 return 0; 943 944 regulator_disable(s_reg->regulator); 945 regulator_put(s_reg->regulator); 946 s_reg->regulator = NULL; 947 948 return 0; 949 } 950 951 static const struct pinmux_ops sunxi_pmx_ops = { 952 .get_functions_count = sunxi_pmx_get_funcs_cnt, 953 .get_function_name = sunxi_pmx_get_func_name, 954 .get_function_groups = sunxi_pmx_get_func_groups, 955 .set_mux = sunxi_pmx_set_mux, 956 .gpio_set_direction = sunxi_pmx_gpio_set_direction, 957 .request = sunxi_pmx_request, 958 .free = sunxi_pmx_free, 959 .strict = true, 960 }; 961 962 static int sunxi_pinctrl_gpio_get_direction(struct gpio_chip *chip, 963 unsigned int offset) 964 { 965 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 966 const struct sunxi_desc_function *func; 967 u32 pin = offset + chip->base; 968 u32 reg, shift, mask; 969 u8 muxval; 970 971 sunxi_mux_reg(pctl, offset, ®, &shift, &mask); 972 973 muxval = (readl(pctl->membase + reg) & mask) >> shift; 974 975 func = sunxi_pinctrl_desc_find_function_by_pin_and_mux(pctl, pin, muxval); 976 if (!func) 977 return -ENODEV; 978 979 if (!strcmp(func->name, "gpio_out")) 980 return GPIO_LINE_DIRECTION_OUT; 981 if (!strcmp(func->name, "gpio_in") || !strcmp(func->name, "irq")) 982 return GPIO_LINE_DIRECTION_IN; 983 return -EINVAL; 984 } 985 986 static int sunxi_pinctrl_gpio_direction_input(struct gpio_chip *chip, 987 unsigned offset) 988 { 989 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 990 991 return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL, 992 chip->base + offset, true); 993 } 994 995 static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) 996 { 997 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 998 bool set_mux = pctl->desc->irq_read_needs_mux && 999 gpiochip_line_is_irq(chip, offset); 1000 u32 pin = offset + chip->base; 1001 u32 reg, shift, mask, val; 1002 1003 sunxi_data_reg(pctl, offset, ®, &shift, &mask); 1004 1005 if (set_mux) 1006 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); 1007 1008 val = (readl(pctl->membase + reg) & mask) >> shift; 1009 1010 if (set_mux) 1011 sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); 1012 1013 return val; 1014 } 1015 1016 static int sunxi_pinctrl_gpio_set(struct gpio_chip *chip, unsigned int offset, 1017 int value) 1018 { 1019 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 1020 u32 reg, shift, mask, val; 1021 unsigned long flags; 1022 1023 sunxi_data_reg(pctl, offset, ®, &shift, &mask); 1024 1025 raw_spin_lock_irqsave(&pctl->lock, flags); 1026 1027 val = readl(pctl->membase + reg); 1028 1029 if (value) 1030 val |= mask; 1031 else 1032 val &= ~mask; 1033 1034 writel(val, pctl->membase + reg); 1035 1036 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1037 1038 return 0; 1039 } 1040 1041 static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip, 1042 unsigned offset, int value) 1043 { 1044 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 1045 1046 sunxi_pinctrl_gpio_set(chip, offset, value); 1047 return sunxi_pmx_gpio_set_direction(pctl->pctl_dev, NULL, 1048 chip->base + offset, false); 1049 } 1050 1051 static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 1052 const struct of_phandle_args *gpiospec, 1053 u32 *flags) 1054 { 1055 int pin, base; 1056 1057 base = PINS_PER_BANK * gpiospec->args[0]; 1058 pin = base + gpiospec->args[1]; 1059 1060 if (pin > gc->ngpio) 1061 return -EINVAL; 1062 1063 if (flags) 1064 *flags = gpiospec->args[2]; 1065 1066 return pin; 1067 } 1068 1069 static int sunxi_pinctrl_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 1070 { 1071 struct sunxi_pinctrl *pctl = gpiochip_get_data(chip); 1072 struct sunxi_desc_function *desc; 1073 unsigned pinnum = pctl->desc->pin_base + offset; 1074 unsigned irqnum; 1075 1076 if (offset >= chip->ngpio) 1077 return -ENXIO; 1078 1079 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pinnum, "irq"); 1080 if (!desc) 1081 return -EINVAL; 1082 1083 irqnum = desc->irqbank * IRQ_PER_BANK + desc->irqnum; 1084 1085 dev_dbg(chip->parent, "%s: request IRQ for GPIO %d, return %d\n", 1086 chip->label, offset + chip->base, irqnum); 1087 1088 return irq_find_mapping(pctl->domain, irqnum); 1089 } 1090 1091 static int sunxi_pinctrl_irq_request_resources(struct irq_data *d) 1092 { 1093 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1094 struct sunxi_desc_function *func; 1095 unsigned int offset; 1096 u32 reg, shift, mask; 1097 u8 disabled_mux, muxval; 1098 int ret; 1099 1100 func = sunxi_pinctrl_desc_find_function_by_pin(pctl, 1101 pctl->irq_array[d->hwirq], "irq"); 1102 if (!func) 1103 return -EINVAL; 1104 1105 offset = pctl->irq_array[d->hwirq] - pctl->desc->pin_base; 1106 sunxi_mux_reg(pctl, offset, ®, &shift, &mask); 1107 muxval = (readl(pctl->membase + reg) & mask) >> shift; 1108 1109 /* Change muxing to GPIO INPUT mode if at reset value */ 1110 if (pctl->flags & SUNXI_PINCTRL_NEW_REG_LAYOUT) 1111 disabled_mux = SUN4I_FUNC_DISABLED_NEW; 1112 else 1113 disabled_mux = SUN4I_FUNC_DISABLED_OLD; 1114 1115 if (muxval == disabled_mux) 1116 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], 1117 SUN4I_FUNC_INPUT); 1118 1119 ret = gpiochip_lock_as_irq(pctl->chip, offset); 1120 if (ret) { 1121 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n", 1122 irqd_to_hwirq(d)); 1123 return ret; 1124 } 1125 1126 /* Change muxing to INT mode */ 1127 sunxi_pmx_set(pctl->pctl_dev, pctl->irq_array[d->hwirq], func->muxval); 1128 1129 return 0; 1130 } 1131 1132 static void sunxi_pinctrl_irq_release_resources(struct irq_data *d) 1133 { 1134 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1135 1136 gpiochip_unlock_as_irq(pctl->chip, 1137 pctl->irq_array[d->hwirq] - pctl->desc->pin_base); 1138 } 1139 1140 static int sunxi_pinctrl_irq_set_type(struct irq_data *d, unsigned int type) 1141 { 1142 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1143 u32 reg = sunxi_irq_cfg_reg(pctl->desc, d->hwirq); 1144 u8 index = sunxi_irq_cfg_offset(d->hwirq); 1145 unsigned long flags; 1146 u32 regval; 1147 u8 mode; 1148 1149 switch (type) { 1150 case IRQ_TYPE_EDGE_RISING: 1151 mode = IRQ_EDGE_RISING; 1152 break; 1153 case IRQ_TYPE_EDGE_FALLING: 1154 mode = IRQ_EDGE_FALLING; 1155 break; 1156 case IRQ_TYPE_EDGE_BOTH: 1157 mode = IRQ_EDGE_BOTH; 1158 break; 1159 case IRQ_TYPE_LEVEL_HIGH: 1160 mode = IRQ_LEVEL_HIGH; 1161 break; 1162 case IRQ_TYPE_LEVEL_LOW: 1163 mode = IRQ_LEVEL_LOW; 1164 break; 1165 default: 1166 return -EINVAL; 1167 } 1168 1169 raw_spin_lock_irqsave(&pctl->lock, flags); 1170 1171 if (type & IRQ_TYPE_LEVEL_MASK) 1172 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_level_irq_chip, 1173 handle_fasteoi_irq, NULL); 1174 else 1175 irq_set_chip_handler_name_locked(d, &sunxi_pinctrl_edge_irq_chip, 1176 handle_edge_irq, NULL); 1177 1178 regval = readl(pctl->membase + reg); 1179 regval &= ~(IRQ_CFG_IRQ_MASK << index); 1180 writel(regval | (mode << index), pctl->membase + reg); 1181 1182 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1183 1184 return 0; 1185 } 1186 1187 static void sunxi_pinctrl_irq_ack(struct irq_data *d) 1188 { 1189 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1190 u32 status_reg = sunxi_irq_status_reg(pctl->desc, d->hwirq); 1191 u8 status_idx = sunxi_irq_status_offset(d->hwirq); 1192 1193 /* Clear the IRQ */ 1194 writel(1 << status_idx, pctl->membase + status_reg); 1195 } 1196 1197 static void sunxi_pinctrl_irq_mask(struct irq_data *d) 1198 { 1199 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1200 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); 1201 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 1202 unsigned long flags; 1203 u32 val; 1204 1205 raw_spin_lock_irqsave(&pctl->lock, flags); 1206 1207 /* Mask the IRQ */ 1208 val = readl(pctl->membase + reg); 1209 writel(val & ~(1 << idx), pctl->membase + reg); 1210 1211 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1212 } 1213 1214 static void sunxi_pinctrl_irq_unmask(struct irq_data *d) 1215 { 1216 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1217 u32 reg = sunxi_irq_ctrl_reg(pctl->desc, d->hwirq); 1218 u8 idx = sunxi_irq_ctrl_offset(d->hwirq); 1219 unsigned long flags; 1220 u32 val; 1221 1222 raw_spin_lock_irqsave(&pctl->lock, flags); 1223 1224 /* Unmask the IRQ */ 1225 val = readl(pctl->membase + reg); 1226 writel(val | (1 << idx), pctl->membase + reg); 1227 1228 raw_spin_unlock_irqrestore(&pctl->lock, flags); 1229 } 1230 1231 static void sunxi_pinctrl_irq_ack_unmask(struct irq_data *d) 1232 { 1233 sunxi_pinctrl_irq_ack(d); 1234 sunxi_pinctrl_irq_unmask(d); 1235 } 1236 1237 static int sunxi_pinctrl_irq_set_wake(struct irq_data *d, unsigned int on) 1238 { 1239 struct sunxi_pinctrl *pctl = irq_data_get_irq_chip_data(d); 1240 u8 bank = d->hwirq / IRQ_PER_BANK; 1241 1242 return irq_set_irq_wake(pctl->irq[bank], on); 1243 } 1244 1245 static struct irq_chip sunxi_pinctrl_edge_irq_chip = { 1246 .name = "sunxi_pio_edge", 1247 .irq_ack = sunxi_pinctrl_irq_ack, 1248 .irq_mask = sunxi_pinctrl_irq_mask, 1249 .irq_unmask = sunxi_pinctrl_irq_unmask, 1250 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 1251 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 1252 .irq_set_type = sunxi_pinctrl_irq_set_type, 1253 .irq_set_wake = sunxi_pinctrl_irq_set_wake, 1254 .flags = IRQCHIP_MASK_ON_SUSPEND, 1255 }; 1256 1257 static struct irq_chip sunxi_pinctrl_level_irq_chip = { 1258 .name = "sunxi_pio_level", 1259 .irq_eoi = sunxi_pinctrl_irq_ack, 1260 .irq_mask = sunxi_pinctrl_irq_mask, 1261 .irq_unmask = sunxi_pinctrl_irq_unmask, 1262 /* Define irq_enable / disable to avoid spurious irqs for drivers 1263 * using these to suppress irqs while they clear the irq source */ 1264 .irq_enable = sunxi_pinctrl_irq_ack_unmask, 1265 .irq_disable = sunxi_pinctrl_irq_mask, 1266 .irq_request_resources = sunxi_pinctrl_irq_request_resources, 1267 .irq_release_resources = sunxi_pinctrl_irq_release_resources, 1268 .irq_set_type = sunxi_pinctrl_irq_set_type, 1269 .irq_set_wake = sunxi_pinctrl_irq_set_wake, 1270 .flags = IRQCHIP_EOI_THREADED | 1271 IRQCHIP_MASK_ON_SUSPEND | 1272 IRQCHIP_EOI_IF_HANDLED, 1273 }; 1274 1275 static int sunxi_pinctrl_irq_of_xlate(struct irq_domain *d, 1276 struct device_node *node, 1277 const u32 *intspec, 1278 unsigned int intsize, 1279 unsigned long *out_hwirq, 1280 unsigned int *out_type) 1281 { 1282 struct sunxi_pinctrl *pctl = d->host_data; 1283 struct sunxi_desc_function *desc; 1284 int pin, base; 1285 1286 if (intsize < 3) 1287 return -EINVAL; 1288 1289 base = PINS_PER_BANK * intspec[0]; 1290 pin = pctl->desc->pin_base + base + intspec[1]; 1291 1292 desc = sunxi_pinctrl_desc_find_function_by_pin(pctl, pin, "irq"); 1293 if (!desc) 1294 return -EINVAL; 1295 1296 *out_hwirq = desc->irqbank * PINS_PER_BANK + desc->irqnum; 1297 *out_type = intspec[2]; 1298 1299 return 0; 1300 } 1301 1302 static const struct irq_domain_ops sunxi_pinctrl_irq_domain_ops = { 1303 .xlate = sunxi_pinctrl_irq_of_xlate, 1304 }; 1305 1306 static void sunxi_pinctrl_irq_handler(struct irq_desc *desc) 1307 { 1308 unsigned int irq = irq_desc_get_irq(desc); 1309 struct irq_chip *chip = irq_desc_get_chip(desc); 1310 struct sunxi_pinctrl *pctl = irq_desc_get_handler_data(desc); 1311 unsigned long bank, reg, val; 1312 1313 for (bank = 0; bank < pctl->desc->irq_banks; bank++) 1314 if (irq == pctl->irq[bank]) 1315 break; 1316 1317 WARN_ON(bank == pctl->desc->irq_banks); 1318 1319 chained_irq_enter(chip, desc); 1320 1321 reg = sunxi_irq_status_reg_from_bank(pctl->desc, bank); 1322 val = readl(pctl->membase + reg); 1323 1324 if (val) { 1325 int irqoffset; 1326 1327 for_each_set_bit(irqoffset, &val, IRQ_PER_BANK) 1328 generic_handle_domain_irq(pctl->domain, 1329 bank * IRQ_PER_BANK + irqoffset); 1330 } 1331 1332 chained_irq_exit(chip, desc); 1333 } 1334 1335 static int sunxi_pinctrl_add_function(struct sunxi_pinctrl *pctl, 1336 const char *name) 1337 { 1338 struct sunxi_pinctrl_function *func = pctl->functions; 1339 1340 while (func->name) { 1341 /* function already there */ 1342 if (strcmp(func->name, name) == 0) { 1343 func->ngroups++; 1344 return -EEXIST; 1345 } 1346 func++; 1347 } 1348 1349 func->name = name; 1350 func->ngroups = 1; 1351 1352 pctl->nfunctions++; 1353 1354 return 0; 1355 } 1356 1357 static int sunxi_pinctrl_build_state(struct platform_device *pdev) 1358 { 1359 struct sunxi_pinctrl *pctl = platform_get_drvdata(pdev); 1360 unsigned long variant = pctl->flags & SUNXI_PINCTRL_VARIANT_MASK; 1361 void *ptr; 1362 int i; 1363 1364 /* 1365 * Allocate groups 1366 * 1367 * We assume that the number of groups is the number of pins 1368 * given in the data array. 1369 1370 * This will not always be true, since some pins might not be 1371 * available in the current variant, but fortunately for us, 1372 * this means that the number of pins is the maximum group 1373 * number we will ever see. 1374 */ 1375 pctl->groups = devm_kcalloc(&pdev->dev, 1376 pctl->desc->npins, sizeof(*pctl->groups), 1377 GFP_KERNEL); 1378 if (!pctl->groups) 1379 return -ENOMEM; 1380 1381 for (i = 0; i < pctl->desc->npins; i++) { 1382 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1383 struct sunxi_pinctrl_group *group = pctl->groups + pctl->ngroups; 1384 1385 if (pin->variant && !(variant & pin->variant)) 1386 continue; 1387 1388 group->name = pin->pin.name; 1389 group->pin = pin->pin.number; 1390 1391 /* And now we count the actual number of pins / groups */ 1392 pctl->ngroups++; 1393 } 1394 1395 /* 1396 * Find an upper bound for the maximum number of functions: in 1397 * the worst case we have gpio_in, gpio_out, irq and up to seven 1398 * special functions per pin, plus one entry for the sentinel. 1399 * We'll reallocate that later anyway. 1400 */ 1401 pctl->functions = kzalloc_objs(*pctl->functions, 7 * pctl->ngroups + 4); 1402 if (!pctl->functions) 1403 return -ENOMEM; 1404 1405 /* Count functions and their associated groups */ 1406 for (i = 0; i < pctl->desc->npins; i++) { 1407 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1408 struct sunxi_desc_function *func; 1409 1410 if (pin->variant && !(variant & pin->variant)) 1411 continue; 1412 1413 for (func = pin->functions; func->name; func++) { 1414 if (func->variant && !(variant & func->variant)) 1415 continue; 1416 1417 /* Create interrupt mapping while we're at it */ 1418 if (!strcmp(func->name, "irq")) { 1419 int irqnum = func->irqnum + func->irqbank * IRQ_PER_BANK; 1420 pctl->irq_array[irqnum] = pin->pin.number; 1421 } 1422 1423 sunxi_pinctrl_add_function(pctl, func->name); 1424 } 1425 } 1426 1427 /* And now allocated and fill the array for real */ 1428 ptr = krealloc(pctl->functions, 1429 pctl->nfunctions * sizeof(*pctl->functions), 1430 GFP_KERNEL); 1431 if (!ptr) { 1432 kfree(pctl->functions); 1433 pctl->functions = NULL; 1434 return -ENOMEM; 1435 } 1436 pctl->functions = ptr; 1437 1438 for (i = 0; i < pctl->desc->npins; i++) { 1439 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1440 struct sunxi_desc_function *func; 1441 1442 if (pin->variant && !(variant & pin->variant)) 1443 continue; 1444 1445 for (func = pin->functions; func->name; func++) { 1446 struct sunxi_pinctrl_function *func_item; 1447 const char **func_grp; 1448 1449 if (func->variant && !(variant & func->variant)) 1450 continue; 1451 1452 func_item = sunxi_pinctrl_find_function_by_name(pctl, 1453 func->name); 1454 if (!func_item) { 1455 kfree(pctl->functions); 1456 return -EINVAL; 1457 } 1458 1459 if (!func_item->groups) { 1460 func_item->groups = 1461 devm_kcalloc(&pdev->dev, 1462 func_item->ngroups, 1463 sizeof(*func_item->groups), 1464 GFP_KERNEL); 1465 if (!func_item->groups) { 1466 kfree(pctl->functions); 1467 return -ENOMEM; 1468 } 1469 } 1470 1471 func_grp = func_item->groups; 1472 while (*func_grp) 1473 func_grp++; 1474 1475 *func_grp = pin->pin.name; 1476 } 1477 } 1478 1479 return 0; 1480 } 1481 1482 static int sunxi_pinctrl_get_debounce_div(struct clk *clk, int freq, int *diff) 1483 { 1484 unsigned long clock = clk_get_rate(clk); 1485 unsigned int best_diff, best_div; 1486 int i; 1487 1488 best_diff = abs(freq - clock); 1489 best_div = 0; 1490 1491 for (i = 1; i < 8; i++) { 1492 int cur_diff = abs(freq - (clock >> i)); 1493 1494 if (cur_diff < best_diff) { 1495 best_diff = cur_diff; 1496 best_div = i; 1497 } 1498 } 1499 1500 *diff = best_diff; 1501 return best_div; 1502 } 1503 1504 static int sunxi_pinctrl_setup_debounce(struct sunxi_pinctrl *pctl, 1505 struct device_node *node) 1506 { 1507 unsigned int hosc_diff, losc_diff; 1508 unsigned int hosc_div, losc_div; 1509 struct clk *hosc, *losc; 1510 u8 div, src; 1511 int i, ret; 1512 1513 /* Deal with old DTs that didn't have the oscillators */ 1514 if (of_clk_get_parent_count(node) != 3) 1515 return 0; 1516 1517 /* If we don't have any setup, bail out */ 1518 if (!of_property_present(node, "input-debounce")) 1519 return 0; 1520 1521 losc = devm_clk_get(pctl->dev, "losc"); 1522 if (IS_ERR(losc)) 1523 return PTR_ERR(losc); 1524 1525 hosc = devm_clk_get(pctl->dev, "hosc"); 1526 if (IS_ERR(hosc)) 1527 return PTR_ERR(hosc); 1528 1529 for (i = 0; i < pctl->desc->irq_banks; i++) { 1530 unsigned long debounce_freq; 1531 u32 debounce; 1532 1533 ret = of_property_read_u32_index(node, "input-debounce", 1534 i, &debounce); 1535 if (ret) 1536 return ret; 1537 1538 if (!debounce) 1539 continue; 1540 1541 debounce_freq = DIV_ROUND_CLOSEST(USEC_PER_SEC, debounce); 1542 losc_div = sunxi_pinctrl_get_debounce_div(losc, 1543 debounce_freq, 1544 &losc_diff); 1545 1546 hosc_div = sunxi_pinctrl_get_debounce_div(hosc, 1547 debounce_freq, 1548 &hosc_diff); 1549 1550 if (hosc_diff < losc_diff) { 1551 div = hosc_div; 1552 src = 1; 1553 } else { 1554 div = losc_div; 1555 src = 0; 1556 } 1557 1558 writel(src | div << 4, 1559 pctl->membase + 1560 sunxi_irq_debounce_reg_from_bank(pctl->desc, i)); 1561 } 1562 1563 return 0; 1564 } 1565 1566 int sunxi_pinctrl_init_with_flags(struct platform_device *pdev, 1567 const struct sunxi_pinctrl_desc *desc, 1568 unsigned long flags) 1569 { 1570 struct device_node *node = pdev->dev.of_node; 1571 struct pinctrl_desc *pctrl_desc; 1572 struct pinctrl_pin_desc *pins; 1573 struct sunxi_pinctrl *pctl; 1574 struct pinmux_ops *pmxops; 1575 int i, ret, last_pin, pin_idx; 1576 struct clk *clk; 1577 1578 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL); 1579 if (!pctl) 1580 return -ENOMEM; 1581 platform_set_drvdata(pdev, pctl); 1582 1583 raw_spin_lock_init(&pctl->lock); 1584 1585 pctl->membase = devm_platform_ioremap_resource(pdev, 0); 1586 if (IS_ERR(pctl->membase)) 1587 return PTR_ERR(pctl->membase); 1588 1589 pctl->dev = &pdev->dev; 1590 pctl->desc = desc; 1591 pctl->flags = flags; 1592 if (flags & SUNXI_PINCTRL_NEW_REG_LAYOUT) { 1593 pctl->bank_mem_size = D1_BANK_MEM_SIZE; 1594 pctl->pull_regs_offset = D1_PULL_REGS_OFFSET; 1595 pctl->dlevel_field_width = D1_DLEVEL_FIELD_WIDTH; 1596 } else { 1597 pctl->bank_mem_size = BANK_MEM_SIZE; 1598 pctl->pull_regs_offset = PULL_REGS_OFFSET; 1599 pctl->dlevel_field_width = DLEVEL_FIELD_WIDTH; 1600 } 1601 if (flags & SUNXI_PINCTRL_ELEVEN_BANKS) 1602 pctl->pow_mod_sel_offset = PIO_11B_POW_MOD_SEL_REG; 1603 else 1604 pctl->pow_mod_sel_offset = PIO_POW_MOD_SEL_REG; 1605 1606 pctl->irq_array = devm_kcalloc(&pdev->dev, 1607 IRQ_PER_BANK * pctl->desc->irq_banks, 1608 sizeof(*pctl->irq_array), 1609 GFP_KERNEL); 1610 if (!pctl->irq_array) 1611 return -ENOMEM; 1612 1613 ret = sunxi_pinctrl_build_state(pdev); 1614 if (ret) { 1615 dev_err(&pdev->dev, "dt probe failed: %d\n", ret); 1616 return ret; 1617 } 1618 1619 pins = devm_kcalloc(&pdev->dev, 1620 pctl->desc->npins, sizeof(*pins), 1621 GFP_KERNEL); 1622 if (!pins) 1623 return -ENOMEM; 1624 1625 for (i = 0, pin_idx = 0; i < pctl->desc->npins; i++) { 1626 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1627 unsigned long variant = pctl->flags & SUNXI_PINCTRL_VARIANT_MASK; 1628 1629 if (pin->variant && !(variant & pin->variant)) 1630 continue; 1631 1632 pins[pin_idx++] = pin->pin; 1633 } 1634 1635 pctrl_desc = devm_kzalloc(&pdev->dev, 1636 sizeof(*pctrl_desc), 1637 GFP_KERNEL); 1638 if (!pctrl_desc) 1639 return -ENOMEM; 1640 1641 pctrl_desc->name = dev_name(&pdev->dev); 1642 pctrl_desc->owner = THIS_MODULE; 1643 pctrl_desc->pins = pins; 1644 pctrl_desc->npins = pctl->ngroups; 1645 pctrl_desc->confops = &sunxi_pconf_ops; 1646 pctrl_desc->pctlops = &sunxi_pctrl_ops; 1647 1648 pmxops = devm_kmemdup(&pdev->dev, &sunxi_pmx_ops, sizeof(sunxi_pmx_ops), 1649 GFP_KERNEL); 1650 if (!pmxops) 1651 return -ENOMEM; 1652 1653 if (desc->disable_strict_mode) 1654 pmxops->strict = false; 1655 1656 pctrl_desc->pmxops = pmxops; 1657 1658 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl); 1659 if (IS_ERR(pctl->pctl_dev)) { 1660 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1661 return PTR_ERR(pctl->pctl_dev); 1662 } 1663 1664 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1665 if (!pctl->chip) 1666 return -ENOMEM; 1667 1668 last_pin = pctl->desc->pins[pctl->desc->npins - 1].pin.number; 1669 pctl->chip->owner = THIS_MODULE; 1670 pctl->chip->request = gpiochip_generic_request; 1671 pctl->chip->free = gpiochip_generic_free; 1672 pctl->chip->set_config = gpiochip_generic_config; 1673 pctl->chip->get_direction = sunxi_pinctrl_gpio_get_direction; 1674 pctl->chip->direction_input = sunxi_pinctrl_gpio_direction_input; 1675 pctl->chip->direction_output = sunxi_pinctrl_gpio_direction_output; 1676 pctl->chip->get = sunxi_pinctrl_gpio_get; 1677 pctl->chip->set = sunxi_pinctrl_gpio_set; 1678 pctl->chip->of_xlate = sunxi_pinctrl_gpio_of_xlate; 1679 pctl->chip->to_irq = sunxi_pinctrl_gpio_to_irq; 1680 pctl->chip->of_gpio_n_cells = 3; 1681 pctl->chip->can_sleep = false; 1682 pctl->chip->ngpio = round_up(last_pin, PINS_PER_BANK) - 1683 pctl->desc->pin_base; 1684 pctl->chip->label = dev_name(&pdev->dev); 1685 pctl->chip->parent = &pdev->dev; 1686 pctl->chip->base = pctl->desc->pin_base; 1687 1688 ret = gpiochip_add_data(pctl->chip, pctl); 1689 if (ret) 1690 return ret; 1691 1692 for (i = 0; i < pctl->desc->npins; i++) { 1693 const struct sunxi_desc_pin *pin = pctl->desc->pins + i; 1694 1695 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev), 1696 pin->pin.number - pctl->desc->pin_base, 1697 pin->pin.number, 1); 1698 if (ret) 1699 goto gpiochip_error; 1700 } 1701 1702 ret = of_clk_get_parent_count(node); 1703 clk = devm_clk_get_enabled(&pdev->dev, ret == 1 ? NULL : "apb"); 1704 if (IS_ERR(clk)) { 1705 ret = PTR_ERR(clk); 1706 goto gpiochip_error; 1707 } 1708 1709 pctl->irq = devm_kcalloc(&pdev->dev, 1710 pctl->desc->irq_banks, 1711 sizeof(*pctl->irq), 1712 GFP_KERNEL); 1713 if (!pctl->irq) { 1714 ret = -ENOMEM; 1715 goto gpiochip_error; 1716 } 1717 1718 for (i = 0; i < pctl->desc->irq_banks; i++) { 1719 pctl->irq[i] = platform_get_irq(pdev, i); 1720 if (pctl->irq[i] < 0) { 1721 ret = pctl->irq[i]; 1722 goto gpiochip_error; 1723 } 1724 } 1725 1726 pctl->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), 1727 pctl->desc->irq_banks * IRQ_PER_BANK, 1728 &sunxi_pinctrl_irq_domain_ops, pctl); 1729 if (!pctl->domain) { 1730 dev_err(&pdev->dev, "Couldn't register IRQ domain\n"); 1731 ret = -ENOMEM; 1732 goto gpiochip_error; 1733 } 1734 1735 for (i = 0; i < (pctl->desc->irq_banks * IRQ_PER_BANK); i++) { 1736 int irqno = irq_create_mapping(pctl->domain, i); 1737 1738 irq_set_lockdep_class(irqno, &sunxi_pinctrl_irq_lock_class, 1739 &sunxi_pinctrl_irq_request_class); 1740 irq_set_chip_and_handler(irqno, &sunxi_pinctrl_edge_irq_chip, 1741 handle_edge_irq); 1742 irq_set_chip_data(irqno, pctl); 1743 } 1744 1745 for (i = 0; i < pctl->desc->irq_banks; i++) { 1746 /* Mask and clear all IRQs before registering a handler */ 1747 writel(0, pctl->membase + 1748 sunxi_irq_ctrl_reg_from_bank(pctl->desc, i)); 1749 writel(0xffffffff, 1750 pctl->membase + 1751 sunxi_irq_status_reg_from_bank(pctl->desc, i)); 1752 1753 irq_set_chained_handler_and_data(pctl->irq[i], 1754 sunxi_pinctrl_irq_handler, 1755 pctl); 1756 } 1757 1758 sunxi_pinctrl_setup_debounce(pctl, node); 1759 1760 dev_info(&pdev->dev, "initialized sunXi PIO driver\n"); 1761 1762 return 0; 1763 1764 gpiochip_error: 1765 gpiochip_remove(pctl->chip); 1766 return ret; 1767 } 1768