1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2016 Maxime Ripard. All rights reserved.
4 */
5
6 #include <linux/clk-provider.h>
7 #include <linux/io.h>
8 #include <linux/module.h>
9 #include <linux/platform_device.h>
10
11 #include "ccu_common.h"
12 #include "ccu_reset.h"
13
14 #include "ccu_div.h"
15 #include "ccu_gate.h"
16 #include "ccu_mp.h"
17 #include "ccu_mult.h"
18 #include "ccu_nk.h"
19 #include "ccu_nkm.h"
20 #include "ccu_nkmp.h"
21 #include "ccu_nm.h"
22 #include "ccu_phase.h"
23
24 #include "ccu-sun8i-a23-a33.h"
25
26 static struct ccu_nkmp pll_cpux_clk = {
27 .enable = BIT(31),
28 .lock = BIT(28),
29
30 .n = _SUNXI_CCU_MULT(8, 5),
31 .k = _SUNXI_CCU_MULT(4, 2),
32 .m = _SUNXI_CCU_DIV(0, 2),
33 .p = _SUNXI_CCU_DIV_MAX(16, 2, 4),
34
35 .common = {
36 .reg = 0x000,
37 .hw.init = CLK_HW_INIT("pll-cpux", "osc24M",
38 &ccu_nkmp_ops,
39 0),
40 },
41 };
42
43 /*
44 * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
45 * the base (2x, 4x and 8x), and one variable divider (the one true
46 * pll audio).
47 *
48 * With sigma-delta modulation for fractional-N on the audio PLL,
49 * we have to use specific dividers. This means the variable divider
50 * can no longer be used, as the audio codec requests the exact clock
51 * rates we support through this mechanism. So we now hard code the
52 * variable divider to 1. This means the clock rates will no longer
53 * match the clock names.
54 */
55 #define SUN8I_A33_PLL_AUDIO_REG 0x008
56
57 static struct ccu_sdm_setting pll_audio_sdm_table[] = {
58 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
59 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
60 };
61
62 static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
63 "osc24M", 0x008,
64 8, 7, /* N */
65 0, 5, /* M */
66 pll_audio_sdm_table, BIT(24),
67 0x284, BIT(31),
68 BIT(31), /* gate */
69 BIT(28), /* lock */
70 CLK_SET_RATE_UNGATE);
71
72 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
73 "osc24M", 0x010,
74 8, 7, /* N */
75 0, 4, /* M */
76 BIT(24), /* frac enable */
77 BIT(25), /* frac select */
78 270000000, /* frac rate 0 */
79 297000000, /* frac rate 1 */
80 BIT(31), /* gate */
81 BIT(28), /* lock */
82 CLK_SET_RATE_UNGATE);
83
84 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
85 "osc24M", 0x018,
86 8, 7, /* N */
87 0, 4, /* M */
88 BIT(24), /* frac enable */
89 BIT(25), /* frac select */
90 270000000, /* frac rate 0 */
91 297000000, /* frac rate 1 */
92 BIT(31), /* gate */
93 BIT(28), /* lock */
94 CLK_SET_RATE_UNGATE);
95
96 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr0_clk, "pll-ddr0",
97 "osc24M", 0x020,
98 8, 5, /* N */
99 4, 2, /* K */
100 0, 2, /* M */
101 BIT(31), /* gate */
102 BIT(28), /* lock */
103 0);
104
105 static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph_clk, "pll-periph",
106 "osc24M", 0x028,
107 8, 5, /* N */
108 4, 2, /* K */
109 BIT(31), /* gate */
110 BIT(28), /* lock */
111 2, /* post-div */
112 CLK_SET_RATE_UNGATE);
113
114 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
115 "osc24M", 0x038,
116 8, 7, /* N */
117 0, 4, /* M */
118 BIT(24), /* frac enable */
119 BIT(25), /* frac select */
120 270000000, /* frac rate 0 */
121 297000000, /* frac rate 1 */
122 BIT(31), /* gate */
123 BIT(28), /* lock */
124 CLK_SET_RATE_UNGATE);
125
126 /*
127 * The MIPI PLL has 2 modes: "MIPI" and "HDMI".
128 *
129 * The MIPI mode is a standard NKM-style clock. The HDMI mode is an
130 * integer / fractional clock with switchable multipliers and dividers.
131 * This is not supported here. We hardcode the PLL to MIPI mode.
132 */
133 #define SUN8I_A33_PLL_MIPI_REG 0x040
134 static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_mipi_clk, "pll-mipi",
135 "pll-video", 0x040,
136 8, 4, /* N */
137 4, 2, /* K */
138 0, 4, /* M */
139 BIT(31) | BIT(23) | BIT(22), /* gate */
140 BIT(28), /* lock */
141 CLK_SET_RATE_UNGATE);
142
143 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_hsic_clk, "pll-hsic",
144 "osc24M", 0x044,
145 8, 7, /* N */
146 0, 4, /* M */
147 BIT(24), /* frac enable */
148 BIT(25), /* frac select */
149 270000000, /* frac rate 0 */
150 297000000, /* frac rate 1 */
151 BIT(31), /* gate */
152 BIT(28), /* lock */
153 CLK_SET_RATE_UNGATE);
154
155 static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_de_clk, "pll-de",
156 "osc24M", 0x048,
157 8, 7, /* N */
158 0, 4, /* M */
159 BIT(24), /* frac enable */
160 BIT(25), /* frac select */
161 270000000, /* frac rate 0 */
162 297000000, /* frac rate 1 */
163 BIT(31), /* gate */
164 BIT(28), /* lock */
165 CLK_SET_RATE_UNGATE);
166
167 static struct ccu_mult pll_ddr1_clk = {
168 .enable = BIT(31),
169 .lock = BIT(28),
170 .mult = _SUNXI_CCU_MULT_OFFSET_MIN_MAX(8, 6, 0, 12, 0),
171 .common = {
172 .reg = 0x04c,
173 .hw.init = CLK_HW_INIT("pll-ddr1", "osc24M",
174 &ccu_mult_ops,
175 CLK_SET_RATE_UNGATE),
176 },
177 };
178
179 static const char * const cpux_parents[] = { "osc32k", "osc24M",
180 "pll-cpux" , "pll-cpux" };
181 static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents,
182 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT);
183
184 static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0);
185
186 static const char * const ahb1_parents[] = { "osc32k", "osc24M",
187 "axi" , "pll-periph" };
188 static const struct ccu_mux_var_prediv ahb1_predivs[] = {
189 { .index = 3, .shift = 6, .width = 2 },
190 };
191 static struct ccu_div ahb1_clk = {
192 .div = _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
193
194 .mux = {
195 .shift = 12,
196 .width = 2,
197
198 .var_predivs = ahb1_predivs,
199 .n_var_predivs = ARRAY_SIZE(ahb1_predivs),
200 },
201
202 .common = {
203 .reg = 0x054,
204 .features = CCU_FEATURE_VARIABLE_PREDIV,
205 .hw.init = CLK_HW_INIT_PARENTS("ahb1",
206 ahb1_parents,
207 &ccu_div_ops,
208 0),
209 },
210 };
211
212 static struct clk_div_table apb1_div_table[] = {
213 { .val = 0, .div = 2 },
214 { .val = 1, .div = 2 },
215 { .val = 2, .div = 4 },
216 { .val = 3, .div = 8 },
217 { /* Sentinel */ },
218 };
219 static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
220 0x054, 8, 2, apb1_div_table, 0);
221
222 static const char * const apb2_parents[] = { "osc32k", "osc24M",
223 "pll-periph" , "pll-periph" };
224 static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
225 0, 5, /* M */
226 16, 2, /* P */
227 24, 2, /* mux */
228 0);
229
230 static SUNXI_CCU_GATE(bus_mipi_dsi_clk, "bus-mipi-dsi", "ahb1",
231 0x060, BIT(1), 0);
232 static SUNXI_CCU_GATE(bus_ss_clk, "bus-ss", "ahb1",
233 0x060, BIT(5), 0);
234 static SUNXI_CCU_GATE(bus_dma_clk, "bus-dma", "ahb1",
235 0x060, BIT(6), 0);
236 static SUNXI_CCU_GATE(bus_mmc0_clk, "bus-mmc0", "ahb1",
237 0x060, BIT(8), 0);
238 static SUNXI_CCU_GATE(bus_mmc1_clk, "bus-mmc1", "ahb1",
239 0x060, BIT(9), 0);
240 static SUNXI_CCU_GATE(bus_mmc2_clk, "bus-mmc2", "ahb1",
241 0x060, BIT(10), 0);
242 static SUNXI_CCU_GATE(bus_nand_clk, "bus-nand", "ahb1",
243 0x060, BIT(13), 0);
244 static SUNXI_CCU_GATE(bus_dram_clk, "bus-dram", "ahb1",
245 0x060, BIT(14), 0);
246 static SUNXI_CCU_GATE(bus_hstimer_clk, "bus-hstimer", "ahb1",
247 0x060, BIT(19), 0);
248 static SUNXI_CCU_GATE(bus_spi0_clk, "bus-spi0", "ahb1",
249 0x060, BIT(20), 0);
250 static SUNXI_CCU_GATE(bus_spi1_clk, "bus-spi1", "ahb1",
251 0x060, BIT(21), 0);
252 static SUNXI_CCU_GATE(bus_otg_clk, "bus-otg", "ahb1",
253 0x060, BIT(24), 0);
254 static SUNXI_CCU_GATE(bus_ehci_clk, "bus-ehci", "ahb1",
255 0x060, BIT(26), 0);
256 static SUNXI_CCU_GATE(bus_ohci_clk, "bus-ohci", "ahb1",
257 0x060, BIT(29), 0);
258
259 static SUNXI_CCU_GATE(bus_ve_clk, "bus-ve", "ahb1",
260 0x064, BIT(0), 0);
261 static SUNXI_CCU_GATE(bus_lcd_clk, "bus-lcd", "ahb1",
262 0x064, BIT(4), 0);
263 static SUNXI_CCU_GATE(bus_csi_clk, "bus-csi", "ahb1",
264 0x064, BIT(8), 0);
265 static SUNXI_CCU_GATE(bus_de_be_clk, "bus-de-be", "ahb1",
266 0x064, BIT(12), 0);
267 static SUNXI_CCU_GATE(bus_de_fe_clk, "bus-de-fe", "ahb1",
268 0x064, BIT(14), 0);
269 static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "ahb1",
270 0x064, BIT(20), 0);
271 static SUNXI_CCU_GATE(bus_msgbox_clk, "bus-msgbox", "ahb1",
272 0x064, BIT(21), 0);
273 static SUNXI_CCU_GATE(bus_spinlock_clk, "bus-spinlock", "ahb1",
274 0x064, BIT(22), 0);
275 static SUNXI_CCU_GATE(bus_drc_clk, "bus-drc", "ahb1",
276 0x064, BIT(25), 0);
277 static SUNXI_CCU_GATE(bus_sat_clk, "bus-sat", "ahb1",
278 0x064, BIT(26), 0);
279
280 static SUNXI_CCU_GATE(bus_codec_clk, "bus-codec", "apb1",
281 0x068, BIT(0), 0);
282 static SUNXI_CCU_GATE(bus_pio_clk, "bus-pio", "apb1",
283 0x068, BIT(5), 0);
284 static SUNXI_CCU_GATE(bus_i2s0_clk, "bus-i2s0", "apb1",
285 0x068, BIT(12), 0);
286 static SUNXI_CCU_GATE(bus_i2s1_clk, "bus-i2s1", "apb1",
287 0x068, BIT(13), 0);
288
289 static SUNXI_CCU_GATE(bus_i2c0_clk, "bus-i2c0", "apb2",
290 0x06c, BIT(0), 0);
291 static SUNXI_CCU_GATE(bus_i2c1_clk, "bus-i2c1", "apb2",
292 0x06c, BIT(1), 0);
293 static SUNXI_CCU_GATE(bus_i2c2_clk, "bus-i2c2", "apb2",
294 0x06c, BIT(2), 0);
295 static SUNXI_CCU_GATE(bus_uart0_clk, "bus-uart0", "apb2",
296 0x06c, BIT(16), 0);
297 static SUNXI_CCU_GATE(bus_uart1_clk, "bus-uart1", "apb2",
298 0x06c, BIT(17), 0);
299 static SUNXI_CCU_GATE(bus_uart2_clk, "bus-uart2", "apb2",
300 0x06c, BIT(18), 0);
301 static SUNXI_CCU_GATE(bus_uart3_clk, "bus-uart3", "apb2",
302 0x06c, BIT(19), 0);
303 static SUNXI_CCU_GATE(bus_uart4_clk, "bus-uart4", "apb2",
304 0x06c, BIT(20), 0);
305
306 static const char * const mod0_default_parents[] = { "osc24M", "pll-periph" };
307 static SUNXI_CCU_MP_WITH_MUX_GATE(nand_clk, "nand", mod0_default_parents, 0x080,
308 0, 4, /* M */
309 16, 2, /* P */
310 24, 2, /* mux */
311 BIT(31), /* gate */
312 0);
313
314 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
315 0, 4, /* M */
316 16, 2, /* P */
317 24, 2, /* mux */
318 BIT(31), /* gate */
319 0);
320
321 static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
322 0x088, 20, 3, 0);
323 static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
324 0x088, 8, 3, 0);
325
326 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
327 0, 4, /* M */
328 16, 2, /* P */
329 24, 2, /* mux */
330 BIT(31), /* gate */
331 0);
332
333 static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
334 0x08c, 20, 3, 0);
335 static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
336 0x08c, 8, 3, 0);
337
338 static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
339 0, 4, /* M */
340 16, 2, /* P */
341 24, 2, /* mux */
342 BIT(31), /* gate */
343 0);
344
345 static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
346 0x090, 20, 3, 0);
347 static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
348 0x090, 8, 3, 0);
349
350 static SUNXI_CCU_MP_WITH_MUX_GATE(ss_clk, "ss", mod0_default_parents, 0x09c,
351 0, 4, /* M */
352 16, 2, /* P */
353 24, 2, /* mux */
354 BIT(31), /* gate */
355 0);
356
357 static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
358 0, 4, /* M */
359 16, 2, /* P */
360 24, 2, /* mux */
361 BIT(31), /* gate */
362 0);
363
364 static SUNXI_CCU_MP_WITH_MUX_GATE(spi1_clk, "spi1", mod0_default_parents, 0x0a4,
365 0, 4, /* M */
366 16, 2, /* P */
367 24, 2, /* mux */
368 BIT(31), /* gate */
369 0);
370
371 static const char * const i2s_parents[] = { "pll-audio-8x", "pll-audio-4x",
372 "pll-audio-2x", "pll-audio" };
373 static SUNXI_CCU_MUX_WITH_GATE(i2s0_clk, "i2s0", i2s_parents,
374 0x0b0, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
375
376 static SUNXI_CCU_MUX_WITH_GATE(i2s1_clk, "i2s1", i2s_parents,
377 0x0b4, 16, 2, BIT(31), CLK_SET_RATE_PARENT);
378
379 /* TODO: the parent for most of the USB clocks is not known */
380 static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
381 0x0cc, BIT(8), 0);
382 static SUNXI_CCU_GATE(usb_phy1_clk, "usb-phy1", "osc24M",
383 0x0cc, BIT(9), 0);
384 static SUNXI_CCU_GATE(usb_hsic_clk, "usb-hsic", "pll-hsic",
385 0x0cc, BIT(10), 0);
386 static SUNXI_CCU_GATE(usb_hsic_12M_clk, "usb-hsic-12M", "osc24M",
387 0x0cc, BIT(11), 0);
388 static SUNXI_CCU_GATE(usb_ohci_clk, "usb-ohci", "osc24M",
389 0x0cc, BIT(16), 0);
390
391 static SUNXI_CCU_M(dram_clk, "dram", "pll-ddr",
392 0x0f4, 0, 4, CLK_IS_CRITICAL);
393
394 static const char * const pll_ddr_parents[] = { "pll-ddr0", "pll-ddr1" };
395 static SUNXI_CCU_MUX(pll_ddr_clk, "pll-ddr", pll_ddr_parents,
396 0x0f8, 16, 1, 0);
397
398 static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "dram",
399 0x100, BIT(0), 0);
400 static SUNXI_CCU_GATE(dram_csi_clk, "dram-csi", "dram",
401 0x100, BIT(1), 0);
402 static SUNXI_CCU_GATE(dram_drc_clk, "dram-drc", "dram",
403 0x100, BIT(16), 0);
404 static SUNXI_CCU_GATE(dram_de_fe_clk, "dram-de-fe", "dram",
405 0x100, BIT(24), 0);
406 static SUNXI_CCU_GATE(dram_de_be_clk, "dram-de-be", "dram",
407 0x100, BIT(26), 0);
408
409 static const char * const de_parents[] = { "pll-video", "pll-periph-2x",
410 "pll-gpu", "pll-de" };
411 static const u8 de_table[] = { 0, 2, 3, 5 };
412 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_be_clk, "de-be",
413 de_parents, de_table,
414 0x104, 0, 4, 24, 3, BIT(31), 0);
415
416 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(de_fe_clk, "de-fe",
417 de_parents, de_table,
418 0x10c, 0, 4, 24, 3, BIT(31), 0);
419
420 static const char * const lcd_ch0_parents[] = { "pll-video", "pll-video-2x",
421 "pll-mipi" };
422 static const u8 lcd_ch0_table[] = { 0, 2, 4 };
423 static SUNXI_CCU_MUX_TABLE_WITH_GATE(lcd_ch0_clk, "lcd-ch0",
424 lcd_ch0_parents, lcd_ch0_table,
425 0x118, 24, 3, BIT(31),
426 CLK_SET_RATE_PARENT);
427
428 static const char * const lcd_ch1_parents[] = { "pll-video", "pll-video-2x" };
429 static const u8 lcd_ch1_table[] = { 0, 2 };
430 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(lcd_ch1_clk, "lcd-ch1",
431 lcd_ch1_parents, lcd_ch1_table,
432 0x12c, 0, 4, 24, 2, BIT(31), 0);
433
434 static const char * const csi_sclk_parents[] = { "pll-video", "pll-de",
435 "pll-mipi", "pll-ve" };
436 static const u8 csi_sclk_table[] = { 0, 3, 4, 5 };
437 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_sclk_clk, "csi-sclk",
438 csi_sclk_parents, csi_sclk_table,
439 0x134, 16, 4, 24, 3, BIT(31), 0);
440
441 static const char * const csi_mclk_parents[] = { "pll-video", "pll-de",
442 "osc24M" };
443 static const u8 csi_mclk_table[] = { 0, 3, 5 };
444 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(csi_mclk_clk, "csi-mclk",
445 csi_mclk_parents, csi_mclk_table,
446 0x134, 0, 5, 8, 3, BIT(15), 0);
447
448 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
449 0x13c, 16, 3, BIT(31), CLK_SET_RATE_PARENT);
450
451 static SUNXI_CCU_GATE(ac_dig_clk, "ac-dig", "pll-audio",
452 0x140, BIT(31), CLK_SET_RATE_PARENT);
453 static SUNXI_CCU_GATE(ac_dig_4x_clk, "ac-dig-4x", "pll-audio-4x",
454 0x140, BIT(30), CLK_SET_RATE_PARENT);
455 static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
456 0x144, BIT(31), 0);
457
458 static const char * const mbus_parents[] = { "osc24M", "pll-periph-2x",
459 "pll-ddr0", "pll-ddr1" };
460 static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
461 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
462
463 static const char * const dsi_sclk_parents[] = { "pll-video", "pll-video-2x" };
464 static const u8 dsi_sclk_table[] = { 0, 2 };
465 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_sclk_clk, "dsi-sclk",
466 dsi_sclk_parents, dsi_sclk_table,
467 0x168, 16, 4, 24, 2, BIT(31), 0);
468
469 static const char * const dsi_dphy_parents[] = { "pll-video", "pll-periph" };
470 static const u8 dsi_dphy_table[] = { 0, 2 };
471 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(dsi_dphy_clk, "dsi-dphy",
472 dsi_dphy_parents, dsi_dphy_table,
473 0x168, 0, 4, 8, 2, BIT(15), 0);
474
475 static SUNXI_CCU_M_WITH_MUX_TABLE_GATE(drc_clk, "drc",
476 de_parents, de_table,
477 0x180, 0, 4, 24, 3, BIT(31), 0);
478
479 static SUNXI_CCU_M_WITH_GATE(gpu_clk, "gpu", "pll-gpu",
480 0x1a0, 0, 3, BIT(31), CLK_SET_RATE_PARENT);
481
482 static const char * const ats_parents[] = { "osc24M", "pll-periph" };
483 static SUNXI_CCU_M_WITH_MUX_GATE(ats_clk, "ats", ats_parents,
484 0x1b0, 0, 3, 24, 2, BIT(31), 0);
485
486 static struct ccu_common *sun8i_a33_ccu_clks[] = {
487 &pll_cpux_clk.common,
488 &pll_audio_base_clk.common,
489 &pll_video_clk.common,
490 &pll_ve_clk.common,
491 &pll_ddr0_clk.common,
492 &pll_periph_clk.common,
493 &pll_gpu_clk.common,
494 &pll_mipi_clk.common,
495 &pll_hsic_clk.common,
496 &pll_de_clk.common,
497 &pll_ddr1_clk.common,
498 &pll_ddr_clk.common,
499 &cpux_clk.common,
500 &axi_clk.common,
501 &ahb1_clk.common,
502 &apb1_clk.common,
503 &apb2_clk.common,
504 &bus_mipi_dsi_clk.common,
505 &bus_ss_clk.common,
506 &bus_dma_clk.common,
507 &bus_mmc0_clk.common,
508 &bus_mmc1_clk.common,
509 &bus_mmc2_clk.common,
510 &bus_nand_clk.common,
511 &bus_dram_clk.common,
512 &bus_hstimer_clk.common,
513 &bus_spi0_clk.common,
514 &bus_spi1_clk.common,
515 &bus_otg_clk.common,
516 &bus_ehci_clk.common,
517 &bus_ohci_clk.common,
518 &bus_ve_clk.common,
519 &bus_lcd_clk.common,
520 &bus_csi_clk.common,
521 &bus_de_fe_clk.common,
522 &bus_de_be_clk.common,
523 &bus_gpu_clk.common,
524 &bus_msgbox_clk.common,
525 &bus_spinlock_clk.common,
526 &bus_drc_clk.common,
527 &bus_sat_clk.common,
528 &bus_codec_clk.common,
529 &bus_pio_clk.common,
530 &bus_i2s0_clk.common,
531 &bus_i2s1_clk.common,
532 &bus_i2c0_clk.common,
533 &bus_i2c1_clk.common,
534 &bus_i2c2_clk.common,
535 &bus_uart0_clk.common,
536 &bus_uart1_clk.common,
537 &bus_uart2_clk.common,
538 &bus_uart3_clk.common,
539 &bus_uart4_clk.common,
540 &nand_clk.common,
541 &mmc0_clk.common,
542 &mmc0_sample_clk.common,
543 &mmc0_output_clk.common,
544 &mmc1_clk.common,
545 &mmc1_sample_clk.common,
546 &mmc1_output_clk.common,
547 &mmc2_clk.common,
548 &mmc2_sample_clk.common,
549 &mmc2_output_clk.common,
550 &ss_clk.common,
551 &spi0_clk.common,
552 &spi1_clk.common,
553 &i2s0_clk.common,
554 &i2s1_clk.common,
555 &usb_phy0_clk.common,
556 &usb_phy1_clk.common,
557 &usb_hsic_clk.common,
558 &usb_hsic_12M_clk.common,
559 &usb_ohci_clk.common,
560 &dram_clk.common,
561 &dram_ve_clk.common,
562 &dram_csi_clk.common,
563 &dram_drc_clk.common,
564 &dram_de_fe_clk.common,
565 &dram_de_be_clk.common,
566 &de_be_clk.common,
567 &de_fe_clk.common,
568 &lcd_ch0_clk.common,
569 &lcd_ch1_clk.common,
570 &csi_sclk_clk.common,
571 &csi_mclk_clk.common,
572 &ve_clk.common,
573 &ac_dig_clk.common,
574 &ac_dig_4x_clk.common,
575 &avs_clk.common,
576 &mbus_clk.common,
577 &dsi_sclk_clk.common,
578 &dsi_dphy_clk.common,
579 &drc_clk.common,
580 &gpu_clk.common,
581 &ats_clk.common,
582 };
583
584 static const struct clk_hw *clk_parent_pll_audio[] = {
585 &pll_audio_base_clk.common.hw
586 };
587
588 /* We hardcode the divider to 1 for now */
589 static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
590 clk_parent_pll_audio,
591 1, 1, CLK_SET_RATE_PARENT);
592 static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
593 clk_parent_pll_audio,
594 2, 1, CLK_SET_RATE_PARENT);
595 static CLK_FIXED_FACTOR_HWS(pll_audio_4x_clk, "pll-audio-4x",
596 clk_parent_pll_audio,
597 1, 1, CLK_SET_RATE_PARENT);
598 static CLK_FIXED_FACTOR_HWS(pll_audio_8x_clk, "pll-audio-8x",
599 clk_parent_pll_audio,
600 1, 2, CLK_SET_RATE_PARENT);
601 static CLK_FIXED_FACTOR_HW(pll_periph_2x_clk, "pll-periph-2x",
602 &pll_periph_clk.common.hw,
603 1, 2, 0);
604 static CLK_FIXED_FACTOR_HW(pll_video_2x_clk, "pll-video-2x",
605 &pll_video_clk.common.hw,
606 1, 2, 0);
607
608 static struct clk_hw_onecell_data sun8i_a33_hw_clks = {
609 .hws = {
610 [CLK_PLL_CPUX] = &pll_cpux_clk.common.hw,
611 [CLK_PLL_AUDIO_BASE] = &pll_audio_base_clk.common.hw,
612 [CLK_PLL_AUDIO] = &pll_audio_clk.hw,
613 [CLK_PLL_AUDIO_2X] = &pll_audio_2x_clk.hw,
614 [CLK_PLL_AUDIO_4X] = &pll_audio_4x_clk.hw,
615 [CLK_PLL_AUDIO_8X] = &pll_audio_8x_clk.hw,
616 [CLK_PLL_VIDEO] = &pll_video_clk.common.hw,
617 [CLK_PLL_VIDEO_2X] = &pll_video_2x_clk.hw,
618 [CLK_PLL_VE] = &pll_ve_clk.common.hw,
619 [CLK_PLL_DDR0] = &pll_ddr0_clk.common.hw,
620 [CLK_PLL_PERIPH] = &pll_periph_clk.common.hw,
621 [CLK_PLL_PERIPH_2X] = &pll_periph_2x_clk.hw,
622 [CLK_PLL_GPU] = &pll_gpu_clk.common.hw,
623 [CLK_PLL_MIPI] = &pll_mipi_clk.common.hw,
624 [CLK_PLL_HSIC] = &pll_hsic_clk.common.hw,
625 [CLK_PLL_DE] = &pll_de_clk.common.hw,
626 [CLK_PLL_DDR1] = &pll_ddr1_clk.common.hw,
627 [CLK_PLL_DDR] = &pll_ddr_clk.common.hw,
628 [CLK_CPUX] = &cpux_clk.common.hw,
629 [CLK_AXI] = &axi_clk.common.hw,
630 [CLK_AHB1] = &ahb1_clk.common.hw,
631 [CLK_APB1] = &apb1_clk.common.hw,
632 [CLK_APB2] = &apb2_clk.common.hw,
633 [CLK_BUS_MIPI_DSI] = &bus_mipi_dsi_clk.common.hw,
634 [CLK_BUS_SS] = &bus_ss_clk.common.hw,
635 [CLK_BUS_DMA] = &bus_dma_clk.common.hw,
636 [CLK_BUS_MMC0] = &bus_mmc0_clk.common.hw,
637 [CLK_BUS_MMC1] = &bus_mmc1_clk.common.hw,
638 [CLK_BUS_MMC2] = &bus_mmc2_clk.common.hw,
639 [CLK_BUS_NAND] = &bus_nand_clk.common.hw,
640 [CLK_BUS_DRAM] = &bus_dram_clk.common.hw,
641 [CLK_BUS_HSTIMER] = &bus_hstimer_clk.common.hw,
642 [CLK_BUS_SPI0] = &bus_spi0_clk.common.hw,
643 [CLK_BUS_SPI1] = &bus_spi1_clk.common.hw,
644 [CLK_BUS_OTG] = &bus_otg_clk.common.hw,
645 [CLK_BUS_EHCI] = &bus_ehci_clk.common.hw,
646 [CLK_BUS_OHCI] = &bus_ohci_clk.common.hw,
647 [CLK_BUS_VE] = &bus_ve_clk.common.hw,
648 [CLK_BUS_LCD] = &bus_lcd_clk.common.hw,
649 [CLK_BUS_CSI] = &bus_csi_clk.common.hw,
650 [CLK_BUS_DE_BE] = &bus_de_be_clk.common.hw,
651 [CLK_BUS_DE_FE] = &bus_de_fe_clk.common.hw,
652 [CLK_BUS_GPU] = &bus_gpu_clk.common.hw,
653 [CLK_BUS_MSGBOX] = &bus_msgbox_clk.common.hw,
654 [CLK_BUS_SPINLOCK] = &bus_spinlock_clk.common.hw,
655 [CLK_BUS_DRC] = &bus_drc_clk.common.hw,
656 [CLK_BUS_SAT] = &bus_sat_clk.common.hw,
657 [CLK_BUS_CODEC] = &bus_codec_clk.common.hw,
658 [CLK_BUS_PIO] = &bus_pio_clk.common.hw,
659 [CLK_BUS_I2S0] = &bus_i2s0_clk.common.hw,
660 [CLK_BUS_I2S1] = &bus_i2s1_clk.common.hw,
661 [CLK_BUS_I2C0] = &bus_i2c0_clk.common.hw,
662 [CLK_BUS_I2C1] = &bus_i2c1_clk.common.hw,
663 [CLK_BUS_I2C2] = &bus_i2c2_clk.common.hw,
664 [CLK_BUS_UART0] = &bus_uart0_clk.common.hw,
665 [CLK_BUS_UART1] = &bus_uart1_clk.common.hw,
666 [CLK_BUS_UART2] = &bus_uart2_clk.common.hw,
667 [CLK_BUS_UART3] = &bus_uart3_clk.common.hw,
668 [CLK_BUS_UART4] = &bus_uart4_clk.common.hw,
669 [CLK_NAND] = &nand_clk.common.hw,
670 [CLK_MMC0] = &mmc0_clk.common.hw,
671 [CLK_MMC0_SAMPLE] = &mmc0_sample_clk.common.hw,
672 [CLK_MMC0_OUTPUT] = &mmc0_output_clk.common.hw,
673 [CLK_MMC1] = &mmc1_clk.common.hw,
674 [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
675 [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
676 [CLK_MMC2] = &mmc2_clk.common.hw,
677 [CLK_MMC2_SAMPLE] = &mmc2_sample_clk.common.hw,
678 [CLK_MMC2_OUTPUT] = &mmc2_output_clk.common.hw,
679 [CLK_SS] = &ss_clk.common.hw,
680 [CLK_SPI0] = &spi0_clk.common.hw,
681 [CLK_SPI1] = &spi1_clk.common.hw,
682 [CLK_I2S0] = &i2s0_clk.common.hw,
683 [CLK_I2S1] = &i2s1_clk.common.hw,
684 [CLK_USB_PHY0] = &usb_phy0_clk.common.hw,
685 [CLK_USB_PHY1] = &usb_phy1_clk.common.hw,
686 [CLK_USB_HSIC] = &usb_hsic_clk.common.hw,
687 [CLK_USB_HSIC_12M] = &usb_hsic_12M_clk.common.hw,
688 [CLK_USB_OHCI] = &usb_ohci_clk.common.hw,
689 [CLK_DRAM] = &dram_clk.common.hw,
690 [CLK_DRAM_VE] = &dram_ve_clk.common.hw,
691 [CLK_DRAM_CSI] = &dram_csi_clk.common.hw,
692 [CLK_DRAM_DRC] = &dram_drc_clk.common.hw,
693 [CLK_DRAM_DE_FE] = &dram_de_fe_clk.common.hw,
694 [CLK_DRAM_DE_BE] = &dram_de_be_clk.common.hw,
695 [CLK_DE_BE] = &de_be_clk.common.hw,
696 [CLK_DE_FE] = &de_fe_clk.common.hw,
697 [CLK_LCD_CH0] = &lcd_ch0_clk.common.hw,
698 [CLK_LCD_CH1] = &lcd_ch1_clk.common.hw,
699 [CLK_CSI_SCLK] = &csi_sclk_clk.common.hw,
700 [CLK_CSI_MCLK] = &csi_mclk_clk.common.hw,
701 [CLK_VE] = &ve_clk.common.hw,
702 [CLK_AC_DIG] = &ac_dig_clk.common.hw,
703 [CLK_AC_DIG_4X] = &ac_dig_4x_clk.common.hw,
704 [CLK_AVS] = &avs_clk.common.hw,
705 [CLK_MBUS] = &mbus_clk.common.hw,
706 [CLK_DSI_SCLK] = &dsi_sclk_clk.common.hw,
707 [CLK_DSI_DPHY] = &dsi_dphy_clk.common.hw,
708 [CLK_DRC] = &drc_clk.common.hw,
709 [CLK_GPU] = &gpu_clk.common.hw,
710 [CLK_ATS] = &ats_clk.common.hw,
711 },
712 .num = CLK_NUMBER,
713 };
714
715 static const struct ccu_reset_map sun8i_a33_ccu_resets[] = {
716 [RST_USB_PHY0] = { 0x0cc, BIT(0) },
717 [RST_USB_PHY1] = { 0x0cc, BIT(1) },
718 [RST_USB_HSIC] = { 0x0cc, BIT(2) },
719
720 [RST_MBUS] = { 0x0fc, BIT(31) },
721
722 [RST_BUS_MIPI_DSI] = { 0x2c0, BIT(1) },
723 [RST_BUS_SS] = { 0x2c0, BIT(5) },
724 [RST_BUS_DMA] = { 0x2c0, BIT(6) },
725 [RST_BUS_MMC0] = { 0x2c0, BIT(8) },
726 [RST_BUS_MMC1] = { 0x2c0, BIT(9) },
727 [RST_BUS_MMC2] = { 0x2c0, BIT(10) },
728 [RST_BUS_NAND] = { 0x2c0, BIT(13) },
729 [RST_BUS_DRAM] = { 0x2c0, BIT(14) },
730 [RST_BUS_HSTIMER] = { 0x2c0, BIT(19) },
731 [RST_BUS_SPI0] = { 0x2c0, BIT(20) },
732 [RST_BUS_SPI1] = { 0x2c0, BIT(21) },
733 [RST_BUS_OTG] = { 0x2c0, BIT(24) },
734 [RST_BUS_EHCI] = { 0x2c0, BIT(26) },
735 [RST_BUS_OHCI] = { 0x2c0, BIT(29) },
736
737 [RST_BUS_VE] = { 0x2c4, BIT(0) },
738 [RST_BUS_LCD] = { 0x2c4, BIT(4) },
739 [RST_BUS_CSI] = { 0x2c4, BIT(8) },
740 [RST_BUS_DE_BE] = { 0x2c4, BIT(12) },
741 [RST_BUS_DE_FE] = { 0x2c4, BIT(14) },
742 [RST_BUS_GPU] = { 0x2c4, BIT(20) },
743 [RST_BUS_MSGBOX] = { 0x2c4, BIT(21) },
744 [RST_BUS_SPINLOCK] = { 0x2c4, BIT(22) },
745 [RST_BUS_DRC] = { 0x2c4, BIT(25) },
746 [RST_BUS_SAT] = { 0x2c4, BIT(26) },
747
748 [RST_BUS_LVDS] = { 0x2c8, BIT(0) },
749
750 [RST_BUS_CODEC] = { 0x2d0, BIT(0) },
751 [RST_BUS_I2S0] = { 0x2d0, BIT(12) },
752 [RST_BUS_I2S1] = { 0x2d0, BIT(13) },
753
754 [RST_BUS_I2C0] = { 0x2d8, BIT(0) },
755 [RST_BUS_I2C1] = { 0x2d8, BIT(1) },
756 [RST_BUS_I2C2] = { 0x2d8, BIT(2) },
757 [RST_BUS_UART0] = { 0x2d8, BIT(16) },
758 [RST_BUS_UART1] = { 0x2d8, BIT(17) },
759 [RST_BUS_UART2] = { 0x2d8, BIT(18) },
760 [RST_BUS_UART3] = { 0x2d8, BIT(19) },
761 [RST_BUS_UART4] = { 0x2d8, BIT(20) },
762 };
763
764 static const struct sunxi_ccu_desc sun8i_a33_ccu_desc = {
765 .ccu_clks = sun8i_a33_ccu_clks,
766 .num_ccu_clks = ARRAY_SIZE(sun8i_a33_ccu_clks),
767
768 .hw_clks = &sun8i_a33_hw_clks,
769
770 .resets = sun8i_a33_ccu_resets,
771 .num_resets = ARRAY_SIZE(sun8i_a33_ccu_resets),
772 };
773
774 static struct ccu_pll_nb sun8i_a33_pll_cpu_nb = {
775 .common = &pll_cpux_clk.common,
776 /* copy from pll_cpux_clk */
777 .enable = BIT(31),
778 .lock = BIT(28),
779 };
780
781 static struct ccu_mux_nb sun8i_a33_cpu_nb = {
782 .common = &cpux_clk.common,
783 .cm = &cpux_clk.mux,
784 .delay_us = 1, /* > 8 clock cycles at 24 MHz */
785 .bypass_index = 1, /* index of 24 MHz oscillator */
786 };
787
sun8i_a33_ccu_probe(struct platform_device * pdev)788 static int sun8i_a33_ccu_probe(struct platform_device *pdev)
789 {
790 void __iomem *reg;
791 int ret;
792 u32 val;
793
794 reg = devm_platform_ioremap_resource(pdev, 0);
795 if (IS_ERR(reg))
796 return PTR_ERR(reg);
797
798 /* Force the PLL-Audio-1x divider to 1 */
799 val = readl(reg + SUN8I_A33_PLL_AUDIO_REG);
800 val &= ~GENMASK(19, 16);
801 writel(val | (0 << 16), reg + SUN8I_A33_PLL_AUDIO_REG);
802
803 /* Force PLL-MIPI to MIPI mode */
804 val = readl(reg + SUN8I_A33_PLL_MIPI_REG);
805 val &= ~BIT(16);
806 writel(val, reg + SUN8I_A33_PLL_MIPI_REG);
807
808 ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun8i_a33_ccu_desc);
809 if (ret)
810 return ret;
811
812 /* Gate then ungate PLL CPU after any rate changes */
813 ccu_pll_notifier_register(&sun8i_a33_pll_cpu_nb);
814
815 /* Reparent CPU during PLL CPU rate changes */
816 ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
817 &sun8i_a33_cpu_nb);
818
819 return 0;
820 }
821
822 static const struct of_device_id sun8i_a33_ccu_ids[] = {
823 { .compatible = "allwinner,sun8i-a33-ccu" },
824 { }
825 };
826 MODULE_DEVICE_TABLE(of, sun8i_a33_ccu_ids);
827
828 static struct platform_driver sun8i_a33_ccu_driver = {
829 .probe = sun8i_a33_ccu_probe,
830 .driver = {
831 .name = "sun8i-a33-ccu",
832 .suppress_bind_attrs = true,
833 .of_match_table = sun8i_a33_ccu_ids,
834 },
835 };
836 module_platform_driver(sun8i_a33_ccu_driver);
837
838 MODULE_IMPORT_NS("SUNXI_CCU");
839 MODULE_DESCRIPTION("Support for the Allwinner A33 CCU");
840 MODULE_LICENSE("GPL");
841