xref: /linux/arch/powerpc/platforms/85xx/stx_gp3.c (revision a1c613ae4c322ddd58d5a8539dbfba2a0380a8c0)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Based on MPC8560 ADS and arch/ppc stx_gp3 ports
4  *
5  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
6  *
7  * Copyright 2008 Freescale Semiconductor Inc.
8  *
9  * Dan Malek <dan@embeddededge.com>
10  * Copyright 2004 Embedded Edge, LLC
11  *
12  * Copied from mpc8560_ads.c
13  * Copyright 2002, 2003 Motorola Inc.
14  *
15  * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
16  * Copyright 2004-2005 MontaVista Software, Inc.
17  */
18 
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/delay.h>
24 #include <linux/seq_file.h>
25 #include <linux/of.h>
26 
27 #include <asm/time.h>
28 #include <asm/machdep.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/mpic.h>
31 #include <mm/mmu_decl.h>
32 #include <asm/udbg.h>
33 
34 #include <sysdev/fsl_soc.h>
35 #include <sysdev/fsl_pci.h>
36 
37 #include "mpc85xx.h"
38 
39 #ifdef CONFIG_CPM2
40 #include <asm/cpm2.h>
41 #endif /* CONFIG_CPM2 */
42 
stx_gp3_pic_init(void)43 static void __init stx_gp3_pic_init(void)
44 {
45 	struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
46 			0, 256, " OpenPIC  ");
47 	BUG_ON(mpic == NULL);
48 	mpic_init(mpic);
49 
50 	mpc85xx_cpm2_pic_init();
51 }
52 
53 /*
54  * Setup the architecture
55  */
stx_gp3_setup_arch(void)56 static void __init stx_gp3_setup_arch(void)
57 {
58 	if (ppc_md.progress)
59 		ppc_md.progress("stx_gp3_setup_arch()", 0);
60 
61 	fsl_pci_assign_primary();
62 
63 #ifdef CONFIG_CPM2
64 	cpm2_reset();
65 #endif
66 }
67 
stx_gp3_show_cpuinfo(struct seq_file * m)68 static void stx_gp3_show_cpuinfo(struct seq_file *m)
69 {
70 	uint pvid, svid, phid1;
71 
72 	pvid = mfspr(SPRN_PVR);
73 	svid = mfspr(SPRN_SVR);
74 
75 	seq_printf(m, "Vendor\t\t: RPC Electronics STx\n");
76 	seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
77 	seq_printf(m, "SVR\t\t: 0x%x\n", svid);
78 
79 	/* Display cpu Pll setting */
80 	phid1 = mfspr(SPRN_HID1);
81 	seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
82 }
83 
84 machine_arch_initcall(stx_gp3, mpc85xx_common_publish_devices);
85 
define_machine(stx_gp3)86 define_machine(stx_gp3) {
87 	.name			= "STX GP3",
88 	.compatible		= "stx,gp3-8560",
89 	.setup_arch		= stx_gp3_setup_arch,
90 	.init_IRQ		= stx_gp3_pic_init,
91 	.show_cpuinfo		= stx_gp3_show_cpuinfo,
92 	.get_irq		= mpic_get_irq,
93 	.progress		= udbg_progress,
94 };
95