1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * AMD Platform Management Framework Driver 4 * 5 * Copyright (c) 2022, Advanced Micro Devices, Inc. 6 * All Rights Reserved. 7 * 8 * Author: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 9 */ 10 11 #ifndef PMF_H 12 #define PMF_H 13 14 #include <linux/acpi.h> 15 #include <linux/input.h> 16 #include <linux/platform_device.h> 17 #include <linux/platform_profile.h> 18 19 #define POLICY_BUF_MAX_SZ 0x4b000 20 #define POLICY_SIGN_COOKIE 0x31535024 21 #define POLICY_COOKIE_OFFSET 0x10 22 23 /* List of supported CPU ids */ 24 #define AMD_CPU_ID_RMB 0x14b5 25 #define AMD_CPU_ID_PS 0x14e8 26 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 27 #define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 28 29 struct cookie_header { 30 u32 sign; 31 u32 length; 32 } __packed; 33 34 /* APMF Functions */ 35 #define APMF_FUNC_VERIFY_INTERFACE 0 36 #define APMF_FUNC_GET_SYS_PARAMS 1 37 #define APMF_FUNC_SBIOS_REQUESTS 2 38 #define APMF_FUNC_SBIOS_HEARTBEAT 4 39 #define APMF_FUNC_AUTO_MODE 5 40 #define APMF_FUNC_SET_FAN_IDX 7 41 #define APMF_FUNC_OS_POWER_SLIDER_UPDATE 8 42 #define APMF_FUNC_STATIC_SLIDER_GRANULAR 9 43 #define APMF_FUNC_DYN_SLIDER_AC 11 44 #define APMF_FUNC_DYN_SLIDER_DC 12 45 #define APMF_FUNC_NOTIFY_SMART_PC_UPDATES 14 46 #define APMF_FUNC_SBIOS_HEARTBEAT_V2 16 47 48 /* Message Definitions */ 49 #define SET_SPL 0x03 /* SPL: Sustained Power Limit */ 50 #define SET_SPPT 0x05 /* SPPT: Slow Package Power Tracking */ 51 #define SET_FPPT 0x07 /* FPPT: Fast Package Power Tracking */ 52 #define GET_SPL 0x0B 53 #define GET_SPPT 0x0D 54 #define GET_FPPT 0x0F 55 #define SET_DRAM_ADDR_HIGH 0x14 56 #define SET_DRAM_ADDR_LOW 0x15 57 #define SET_TRANSFER_TABLE 0x16 58 #define SET_STT_MIN_LIMIT 0x18 /* STT: Skin Temperature Tracking */ 59 #define SET_STT_LIMIT_APU 0x19 60 #define SET_STT_LIMIT_HS2 0x1A 61 #define SET_SPPT_APU_ONLY 0x1D 62 #define GET_SPPT_APU_ONLY 0x1E 63 #define GET_STT_MIN_LIMIT 0x1F 64 #define GET_STT_LIMIT_APU 0x20 65 #define GET_STT_LIMIT_HS2 0x21 66 #define SET_P3T 0x23 /* P3T: Peak Package Power Limit */ 67 #define SET_PMF_PPT 0x25 68 #define SET_PMF_PPT_APU_ONLY 0x26 69 70 /* OS slider update notification */ 71 #define DC_BEST_PERF 0 72 #define DC_BETTER_PERF 1 73 #define DC_BATTERY_SAVER 3 74 #define AC_BEST_PERF 4 75 #define AC_BETTER_PERF 5 76 #define AC_BETTER_BATTERY 6 77 78 /* Fan Index for Auto Mode */ 79 #define FAN_INDEX_AUTO 0xFFFFFFFF 80 81 #define ARG_NONE 0 82 #define AVG_SAMPLE_SIZE 3 83 84 /* Policy Actions */ 85 #define PMF_POLICY_SPL 2 86 #define PMF_POLICY_SPPT 3 87 #define PMF_POLICY_FPPT 4 88 #define PMF_POLICY_SPPT_APU_ONLY 5 89 #define PMF_POLICY_STT_MIN 6 90 #define PMF_POLICY_STT_SKINTEMP_APU 7 91 #define PMF_POLICY_STT_SKINTEMP_HS2 8 92 #define PMF_POLICY_SYSTEM_STATE 9 93 #define PMF_POLICY_BIOS_OUTPUT_1 10 94 #define PMF_POLICY_BIOS_OUTPUT_2 11 95 #define PMF_POLICY_P3T 38 96 #define PMF_POLICY_PMF_PPT 54 97 #define PMF_POLICY_PMF_PPT_APU_ONLY 55 98 #define PMF_POLICY_BIOS_OUTPUT_3 57 99 #define PMF_POLICY_BIOS_OUTPUT_4 58 100 #define PMF_POLICY_BIOS_OUTPUT_5 59 101 #define PMF_POLICY_BIOS_OUTPUT_6 60 102 #define PMF_POLICY_BIOS_OUTPUT_7 61 103 #define PMF_POLICY_BIOS_OUTPUT_8 62 104 #define PMF_POLICY_BIOS_OUTPUT_9 63 105 #define PMF_POLICY_BIOS_OUTPUT_10 64 106 107 /* TA macros */ 108 #define PMF_TA_IF_VERSION_MAJOR 1 109 #define TA_PMF_ACTION_MAX 32 110 #define TA_PMF_UNDO_MAX 8 111 #define TA_OUTPUT_RESERVED_MEM 922 112 #define MAX_OPERATION_PARAMS 4 113 114 #define TA_ERROR_CRYPTO_INVALID_PARAM 0x20002 115 #define TA_ERROR_CRYPTO_BIN_TOO_LARGE 0x2000d 116 117 #define PMF_IF_V1 1 118 #define PMF_IF_V2 2 119 120 #define APTS_MAX_STATES 16 121 #define CUSTOM_BIOS_INPUT_BITS GENMASK(16, 7) 122 #define BIOS_INPUTS_MAX 10 123 124 /* amd_pmf_send_cmd() set/get */ 125 #define SET_CMD false 126 #define GET_CMD true 127 128 #define METRICS_TABLE_ID 7 129 130 typedef void (*apmf_event_handler_t)(acpi_handle handle, u32 event, void *data); 131 132 /* APTS PMF BIOS Interface */ 133 struct amd_pmf_apts_output { 134 u16 table_version; 135 u32 fan_table_idx; 136 u32 pmf_ppt; 137 u32 ppt_pmf_apu_only; 138 u32 stt_min_limit; 139 u8 stt_skin_temp_limit_apu; 140 u8 stt_skin_temp_limit_hs2; 141 } __packed; 142 143 struct amd_pmf_apts_granular_output { 144 u16 size; 145 struct amd_pmf_apts_output val; 146 } __packed; 147 148 struct amd_pmf_apts_granular { 149 u16 size; 150 struct amd_pmf_apts_output val[APTS_MAX_STATES]; 151 }; 152 153 struct sbios_hb_event_v2 { 154 u16 size; 155 u8 load; 156 u8 unload; 157 u8 suspend; 158 u8 resume; 159 } __packed; 160 161 enum sbios_hb_v2 { 162 ON_LOAD, 163 ON_UNLOAD, 164 ON_SUSPEND, 165 ON_RESUME, 166 }; 167 168 /* AMD PMF BIOS interfaces */ 169 struct apmf_verify_interface { 170 u16 size; 171 u16 version; 172 u32 notification_mask; 173 u32 supported_functions; 174 } __packed; 175 176 struct apmf_system_params { 177 u16 size; 178 u32 valid_mask; 179 u32 flags; 180 u8 command_code; 181 u32 heartbeat_int; 182 } __packed; 183 184 struct apmf_sbios_req { 185 u16 size; 186 u32 pending_req; 187 u8 rsd; 188 u8 cql_event; 189 u8 amt_event; 190 u32 fppt; 191 u32 sppt; 192 u32 fppt_apu_only; 193 u32 spl; 194 u32 stt_min_limit; 195 u8 skin_temp_apu; 196 u8 skin_temp_hs2; 197 } __packed; 198 199 /* As per APMF spec 1.3 */ 200 struct apmf_sbios_req_v1 { 201 u16 size; 202 u32 pending_req; 203 u8 rsvd; 204 u8 cql_event; 205 u8 amt_event; 206 u32 fppt; 207 u32 sppt; 208 u32 sppt_apu_only; 209 u32 spl; 210 u32 stt_min_limit; 211 u8 skin_temp_apu; 212 u8 skin_temp_hs2; 213 u8 enable_cnqf; 214 u32 custom_policy[BIOS_INPUTS_MAX]; 215 } __packed; 216 217 struct apmf_sbios_req_v2 { 218 u16 size; 219 u32 pending_req; 220 u8 rsd; 221 u32 ppt_pmf; 222 u32 ppt_pmf_apu_only; 223 u32 stt_min_limit; 224 u8 skin_temp_apu; 225 u8 skin_temp_hs2; 226 u32 custom_policy[BIOS_INPUTS_MAX]; 227 } __packed; 228 229 struct apmf_fan_idx { 230 u16 size; 231 u8 fan_ctl_mode; 232 u32 fan_ctl_idx; 233 } __packed; 234 235 struct smu_pmf_metrics_v2 { 236 u16 core_frequency[16]; /* MHz */ 237 u16 core_power[16]; /* mW */ 238 u16 core_temp[16]; /* centi-C */ 239 u16 gfx_temp; /* centi-C */ 240 u16 soc_temp; /* centi-C */ 241 u16 stapm_opn_limit; /* mW */ 242 u16 stapm_cur_limit; /* mW */ 243 u16 infra_cpu_maxfreq; /* MHz */ 244 u16 infra_gfx_maxfreq; /* MHz */ 245 u16 skin_temp; /* centi-C */ 246 u16 gfxclk_freq; /* MHz */ 247 u16 fclk_freq; /* MHz */ 248 u16 gfx_activity; /* GFX busy % [0-100] */ 249 u16 socclk_freq; /* MHz */ 250 u16 vclk_freq; /* MHz */ 251 u16 vcn_activity; /* VCN busy % [0-100] */ 252 u16 vpeclk_freq; /* MHz */ 253 u16 npuclk_freq; /* MHz */ 254 u16 npu_busy[8]; /* NPU busy % [0-100] */ 255 u16 dram_reads; /* MB/sec */ 256 u16 dram_writes; /* MB/sec */ 257 u16 core_c0residency[16]; /* C0 residency % [0-100] */ 258 u16 npu_power; /* mW */ 259 u32 apu_power; /* mW */ 260 u32 gfx_power; /* mW */ 261 u32 dgpu_power; /* mW */ 262 u32 socket_power; /* mW */ 263 u32 all_core_power; /* mW */ 264 u32 filter_alpha_value; /* time constant [us] */ 265 u32 metrics_counter; 266 u16 memclk_freq; /* MHz */ 267 u16 mpnpuclk_freq; /* MHz */ 268 u16 npu_reads; /* MB/sec */ 269 u16 npu_writes; /* MB/sec */ 270 u32 throttle_residency_prochot; 271 u32 throttle_residency_spl; 272 u32 throttle_residency_fppt; 273 u32 throttle_residency_sppt; 274 u32 throttle_residency_thm_core; 275 u32 throttle_residency_thm_gfx; 276 u32 throttle_residency_thm_soc; 277 u16 psys; 278 u16 spare1; 279 u32 spare[6]; 280 } __packed; 281 282 struct smu_pmf_metrics { 283 u16 gfxclk_freq; /* in MHz */ 284 u16 socclk_freq; /* in MHz */ 285 u16 vclk_freq; /* in MHz */ 286 u16 dclk_freq; /* in MHz */ 287 u16 memclk_freq; /* in MHz */ 288 u16 spare; 289 u16 gfx_activity; /* in Centi */ 290 u16 uvd_activity; /* in Centi */ 291 u16 voltage[2]; /* in mV */ 292 u16 currents[2]; /* in mA */ 293 u16 power[2];/* in mW */ 294 u16 core_freq[8]; /* in MHz */ 295 u16 core_power[8]; /* in mW */ 296 u16 core_temp[8]; /* in centi-Celsius */ 297 u16 l3_freq; /* in MHz */ 298 u16 l3_temp; /* in centi-Celsius */ 299 u16 gfx_temp; /* in centi-Celsius */ 300 u16 soc_temp; /* in centi-Celsius */ 301 u16 throttler_status; 302 u16 current_socketpower; /* in mW */ 303 u16 stapm_orig_limit; /* in W */ 304 u16 stapm_cur_limit; /* in W */ 305 u32 apu_power; /* in mW */ 306 u32 dgpu_power; /* in mW */ 307 u16 vdd_tdc_val; /* in mA */ 308 u16 soc_tdc_val; /* in mA */ 309 u16 vdd_edc_val; /* in mA */ 310 u16 soc_edcv_al; /* in mA */ 311 u16 infra_cpu_maxfreq; /* in MHz */ 312 u16 infra_gfx_maxfreq; /* in MHz */ 313 u16 skin_temp; /* in centi-Celsius */ 314 u16 device_state; 315 u16 curtemp; /* in centi-Celsius */ 316 u16 filter_alpha_value; 317 u16 avg_gfx_clkfrequency; 318 u16 avg_fclk_frequency; 319 u16 avg_gfx_activity; 320 u16 avg_socclk_frequency; 321 u16 avg_vclk_frequency; 322 u16 avg_vcn_activity; 323 u16 avg_dram_reads; 324 u16 avg_dram_writes; 325 u16 avg_socket_power; 326 u16 avg_core_power[2]; 327 u16 avg_core_c0residency[16]; 328 u16 spare1; 329 u32 metrics_counter; 330 } __packed; 331 332 enum amd_stt_skin_temp { 333 STT_TEMP_APU, 334 STT_TEMP_HS2, 335 STT_TEMP_COUNT, 336 }; 337 338 enum amd_slider_op { 339 SLIDER_OP_GET, 340 SLIDER_OP_SET, 341 }; 342 343 enum power_source { 344 POWER_SOURCE_AC, 345 POWER_SOURCE_DC, 346 POWER_SOURCE_MAX, 347 }; 348 349 enum power_modes { 350 POWER_MODE_PERFORMANCE, 351 POWER_MODE_BALANCED_POWER, 352 POWER_MODE_POWER_SAVER, 353 POWER_MODE_MAX, 354 }; 355 356 enum power_modes_v2 { 357 POWER_MODE_BEST_PERFORMANCE, 358 POWER_MODE_BALANCED, 359 POWER_MODE_BEST_POWER_EFFICIENCY, 360 POWER_MODE_ENERGY_SAVE, 361 POWER_MODE_V2_MAX, 362 }; 363 364 struct pmf_bios_inputs_prev { 365 u32 custom_bios_inputs[BIOS_INPUTS_MAX]; 366 }; 367 368 struct amd_pmf_dev { 369 void __iomem *regbase; 370 void __iomem *smu_virt_addr; 371 void *buf; 372 u32 base_addr; 373 u32 cpu_id; 374 struct device *dev; 375 struct mutex lock; /* protects the PMF interface */ 376 u32 supported_func; 377 enum platform_profile_option current_profile; 378 struct device *ppdev; /* platform profile class device */ 379 struct dentry *dbgfs_dir; 380 int hb_interval; /* SBIOS heartbeat interval */ 381 struct delayed_work heart_beat; 382 struct smu_pmf_metrics m_table; 383 struct smu_pmf_metrics_v2 m_table_v2; 384 struct delayed_work work_buffer; 385 ktime_t start_time; 386 int socket_power_history[AVG_SAMPLE_SIZE]; 387 int socket_power_history_idx; 388 bool amt_enabled; 389 struct mutex update_mutex; /* protects race between ACPI handler and metrics thread */ 390 bool cnqf_enabled; 391 bool cnqf_supported; 392 struct notifier_block pwr_src_notifier; 393 /* Smart PC solution builder */ 394 struct dentry *esbin; 395 unsigned char *policy_buf; 396 resource_size_t policy_sz; 397 struct tee_context *tee_ctx; 398 struct tee_shm *fw_shm_pool; 399 u32 session_id; 400 void *shbuf; 401 struct delayed_work pb_work; 402 struct pmf_action_table *prev_data; 403 resource_size_t policy_addr; 404 void __iomem *policy_base; 405 bool smart_pc_enabled; 406 u16 pmf_if_version; 407 struct input_dev *pmf_idev; 408 size_t mtable_size; 409 struct resource *res; 410 struct apmf_sbios_req_v2 req; /* To get custom bios pending request */ 411 struct mutex cb_mutex; 412 u32 notifications; 413 struct apmf_sbios_req_v1 req1; 414 struct pmf_bios_inputs_prev cb_prev; /* To preserve custom BIOS inputs */ 415 bool cb_flag; /* To handle first custom BIOS input */ 416 }; 417 418 struct apmf_sps_prop_granular_v2 { 419 u8 power_states[POWER_SOURCE_MAX][POWER_MODE_V2_MAX]; 420 } __packed; 421 422 struct apmf_sps_prop_granular { 423 u32 fppt; 424 u32 sppt; 425 u32 sppt_apu_only; 426 u32 spl; 427 u32 stt_min; 428 u8 stt_skin_temp[STT_TEMP_COUNT]; 429 u32 fan_id; 430 } __packed; 431 432 /* Static Slider */ 433 struct apmf_static_slider_granular_output { 434 u16 size; 435 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX * POWER_MODE_MAX]; 436 } __packed; 437 438 struct amd_pmf_static_slider_granular { 439 u16 size; 440 struct apmf_sps_prop_granular prop[POWER_SOURCE_MAX][POWER_MODE_MAX]; 441 }; 442 443 struct apmf_static_slider_granular_output_v2 { 444 u16 size; 445 struct apmf_sps_prop_granular_v2 sps_idx; 446 } __packed; 447 448 struct amd_pmf_static_slider_granular_v2 { 449 u16 size; 450 struct apmf_sps_prop_granular_v2 sps_idx; 451 }; 452 453 struct os_power_slider { 454 u16 size; 455 u8 slider_event; 456 } __packed; 457 458 struct amd_pmf_notify_smart_pc_update { 459 u16 size; 460 u32 pending_req; 461 u32 custom_bios[BIOS_INPUTS_MAX]; 462 } __packed; 463 464 struct fan_table_control { 465 bool manual; 466 unsigned long fan_id; 467 }; 468 469 struct power_table_control { 470 u32 spl; 471 u32 sppt; 472 u32 fppt; 473 u32 sppt_apu_only; 474 u32 stt_min; 475 u32 stt_skin_temp[STT_TEMP_COUNT]; 476 u32 reserved[16]; 477 }; 478 479 /* Auto Mode Layer */ 480 enum auto_mode_transition_priority { 481 AUTO_TRANSITION_TO_PERFORMANCE, /* Any other mode to Performance Mode */ 482 AUTO_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 483 AUTO_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 484 AUTO_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance Mode to Balance Mode */ 485 AUTO_TRANSITION_MAX, 486 }; 487 488 enum auto_mode_mode { 489 AUTO_QUIET, 490 AUTO_BALANCE, 491 AUTO_PERFORMANCE_ON_LAP, 492 AUTO_PERFORMANCE, 493 AUTO_MODE_MAX, 494 }; 495 496 struct auto_mode_trans_params { 497 u32 time_constant; /* minimum time required to switch to next mode */ 498 u32 power_delta; /* delta power to shift mode */ 499 u32 power_threshold; 500 u32 timer; /* elapsed time. if timer > TimeThreshold, it will move to next mode */ 501 u32 applied; 502 enum auto_mode_mode target_mode; 503 u32 shifting_up; 504 }; 505 506 struct auto_mode_mode_settings { 507 struct power_table_control power_control; 508 struct fan_table_control fan_control; 509 u32 power_floor; 510 }; 511 512 struct auto_mode_mode_config { 513 struct auto_mode_trans_params transition[AUTO_TRANSITION_MAX]; 514 struct auto_mode_mode_settings mode_set[AUTO_MODE_MAX]; 515 enum auto_mode_mode current_mode; 516 }; 517 518 struct apmf_auto_mode { 519 u16 size; 520 /* time constant */ 521 u32 balanced_to_perf; 522 u32 perf_to_balanced; 523 u32 quiet_to_balanced; 524 u32 balanced_to_quiet; 525 /* power floor */ 526 u32 pfloor_perf; 527 u32 pfloor_balanced; 528 u32 pfloor_quiet; 529 /* Power delta for mode change */ 530 u32 pd_balanced_to_perf; 531 u32 pd_perf_to_balanced; 532 u32 pd_quiet_to_balanced; 533 u32 pd_balanced_to_quiet; 534 /* skin temperature limits */ 535 u8 stt_apu_perf_on_lap; /* CQL ON */ 536 u8 stt_hs2_perf_on_lap; /* CQL ON */ 537 u8 stt_apu_perf; 538 u8 stt_hs2_perf; 539 u8 stt_apu_balanced; 540 u8 stt_hs2_balanced; 541 u8 stt_apu_quiet; 542 u8 stt_hs2_quiet; 543 u32 stt_min_limit_perf_on_lap; /* CQL ON */ 544 u32 stt_min_limit_perf; 545 u32 stt_min_limit_balanced; 546 u32 stt_min_limit_quiet; 547 /* SPL based */ 548 u32 fppt_perf_on_lap; /* CQL ON */ 549 u32 sppt_perf_on_lap; /* CQL ON */ 550 u32 spl_perf_on_lap; /* CQL ON */ 551 u32 sppt_apu_only_perf_on_lap; /* CQL ON */ 552 u32 fppt_perf; 553 u32 sppt_perf; 554 u32 spl_perf; 555 u32 sppt_apu_only_perf; 556 u32 fppt_balanced; 557 u32 sppt_balanced; 558 u32 spl_balanced; 559 u32 sppt_apu_only_balanced; 560 u32 fppt_quiet; 561 u32 sppt_quiet; 562 u32 spl_quiet; 563 u32 sppt_apu_only_quiet; 564 /* Fan ID */ 565 u32 fan_id_perf; 566 u32 fan_id_balanced; 567 u32 fan_id_quiet; 568 } __packed; 569 570 /* CnQF Layer */ 571 enum cnqf_trans_priority { 572 CNQF_TRANSITION_TO_TURBO, /* Any other mode to Turbo Mode */ 573 CNQF_TRANSITION_FROM_BALANCE_TO_PERFORMANCE, /* quiet/balance to Performance Mode */ 574 CNQF_TRANSITION_FROM_QUIET_TO_BALANCE, /* Quiet Mode to Balance Mode */ 575 CNQF_TRANSITION_TO_QUIET, /* Any other mode to Quiet Mode */ 576 CNQF_TRANSITION_FROM_PERFORMANCE_TO_BALANCE, /* Performance/Turbo to Balance Mode */ 577 CNQF_TRANSITION_FROM_TURBO_TO_PERFORMANCE, /* Turbo mode to Performance Mode */ 578 CNQF_TRANSITION_MAX, 579 }; 580 581 enum cnqf_mode { 582 CNQF_MODE_QUIET, 583 CNQF_MODE_BALANCE, 584 CNQF_MODE_PERFORMANCE, 585 CNQF_MODE_TURBO, 586 CNQF_MODE_MAX, 587 }; 588 589 enum apmf_cnqf_pos { 590 APMF_CNQF_TURBO, 591 APMF_CNQF_PERFORMANCE, 592 APMF_CNQF_BALANCE, 593 APMF_CNQF_QUIET, 594 APMF_CNQF_MAX, 595 }; 596 597 struct cnqf_mode_settings { 598 struct power_table_control power_control; 599 struct fan_table_control fan_control; 600 u32 power_floor; 601 }; 602 603 struct cnqf_tran_params { 604 u32 time_constant; /* minimum time required to switch to next mode */ 605 u32 power_threshold; 606 u32 timer; /* elapsed time. if timer > timethreshold, it will move to next mode */ 607 u32 total_power; 608 u32 count; 609 bool priority; 610 bool shifting_up; 611 enum cnqf_mode target_mode; 612 }; 613 614 struct cnqf_config { 615 struct cnqf_tran_params trans_param[POWER_SOURCE_MAX][CNQF_TRANSITION_MAX]; 616 struct cnqf_mode_settings mode_set[POWER_SOURCE_MAX][CNQF_MODE_MAX]; 617 struct power_table_control defaults; 618 enum cnqf_mode current_mode; 619 u32 power_src; 620 u32 avg_power; 621 }; 622 623 struct apmf_cnqf_power_set { 624 u32 pfloor; 625 u32 fppt; 626 u32 sppt; 627 u32 sppt_apu_only; 628 u32 spl; 629 u32 stt_min_limit; 630 u8 stt_skintemp[STT_TEMP_COUNT]; 631 u32 fan_id; 632 } __packed; 633 634 struct apmf_dyn_slider_output { 635 u16 size; 636 u16 flags; 637 u32 t_perf_to_turbo; 638 u32 t_balanced_to_perf; 639 u32 t_quiet_to_balanced; 640 u32 t_balanced_to_quiet; 641 u32 t_perf_to_balanced; 642 u32 t_turbo_to_perf; 643 struct apmf_cnqf_power_set ps[APMF_CNQF_MAX]; 644 } __packed; 645 646 /* Smart PC - TA internals */ 647 enum system_state { 648 SYSTEM_STATE_S0i3, 649 SYSTEM_STATE_S4, 650 SYSTEM_STATE_SCREEN_LOCK, 651 SYSTEM_STATE_MAX, 652 }; 653 654 enum ta_slider { 655 TA_BEST_BATTERY, 656 TA_BETTER_BATTERY, 657 TA_BETTER_PERFORMANCE, 658 TA_BEST_PERFORMANCE, 659 TA_MAX, 660 }; 661 662 struct amd_pmf_pb_bitmap { 663 const char *name; 664 u32 bit_mask; 665 }; 666 667 static const struct amd_pmf_pb_bitmap custom_bios_inputs[] __used = { 668 {"NOTIFY_CUSTOM_BIOS_INPUT1", BIT(5)}, 669 {"NOTIFY_CUSTOM_BIOS_INPUT2", BIT(6)}, 670 {"NOTIFY_CUSTOM_BIOS_INPUT3", BIT(7)}, 671 {"NOTIFY_CUSTOM_BIOS_INPUT4", BIT(8)}, 672 {"NOTIFY_CUSTOM_BIOS_INPUT5", BIT(9)}, 673 {"NOTIFY_CUSTOM_BIOS_INPUT6", BIT(10)}, 674 {"NOTIFY_CUSTOM_BIOS_INPUT7", BIT(11)}, 675 {"NOTIFY_CUSTOM_BIOS_INPUT8", BIT(12)}, 676 {"NOTIFY_CUSTOM_BIOS_INPUT9", BIT(13)}, 677 {"NOTIFY_CUSTOM_BIOS_INPUT10", BIT(14)}, 678 }; 679 680 static const struct amd_pmf_pb_bitmap custom_bios_inputs_v1[] __used = { 681 {"NOTIFY_CUSTOM_BIOS_INPUT1", BIT(7)}, 682 {"NOTIFY_CUSTOM_BIOS_INPUT2", BIT(8)}, 683 {"NOTIFY_CUSTOM_BIOS_INPUT3", BIT(9)}, 684 {"NOTIFY_CUSTOM_BIOS_INPUT4", BIT(10)}, 685 {"NOTIFY_CUSTOM_BIOS_INPUT5", BIT(11)}, 686 {"NOTIFY_CUSTOM_BIOS_INPUT6", BIT(12)}, 687 {"NOTIFY_CUSTOM_BIOS_INPUT7", BIT(13)}, 688 {"NOTIFY_CUSTOM_BIOS_INPUT8", BIT(14)}, 689 {"NOTIFY_CUSTOM_BIOS_INPUT9", BIT(15)}, 690 {"NOTIFY_CUSTOM_BIOS_INPUT10", BIT(16)}, 691 }; 692 693 enum platform_type { 694 PTYPE_UNKNOWN = 0, 695 LID_CLOSE, 696 CLAMSHELL, 697 FLAT, 698 TENT, 699 STAND, 700 TABLET, 701 BOOK, 702 PRESENTATION, 703 PULL_FWD, 704 PTYPE_INVALID = 0xf, 705 }; 706 707 /* Command ids for TA communication */ 708 enum ta_pmf_command { 709 TA_PMF_COMMAND_POLICY_BUILDER_INITIALIZE, 710 TA_PMF_COMMAND_POLICY_BUILDER_ENACT_POLICIES, 711 }; 712 713 enum ta_pmf_error_type { 714 TA_PMF_TYPE_SUCCESS, 715 TA_PMF_ERROR_TYPE_GENERIC, 716 TA_PMF_ERROR_TYPE_CRYPTO, 717 TA_PMF_ERROR_TYPE_CRYPTO_VALIDATE, 718 TA_PMF_ERROR_TYPE_CRYPTO_VERIFY_OEM, 719 TA_PMF_ERROR_TYPE_POLICY_BUILDER, 720 TA_PMF_ERROR_TYPE_PB_CONVERT, 721 TA_PMF_ERROR_TYPE_PB_SETUP, 722 TA_PMF_ERROR_TYPE_PB_ENACT, 723 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_INFO, 724 TA_PMF_ERROR_TYPE_ASD_GET_DEVICE_PCIE_INFO, 725 TA_PMF_ERROR_TYPE_SYS_DRV_FW_VALIDATION, 726 TA_PMF_ERROR_TYPE_MAX, 727 }; 728 729 struct pmf_action_table { 730 enum system_state system_state; 731 u32 spl; /* in mW */ 732 u32 sppt; /* in mW */ 733 u32 sppt_apuonly; /* in mW */ 734 u32 fppt; /* in mW */ 735 u32 stt_minlimit; /* in mW */ 736 u32 stt_skintemp_apu; /* in C */ 737 u32 stt_skintemp_hs2; /* in C */ 738 u32 p3t_limit; /* in mW */ 739 u32 pmf_ppt; /* in mW */ 740 u32 pmf_ppt_apu_only; /* in mW */ 741 }; 742 743 /* Input conditions */ 744 struct ta_pmf_condition_info { 745 u32 power_source; 746 u32 bat_percentage; 747 u32 power_slider; 748 u32 lid_state; 749 bool user_present; 750 u32 bios_input_1[2]; 751 u32 monitor_count; 752 u32 rsvd2[2]; 753 u32 bat_design; 754 u32 full_charge_capacity; 755 int drain_rate; 756 bool user_engaged; 757 u32 device_state; 758 u32 socket_power; 759 u32 skin_temperature; 760 u32 rsvd3[2]; 761 u32 platform_type; 762 u32 rsvd3_1[2]; 763 u32 ambient_light; 764 u32 length; 765 u32 avg_c0residency; 766 u32 max_c0residency; 767 u32 s0i3_entry; 768 u32 gfx_busy; 769 u32 rsvd4[7]; 770 bool camera_state; 771 u32 workload_type; 772 u32 display_type; 773 u32 display_state; 774 u32 rsvd5_1[17]; 775 u32 bios_input_2[8]; 776 u32 rsvd5[125]; 777 }; 778 779 struct ta_pmf_load_policy_table { 780 u32 table_size; 781 u8 table[POLICY_BUF_MAX_SZ]; 782 }; 783 784 /* TA initialization params */ 785 struct ta_pmf_init_table { 786 u32 frequency; /* SMU sampling frequency */ 787 bool validate; 788 bool sku_check; 789 bool metadata_macrocheck; 790 struct ta_pmf_load_policy_table policies_table; 791 }; 792 793 /* Everything the TA needs to Enact Policies */ 794 struct ta_pmf_enact_table { 795 struct ta_pmf_condition_info ev_info; 796 u32 name; 797 }; 798 799 struct ta_pmf_action { 800 u32 action_index; 801 u32 value; 802 u32 spl_arg; 803 }; 804 805 /* Output actions from TA */ 806 struct ta_pmf_enact_result { 807 u32 actions_count; 808 struct ta_pmf_action actions_list[TA_PMF_ACTION_MAX]; 809 u32 undo_count; 810 struct ta_pmf_action undo_list[TA_PMF_UNDO_MAX]; 811 }; 812 813 union ta_pmf_input { 814 struct ta_pmf_enact_table enact_table; 815 struct ta_pmf_init_table init_table; 816 }; 817 818 union ta_pmf_output { 819 struct ta_pmf_enact_result policy_apply_table; 820 u32 rsvd[TA_OUTPUT_RESERVED_MEM]; 821 }; 822 823 struct ta_pmf_shared_memory { 824 int command_id; 825 int resp_id; 826 u32 pmf_result; 827 u32 if_version; 828 union ta_pmf_output pmf_output; 829 union ta_pmf_input pmf_input; 830 }; 831 832 /* Core Layer */ 833 int apmf_acpi_init(struct amd_pmf_dev *pmf_dev); 834 void apmf_acpi_deinit(struct amd_pmf_dev *pmf_dev); 835 int is_apmf_func_supported(struct amd_pmf_dev *pdev, unsigned long index); 836 int amd_pmf_send_cmd(struct amd_pmf_dev *dev, u8 message, bool get, u32 arg, u32 *data); 837 int amd_pmf_init_metrics_table(struct amd_pmf_dev *dev); 838 int amd_pmf_get_power_source(void); 839 int apmf_install_handler(struct amd_pmf_dev *pmf_dev); 840 int apmf_os_power_slider_update(struct amd_pmf_dev *dev, u8 flag); 841 int amd_pmf_set_dram_addr(struct amd_pmf_dev *dev, bool alloc_buffer); 842 int amd_pmf_notify_sbios_heartbeat_event_v2(struct amd_pmf_dev *dev, u8 flag); 843 u32 fixp_q88_fromint(u32 val); 844 int is_apmf_bios_input_notifications_supported(struct amd_pmf_dev *pdev); 845 846 /* SPS Layer */ 847 int amd_pmf_get_pprof_modes(struct amd_pmf_dev *pmf); 848 void amd_pmf_update_slider(struct amd_pmf_dev *dev, bool op, int idx, 849 struct amd_pmf_static_slider_granular *table); 850 int amd_pmf_init_sps(struct amd_pmf_dev *dev); 851 int apmf_get_static_slider_granular(struct amd_pmf_dev *pdev, 852 struct apmf_static_slider_granular_output *output); 853 bool is_pprof_balanced(struct amd_pmf_dev *pmf); 854 int amd_pmf_power_slider_update_event(struct amd_pmf_dev *dev); 855 const char *amd_pmf_source_as_str(unsigned int state); 856 857 const char *amd_pmf_source_as_str(unsigned int state); 858 859 int apmf_update_fan_idx(struct amd_pmf_dev *pdev, bool manual, u32 idx); 860 int amd_pmf_set_sps_power_limits(struct amd_pmf_dev *pmf); 861 int apmf_get_static_slider_granular_v2(struct amd_pmf_dev *dev, 862 struct apmf_static_slider_granular_output_v2 *data); 863 int apts_get_static_slider_granular_v2(struct amd_pmf_dev *pdev, 864 struct amd_pmf_apts_granular_output *data, u32 apts_idx); 865 866 /* Auto Mode Layer */ 867 int apmf_get_auto_mode_def(struct amd_pmf_dev *pdev, struct apmf_auto_mode *data); 868 void amd_pmf_init_auto_mode(struct amd_pmf_dev *dev); 869 void amd_pmf_deinit_auto_mode(struct amd_pmf_dev *dev); 870 void amd_pmf_trans_automode(struct amd_pmf_dev *dev, int socket_power, ktime_t time_elapsed_ms); 871 int apmf_get_sbios_requests(struct amd_pmf_dev *pdev, struct apmf_sbios_req *req); 872 int apmf_get_sbios_requests_v1(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v1 *req); 873 int apmf_get_sbios_requests_v2(struct amd_pmf_dev *pdev, struct apmf_sbios_req_v2 *req); 874 875 void amd_pmf_update_2_cql(struct amd_pmf_dev *dev, bool is_cql_event); 876 int amd_pmf_reset_amt(struct amd_pmf_dev *dev); 877 void amd_pmf_handle_amt(struct amd_pmf_dev *dev); 878 879 /* CnQF Layer */ 880 int apmf_get_dyn_slider_def_ac(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 881 int apmf_get_dyn_slider_def_dc(struct amd_pmf_dev *pdev, struct apmf_dyn_slider_output *data); 882 int amd_pmf_init_cnqf(struct amd_pmf_dev *dev); 883 void amd_pmf_deinit_cnqf(struct amd_pmf_dev *dev); 884 int amd_pmf_trans_cnqf(struct amd_pmf_dev *dev, int socket_power, ktime_t time_lapsed_ms); 885 extern const struct attribute_group cnqf_feature_attribute_group; 886 887 /* Smart PC builder Layer */ 888 int amd_pmf_init_smart_pc(struct amd_pmf_dev *dev); 889 void amd_pmf_deinit_smart_pc(struct amd_pmf_dev *dev); 890 int apmf_check_smart_pc(struct amd_pmf_dev *pmf_dev); 891 int amd_pmf_smartpc_apply_bios_output(struct amd_pmf_dev *dev, u32 val, u32 preq, u32 idx); 892 893 /* Smart PC - TA interfaces */ 894 void amd_pmf_populate_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 895 void amd_pmf_dump_ta_inputs(struct amd_pmf_dev *dev, struct ta_pmf_enact_table *in); 896 int amd_pmf_invoke_cmd_enact(struct amd_pmf_dev *dev); 897 898 #endif /* PMF_H */ 899