xref: /linux/drivers/pci/controller/dwc/pcie-stm32.c (revision 2f2c7254931f41b5736e3ba12aaa9ac1bbeeeb92)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * STMicroelectronics STM32MP25 PCIe root complex driver.
4  *
5  * Copyright (C) 2025 STMicroelectronics
6  * Author: Christian Bruel <christian.bruel@foss.st.com>
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/mfd/syscon.h>
11 #include <linux/of_platform.h>
12 #include <linux/phy/phy.h>
13 #include <linux/pinctrl/consumer.h>
14 #include <linux/platform_device.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/pm_wakeirq.h>
17 #include <linux/regmap.h>
18 #include <linux/reset.h>
19 #include "pcie-designware.h"
20 #include "pcie-stm32.h"
21 #include "../../pci.h"
22 
23 struct stm32_pcie {
24 	struct dw_pcie pci;
25 	struct regmap *regmap;
26 	struct reset_control *rst;
27 	struct phy *phy;
28 	struct clk *clk;
29 	struct gpio_desc *perst_gpio;
30 	struct gpio_desc *wake_gpio;
31 };
32 
stm32_pcie_deassert_perst(struct stm32_pcie * stm32_pcie)33 static void stm32_pcie_deassert_perst(struct stm32_pcie *stm32_pcie)
34 {
35 	if (stm32_pcie->perst_gpio) {
36 		msleep(PCIE_T_PVPERL_MS);
37 		gpiod_set_value(stm32_pcie->perst_gpio, 0);
38 	}
39 
40 	msleep(PCIE_RESET_CONFIG_WAIT_MS);
41 }
42 
stm32_pcie_assert_perst(struct stm32_pcie * stm32_pcie)43 static void stm32_pcie_assert_perst(struct stm32_pcie *stm32_pcie)
44 {
45 	gpiod_set_value(stm32_pcie->perst_gpio, 1);
46 }
47 
stm32_pcie_start_link(struct dw_pcie * pci)48 static int stm32_pcie_start_link(struct dw_pcie *pci)
49 {
50 	struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci);
51 
52 	return regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR,
53 				  STM32MP25_PCIECR_LTSSM_EN,
54 				  STM32MP25_PCIECR_LTSSM_EN);
55 }
56 
stm32_pcie_stop_link(struct dw_pcie * pci)57 static void stm32_pcie_stop_link(struct dw_pcie *pci)
58 {
59 	struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci);
60 
61 	regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR,
62 			   STM32MP25_PCIECR_LTSSM_EN, 0);
63 }
64 
stm32_pcie_suspend_noirq(struct device * dev)65 static int stm32_pcie_suspend_noirq(struct device *dev)
66 {
67 	struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev);
68 	int ret;
69 
70 	ret = dw_pcie_suspend_noirq(&stm32_pcie->pci);
71 	if (ret)
72 		return ret;
73 
74 	stm32_pcie_assert_perst(stm32_pcie);
75 
76 	clk_disable_unprepare(stm32_pcie->clk);
77 
78 	if (!device_wakeup_path(dev))
79 		phy_exit(stm32_pcie->phy);
80 
81 	return pinctrl_pm_select_sleep_state(dev);
82 }
83 
stm32_pcie_resume_noirq(struct device * dev)84 static int stm32_pcie_resume_noirq(struct device *dev)
85 {
86 	struct stm32_pcie *stm32_pcie = dev_get_drvdata(dev);
87 	int ret;
88 
89 	/*
90 	 * The core clock is gated with CLKREQ# from the COMBOPHY REFCLK,
91 	 * thus if no device is present, must deassert it with a GPIO from
92 	 * pinctrl pinmux before accessing the DBI registers.
93 	 */
94 	ret = pinctrl_pm_select_init_state(dev);
95 	if (ret) {
96 		dev_err(dev, "Failed to activate pinctrl pm state: %d\n", ret);
97 		return ret;
98 	}
99 
100 	if (!device_wakeup_path(dev)) {
101 		ret = phy_init(stm32_pcie->phy);
102 		if (ret) {
103 			pinctrl_pm_select_default_state(dev);
104 			return ret;
105 		}
106 	}
107 
108 	ret = clk_prepare_enable(stm32_pcie->clk);
109 	if (ret)
110 		goto err_phy_exit;
111 
112 	stm32_pcie_deassert_perst(stm32_pcie);
113 
114 	ret = dw_pcie_resume_noirq(&stm32_pcie->pci);
115 	if (ret)
116 		goto err_disable_clk;
117 
118 	pinctrl_pm_select_default_state(dev);
119 
120 	return 0;
121 
122 err_disable_clk:
123 	stm32_pcie_assert_perst(stm32_pcie);
124 	clk_disable_unprepare(stm32_pcie->clk);
125 
126 err_phy_exit:
127 	phy_exit(stm32_pcie->phy);
128 	pinctrl_pm_select_default_state(dev);
129 
130 	return ret;
131 }
132 
133 static const struct dev_pm_ops stm32_pcie_pm_ops = {
134 	NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_pcie_suspend_noirq,
135 				  stm32_pcie_resume_noirq)
136 };
137 
138 static const struct dw_pcie_host_ops stm32_pcie_host_ops = {
139 };
140 
141 static const struct dw_pcie_ops dw_pcie_ops = {
142 	.start_link = stm32_pcie_start_link,
143 	.stop_link = stm32_pcie_stop_link
144 };
145 
stm32_add_pcie_port(struct stm32_pcie * stm32_pcie)146 static int stm32_add_pcie_port(struct stm32_pcie *stm32_pcie)
147 {
148 	struct device *dev = stm32_pcie->pci.dev;
149 	unsigned int wake_irq;
150 	int ret;
151 
152 	ret = phy_set_mode(stm32_pcie->phy, PHY_MODE_PCIE);
153 	if (ret)
154 		return ret;
155 
156 	ret = phy_init(stm32_pcie->phy);
157 	if (ret)
158 		return ret;
159 
160 	ret = regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR,
161 				 STM32MP25_PCIECR_TYPE_MASK,
162 				 STM32MP25_PCIECR_RC);
163 	if (ret)
164 		goto err_phy_exit;
165 
166 	stm32_pcie_deassert_perst(stm32_pcie);
167 
168 	if (stm32_pcie->wake_gpio) {
169 		wake_irq = gpiod_to_irq(stm32_pcie->wake_gpio);
170 		ret = dev_pm_set_dedicated_wake_irq(dev, wake_irq);
171 		if (ret) {
172 			dev_err(dev, "Failed to enable wakeup irq %d\n", ret);
173 			goto err_assert_perst;
174 		}
175 		irq_set_irq_type(wake_irq, IRQ_TYPE_EDGE_FALLING);
176 	}
177 
178 	return 0;
179 
180 err_assert_perst:
181 	stm32_pcie_assert_perst(stm32_pcie);
182 
183 err_phy_exit:
184 	phy_exit(stm32_pcie->phy);
185 
186 	return ret;
187 }
188 
stm32_remove_pcie_port(struct stm32_pcie * stm32_pcie)189 static void stm32_remove_pcie_port(struct stm32_pcie *stm32_pcie)
190 {
191 	dev_pm_clear_wake_irq(stm32_pcie->pci.dev);
192 
193 	stm32_pcie_assert_perst(stm32_pcie);
194 
195 	phy_exit(stm32_pcie->phy);
196 }
197 
stm32_pcie_parse_port(struct stm32_pcie * stm32_pcie)198 static int stm32_pcie_parse_port(struct stm32_pcie *stm32_pcie)
199 {
200 	struct device *dev = stm32_pcie->pci.dev;
201 	struct device_node *root_port;
202 
203 	root_port = of_get_next_available_child(dev->of_node, NULL);
204 
205 	stm32_pcie->phy = devm_of_phy_get(dev, root_port, NULL);
206 	if (IS_ERR(stm32_pcie->phy)) {
207 		of_node_put(root_port);
208 		return dev_err_probe(dev, PTR_ERR(stm32_pcie->phy),
209 				     "Failed to get pcie-phy\n");
210 	}
211 
212 	stm32_pcie->perst_gpio = devm_fwnode_gpiod_get(dev, of_fwnode_handle(root_port),
213 						       "reset", GPIOD_OUT_HIGH, NULL);
214 	if (IS_ERR(stm32_pcie->perst_gpio)) {
215 		if (PTR_ERR(stm32_pcie->perst_gpio) != -ENOENT) {
216 			of_node_put(root_port);
217 			return dev_err_probe(dev, PTR_ERR(stm32_pcie->perst_gpio),
218 					     "Failed to get reset GPIO\n");
219 		}
220 		stm32_pcie->perst_gpio = NULL;
221 	}
222 
223 	stm32_pcie->wake_gpio = devm_fwnode_gpiod_get(dev, of_fwnode_handle(root_port),
224 						      "wake", GPIOD_IN, NULL);
225 
226 	if (IS_ERR(stm32_pcie->wake_gpio)) {
227 		if (PTR_ERR(stm32_pcie->wake_gpio) != -ENOENT) {
228 			of_node_put(root_port);
229 			return dev_err_probe(dev, PTR_ERR(stm32_pcie->wake_gpio),
230 					     "Failed to get wake GPIO\n");
231 		}
232 		stm32_pcie->wake_gpio = NULL;
233 	}
234 
235 	of_node_put(root_port);
236 
237 	return 0;
238 }
239 
stm32_pcie_probe(struct platform_device * pdev)240 static int stm32_pcie_probe(struct platform_device *pdev)
241 {
242 	struct stm32_pcie *stm32_pcie;
243 	struct device *dev = &pdev->dev;
244 	int ret;
245 
246 	stm32_pcie = devm_kzalloc(dev, sizeof(*stm32_pcie), GFP_KERNEL);
247 	if (!stm32_pcie)
248 		return -ENOMEM;
249 
250 	stm32_pcie->pci.dev = dev;
251 	stm32_pcie->pci.ops = &dw_pcie_ops;
252 	stm32_pcie->pci.pp.ops = &stm32_pcie_host_ops;
253 
254 	stm32_pcie->regmap = syscon_regmap_lookup_by_compatible("st,stm32mp25-syscfg");
255 	if (IS_ERR(stm32_pcie->regmap))
256 		return dev_err_probe(dev, PTR_ERR(stm32_pcie->regmap),
257 				     "No syscfg specified\n");
258 
259 	stm32_pcie->clk = devm_clk_get(dev, NULL);
260 	if (IS_ERR(stm32_pcie->clk))
261 		return dev_err_probe(dev, PTR_ERR(stm32_pcie->clk),
262 				     "Failed to get PCIe clock source\n");
263 
264 	stm32_pcie->rst = devm_reset_control_get_exclusive(dev, NULL);
265 	if (IS_ERR(stm32_pcie->rst))
266 		return dev_err_probe(dev, PTR_ERR(stm32_pcie->rst),
267 				     "Failed to get PCIe reset\n");
268 
269 	ret = stm32_pcie_parse_port(stm32_pcie);
270 	if (ret)
271 		return ret;
272 
273 	platform_set_drvdata(pdev, stm32_pcie);
274 
275 	ret = stm32_add_pcie_port(stm32_pcie);
276 	if (ret)
277 		return ret;
278 
279 	reset_control_assert(stm32_pcie->rst);
280 	reset_control_deassert(stm32_pcie->rst);
281 
282 	ret = clk_prepare_enable(stm32_pcie->clk);
283 	if (ret) {
284 		dev_err(dev, "Core clock enable failed %d\n", ret);
285 		goto err_remove_port;
286 	}
287 
288 	ret = pm_runtime_set_active(dev);
289 	if (ret < 0) {
290 		dev_err_probe(dev, ret, "Failed to activate runtime PM\n");
291 		goto err_disable_clk;
292 	}
293 
294 	pm_runtime_no_callbacks(dev);
295 
296 	ret = devm_pm_runtime_enable(dev);
297 	if (ret < 0) {
298 		dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
299 		goto err_disable_clk;
300 	}
301 
302 	ret = dw_pcie_host_init(&stm32_pcie->pci.pp);
303 	if (ret)
304 		goto err_disable_clk;
305 
306 	if (stm32_pcie->wake_gpio)
307 		device_init_wakeup(dev, true);
308 
309 	return 0;
310 
311 err_disable_clk:
312 	clk_disable_unprepare(stm32_pcie->clk);
313 
314 err_remove_port:
315 	stm32_remove_pcie_port(stm32_pcie);
316 
317 	return ret;
318 }
319 
stm32_pcie_remove(struct platform_device * pdev)320 static void stm32_pcie_remove(struct platform_device *pdev)
321 {
322 	struct stm32_pcie *stm32_pcie = platform_get_drvdata(pdev);
323 	struct dw_pcie_rp *pp = &stm32_pcie->pci.pp;
324 
325 	if (stm32_pcie->wake_gpio)
326 		device_init_wakeup(&pdev->dev, false);
327 
328 	dw_pcie_host_deinit(pp);
329 
330 	clk_disable_unprepare(stm32_pcie->clk);
331 
332 	stm32_remove_pcie_port(stm32_pcie);
333 
334 	pm_runtime_put_noidle(&pdev->dev);
335 }
336 
337 static const struct of_device_id stm32_pcie_of_match[] = {
338 	{ .compatible = "st,stm32mp25-pcie-rc" },
339 	{},
340 };
341 
342 static struct platform_driver stm32_pcie_driver = {
343 	.probe = stm32_pcie_probe,
344 	.remove = stm32_pcie_remove,
345 	.driver = {
346 		.name = "stm32-pcie",
347 		.of_match_table = stm32_pcie_of_match,
348 		.pm = &stm32_pcie_pm_ops,
349 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
350 	},
351 };
352 
353 module_platform_driver(stm32_pcie_driver);
354 
355 MODULE_AUTHOR("Christian Bruel <christian.bruel@foss.st.com>");
356 MODULE_DESCRIPTION("STM32MP25 PCIe Controller driver");
357 MODULE_LICENSE("GPL");
358 MODULE_DEVICE_TABLE(of, stm32_pcie_of_match);
359