1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * wanXL serial card driver for Linux
4 * host part
5 *
6 * Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>
7 *
8 * Status:
9 * - Only DTE (external clock) support with NRZ and NRZI encodings
10 * - wanXL100 will require minor driver modifications, no access to hw
11 */
12
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/slab.h>
18 #include <linux/sched.h>
19 #include <linux/types.h>
20 #include <linux/fcntl.h>
21 #include <linux/string.h>
22 #include <linux/errno.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/ioport.h>
26 #include <linux/netdevice.h>
27 #include <linux/hdlc.h>
28 #include <linux/pci.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/delay.h>
31 #include <asm/io.h>
32
33 #include "wanxl.h"
34
35 static const char *version = "wanXL serial card driver version: 0.48";
36
37 #define PLX_CTL_RESET 0x40000000 /* adapter reset */
38
39 #undef DEBUG_PKT
40
41 /* MAILBOX #1 - PUTS COMMANDS */
42 #define MBX1_CMD_ABORTJ 0x85000000 /* Abort and Jump */
43 #ifdef __LITTLE_ENDIAN
44 #define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */
45 #else
46 #define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */
47 #endif
48
49 /* MAILBOX #2 - DRAM SIZE */
50 #define MBX2_MEMSZ_MASK 0xFFFF0000 /* PUTS Memory Size Register mask */
51
52 struct port {
53 struct net_device *dev;
54 struct card *card;
55 spinlock_t lock; /* for wanxl_xmit */
56 int node; /* physical port #0 - 3 */
57 unsigned int clock_type;
58 int tx_in, tx_out;
59 struct sk_buff *tx_skbs[TX_BUFFERS];
60 };
61
62 struct card_status {
63 desc_t rx_descs[RX_QUEUE_LENGTH];
64 port_status_t port_status[4];
65 };
66
67 struct card {
68 int n_ports; /* 1, 2 or 4 ports */
69 u8 irq;
70
71 u8 __iomem *plx; /* PLX PCI9060 virtual base address */
72 struct pci_dev *pdev; /* for pci_name(pdev) */
73 int rx_in;
74 struct sk_buff *rx_skbs[RX_QUEUE_LENGTH];
75 struct card_status *status; /* shared between host and card */
76 dma_addr_t status_address;
77 struct port ports[]; /* 1 - 4 port structures follow */
78 };
79
dev_to_port(struct net_device * dev)80 static inline struct port *dev_to_port(struct net_device *dev)
81 {
82 return (struct port *)dev_to_hdlc(dev)->priv;
83 }
84
get_status(struct port * port)85 static inline port_status_t *get_status(struct port *port)
86 {
87 return &port->card->status->port_status[port->node];
88 }
89
90 /* Cable and/or personality module change interrupt service */
wanxl_cable_intr(struct port * port)91 static inline void wanxl_cable_intr(struct port *port)
92 {
93 u32 value = get_status(port)->cable;
94 int valid = 1;
95 const char *cable, *pm, *dte = "", *dsr = "", *dcd = "";
96
97 switch (value & 0x7) {
98 case STATUS_CABLE_V35:
99 cable = "V.35";
100 break;
101 case STATUS_CABLE_X21:
102 cable = "X.21";
103 break;
104 case STATUS_CABLE_V24:
105 cable = "V.24";
106 break;
107 case STATUS_CABLE_EIA530:
108 cable = "EIA530";
109 break;
110 case STATUS_CABLE_NONE:
111 cable = "no";
112 break;
113 default:
114 cable = "invalid";
115 }
116
117 switch ((value >> STATUS_CABLE_PM_SHIFT) & 0x7) {
118 case STATUS_CABLE_V35:
119 pm = "V.35";
120 break;
121 case STATUS_CABLE_X21:
122 pm = "X.21";
123 break;
124 case STATUS_CABLE_V24:
125 pm = "V.24";
126 break;
127 case STATUS_CABLE_EIA530:
128 pm = "EIA530";
129 break;
130 case STATUS_CABLE_NONE:
131 pm = "no personality";
132 valid = 0;
133 break;
134 default:
135 pm = "invalid personality";
136 valid = 0;
137 }
138
139 if (valid) {
140 if ((value & 7) == ((value >> STATUS_CABLE_PM_SHIFT) & 7)) {
141 dsr = (value & STATUS_CABLE_DSR) ? ", DSR ON" :
142 ", DSR off";
143 dcd = (value & STATUS_CABLE_DCD) ? ", carrier ON" :
144 ", carrier off";
145 }
146 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE";
147 }
148 netdev_info(port->dev, "%s%s module, %s cable%s%s\n",
149 pm, dte, cable, dsr, dcd);
150
151 if (value & STATUS_CABLE_DCD)
152 netif_carrier_on(port->dev);
153 else
154 netif_carrier_off(port->dev);
155 }
156
157 /* Transmit complete interrupt service */
wanxl_tx_intr(struct port * port)158 static inline void wanxl_tx_intr(struct port *port)
159 {
160 struct net_device *dev = port->dev;
161
162 while (1) {
163 desc_t *desc = &get_status(port)->tx_descs[port->tx_in];
164 struct sk_buff *skb = port->tx_skbs[port->tx_in];
165
166 switch (desc->stat) {
167 case PACKET_FULL:
168 case PACKET_EMPTY:
169 netif_wake_queue(dev);
170 return;
171
172 case PACKET_UNDERRUN:
173 dev->stats.tx_errors++;
174 dev->stats.tx_fifo_errors++;
175 break;
176
177 default:
178 dev->stats.tx_packets++;
179 dev->stats.tx_bytes += skb->len;
180 }
181 desc->stat = PACKET_EMPTY; /* Free descriptor */
182 dma_unmap_single(&port->card->pdev->dev, desc->address,
183 skb->len, DMA_TO_DEVICE);
184 dev_consume_skb_irq(skb);
185 port->tx_in = (port->tx_in + 1) % TX_BUFFERS;
186 }
187 }
188
189 /* Receive complete interrupt service */
wanxl_rx_intr(struct card * card)190 static inline void wanxl_rx_intr(struct card *card)
191 {
192 desc_t *desc;
193
194 while (desc = &card->status->rx_descs[card->rx_in],
195 desc->stat != PACKET_EMPTY) {
196 if ((desc->stat & PACKET_PORT_MASK) > card->n_ports) {
197 pr_crit("%s: received packet for nonexistent port\n",
198 pci_name(card->pdev));
199 } else {
200 struct sk_buff *skb = card->rx_skbs[card->rx_in];
201 struct port *port = &card->ports[desc->stat &
202 PACKET_PORT_MASK];
203 struct net_device *dev = port->dev;
204
205 if (!skb) {
206 dev->stats.rx_dropped++;
207 } else {
208 dma_unmap_single(&card->pdev->dev,
209 desc->address, BUFFER_LENGTH,
210 DMA_FROM_DEVICE);
211 skb_put(skb, desc->length);
212
213 #ifdef DEBUG_PKT
214 printk(KERN_DEBUG "%s RX(%i):", dev->name,
215 skb->len);
216 debug_frame(skb);
217 #endif
218 dev->stats.rx_packets++;
219 dev->stats.rx_bytes += skb->len;
220 skb->protocol = hdlc_type_trans(skb, dev);
221 netif_rx(skb);
222 skb = NULL;
223 }
224
225 if (!skb) {
226 skb = dev_alloc_skb(BUFFER_LENGTH);
227 desc->address = skb ?
228 dma_map_single(&card->pdev->dev,
229 skb->data,
230 BUFFER_LENGTH,
231 DMA_FROM_DEVICE) : 0;
232 card->rx_skbs[card->rx_in] = skb;
233 }
234 }
235 desc->stat = PACKET_EMPTY; /* Free descriptor */
236 card->rx_in = (card->rx_in + 1) % RX_QUEUE_LENGTH;
237 }
238 }
239
wanxl_intr(int irq,void * dev_id)240 static irqreturn_t wanxl_intr(int irq, void *dev_id)
241 {
242 struct card *card = dev_id;
243 int i;
244 u32 stat;
245 int handled = 0;
246
247 while ((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {
248 handled = 1;
249 writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);
250
251 for (i = 0; i < card->n_ports; i++) {
252 if (stat & (1 << (DOORBELL_FROM_CARD_TX_0 + i)))
253 wanxl_tx_intr(&card->ports[i]);
254 if (stat & (1 << (DOORBELL_FROM_CARD_CABLE_0 + i)))
255 wanxl_cable_intr(&card->ports[i]);
256 }
257 if (stat & (1 << DOORBELL_FROM_CARD_RX))
258 wanxl_rx_intr(card);
259 }
260
261 return IRQ_RETVAL(handled);
262 }
263
wanxl_xmit(struct sk_buff * skb,struct net_device * dev)264 static netdev_tx_t wanxl_xmit(struct sk_buff *skb, struct net_device *dev)
265 {
266 struct port *port = dev_to_port(dev);
267 desc_t *desc;
268
269 spin_lock(&port->lock);
270
271 desc = &get_status(port)->tx_descs[port->tx_out];
272 if (desc->stat != PACKET_EMPTY) {
273 /* should never happen - previous xmit should stop queue */
274 #ifdef DEBUG_PKT
275 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
276 #endif
277 netif_stop_queue(dev);
278 spin_unlock(&port->lock);
279 return NETDEV_TX_BUSY; /* request packet to be queued */
280 }
281
282 #ifdef DEBUG_PKT
283 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
284 debug_frame(skb);
285 #endif
286
287 port->tx_skbs[port->tx_out] = skb;
288 desc->address = dma_map_single(&port->card->pdev->dev, skb->data,
289 skb->len, DMA_TO_DEVICE);
290 desc->length = skb->len;
291 desc->stat = PACKET_FULL;
292 writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node),
293 port->card->plx + PLX_DOORBELL_TO_CARD);
294
295 port->tx_out = (port->tx_out + 1) % TX_BUFFERS;
296
297 if (get_status(port)->tx_descs[port->tx_out].stat != PACKET_EMPTY) {
298 netif_stop_queue(dev);
299 #ifdef DEBUG_PKT
300 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
301 #endif
302 }
303
304 spin_unlock(&port->lock);
305 return NETDEV_TX_OK;
306 }
307
wanxl_attach(struct net_device * dev,unsigned short encoding,unsigned short parity)308 static int wanxl_attach(struct net_device *dev, unsigned short encoding,
309 unsigned short parity)
310 {
311 struct port *port = dev_to_port(dev);
312
313 if (encoding != ENCODING_NRZ &&
314 encoding != ENCODING_NRZI)
315 return -EINVAL;
316
317 if (parity != PARITY_NONE &&
318 parity != PARITY_CRC32_PR1_CCITT &&
319 parity != PARITY_CRC16_PR1_CCITT &&
320 parity != PARITY_CRC32_PR0_CCITT &&
321 parity != PARITY_CRC16_PR0_CCITT)
322 return -EINVAL;
323
324 get_status(port)->encoding = encoding;
325 get_status(port)->parity = parity;
326 return 0;
327 }
328
wanxl_ioctl(struct net_device * dev,struct if_settings * ifs)329 static int wanxl_ioctl(struct net_device *dev, struct if_settings *ifs)
330 {
331 const size_t size = sizeof(sync_serial_settings);
332 sync_serial_settings line;
333 struct port *port = dev_to_port(dev);
334
335 switch (ifs->type) {
336 case IF_GET_IFACE:
337 ifs->type = IF_IFACE_SYNC_SERIAL;
338 if (ifs->size < size) {
339 ifs->size = size; /* data size wanted */
340 return -ENOBUFS;
341 }
342 memset(&line, 0, sizeof(line));
343 line.clock_type = get_status(port)->clocking;
344 line.clock_rate = 0;
345 line.loopback = 0;
346
347 if (copy_to_user(ifs->ifs_ifsu.sync, &line, size))
348 return -EFAULT;
349 return 0;
350
351 case IF_IFACE_SYNC_SERIAL:
352 if (!capable(CAP_NET_ADMIN))
353 return -EPERM;
354 if (dev->flags & IFF_UP)
355 return -EBUSY;
356
357 if (copy_from_user(&line, ifs->ifs_ifsu.sync,
358 size))
359 return -EFAULT;
360
361 if (line.clock_type != CLOCK_EXT &&
362 line.clock_type != CLOCK_TXFROMRX)
363 return -EINVAL; /* No such clock setting */
364
365 if (line.loopback != 0)
366 return -EINVAL;
367
368 get_status(port)->clocking = line.clock_type;
369 return 0;
370
371 default:
372 return hdlc_ioctl(dev, ifs);
373 }
374 }
375
wanxl_open(struct net_device * dev)376 static int wanxl_open(struct net_device *dev)
377 {
378 struct port *port = dev_to_port(dev);
379 u8 __iomem *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
380 unsigned long timeout;
381 int i;
382
383 if (get_status(port)->open) {
384 netdev_err(dev, "port already open\n");
385 return -EIO;
386 }
387
388 i = hdlc_open(dev);
389 if (i)
390 return i;
391
392 port->tx_in = port->tx_out = 0;
393 for (i = 0; i < TX_BUFFERS; i++)
394 get_status(port)->tx_descs[i].stat = PACKET_EMPTY;
395 /* signal the card */
396 writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr);
397
398 timeout = jiffies + HZ;
399 do {
400 if (get_status(port)->open) {
401 netif_start_queue(dev);
402 return 0;
403 }
404 } while (time_after(timeout, jiffies));
405
406 netdev_err(dev, "unable to open port\n");
407 /* ask the card to close the port, should it be still alive */
408 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr);
409 return -EFAULT;
410 }
411
wanxl_close(struct net_device * dev)412 static int wanxl_close(struct net_device *dev)
413 {
414 struct port *port = dev_to_port(dev);
415 unsigned long timeout;
416 int i;
417
418 hdlc_close(dev);
419 /* signal the card */
420 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node),
421 port->card->plx + PLX_DOORBELL_TO_CARD);
422
423 timeout = jiffies + HZ;
424 do {
425 if (!get_status(port)->open)
426 break;
427 } while (time_after(timeout, jiffies));
428
429 if (get_status(port)->open)
430 netdev_err(dev, "unable to close port\n");
431
432 netif_stop_queue(dev);
433
434 for (i = 0; i < TX_BUFFERS; i++) {
435 desc_t *desc = &get_status(port)->tx_descs[i];
436
437 if (desc->stat != PACKET_EMPTY) {
438 desc->stat = PACKET_EMPTY;
439 dma_unmap_single(&port->card->pdev->dev,
440 desc->address, port->tx_skbs[i]->len,
441 DMA_TO_DEVICE);
442 dev_kfree_skb(port->tx_skbs[i]);
443 }
444 }
445 return 0;
446 }
447
wanxl_get_stats(struct net_device * dev)448 static struct net_device_stats *wanxl_get_stats(struct net_device *dev)
449 {
450 struct port *port = dev_to_port(dev);
451
452 dev->stats.rx_over_errors = get_status(port)->rx_overruns;
453 dev->stats.rx_frame_errors = get_status(port)->rx_frame_errors;
454 dev->stats.rx_errors = dev->stats.rx_over_errors +
455 dev->stats.rx_frame_errors;
456 return &dev->stats;
457 }
458
wanxl_puts_command(struct card * card,u32 cmd)459 static int wanxl_puts_command(struct card *card, u32 cmd)
460 {
461 unsigned long timeout = jiffies + 5 * HZ;
462
463 writel(cmd, card->plx + PLX_MAILBOX_1);
464 do {
465 if (readl(card->plx + PLX_MAILBOX_1) == 0)
466 return 0;
467
468 schedule();
469 } while (time_after(timeout, jiffies));
470
471 return -1;
472 }
473
wanxl_reset(struct card * card)474 static void wanxl_reset(struct card *card)
475 {
476 u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;
477
478 writel(0x80, card->plx + PLX_MAILBOX_0);
479 writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);
480 readl(card->plx + PLX_CONTROL); /* wait for posted write */
481 udelay(1);
482 writel(old_value, card->plx + PLX_CONTROL);
483 readl(card->plx + PLX_CONTROL); /* wait for posted write */
484 }
485
wanxl_pci_remove_one(struct pci_dev * pdev)486 static void wanxl_pci_remove_one(struct pci_dev *pdev)
487 {
488 struct card *card = pci_get_drvdata(pdev);
489 int i;
490
491 for (i = 0; i < card->n_ports; i++) {
492 unregister_hdlc_device(card->ports[i].dev);
493 free_netdev(card->ports[i].dev);
494 }
495
496 /* unregister and free all host resources */
497 if (card->irq)
498 free_irq(card->irq, card);
499
500 if (card->plx)
501 wanxl_reset(card);
502
503 for (i = 0; i < RX_QUEUE_LENGTH; i++)
504 if (card->rx_skbs[i]) {
505 dma_unmap_single(&card->pdev->dev,
506 card->status->rx_descs[i].address,
507 BUFFER_LENGTH, DMA_FROM_DEVICE);
508 dev_kfree_skb(card->rx_skbs[i]);
509 }
510
511 if (card->plx)
512 iounmap(card->plx);
513
514 if (card->status)
515 dma_free_coherent(&pdev->dev, sizeof(struct card_status),
516 card->status, card->status_address);
517
518 pci_release_regions(pdev);
519 pci_disable_device(pdev);
520 kfree(card);
521 }
522
523 #include "wanxlfw.inc"
524
525 static const struct net_device_ops wanxl_ops = {
526 .ndo_open = wanxl_open,
527 .ndo_stop = wanxl_close,
528 .ndo_start_xmit = hdlc_start_xmit,
529 .ndo_siocwandev = wanxl_ioctl,
530 .ndo_get_stats = wanxl_get_stats,
531 };
532
wanxl_pci_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)533 static int wanxl_pci_init_one(struct pci_dev *pdev,
534 const struct pci_device_id *ent)
535 {
536 struct card *card;
537 u32 ramsize, stat;
538 unsigned long timeout;
539 u32 plx_phy; /* PLX PCI base address */
540 u32 mem_phy; /* memory PCI base addr */
541 u8 __iomem *mem; /* memory virtual base addr */
542 int i, ports;
543
544 #ifndef MODULE
545 pr_info_once("%s\n", version);
546 #endif
547
548 i = pci_enable_device(pdev);
549 if (i)
550 return i;
551
552 /* QUICC can only access first 256 MB of host RAM directly,
553 * but PLX9060 DMA does 32-bits for actual packet data transfers
554 */
555
556 /* FIXME when PCI/DMA subsystems are fixed.
557 * We set both dma_mask and consistent_dma_mask to 28 bits
558 * and pray pci_alloc_consistent() will use this info. It should
559 * work on most platforms
560 */
561 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(28)) ||
562 dma_set_mask(&pdev->dev, DMA_BIT_MASK(28))) {
563 pr_err("No usable DMA configuration\n");
564 pci_disable_device(pdev);
565 return -EIO;
566 }
567
568 i = pci_request_regions(pdev, "wanXL");
569 if (i) {
570 pci_disable_device(pdev);
571 return i;
572 }
573
574 switch (pdev->device) {
575 case PCI_DEVICE_ID_SBE_WANXL100:
576 ports = 1;
577 break;
578 case PCI_DEVICE_ID_SBE_WANXL200:
579 ports = 2;
580 break;
581 default:
582 ports = 4;
583 }
584
585 card = kzalloc_flex(*card, ports, ports);
586 if (!card) {
587 pci_release_regions(pdev);
588 pci_disable_device(pdev);
589 return -ENOBUFS;
590 }
591
592 pci_set_drvdata(pdev, card);
593 card->pdev = pdev;
594
595 card->status = dma_alloc_coherent(&pdev->dev,
596 sizeof(struct card_status),
597 &card->status_address, GFP_KERNEL);
598 if (!card->status) {
599 wanxl_pci_remove_one(pdev);
600 return -ENOBUFS;
601 }
602
603 #ifdef DEBUG_PCI
604 printk(KERN_DEBUG "wanXL %s: pci_alloc_consistent() returned memory"
605 " at 0x%LX\n", pci_name(pdev),
606 (unsigned long long)card->status_address);
607 #endif
608
609 /* FIXME when PCI/DMA subsystems are fixed.
610 * We set both dma_mask and consistent_dma_mask back to 32 bits
611 * to indicate the card can do 32-bit DMA addressing
612 */
613 if (dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)) ||
614 dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) {
615 pr_err("No usable DMA configuration\n");
616 wanxl_pci_remove_one(pdev);
617 return -EIO;
618 }
619
620 /* set up PLX mapping */
621 plx_phy = pci_resource_start(pdev, 0);
622
623 card->plx = ioremap(plx_phy, 0x70);
624 if (!card->plx) {
625 pr_err("ioremap() failed\n");
626 wanxl_pci_remove_one(pdev);
627 return -EFAULT;
628 }
629
630 #if RESET_WHILE_LOADING
631 wanxl_reset(card);
632 #endif
633
634 timeout = jiffies + 20 * HZ;
635 while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {
636 if (time_before(timeout, jiffies)) {
637 pr_warn("%s: timeout waiting for PUTS to complete\n",
638 pci_name(pdev));
639 wanxl_pci_remove_one(pdev);
640 return -ENODEV;
641 }
642
643 switch (stat & 0xC0) {
644 case 0x00: /* hmm - PUTS completed with non-zero code? */
645 case 0x80: /* PUTS still testing the hardware */
646 break;
647
648 default:
649 pr_warn("%s: PUTS test 0x%X failed\n",
650 pci_name(pdev), stat & 0x30);
651 wanxl_pci_remove_one(pdev);
652 return -ENODEV;
653 }
654
655 schedule();
656 }
657
658 /* get on-board memory size (PUTS detects no more than 4 MB) */
659 ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;
660
661 /* set up on-board RAM mapping */
662 mem_phy = pci_resource_start(pdev, 2);
663
664 /* sanity check the board's reported memory size */
665 if (ramsize < BUFFERS_ADDR +
666 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports) {
667 pr_warn("%s: no enough on-board RAM (%u bytes detected, %u bytes required)\n",
668 pci_name(pdev), ramsize,
669 BUFFERS_ADDR +
670 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports);
671 wanxl_pci_remove_one(pdev);
672 return -ENODEV;
673 }
674
675 if (wanxl_puts_command(card, MBX1_CMD_BSWAP)) {
676 pr_warn("%s: unable to Set Byte Swap Mode\n", pci_name(pdev));
677 wanxl_pci_remove_one(pdev);
678 return -ENODEV;
679 }
680
681 for (i = 0; i < RX_QUEUE_LENGTH; i++) {
682 struct sk_buff *skb = dev_alloc_skb(BUFFER_LENGTH);
683
684 card->rx_skbs[i] = skb;
685 if (skb)
686 card->status->rx_descs[i].address =
687 dma_map_single(&card->pdev->dev, skb->data,
688 BUFFER_LENGTH, DMA_FROM_DEVICE);
689 }
690
691 mem = ioremap(mem_phy, PDM_OFFSET + sizeof(firmware));
692 if (!mem) {
693 pr_err("ioremap() failed\n");
694 wanxl_pci_remove_one(pdev);
695 return -EFAULT;
696 }
697
698 for (i = 0; i < sizeof(firmware); i += 4)
699 writel(ntohl(*(__be32 *)(firmware + i)), mem + PDM_OFFSET + i);
700
701 for (i = 0; i < ports; i++)
702 writel(card->status_address +
703 (void *)&card->status->port_status[i] -
704 (void *)card->status, mem + PDM_OFFSET + 4 + i * 4);
705 writel(card->status_address, mem + PDM_OFFSET + 20);
706 writel(PDM_OFFSET, mem);
707 iounmap(mem);
708
709 writel(0, card->plx + PLX_MAILBOX_5);
710
711 if (wanxl_puts_command(card, MBX1_CMD_ABORTJ)) {
712 pr_warn("%s: unable to Abort and Jump\n", pci_name(pdev));
713 wanxl_pci_remove_one(pdev);
714 return -ENODEV;
715 }
716
717 timeout = jiffies + 5 * HZ;
718 do {
719 stat = readl(card->plx + PLX_MAILBOX_5);
720 if (stat)
721 break;
722 schedule();
723 } while (time_after(timeout, jiffies));
724
725 if (!stat) {
726 pr_warn("%s: timeout while initializing card firmware\n",
727 pci_name(pdev));
728 wanxl_pci_remove_one(pdev);
729 return -ENODEV;
730 }
731
732 #if DETECT_RAM
733 ramsize = stat;
734 #endif
735
736 pr_info("%s: at 0x%X, %u KB of RAM at 0x%X, irq %u\n",
737 pci_name(pdev), plx_phy, ramsize / 1024, mem_phy, pdev->irq);
738
739 /* Allocate IRQ */
740 if (request_irq(pdev->irq, wanxl_intr, IRQF_SHARED, "wanXL", card)) {
741 pr_warn("%s: could not allocate IRQ%i\n",
742 pci_name(pdev), pdev->irq);
743 wanxl_pci_remove_one(pdev);
744 return -EBUSY;
745 }
746 card->irq = pdev->irq;
747
748 for (i = 0; i < ports; i++) {
749 hdlc_device *hdlc;
750 struct port *port = &card->ports[i];
751 struct net_device *dev = alloc_hdlcdev(port);
752
753 if (!dev) {
754 pr_err("%s: unable to allocate memory\n",
755 pci_name(pdev));
756 wanxl_pci_remove_one(pdev);
757 return -ENOMEM;
758 }
759
760 port->dev = dev;
761 hdlc = dev_to_hdlc(dev);
762 spin_lock_init(&port->lock);
763 dev->tx_queue_len = 50;
764 dev->netdev_ops = &wanxl_ops;
765 hdlc->attach = wanxl_attach;
766 hdlc->xmit = wanxl_xmit;
767 port->card = card;
768 port->node = i;
769 get_status(port)->clocking = CLOCK_EXT;
770 if (register_hdlc_device(dev)) {
771 pr_err("%s: unable to register hdlc device\n",
772 pci_name(pdev));
773 free_netdev(dev);
774 wanxl_pci_remove_one(pdev);
775 return -ENOBUFS;
776 }
777 card->n_ports++;
778 }
779
780 pr_info("%s: port", pci_name(pdev));
781 for (i = 0; i < ports; i++)
782 pr_cont("%s #%i: %s",
783 i ? "," : "", i, card->ports[i].dev->name);
784 pr_cont("\n");
785
786 for (i = 0; i < ports; i++)
787 wanxl_cable_intr(&card->ports[i]); /* get carrier status etc.*/
788
789 return 0;
790 }
791
792 static const struct pci_device_id wanxl_pci_tbl[] = {
793 { PCI_VDEVICE(SBE, PCI_DEVICE_ID_SBE_WANXL100) },
794 { PCI_VDEVICE(SBE, PCI_DEVICE_ID_SBE_WANXL200) },
795 { PCI_VDEVICE(SBE, PCI_DEVICE_ID_SBE_WANXL400) },
796 { }
797 };
798
799 static struct pci_driver wanxl_pci_driver = {
800 .name = "wanXL",
801 .id_table = wanxl_pci_tbl,
802 .probe = wanxl_pci_init_one,
803 .remove = wanxl_pci_remove_one,
804 };
805
wanxl_init_module(void)806 static int __init wanxl_init_module(void)
807 {
808 #ifdef MODULE
809 pr_info("%s\n", version);
810 #endif
811 return pci_register_driver(&wanxl_pci_driver);
812 }
813
wanxl_cleanup_module(void)814 static void __exit wanxl_cleanup_module(void)
815 {
816 pci_unregister_driver(&wanxl_pci_driver);
817 }
818
819 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
820 MODULE_DESCRIPTION("SBE Inc. wanXL serial port driver");
821 MODULE_LICENSE("GPL v2");
822 MODULE_DEVICE_TABLE(pci, wanxl_pci_tbl);
823
824 module_init(wanxl_init_module);
825 module_exit(wanxl_cleanup_module);
826