1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for panels based on Himax HX83102 controller, such as: 4 * 5 * - Starry 10.51" WUXGA MIPI-DSI panel 6 * 7 * Based on drivers/gpu/drm/panel/panel-himax-hx8394.c 8 */ 9 10 #include <linux/backlight.h> 11 #include <linux/delay.h> 12 #include <linux/gpio/consumer.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/regulator/consumer.h> 16 17 #include <drm/drm_connector.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_mipi_dsi.h> 20 #include <drm/drm_panel.h> 21 22 #include <video/mipi_display.h> 23 24 /* Manufacturer specific DSI commands */ 25 #define HX83102_SETPOWER 0xb1 26 #define HX83102_SETDISP 0xb2 27 #define HX83102_SETCYC 0xb4 28 #define HX83102_UNKNOWN_B6 0xb6 29 #define HX83102_UNKNOWN_B8 0xb8 30 #define HX83102_SETEXTC 0xb9 31 #define HX83102_SETMIPI 0xba 32 #define HX83102_UNKNOWN_BB 0xbb 33 #define HX83102_SETVDC 0xbc 34 #define HX83102_SETBANK 0xbd 35 #define HX83102_UNKNOWN_BE 0xbe 36 #define HX83102_SETPTBA 0xbf 37 #define HX83102_SETSTBA 0xc0 38 #define HX83102_UNKNOWN_C2 0xc2 39 #define HX83102_UNKNOWN_C6 0xc6 40 #define HX83102_SETTCON 0xc7 41 #define HX83102_SETRAMDMY 0xc8 42 #define HX83102_SETPWM 0xc9 43 #define HX83102_SETCLOCK 0xcb 44 #define HX83102_SETPANEL 0xcc 45 #define HX83102_SETCASCADE 0xd0 46 #define HX83102_SETPCTRL 0xd1 47 #define HX83102_UNKNOWN_D2 0xd2 48 #define HX83102_SETGIP0 0xd3 49 #define HX83102_SETGIP1 0xd5 50 #define HX83102_SETGIP2 0xd6 51 #define HX83102_SETGIP3 0xd8 52 #define HX83102_UNKNOWN_D9 0xd9 53 #define HX83102_SETGMA 0xe0 54 #define HX83102_UNKNOWN_E1 0xe1 55 #define HX83102_SETTP1 0xe7 56 #define HX83102_SETSPCCMD 0xe9 57 58 struct hx83102 { 59 struct drm_panel base; 60 struct mipi_dsi_device *dsi; 61 62 const struct hx83102_panel_desc *desc; 63 64 enum drm_panel_orientation orientation; 65 struct regulator *pp1800; 66 struct regulator *avee; 67 struct regulator *avdd; 68 struct gpio_desc *enable_gpio; 69 }; 70 71 struct hx83102_panel_desc { 72 const struct drm_display_mode *modes; 73 74 /** 75 * @width_mm: width of the panel's active display area 76 * @height_mm: height of the panel's active display area 77 */ 78 struct { 79 unsigned int width_mm; 80 unsigned int height_mm; 81 } size; 82 83 bool has_backlight; 84 unsigned long mode_flags; 85 86 int (*init)(struct hx83102 *ctx); 87 }; 88 89 static inline struct hx83102 *panel_to_hx83102(struct drm_panel *panel) 90 { 91 return container_of(panel, struct hx83102, base); 92 } 93 94 static void hx83102_enable_extended_cmds(struct mipi_dsi_multi_context *dsi_ctx, bool enable) 95 { 96 if (enable) 97 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX83102_SETEXTC, 0x83, 0x10, 0x21, 0x55, 0x00); 98 else 99 mipi_dsi_dcs_write_seq_multi(dsi_ctx, HX83102_SETEXTC, 0x00, 0x00, 0x00); 100 } 101 102 static int starry_himax83102_j02_init(struct hx83102 *ctx) 103 { 104 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 105 106 hx83102_enable_extended_cmds(&dsi_ctx, true); 107 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb5, 0xb5, 0x31, 0xf1, 108 0x31, 0xd7, 0x2f, 0x36, 0x36, 0x36, 0x36, 0x1a, 0x8b, 0x11, 109 0x65, 0x00, 0x88, 0xfa, 0xff, 0xff, 0x8f, 0xff, 0x08, 0x74, 110 0x33); 111 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 112 0x12, 0x72, 0x3c, 0xa3, 0x03, 0x03, 0x00, 0x00, 0x88, 0xf5); 113 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x76, 0x76, 0x76, 0x76, 0x76, 114 0x76, 0x63, 0x5c, 0x63, 0x5c, 0x01, 0x9e); 115 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd); 116 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); 117 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 118 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); 119 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); 120 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4); 121 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x36, 0x36, 0x22, 0x11, 0x22, 122 0xa0, 0x61, 0x08, 0xf5, 0x03); 123 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 124 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); 125 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 126 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 127 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); 128 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 129 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x13, 0x88, 0x01); 130 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, 0x33); 131 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02); 132 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 133 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x03); 134 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 135 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0c, 136 0xff); 137 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x1f, 0x11, 0x1f); 138 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 139 0x08, 0x00, 0x08, 0x37, 0x47, 0x34, 0x3b, 0x12, 0x12, 0x03, 0x03, 140 0x32, 0x10, 0x10, 0x00, 0x10, 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, 141 0x17, 0x94, 0x07, 0x94, 0x00, 0x00); 142 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 143 0x18, 0x18, 0x18, 0x18, 0x19, 0x19, 0x40, 0x40, 0x1a, 0x1a, 0x1b, 144 0x1b, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x20, 0x21, 145 0x28, 0x29, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 146 0x18, 0x18, 0x18, 0x18, 0x18); 147 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 148 0x18, 0x18, 0x18, 0x18, 0x40, 0x40, 0x19, 0x19, 0x1a, 0x1a, 0x1b, 149 0x1b, 0x07, 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x29, 0x28, 150 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 151 0x18, 0x18, 0x18, 0x18, 0x18); 152 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xba, 0xea, 0xaa, 0xaa, 0xa0, 153 0xaa, 0xba, 0xea, 0xaa, 0xaa, 0xa0, 0xaa, 0xba, 0xea, 0xaa, 0xaa, 154 0xa0, 0xaa, 0xba, 0xea, 0xaa, 0xaa, 0xa0, 0xaa, 0xba, 0xea, 0xaa, 155 0xaa, 0xa0, 0xaa, 0xba, 0xea, 0xaa, 0xaa, 0xa0); 156 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA, 0x00, 0x09, 0x14, 0x1e, 0x26, 0x48, 157 0x61, 0x67, 0x6c, 0x67, 0x7d, 0x7f, 0x80, 0x8b, 0x87, 0x8f, 0x98, 158 0xab, 0xab, 0x55, 0x5c, 0x68, 0x73, 0x00, 0x09, 0x14, 0x1e, 0x26, 159 0x48, 0x61, 0x67, 0x6c, 0x67, 0x7d, 0x7f, 0x80, 0x8b, 0x87, 0x8f, 160 0x98, 0xab, 0xab, 0x55, 0x5c, 0x68, 0x73); 161 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x0e, 0x10, 0x10, 0x21, 0x2b, 0x9a, 162 0x02, 0x54, 0x9a, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x05, 163 0x02, 0x02, 0x10); 164 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 165 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0xbf, 0x11); 166 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); 167 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x3c, 0xfa); 168 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 169 0x00, 0x00, 0x80, 0x0c, 0x01); 170 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x28, 0x01, 0x7e, 0x0f, 171 0x7e, 0x10, 0xa0, 0x00, 0x00, 0x20, 0x40, 0x50, 0x40); 172 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 173 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xff, 0xbf, 0xfe, 0xaa, 0xa0, 174 0xff, 0xff, 0xbf, 0xfe, 0xaa, 0xa0); 175 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x04, 0xfe, 0x04, 0xfe, 0x04, 176 0x03, 0x03, 0x03, 0x26, 0x00, 0x26, 0x81, 0x02, 0x40, 0x00, 0x20, 177 0x9e, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00); 178 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 179 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 180 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); 181 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 182 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x00, 0x2a, 0xaa, 0xa8, 0x00, 0x00, 183 0x00, 0x2a, 0xaa, 0xa8, 0x00, 0x00, 0x00, 0x3f, 0xff, 0xfc, 0x00, 184 0x00, 0x00, 0x3f, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xa8, 185 0x00, 0x00, 0x00, 0x2a, 0xaa, 0xa8, 0x00, 0x00); 186 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 187 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 188 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x96); 189 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 190 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 191 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 192 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); 193 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 194 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 195 196 return dsi_ctx.accum_err; 197 }; 198 199 static int boe_nv110wum_init(struct hx83102 *ctx) 200 { 201 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 202 203 msleep(60); 204 205 hx83102_enable_extended_cmds(&dsi_ctx, true); 206 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xaf, 0xaf, 0x2b, 0xeb, 0x42, 207 0xe1, 0x4d, 0x36, 0x36, 0x36, 0x36, 0x1a, 0x8b, 0x11, 0x65, 0x00, 208 0x88, 0xfa, 0xff, 0xff, 0x8f, 0xff, 0x08, 0x9a, 0x33); 209 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x12, 210 0x71, 0x3c, 0xa3, 0x11, 0x00, 0x00, 0x00, 0x88, 0xf5, 0x22, 0x8f); 211 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x49, 0x49, 0x32, 0x32, 0x14, 0x32, 212 0x84, 0x6e, 0x84, 0x6e, 0x01, 0x9c); 213 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd); 214 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); 215 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 216 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); 217 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); 218 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x84); 219 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x36, 0x36, 0x22, 0x00, 0x00, 0xa0, 220 0x61, 0x08, 0xf5, 0x03); 221 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 222 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); 223 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 224 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 225 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); 226 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 227 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x30, 0xd4, 0x01); 228 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, 0x34); 229 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); 230 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 231 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x03); 232 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 233 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x37, 0x06, 0x00, 0x02, 0x04, 0x0c, 0xff); 234 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x1f, 0x11, 0x1f, 0x11); 235 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x04, 236 0x08, 0x04, 0x08, 0x37, 0x37, 0x64, 0x4b, 0x11, 0x11, 0x03, 0x03, 0x32, 237 0x10, 0x0e, 0x00, 0x0e, 0x32, 0x10, 0x0a, 0x00, 0x0a, 0x32, 0x17, 0x98, 238 0x07, 0x98, 0x00, 0x00); 239 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x1e, 0x1e, 240 0x1e, 0x1e, 0x1f, 0x1f, 0x1f, 0x1f, 0x24, 0x24, 0x24, 0x24, 0x07, 0x06, 241 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 242 0x01, 0x00, 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 243 0x18, 0x18); 244 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaf, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 245 0xaf, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0); 246 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA, 0x00, 0x05, 0x0d, 0x14, 0x1b, 0x2c, 247 0x44, 0x49, 0x51, 0x4c, 0x67, 0x6c, 0x71, 0x80, 0x7d, 0x84, 0x8d, 0xa0, 248 0xa0, 0x4f, 0x58, 0x64, 0x73, 0x00, 0x05, 0x0d, 0x14, 0x1b, 0x2c, 0x44, 249 0x49, 0x51, 0x4c, 0x67, 0x6c, 0x71, 0x80, 0x7d, 0x84, 0x8d, 0xa0, 0xa0, 250 0x4f, 0x58, 0x64, 0x73); 251 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x07, 0x10, 0x10, 0x1a, 0x26, 0x9e, 252 0x00, 0x53, 0x9b, 0x14, 0x14); 253 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0x11, 0x00, 0x00, 0x89, 0x30, 0x80, 254 0x07, 0x80, 0x02, 0x58, 0x00, 0x14, 0x02, 0x58, 0x02, 0x58, 0x02, 0x00, 255 0x02, 0x2c, 0x00, 0x20, 0x02, 0x02, 0x00, 0x08, 0x00, 0x0c, 0x05, 0x0e, 256 0x04, 0x94, 0x18, 0x00, 0x10, 0xf0, 0x03, 0x0c, 0x20, 0x00, 0x06, 0x0b, 257 0x0b, 0x33, 0x0e); 258 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 259 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0, 260 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0); 261 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0xbf, 0x11); 262 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); 263 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x96); 264 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc9); 265 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x84); 266 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 267 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xd1); 268 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0xf6, 0x2b, 0x34, 0x2b, 0x74, 0x3b, 269 0x74, 0x6b, 0x74); 270 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 271 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x2b, 0x01, 0x7e, 0x0f, 272 0x7e, 0x10, 0xa0, 0x00, 0x00); 273 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 274 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x02, 0x00, 0xbb, 0x11); 275 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xaf, 0xff, 0xff, 0xfa, 0xa0, 276 0xff, 0xaf, 0xff, 0xff, 0xfa, 0xa0); 277 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, 278 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 0x20, 0x65, 279 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00); 280 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 281 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xaf, 0xaa, 0xaa, 0xa0, 0x00, 282 0xaa, 0xaf, 0xaa, 0xaa, 0xa0, 0x00, 0xaa, 0xaf, 0xaa, 0xaa, 0xa0, 0x00, 283 0xaa, 0xaf, 0xaa, 0xaa, 0xa0, 0x00); 284 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 285 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); 286 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 287 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0x00); 288 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 289 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 290 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x96); 291 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 292 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 293 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 294 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); 295 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 296 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 297 hx83102_enable_extended_cmds(&dsi_ctx, false); 298 299 mipi_dsi_msleep(&dsi_ctx, 50); 300 301 return dsi_ctx.accum_err; 302 }; 303 304 static int csot_pna957qt1_1_init(struct hx83102 *ctx) 305 { 306 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 307 308 msleep(60); 309 310 hx83102_enable_extended_cmds(&dsi_ctx, true); 311 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 312 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0xd2); 313 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 314 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb3, 0xb3, 0x31, 0xf1, 0x33, 315 0xe0, 0x54, 0x36, 0x36, 0x3a, 0x3a, 0x32, 0x8b, 0x11, 0xe5, 316 0x98); 317 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xd9); 318 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x8b, 0x33); 319 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 320 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x2c, 321 0x80, 0x3c, 0x9f, 0x22, 0x20, 0x00, 0x00, 0x98, 0x51); 322 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x41, 0x41, 0x41, 0x41, 0x64, 0x64, 323 0x40, 0x84, 0x64, 0x84, 0x01, 0x9d, 0x01, 0x02, 0x01, 0x00, 324 0x00); 325 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); 326 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); 327 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4, 0x80, 0x9c, 0x36, 0x00, 328 0x0d, 0x04); 329 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x32, 0x32, 0x22, 0x11, 0x22, 0xa0, 330 0x31, 0x08, 0xf5, 0x03); 331 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 332 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); 333 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 334 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 335 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); 336 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 337 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x13, 0x88, 0x01); 338 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, 339 0x36); 340 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); 341 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x07, 0x06, 0x00, 0x02, 0x04, 0x2c, 342 0xff); 343 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x40, 0x04, 344 0x08, 0x04, 0x08, 0x37, 0x07, 0x44, 0x37, 0x2b, 0x2b, 0x03, 345 0x03, 0x32, 0x10, 0x22, 0x00, 0x25, 0x32, 0x10, 0x29, 0x00, 346 0x29, 0x32, 0x10, 0x08, 0x00, 0x08, 0x00, 0x00); 347 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 348 0x18, 0x18, 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 349 0x05, 0x04, 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 350 0x18, 0x18, 0x25, 0x24, 0x25, 0x24, 0x1f, 0x1f, 0x1f, 0x1f, 351 0x1e, 0x1e, 0x1e, 0x1e, 0x20, 0x20, 0x20, 0x20); 352 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 353 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); 354 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA, 0x0a, 0x0e, 0x1a, 0x21, 0x28, 0x46, 355 0x5c, 0x61, 0x63, 0x5e, 0x78, 0x7d, 0x80, 0x8e, 0x89, 0x90, 356 0x98, 0xaa, 0xa8, 0x52, 0x59, 0x60, 0x6f, 0x06, 0x0a, 0x16, 357 0x1d, 0x24, 0x46, 0x5c, 0x61, 0x6b, 0x66, 0x7c, 0x7d, 0x80, 358 0x8e, 0x89, 0x90, 0x98, 0xaa, 0xa8, 0x52, 0x59, 0x60, 0x6f); 359 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xe0, 0x10, 0x10, 0x0d, 0x1e, 0x9d, 360 0x02, 0x52, 0x9d, 0x14, 0x14); 361 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 362 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x7f, 0x11, 0xfd); 363 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 364 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); 365 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 366 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); 367 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x64); 368 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 369 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00); 370 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 371 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 372 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x05, 0x15, 0x55, 0x45, 373 0x55, 0x50, 0x05, 0x15, 0x55, 0x45, 0x55, 0x50); 374 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x24, 0x01, 0x7e, 0x0f, 375 0x7c, 0x10, 0xa0, 0x00, 0x00); 376 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 377 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x03, 0x07, 0x00, 0x10, 0x7b); 378 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0, 379 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0); 380 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, 381 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 382 0x20, 0x9d, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 383 0x01, 0x00); 384 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 385 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x66, 0x81); 386 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 387 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); 388 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 389 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 390 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x0f, 0x2a, 0xaa, 0x8a, 391 0xaa, 0xf0, 0x0f, 0x2a, 0xaa, 0x8a, 0xaa, 0xf0, 0x0a, 0x2a, 392 0xaa, 0x8a, 0xaa, 0xa0, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); 393 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 394 hx83102_enable_extended_cmds(&dsi_ctx, false); 395 396 mipi_dsi_msleep(&dsi_ctx, 60); 397 398 return dsi_ctx.accum_err; 399 }; 400 401 static int ivo_t109nw41_init(struct hx83102 *ctx) 402 { 403 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 404 405 msleep(60); 406 407 hx83102_enable_extended_cmds(&dsi_ctx, true); 408 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xed, 0xed, 0x27, 0xe7, 0x52, 409 0xf5, 0x39, 0x36, 0x36, 0x36, 0x36, 0x32, 0x8b, 0x11, 0x65, 0x00, 0x88, 410 0xfa, 0xff, 0xff, 0x8f, 0xff, 0x08, 0xd6, 0x33); 411 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x12, 412 0x71, 0x3c, 0xa3, 0x22, 0x20, 0x00, 0x00, 0x88, 0x01); 413 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x35, 0x35, 0x43, 0x43, 0x35, 0x35, 414 0x30, 0x7a, 0x30, 0x7a, 0x01, 0x9d); 415 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd); 416 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); 417 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 418 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); 419 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); 420 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4); 421 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x34, 0x34, 0x22, 0x11, 0x22, 0xa0, 422 0x31, 0x08, 0xf5, 0x03); 423 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 424 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); 425 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 426 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xd3); 427 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x22); 428 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 429 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 430 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); 431 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 432 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x13, 0x88, 0x01); 433 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, 0x34); 434 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); 435 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 436 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x03); 437 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 438 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x07, 0x06, 0x00, 0x02, 0x04, 0x2c, 439 0xff); 440 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x08, 441 0x08, 0x08, 0x08, 0x37, 0x07, 0x64, 0x7c, 0x11, 0x11, 0x03, 0x03, 0x32, 442 0x10, 0x0e, 0x00, 0x0e, 0x32, 0x17, 0x97, 0x07, 0x97, 0x32, 0x00, 0x02, 443 0x00, 0x02, 0x00, 0x00); 444 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x25, 0x24, 0x25, 0x24, 0x18, 0x18, 445 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 0x05, 0x04, 0x03, 0x02, 446 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 0x1e, 0x1e, 0x1e, 0x1e, 0x1f, 0x1f, 447 0x1f, 0x1f, 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 448 0x18, 0x18); 449 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 450 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 451 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 452 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 453 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA, 0x00, 0x07, 0x10, 0x17, 0x1c, 0x33, 454 0x48, 0x50, 0x57, 0x50, 0x68, 0x6e, 0x71, 0x7f, 0x81, 0x8a, 0x8e, 0x9b, 455 0x9c, 0x4d, 0x56, 0x5d, 0x73, 0x00, 0x07, 0x10, 0x17, 0x1c, 0x33, 0x48, 456 0x50, 0x57, 0x50, 0x68, 0x6e, 0x71, 0x7f, 0x81, 0x8a, 0x8e, 0x9b, 0x9c, 457 0x4d, 0x56, 0x5d, 0x73); 458 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x07, 0x10, 0x10, 0x1a, 0x26, 0x9e, 459 0x00, 0x4f, 0xa0, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 0x0a, 0x02, 460 0x02, 0x00, 0x33, 0x02, 0x04, 0x18, 0x01); 461 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 462 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x7f, 0x11, 0xfd); 463 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); 464 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00, 0x04, 0x00, 0x00); 465 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 466 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 467 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 468 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 469 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x2b, 0x01, 0x7e, 0x0f, 470 0x7e, 0x10, 0xa0, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00); 471 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 472 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xf2); 473 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x03, 0x07, 0x00, 0x10, 0x79); 474 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0, 475 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0); 476 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, 477 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 0x20, 0x6e, 478 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 479 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 480 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 481 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0, 482 0xff, 0xff, 0xff, 0xff, 0xfa, 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 483 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 484 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 485 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 486 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); 487 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 488 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0x00); 489 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 490 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff); 491 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 492 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x96); 493 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 494 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 495 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 496 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); 497 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 498 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 499 hx83102_enable_extended_cmds(&dsi_ctx, false); 500 501 mipi_dsi_msleep(&dsi_ctx, 60); 502 503 return dsi_ctx.accum_err; 504 }; 505 506 static int kingdisplay_kd110n11_51ie_init(struct hx83102 *ctx) 507 { 508 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 509 510 msleep(50); 511 512 hx83102_enable_extended_cmds(&dsi_ctx, true); 513 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 514 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0xd1); 515 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 516 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb3, 0xb3, 0x31, 0xf1, 517 0x33, 0xe0, 0x54, 0x36, 0x36, 0x3a, 0x3a, 0x32, 0x8b, 518 0x11, 0xe5, 0x98); 519 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xd9); 520 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x8b, 0x33); 521 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 522 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x2c, 523 0x80, 0x3c, 0x9f, 0x22, 0x20, 0x00, 0x00, 0x98, 0x51); 524 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x64, 0x64, 0x64, 0x64, 0x64, 0x64, 525 0x40, 0x84, 0x64, 0x84, 0x01, 0x9d, 0x01, 0x02, 0x01, 0x00, 526 0x00); 527 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); 528 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); 529 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4, 0x80, 0x9c, 0x36, 0x00, 530 0x0d, 0x04); 531 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x32, 0x32, 0x22, 0x11, 0x22, 0xa0, 532 0x31, 0x08, 0xf5, 0x03); 533 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 534 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); 535 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 536 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 537 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); 538 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 539 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x13, 0x88, 0x01); 540 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 541 0x0f, 0x36); 542 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); 543 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x07, 0x06, 0x00, 0x02, 544 0x04, 0x2c, 0xff); 545 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x40, 0x04, 546 0x08, 0x04, 0x08, 0x37, 0x07, 0x44, 0x37, 0x2b, 0x2b, 0x03, 547 0x03, 0x32, 0x10, 0x22, 0x00, 0x25, 0x32, 0x10, 0x29, 0x00, 548 0x29, 0x32, 0x10, 0x08, 0x00, 0x08, 0x00, 0x00); 549 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 550 0x18, 0x18, 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, 551 0x05, 0x04, 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, 552 0x18, 0x18, 0x25, 0x24, 0x25, 0x24, 0x1f, 0x1f, 0x1f, 0x1f, 553 0x1e, 0x1e, 0x1e, 0x1e, 0x20, 0x20, 0x20, 0x20); 554 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 555 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); 556 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xe0, 0x10, 0x10, 0x0d, 0x1e, 0x9d, 557 0x02, 0x52, 0x9d, 0x14, 0x14); 558 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 559 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x7f, 0x11, 0xfd); 560 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 561 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); 562 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 563 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); 564 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x64); 565 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 566 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00); 567 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 568 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 569 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x05, 0x15, 0x55, 0x45, 570 0x55, 0x50, 0x05, 0x15, 0x55, 0x45, 0x55, 0x50); 571 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x24, 0x01, 0x7e, 0x0f, 572 0x7c, 0x10, 0xa0, 0x00, 0x00); 573 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 574 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x03, 0x07, 0x00, 0x10, 0x7b); 575 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0, 576 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0); 577 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, 578 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, 579 0x20, 0x9d, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 580 0x01, 0x00); 581 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 582 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x66, 0x81); 583 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 584 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); 585 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 586 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 587 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x0f, 0x2a, 0xaa, 0x8a, 588 0xaa, 0xf0, 0x0f, 0x2a, 0xaa, 0x8a, 0xaa, 0xf0, 0x0a, 0x2a, 589 0xaa, 0x8a, 0xaa, 0xa0, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); 590 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 591 hx83102_enable_extended_cmds(&dsi_ctx, false); 592 593 return dsi_ctx.accum_err; 594 } 595 596 static int starry_2082109qfh040022_50e_init(struct hx83102 *ctx) 597 { 598 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 599 600 msleep(50); 601 602 hx83102_enable_extended_cmds(&dsi_ctx, true); 603 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 604 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0xd1); 605 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 606 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb5, 0xb5, 0x31, 0xf1, 0x33, 607 0xc3, 0x57, 0x36, 0x36, 0x36, 0x36, 0x1a, 0x8b, 0x11, 0x65, 608 0x00, 0x88, 0xfa, 0xff, 0xff, 0x8f, 0xff, 0x08, 0x3c, 0x33); 609 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0, 0x80, 0x00, 0x22, 610 0x70, 0x3c, 0xa1, 0x22, 0x00, 0x00, 0x00, 0x88, 0xf4); 611 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x14, 0x16, 0x14, 0x50, 0x14, 0x50, 612 0x0d, 0x6a, 0x0d, 0x6a, 0x01, 0x9e); 613 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B6, 0x34, 0x34, 0x03); 614 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B8, 0x40); 615 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd); 616 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); 617 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 618 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); 619 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); 620 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4); 621 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x38, 0x38, 0x22, 0x11, 0x33, 0xa0, 622 0x61, 0x08, 0xf5, 0x03); 623 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 624 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); 625 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 626 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 627 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); 628 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 629 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x30, 0xd4, 0x01); 630 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07, 0x00, 0x0f, 631 0x16); 632 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44); 633 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 634 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x03); 635 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 636 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x37, 0x06, 0x00, 0x02, 0x04, 637 0x2c, 0xff); 638 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 639 0x00, 0x00, 0x00, 0x3b, 0x03, 0x73, 0x3b, 0x21, 0x21, 0x03, 640 0x03, 0x98, 0x10, 0x1d, 0x00, 0x1d, 0x32, 0x17, 0xa1, 0x07, 641 0xa1, 0x43, 0x17, 0xa6, 0x07, 0xa6, 0x00, 0x00); 642 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 643 0x40, 0x40, 0x18, 0x18, 0x18, 0x18, 0x2a, 0x2b, 0x1f, 0x1f, 644 0x1e, 0x1e, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 645 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 646 0x0a, 0x0b, 0x20, 0x21, 0x18, 0x18, 0x18, 0x18); 647 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x02, 0xaa, 0xea, 0xaa, 0xaa, 0x00, 648 0x02, 0xaa, 0xea, 0xaa, 0xaa, 0x00, 0x00, 0x00, 0x00, 0x00, 649 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 650 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 651 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x07, 0x10, 0x10, 0x2a, 0x32, 0x9f, 652 0x01, 0x5a, 0x91, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x12, 653 0x05, 0x02, 0x02, 0x10, 0x33, 0x02, 0x04, 0x18, 0x01); 654 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 655 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x7f, 0x11, 0xfd); 656 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); 657 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x3d); 658 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 659 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00, 0x00, 0x80, 0x80, 0x0c, 660 0xa1); 661 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 662 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x03, 0xff, 0xff, 0xff, 0xff, 0x00, 663 0x03, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 664 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 665 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); 666 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x2d, 0x01, 0x7f, 0x0f, 667 0x7c, 0x10, 0xa0, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00); 668 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 669 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xf2); 670 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x02, 0x00, 0x00, 0x10, 0x58); 671 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x0a, 0x0a, 0x05, 0x03, 0x0a, 672 0x0a, 0x01, 0x03, 0x01, 0x01, 0x05, 0x0e); 673 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 674 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x03, 0x1f, 0xe0, 0x11, 0x70); 675 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 676 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xab, 0xff, 0xff, 0xff, 0xff, 0xa0, 677 0xab, 0xff, 0xff, 0xff, 0xff, 0xa0); 678 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, 0x01, 0xfe, 0x01, 679 0x00, 0x00, 0x00, 0x03, 0x00, 0x03, 0x81, 0x02, 0x40, 0x00, 680 0x20, 0x9e, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 681 0x00, 0x00); 682 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 683 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); 684 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); 685 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 686 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xab, 0xea, 0xaa, 0xaa, 0xa0, 687 0xaa, 0xab, 0xea, 0xaa, 0xaa, 0xa0, 0xaa, 0xbf, 0xff, 0xff, 688 0xfe, 0xa0, 0xaa, 0xbf, 0xff, 0xff, 0xfe, 0xa0, 0xaa, 0xaa, 689 0xaa, 0xaa, 0xaa, 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0); 690 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_E1, 0x00); 691 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 692 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); 693 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x96); 694 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 695 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 696 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); 697 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); 698 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 699 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 700 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); 701 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x84); 702 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); 703 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 704 hx83102_enable_extended_cmds(&dsi_ctx, false); 705 706 mipi_dsi_msleep(&dsi_ctx, 110); 707 708 return dsi_ctx.accum_err; 709 } 710 711 static int holitech_htf065h045_init(struct hx83102 *ctx) 712 { 713 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 714 715 msleep(50); 716 717 hx83102_enable_extended_cmds(&dsi_ctx, true); 718 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x22, 0x44, 0x27, 0x27, 0x32, 719 0x52, 0x57, 0x39, 0x08, 0x08, 0x08); 720 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x00, 0x06, 0x40, 0x00, 721 0x0e, 0xae, 0x38, 0x00, 0x00, 0x00, 0x00, 0xf4, 0xa0); 722 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x01, 0x58, 0x01, 0x58, 0x01, 723 0x58, 0x03, 0x58, 0x03, 0xff, 0x01, 0x20, 0x00, 0xff); 724 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02); 725 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00, 0x00, 0x00, 0x00, 0x00, 726 0x10, 0x00, 0x17, 0x00, 0x63, 0x37, 0x0e, 0x0e, 0x00, 0x00, 727 0x32, 0x10, 0x08, 0x00, 0x08, 0x32, 0x16, 0x4e, 0x06, 0x4e); 728 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x04, 0x0c, 0xb2, 0x01); 729 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x24, 0x25, 0x18, 0x18, 0x19, 730 0x19, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 731 0x18, 0x18, 0x18, 0x06, 0x07, 0x04, 0x05, 0x18, 0x18, 0x18, 732 0x18, 0x02, 0x03, 0x00, 0x01, 0x20, 0x21, 0x18, 0x18, 0x18, 733 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18); 734 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2, 0x00, 0x09, 0x16, 0x1f, 0x28, 735 0x4b, 0x65, 0x6d, 0x74, 0x70, 0x89, 0x8d, 0x91, 0xa0, 0x9e, 736 0xa8, 0xb2, 0xc8, 0xc9, 0x65, 0x6d, 0x78, 0x7f, 0x00, 0x09, 737 0x16, 0x1f, 0x28, 0x4b, 0x65, 0x6d, 0x74, 0x70, 0x89, 0x8d, 738 0x91, 0xa0, 0x9e, 0xa8, 0xb2, 0xc8, 0xc9, 0x65, 0x6d, 0x78, 739 0x7f); 740 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xff, 0x14, 0x00, 0x00); 741 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 742 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x01); 743 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 744 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xff, 0xff, 0xff, 0xff, 0xff, 745 0xf0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xf0); 746 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 747 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 748 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0, 0xaa, 0xaa, 0xaa, 749 0xaa, 0xaa, 0xa0, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xa0); 750 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 751 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x70, 0x23, 0xa8, 0x93, 0xb2, 752 0xc0, 0xc0, 0x01, 0x10, 0x00, 0x00, 0x00, 0x0d, 0x3d, 0x82, 753 0x77, 0x04, 0x01, 0x04); 754 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 755 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x01); 756 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 757 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x00, 0x53, 0x00, 0x02, 0x59); 758 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x00, 0x04, 0x9e, 0xf6, 759 0x00, 0x5d); 760 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 761 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x42, 0x00, 0x33, 0x00, 0x33, 762 0x88, 0xb3, 0x00); 763 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 764 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x20, 0x01); 765 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 766 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x7f, 0x03, 0xf5); 767 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 768 769 return dsi_ctx.accum_err; 770 } 771 772 /* This is HX83102-E, assuming commands are the same as the normal HX83102 */ 773 static int waveshare_12_3_a_init(struct hx83102 *ctx) 774 { 775 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; 776 777 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETEXTC, 0x83, 0x10, 0x2e); 778 779 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcd); 780 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BB, 0x01); 781 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x00); 782 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x67, 0x2c, 0xff, 0x05); 783 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x11, 0x96, 0x89); 784 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0x04, 0x03, 0x04); 785 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 786 0x10, 0xfa, 0xaf, 0xaf, 0x33, 0x33, 0xb1, 0x4d, 0x2f, 0x36, 787 0x36, 0x36, 0x36, 0x22, 0x21, 0x15, 0x00); 788 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 789 0x00, 0xd0, 0x27, 0x80, 0x00, 0x14, 0x40, 0x2c, 0x32, 0x02, 790 0x00, 0x00, 0x15, 0x20, 0xd7, 0x00); 791 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 792 0x98, 0xa0, 0x01, 0x01, 0x98, 0xa0, 0x68, 0x50, 0x01, 0xc7, 793 0x01, 0x58, 0x00, 0xff, 0x00, 0xff); 794 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_B6, 0x4d, 0x4d, 0xe3); 795 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0x85, 0x80); 796 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x33, 0x33); 797 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 798 0x00, 0x00, 0x00, 0x00, 0x64, 0x04, 0x00, 0x08, 0x08, 0x27, 799 0x27, 0x22, 0x2f, 0x15, 0x15, 0x04, 0x04, 0x32, 0x10, 0x13, 800 0x00, 0x13, 0x32, 0x10, 0x1f, 0x00, 801 0x02, 0x32, 0x17, 0xfd, 0x00, 0x10, 0x00, 0x00, 0x20, 802 0x30, 0x01, 0x55, 0x21, 0x38, 0x01, 0x55, 0x0f); 803 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGMA, 804 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64, 0x69, 0x6c, 0x64, 805 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85, 0x9a, 0x97, 0x4d, 806 0x56, 0x64, 0x70, 0x00, 0x0c, 0x1a, 0x23, 0x2b, 0x4f, 0x64, 807 0x69, 0x6c, 0x64, 0x77, 0x77, 0x76, 0x80, 0x79, 0x7e, 0x85, 808 0x9a, 0x97, 0x4d, 0x56, 0x64, 0x76); 809 810 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 811 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x9b, 0x01, 0x31); 812 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 813 0x80, 0x36, 0x12, 0x16, 0xc0, 0x28, 0x40, 0x84, 0x22); 814 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 815 0x01, 0x00, 0xfc, 0x00, 0x00, 0x11, 0x10, 0x00, 0x0e, 0x00, 816 0x01); 817 818 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 819 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x4e, 0x00, 0x33, 0x11, 0x33, 0x88); 820 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xf2, 0x00, 0x02); 821 822 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 823 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 824 0x23, 0x23, 0x22, 0x11, 0xa2, 0x17, 0x00, 0x80, 0x00, 0x00, 825 0x08, 0x00, 0x63, 0x63); 826 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C6, 0xf9); 827 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x30); 828 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 829 0x00, 0x04, 0x04, 0x00, 0x00, 0x82, 0x13, 0x01); 830 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCASCADE, 0x07, 0x04, 0x05); 831 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 832 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x21, 0x20, 0x21, 0x20, 833 0x01, 0x00, 0x03, 0x02, 0x05, 0x04, 0x07, 0x06, 0x1a, 0x1a, 834 0x1a, 0x1a, 0x9a, 0x9a, 0x9a, 0x9a, 0x18, 0x18, 0x18, 0x18, 835 0x21, 0x20, 0x21, 0x20, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 836 0x18, 0x18, 0x18, 0x18); 837 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP2, 838 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x20, 0x21, 0x20, 0x21, 839 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x1a, 0x1a, 840 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x1a, 0x18, 0x18, 0x18, 0x18, 841 0x20, 0x21, 0x20, 0x21, 0x98, 0x98, 0x98, 0x98, 0x98, 0x98, 842 0x98, 0x98, 0x98, 0x98); 843 844 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 845 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 846 0x00, 0x34, 0x01, 0x88, 0x0e, 0xbe, 0x0f); 847 848 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 849 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_C2, 0x43, 0xff, 0x10); 850 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02); 851 852 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); 853 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x80); 854 855 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 856 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 857 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 858 0xaa, 0xaa, 0xaa, 0x80, 0x2a, 0xaa, 0xaa, 0xaa, 0xaa, 0x80, 859 0x2a, 0xaa, 0xaa, 0xaa); 860 861 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); 862 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 863 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 864 0xaa, 0xaa); 865 866 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); 867 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 868 0xff, 0xff, 0xff, 0xff, 869 0xff, 0xf0, 0xff, 0xff, 870 0xff, 0xff, 0xff, 0xf0); 871 872 mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); 873 874 return dsi_ctx.accum_err; 875 }; 876 877 static const struct drm_display_mode starry_mode = { 878 .clock = 162680, 879 .hdisplay = 1200, 880 .hsync_start = 1200 + 60, 881 .hsync_end = 1200 + 60 + 20, 882 .htotal = 1200 + 60 + 20 + 40, 883 .vdisplay = 1920, 884 .vsync_start = 1920 + 116, 885 .vsync_end = 1920 + 116 + 8, 886 .vtotal = 1920 + 116 + 8 + 12, 887 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 888 }; 889 890 static const struct hx83102_panel_desc starry_desc = { 891 .modes = &starry_mode, 892 .size = { 893 .width_mm = 141, 894 .height_mm = 226, 895 }, 896 .init = starry_himax83102_j02_init, 897 }; 898 899 static const struct drm_display_mode boe_tv110wum_default_mode = { 900 .clock = 167700, 901 .hdisplay = 1200, 902 .hsync_start = 1200 + 75, 903 .hsync_end = 1200 + 75 + 20, 904 .htotal = 1200 + 75 + 20 + 65, 905 .vdisplay = 1920, 906 .vsync_start = 1920 + 115, 907 .vsync_end = 1920 + 115 + 8, 908 .vtotal = 1920 + 115 + 8 + 12, 909 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 910 }; 911 912 static const struct hx83102_panel_desc boe_nv110wum_desc = { 913 .modes = &boe_tv110wum_default_mode, 914 .size = { 915 .width_mm = 147, 916 .height_mm = 235, 917 }, 918 .init = boe_nv110wum_init, 919 }; 920 921 static const struct drm_display_mode csot_pna957qt1_1_default_mode = { 922 .clock = 177958, 923 .hdisplay = 1200, 924 .hsync_start = 1200 + 124, 925 .hsync_end = 1200 + 124 + 80, 926 .htotal = 1200 + 124 + 80 + 40, 927 .vdisplay = 1920, 928 .vsync_start = 1920 + 88, 929 .vsync_end = 1920 + 88 + 8, 930 .vtotal = 1920 + 88 + 8 + 38, 931 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 932 }; 933 934 static const struct hx83102_panel_desc csot_pna957qt1_1_desc = { 935 .modes = &csot_pna957qt1_1_default_mode, 936 .size = { 937 .width_mm = 147, 938 .height_mm = 235, 939 }, 940 .init = csot_pna957qt1_1_init, 941 }; 942 943 static const struct drm_display_mode ivo_t109nw41_default_mode = { 944 .clock = 167700, 945 .hdisplay = 1200, 946 .hsync_start = 1200 + 75, 947 .hsync_end = 1200 + 75 + 20, 948 .htotal = 1200 + 75 + 20 + 65, 949 .vdisplay = 1920, 950 .vsync_start = 1920 + 115, 951 .vsync_end = 1920 + 115 + 8, 952 .vtotal = 1920 + 115 + 8 + 12, 953 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 954 }; 955 956 static const struct hx83102_panel_desc ivo_t109nw41_desc = { 957 .modes = &ivo_t109nw41_default_mode, 958 .size = { 959 .width_mm = 147, 960 .height_mm = 235, 961 }, 962 .init = ivo_t109nw41_init, 963 }; 964 965 static const struct drm_display_mode kingdisplay_kd110n11_51ie_default_mode = { 966 .clock = 182750, 967 .hdisplay = 1200, 968 .hsync_start = 1200 + 124, 969 .hsync_end = 1200 + 124 + 80, 970 .htotal = 1200 + 124 + 80 + 80, 971 .vdisplay = 1920, 972 .vsync_start = 1920 + 88, 973 .vsync_end = 1920 + 88 + 8, 974 .vtotal = 1920 + 88 + 8 + 38, 975 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 976 }; 977 978 static const struct hx83102_panel_desc kingdisplay_kd110n11_51ie_desc = { 979 .modes = &kingdisplay_kd110n11_51ie_default_mode, 980 .size = { 981 .width_mm = 147, 982 .height_mm = 235, 983 }, 984 .init = kingdisplay_kd110n11_51ie_init, 985 }; 986 987 static const struct drm_display_mode starry_2082109qfh040022_50e_default_mode = { 988 .clock = 192050, 989 .hdisplay = 1200, 990 .hsync_start = 1200 + 160, 991 .hsync_end = 1200 + 160 + 66, 992 .htotal = 1200 + 160 + 66 + 120, 993 .vdisplay = 1920, 994 .vsync_start = 1920 + 115, 995 .vsync_end = 1920 + 115 + 8, 996 .vtotal = 1920 + 115 + 8 + 28, 997 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 998 }; 999 1000 static const struct hx83102_panel_desc starry_2082109qfh040022_50e_desc = { 1001 .modes = &starry_2082109qfh040022_50e_default_mode, 1002 .size = { 1003 .width_mm = 147, 1004 .height_mm = 235, 1005 }, 1006 .init = starry_2082109qfh040022_50e_init, 1007 }; 1008 1009 static const struct drm_display_mode holitech_htf065h045_default_mode = { 1010 .clock = 90720, 1011 .hdisplay = 720, 1012 .hsync_start = 720 + 40, 1013 .hsync_end = 720 + 40 + 40, 1014 .htotal = 720 + 40 + 40 + 40, 1015 .vdisplay = 1600, 1016 .vsync_start = 1600 + 186, 1017 .vsync_end = 1600 + 186 + 2, 1018 .vtotal = 1600 + 186 + 2 + 12, 1019 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 1020 }; 1021 1022 static const struct hx83102_panel_desc holitech_htf065h045_desc = { 1023 .modes = &holitech_htf065h045_default_mode, 1024 .size = { 1025 .width_mm = 68, 1026 .height_mm = 151, 1027 }, 1028 .has_backlight = true, 1029 .init = holitech_htf065h045_init, 1030 }; 1031 1032 static const struct drm_display_mode waveshare_12_3_a_mode = { 1033 .clock = 95000, 1034 .hdisplay = 720, 1035 .hsync_start = 720 + 10, 1036 .hsync_end = 720 + 10 + 10, 1037 .htotal = 720 + 10 + 10 + 12, 1038 .vdisplay = 1920, 1039 .vsync_start = 1920 + 64, 1040 .vsync_end = 1920 + 64 + 18, 1041 .vtotal = 1920 + 64 + 18 + 4, 1042 .type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, 1043 }; 1044 1045 static const struct hx83102_panel_desc waveshare_12_3_inch_a_desc = { 1046 .modes = &waveshare_12_3_a_mode, 1047 .size = { 1048 .width_mm = 109, 1049 .height_mm = 292, 1050 }, 1051 .mode_flags = MIPI_DSI_MODE_VIDEO_HSE | MIPI_DSI_MODE_VIDEO | 1052 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS, 1053 .init = waveshare_12_3_a_init, 1054 }; 1055 1056 static int hx83102_enable(struct drm_panel *panel) 1057 { 1058 msleep(130); 1059 return 0; 1060 } 1061 1062 static int hx83102_disable(struct drm_panel *panel) 1063 { 1064 struct hx83102 *ctx = panel_to_hx83102(panel); 1065 struct mipi_dsi_device *dsi = ctx->dsi; 1066 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 1067 1068 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 1069 1070 mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); 1071 mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); 1072 1073 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 1074 1075 mipi_dsi_msleep(&dsi_ctx, 150); 1076 1077 return dsi_ctx.accum_err; 1078 } 1079 1080 static int hx83102_unprepare(struct drm_panel *panel) 1081 { 1082 struct hx83102 *ctx = panel_to_hx83102(panel); 1083 1084 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 1085 usleep_range(1000, 2000); 1086 regulator_disable(ctx->avee); 1087 regulator_disable(ctx->avdd); 1088 usleep_range(5000, 7000); 1089 regulator_disable(ctx->pp1800); 1090 1091 return 0; 1092 } 1093 1094 static int hx83102_prepare(struct drm_panel *panel) 1095 { 1096 struct hx83102 *ctx = panel_to_hx83102(panel); 1097 struct mipi_dsi_device *dsi = ctx->dsi; 1098 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; 1099 1100 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 1101 usleep_range(1000, 1500); 1102 1103 dsi_ctx.accum_err = regulator_enable(ctx->pp1800); 1104 if (dsi_ctx.accum_err) 1105 return dsi_ctx.accum_err; 1106 1107 usleep_range(3000, 5000); 1108 1109 dsi_ctx.accum_err = regulator_enable(ctx->avdd); 1110 if (dsi_ctx.accum_err) 1111 goto poweroff1v8; 1112 dsi_ctx.accum_err = regulator_enable(ctx->avee); 1113 if (dsi_ctx.accum_err) 1114 goto poweroffavdd; 1115 1116 usleep_range(10000, 11000); 1117 1118 mipi_dsi_dcs_nop_multi(&dsi_ctx); 1119 if (dsi_ctx.accum_err) 1120 goto poweroff; 1121 1122 usleep_range(1000, 2000); 1123 1124 gpiod_set_value_cansleep(ctx->enable_gpio, 1); 1125 usleep_range(1000, 2000); 1126 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 1127 usleep_range(1000, 2000); 1128 gpiod_set_value_cansleep(ctx->enable_gpio, 1); 1129 usleep_range(6000, 10000); 1130 1131 dsi_ctx.accum_err = ctx->desc->init(ctx); 1132 1133 mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); 1134 mipi_dsi_msleep(&dsi_ctx, 120); 1135 mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); 1136 if (dsi_ctx.accum_err) 1137 goto poweroff; 1138 1139 return 0; 1140 1141 poweroff: 1142 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 1143 regulator_disable(ctx->avee); 1144 poweroffavdd: 1145 regulator_disable(ctx->avdd); 1146 poweroff1v8: 1147 usleep_range(5000, 7000); 1148 regulator_disable(ctx->pp1800); 1149 1150 return dsi_ctx.accum_err; 1151 } 1152 1153 static int hx83102_get_modes(struct drm_panel *panel, 1154 struct drm_connector *connector) 1155 { 1156 struct hx83102 *ctx = panel_to_hx83102(panel); 1157 const struct drm_display_mode *m = ctx->desc->modes; 1158 struct drm_display_mode *mode; 1159 1160 mode = drm_mode_duplicate(connector->dev, m); 1161 if (!mode) 1162 return -ENOMEM; 1163 1164 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; 1165 drm_mode_set_name(mode); 1166 drm_mode_probed_add(connector, mode); 1167 1168 connector->display_info.width_mm = ctx->desc->size.width_mm; 1169 connector->display_info.height_mm = ctx->desc->size.height_mm; 1170 connector->display_info.bpc = 8; 1171 1172 return 1; 1173 } 1174 1175 static enum drm_panel_orientation hx83102_get_orientation(struct drm_panel *panel) 1176 { 1177 struct hx83102 *ctx = panel_to_hx83102(panel); 1178 1179 return ctx->orientation; 1180 } 1181 1182 static const struct drm_panel_funcs hx83102_drm_funcs = { 1183 .disable = hx83102_disable, 1184 .unprepare = hx83102_unprepare, 1185 .prepare = hx83102_prepare, 1186 .enable = hx83102_enable, 1187 .get_modes = hx83102_get_modes, 1188 .get_orientation = hx83102_get_orientation, 1189 }; 1190 1191 static int hx83102_bl_update_status(struct backlight_device *bl) 1192 { 1193 struct mipi_dsi_device *dsi = bl_get_data(bl); 1194 u16 brightness = backlight_get_brightness(bl); 1195 int ret; 1196 1197 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 1198 1199 ret = mipi_dsi_dcs_set_display_brightness_large(dsi, brightness); 1200 if (ret < 0) 1201 return ret; 1202 1203 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 1204 1205 return 0; 1206 } 1207 1208 static int hx83102_bl_get_brightness(struct backlight_device *bl) 1209 { 1210 struct mipi_dsi_device *dsi = bl_get_data(bl); 1211 u16 brightness; 1212 int ret; 1213 1214 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; 1215 1216 ret = mipi_dsi_dcs_get_display_brightness_large(dsi, &brightness); 1217 if (ret < 0) 1218 return ret; 1219 1220 dsi->mode_flags |= MIPI_DSI_MODE_LPM; 1221 1222 return brightness; 1223 } 1224 1225 static const struct backlight_ops hx83102_bl_ops = { 1226 .update_status = hx83102_bl_update_status, 1227 .get_brightness = hx83102_bl_get_brightness, 1228 }; 1229 1230 static struct backlight_device * 1231 hx83102_create_dcs_backlight(struct mipi_dsi_device *dsi) 1232 { 1233 struct device *dev = &dsi->dev; 1234 const struct backlight_properties props = { 1235 .type = BACKLIGHT_RAW, 1236 .brightness = 4095, 1237 .max_brightness = 4095, 1238 }; 1239 1240 return devm_backlight_device_register(dev, dev_name(dev), dev, dsi, 1241 &hx83102_bl_ops, &props); 1242 } 1243 1244 static int hx83102_panel_add(struct hx83102 *ctx) 1245 { 1246 struct device *dev = &ctx->dsi->dev; 1247 int err; 1248 1249 ctx->avdd = devm_regulator_get(dev, "avdd"); 1250 if (IS_ERR(ctx->avdd)) 1251 return PTR_ERR(ctx->avdd); 1252 1253 ctx->avee = devm_regulator_get(dev, "avee"); 1254 if (IS_ERR(ctx->avee)) 1255 return PTR_ERR(ctx->avee); 1256 1257 ctx->pp1800 = devm_regulator_get(dev, "pp1800"); 1258 if (IS_ERR(ctx->pp1800)) 1259 return PTR_ERR(ctx->pp1800); 1260 1261 ctx->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); 1262 if (IS_ERR(ctx->enable_gpio)) 1263 return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), "Cannot get enable GPIO\n"); 1264 1265 ctx->base.prepare_prev_first = true; 1266 1267 err = of_drm_get_panel_orientation(dev->of_node, &ctx->orientation); 1268 if (err < 0) 1269 return dev_err_probe(dev, err, "failed to get orientation\n"); 1270 1271 err = drm_panel_of_backlight(&ctx->base); 1272 if (err) 1273 return err; 1274 1275 /* Use DSI-based backlight as fallback if available */ 1276 if (ctx->desc->has_backlight && !ctx->base.backlight) { 1277 ctx->base.backlight = hx83102_create_dcs_backlight(ctx->dsi); 1278 if (IS_ERR(ctx->base.backlight)) 1279 return dev_err_probe(dev, PTR_ERR(ctx->base.backlight), 1280 "Failed to create backlight\n"); 1281 } 1282 1283 ctx->base.funcs = &hx83102_drm_funcs; 1284 ctx->base.dev = &ctx->dsi->dev; 1285 1286 drm_panel_add(&ctx->base); 1287 1288 return 0; 1289 } 1290 1291 static int hx83102_probe(struct mipi_dsi_device *dsi) 1292 { 1293 struct hx83102 *ctx; 1294 int ret; 1295 const struct hx83102_panel_desc *desc; 1296 1297 ctx = devm_drm_panel_alloc(&dsi->dev, __typeof(*ctx), base, 1298 &hx83102_drm_funcs, DRM_MODE_CONNECTOR_DSI); 1299 1300 if (IS_ERR(ctx)) 1301 return PTR_ERR(ctx); 1302 1303 desc = of_device_get_match_data(&dsi->dev); 1304 dsi->lanes = 4; 1305 dsi->format = MIPI_DSI_FMT_RGB888; 1306 if (desc->mode_flags) 1307 dsi->mode_flags = desc->mode_flags; 1308 else 1309 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 1310 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 1311 MIPI_DSI_MODE_LPM; 1312 ctx->desc = desc; 1313 ctx->dsi = dsi; 1314 ret = hx83102_panel_add(ctx); 1315 if (ret < 0) 1316 return ret; 1317 1318 mipi_dsi_set_drvdata(dsi, ctx); 1319 1320 ret = mipi_dsi_attach(dsi); 1321 if (ret) 1322 drm_panel_remove(&ctx->base); 1323 1324 return ret; 1325 } 1326 1327 static void hx83102_remove(struct mipi_dsi_device *dsi) 1328 { 1329 struct hx83102 *ctx = mipi_dsi_get_drvdata(dsi); 1330 int ret; 1331 1332 ret = mipi_dsi_detach(dsi); 1333 if (ret < 0) 1334 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", ret); 1335 1336 if (ctx->base.dev) 1337 drm_panel_remove(&ctx->base); 1338 } 1339 1340 static const struct of_device_id hx83102_of_match[] = { 1341 { .compatible = "boe,nv110wum-l60", 1342 .data = &boe_nv110wum_desc 1343 }, 1344 { .compatible = "csot,pna957qt1-1", 1345 .data = &csot_pna957qt1_1_desc 1346 }, 1347 { .compatible = "ivo,t109nw41", 1348 .data = &ivo_t109nw41_desc 1349 }, 1350 { .compatible = "kingdisplay,kd110n11-51ie", 1351 .data = &kingdisplay_kd110n11_51ie_desc 1352 }, 1353 { .compatible = "starry,2082109qfh040022-50e", 1354 .data = &starry_2082109qfh040022_50e_desc 1355 }, 1356 { .compatible = "starry,himax83102-j02", 1357 .data = &starry_desc 1358 }, 1359 { .compatible = "holitech,htf065h045", 1360 .data = &holitech_htf065h045_desc 1361 }, 1362 { .compatible = "waveshare,12.3-dsi-touch-a", 1363 .data = &waveshare_12_3_inch_a_desc 1364 }, 1365 { /* sentinel */ } 1366 }; 1367 MODULE_DEVICE_TABLE(of, hx83102_of_match); 1368 1369 static struct mipi_dsi_driver hx83102_driver = { 1370 .probe = hx83102_probe, 1371 .remove = hx83102_remove, 1372 .driver = { 1373 .name = "panel-himax-hx83102", 1374 .of_match_table = hx83102_of_match, 1375 }, 1376 }; 1377 module_mipi_dsi_driver(hx83102_driver); 1378 1379 MODULE_AUTHOR("Cong Yang <yangcong5@huaqin.corp-partner.google.com>"); 1380 MODULE_DESCRIPTION("DRM driver for Himax HX83102 based MIPI DSI panels"); 1381 MODULE_LICENSE("GPL"); 1382