xref: /linux/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1 /*
2  * Copyright 2019 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #ifndef AMDGPU_DM_AMDGPU_DM_HDCP_H_
27 #define AMDGPU_DM_AMDGPU_DM_HDCP_H_
28 
29 #include "mod_hdcp.h"
30 #include "hdcp.h"
31 #include "dc.h"
32 #include "dm_cp_psp.h"
33 #include "amdgpu.h"
34 
35 struct mod_hdcp;
36 struct mod_hdcp_link;
37 struct mod_hdcp_display;
38 struct cp_psp;
39 
40 struct hdcp_workqueue {
41 	struct work_struct cpirq_work;
42 	struct work_struct property_update_work;
43 	struct delayed_work callback_dwork;
44 	struct delayed_work watchdog_timer_dwork;
45 	struct delayed_work property_validate_dwork;
46 	struct amdgpu_dm_connector *aconnector[AMDGPU_DM_MAX_DISPLAY_INDEX];
47 	struct mutex mutex;
48 
49 	struct mod_hdcp hdcp;
50 	struct mod_hdcp_output output;
51 	struct mod_hdcp_display display;
52 	struct mod_hdcp_link link;
53 
54 	enum mod_hdcp_encryption_status encryption_status[AMDGPU_DM_MAX_DISPLAY_INDEX];
55 	/* when display is unplugged from mst hub, connctor will be
56 	 * destroyed within dm_dp_mst_connector_destroy. connector
57 	 * hdcp perperties, like type, undesired, desired, enabled,
58 	 * will be lost. So, save hdcp properties into hdcp_work within
59 	 * amdgpu_dm_atomic_commit_tail. if the same display is
60 	 * plugged back with same display index, its hdcp properties
61 	 * will be retrieved from hdcp_work within dm_dp_mst_get_modes
62 	 */
63 	/* un-desired, desired, enabled */
64 	unsigned int content_protection[AMDGPU_DM_MAX_DISPLAY_INDEX];
65 	/* hdcp1.x, hdcp2.x */
66 	unsigned int hdcp_content_type[AMDGPU_DM_MAX_DISPLAY_INDEX];
67 
68 	uint8_t max_link;
69 
70 	uint8_t *srm;
71 	uint8_t *srm_temp;
72 	uint32_t srm_version;
73 	uint32_t srm_size;
74 	struct bin_attribute attr;
75 };
76 
77 void hdcp_update_display(struct hdcp_workqueue *hdcp_work,
78 			 unsigned int link_index,
79 			 struct amdgpu_dm_connector *aconnector,
80 			 uint8_t content_type,
81 			 bool enable_encryption);
82 
83 void hdcp_reset_display(struct hdcp_workqueue *work, unsigned int link_index);
84 void hdcp_handle_cpirq(struct hdcp_workqueue *work, unsigned int link_index);
85 void hdcp_destroy(struct kobject *kobj, struct hdcp_workqueue *work);
86 
87 struct hdcp_workqueue *hdcp_create_workqueue(struct amdgpu_device *adev, struct cp_psp *cp_psp, struct dc *dc);
88 
89 #endif /* AMDGPU_DM_AMDGPU_DM_HDCP_H_ */
90