1 /* CoreChip-sz SR9800 one chip USB 2.0 Ethernet Devices 2 * 3 * Author : Liu Junliang <liujunliang_ljl@163.com> 4 * 5 * Based on asix_common.c, asix_devices.c 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied.* 10 */ 11 12 #include <linux/module.h> 13 #include <linux/kmod.h> 14 #include <linux/init.h> 15 #include <linux/netdevice.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/workqueue.h> 19 #include <linux/mii.h> 20 #include <linux/usb.h> 21 #include <linux/crc32.h> 22 #include <linux/usb/usbnet.h> 23 #include <linux/slab.h> 24 #include <linux/if_vlan.h> 25 26 #include "sr9800.h" 27 28 static int sr_read_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 29 u16 size, void *data) 30 { 31 int err; 32 33 err = usbnet_read_cmd(dev, cmd, SR_REQ_RD_REG, value, index, 34 data, size); 35 if ((err != size) && (err >= 0)) 36 err = -EINVAL; 37 38 return err; 39 } 40 41 static int sr_write_cmd(struct usbnet *dev, u8 cmd, u16 value, u16 index, 42 u16 size, void *data) 43 { 44 int err; 45 46 err = usbnet_write_cmd(dev, cmd, SR_REQ_WR_REG, value, index, 47 data, size); 48 if ((err != size) && (err >= 0)) 49 err = -EINVAL; 50 51 return err; 52 } 53 54 static void 55 sr_write_cmd_async(struct usbnet *dev, u8 cmd, u16 value, u16 index, 56 u16 size, void *data) 57 { 58 usbnet_write_cmd_async(dev, cmd, SR_REQ_WR_REG, value, index, data, 59 size); 60 } 61 62 static int sr_rx_fixup(struct usbnet *dev, struct sk_buff *skb) 63 { 64 int offset = 0; 65 66 /* This check is no longer done by usbnet */ 67 if (skb->len < dev->net->hard_header_len) 68 return 0; 69 70 while (offset + sizeof(u32) < skb->len) { 71 struct sk_buff *sr_skb; 72 u16 size; 73 u32 header = get_unaligned_le32(skb->data + offset); 74 75 offset += sizeof(u32); 76 /* get the packet length */ 77 size = (u16) (header & 0x7ff); 78 if (size != ((~header >> 16) & 0x07ff)) { 79 netdev_err(dev->net, "%s : Bad Header Length\n", 80 __func__); 81 return 0; 82 } 83 84 if ((size > dev->net->mtu + ETH_HLEN + VLAN_HLEN) || 85 (size + offset > skb->len)) { 86 netdev_err(dev->net, "%s : Bad RX Length %d\n", 87 __func__, size); 88 return 0; 89 } 90 sr_skb = netdev_alloc_skb_ip_align(dev->net, size); 91 if (!sr_skb) 92 return 0; 93 94 skb_put(sr_skb, size); 95 memcpy(sr_skb->data, skb->data + offset, size); 96 usbnet_skb_return(dev, sr_skb); 97 98 offset += (size + 1) & 0xfffe; 99 } 100 101 if (skb->len != offset) { 102 netdev_err(dev->net, "%s : Bad SKB Length %d\n", __func__, 103 skb->len); 104 return 0; 105 } 106 107 return 1; 108 } 109 110 static struct sk_buff *sr_tx_fixup(struct usbnet *dev, struct sk_buff *skb, 111 gfp_t flags) 112 { 113 int headroom = skb_headroom(skb); 114 int tailroom = skb_tailroom(skb); 115 u32 padbytes = 0xffff0000; 116 u32 packet_len; 117 int padlen; 118 void *ptr; 119 120 padlen = ((skb->len + 4) % (dev->maxpacket - 1)) ? 0 : 4; 121 122 if ((!skb_cloned(skb)) && ((headroom + tailroom) >= (4 + padlen))) { 123 if ((headroom < 4) || (tailroom < padlen)) { 124 skb->data = memmove(skb->head + 4, skb->data, 125 skb->len); 126 skb_set_tail_pointer(skb, skb->len); 127 } 128 } else { 129 struct sk_buff *skb2; 130 skb2 = skb_copy_expand(skb, 4, padlen, flags); 131 dev_kfree_skb_any(skb); 132 skb = skb2; 133 if (!skb) 134 return NULL; 135 } 136 137 ptr = skb_push(skb, 4); 138 packet_len = (((skb->len - 4) ^ 0x0000ffff) << 16) + (skb->len - 4); 139 put_unaligned_le32(packet_len, ptr); 140 141 if (padlen) { 142 put_unaligned_le32(padbytes, skb_tail_pointer(skb)); 143 skb_put(skb, sizeof(padbytes)); 144 } 145 146 usbnet_set_skb_tx_stats(skb, 1, 0); 147 return skb; 148 } 149 150 static void sr_status(struct usbnet *dev, struct urb *urb) 151 { 152 struct sr9800_int_data *event; 153 int link; 154 155 if (urb->actual_length < 8) 156 return; 157 158 event = urb->transfer_buffer; 159 link = event->link & 0x01; 160 if (netif_carrier_ok(dev->net) != link) { 161 usbnet_link_change(dev, link, 1); 162 netdev_dbg(dev->net, "Link Status is: %d\n", link); 163 } 164 165 return; 166 } 167 168 static inline int sr_set_sw_mii(struct usbnet *dev) 169 { 170 int ret; 171 172 ret = sr_write_cmd(dev, SR_CMD_SET_SW_MII, 0x0000, 0, 0, NULL); 173 if (ret < 0) 174 netdev_err(dev->net, "Failed to enable software MII access\n"); 175 return ret; 176 } 177 178 static inline int sr_set_hw_mii(struct usbnet *dev) 179 { 180 int ret; 181 182 ret = sr_write_cmd(dev, SR_CMD_SET_HW_MII, 0x0000, 0, 0, NULL); 183 if (ret < 0) 184 netdev_err(dev->net, "Failed to enable hardware MII access\n"); 185 return ret; 186 } 187 188 static inline int sr_get_phy_addr(struct usbnet *dev) 189 { 190 u8 buf[2]; 191 int ret; 192 193 ret = sr_read_cmd(dev, SR_CMD_READ_PHY_ID, 0, 0, 2, buf); 194 if (ret < 0) { 195 netdev_err(dev->net, "%s : Error reading PHYID register:%02x\n", 196 __func__, ret); 197 goto out; 198 } 199 netdev_dbg(dev->net, "%s : returning 0x%04x\n", __func__, 200 *((__le16 *)buf)); 201 202 ret = buf[1]; 203 204 out: 205 return ret; 206 } 207 208 static int sr_sw_reset(struct usbnet *dev, u8 flags) 209 { 210 int ret; 211 212 ret = sr_write_cmd(dev, SR_CMD_SW_RESET, flags, 0, 0, NULL); 213 if (ret < 0) 214 netdev_err(dev->net, "Failed to send software reset:%02x\n", 215 ret); 216 217 return ret; 218 } 219 220 static u16 sr_read_rx_ctl(struct usbnet *dev) 221 { 222 __le16 v; 223 int ret; 224 225 ret = sr_read_cmd(dev, SR_CMD_READ_RX_CTL, 0, 0, 2, &v); 226 if (ret < 0) { 227 netdev_err(dev->net, "Error reading RX_CTL register:%02x\n", 228 ret); 229 goto out; 230 } 231 232 ret = le16_to_cpu(v); 233 out: 234 return ret; 235 } 236 237 static int sr_write_rx_ctl(struct usbnet *dev, u16 mode) 238 { 239 int ret; 240 241 netdev_dbg(dev->net, "%s : mode = 0x%04x\n", __func__, mode); 242 ret = sr_write_cmd(dev, SR_CMD_WRITE_RX_CTL, mode, 0, 0, NULL); 243 if (ret < 0) 244 netdev_err(dev->net, 245 "Failed to write RX_CTL mode to 0x%04x:%02x\n", 246 mode, ret); 247 248 return ret; 249 } 250 251 static u16 sr_read_medium_status(struct usbnet *dev) 252 { 253 __le16 v; 254 int ret; 255 256 ret = sr_read_cmd(dev, SR_CMD_READ_MEDIUM_STATUS, 0, 0, 2, &v); 257 if (ret < 0) { 258 netdev_err(dev->net, 259 "Error reading Medium Status register:%02x\n", ret); 260 return ret; /* TODO: callers not checking for error ret */ 261 } 262 263 return le16_to_cpu(v); 264 } 265 266 static int sr_write_medium_mode(struct usbnet *dev, u16 mode) 267 { 268 int ret; 269 270 netdev_dbg(dev->net, "%s : mode = 0x%04x\n", __func__, mode); 271 ret = sr_write_cmd(dev, SR_CMD_WRITE_MEDIUM_MODE, mode, 0, 0, NULL); 272 if (ret < 0) 273 netdev_err(dev->net, 274 "Failed to write Medium Mode mode to 0x%04x:%02x\n", 275 mode, ret); 276 return ret; 277 } 278 279 static int sr_write_gpio(struct usbnet *dev, u16 value, int sleep) 280 { 281 int ret; 282 283 netdev_dbg(dev->net, "%s : value = 0x%04x\n", __func__, value); 284 ret = sr_write_cmd(dev, SR_CMD_WRITE_GPIOS, value, 0, 0, NULL); 285 if (ret < 0) 286 netdev_err(dev->net, "Failed to write GPIO value 0x%04x:%02x\n", 287 value, ret); 288 if (sleep) 289 msleep(sleep); 290 291 return ret; 292 } 293 294 /* SR9800 have a 16-bit RX_CTL value */ 295 static void sr_set_multicast(struct net_device *net) 296 { 297 struct usbnet *dev = netdev_priv(net); 298 struct sr_data *data = (struct sr_data *)&dev->data; 299 u16 rx_ctl = SR_DEFAULT_RX_CTL; 300 301 if (net->flags & IFF_PROMISC) { 302 rx_ctl |= SR_RX_CTL_PRO; 303 } else if (net->flags & IFF_ALLMULTI || 304 netdev_mc_count(net) > SR_MAX_MCAST) { 305 rx_ctl |= SR_RX_CTL_AMALL; 306 } else if (netdev_mc_empty(net)) { 307 /* just broadcast and directed */ 308 } else { 309 /* We use the 20 byte dev->data 310 * for our 8 byte filter buffer 311 * to avoid allocating memory that 312 * is tricky to free later 313 */ 314 struct netdev_hw_addr *ha; 315 u32 crc_bits; 316 317 memset(data->multi_filter, 0, SR_MCAST_FILTER_SIZE); 318 319 /* Build the multicast hash filter. */ 320 netdev_for_each_mc_addr(ha, net) { 321 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26; 322 data->multi_filter[crc_bits >> 3] |= 323 1 << (crc_bits & 7); 324 } 325 326 sr_write_cmd_async(dev, SR_CMD_WRITE_MULTI_FILTER, 0, 0, 327 SR_MCAST_FILTER_SIZE, data->multi_filter); 328 329 rx_ctl |= SR_RX_CTL_AM; 330 } 331 332 sr_write_cmd_async(dev, SR_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL); 333 } 334 335 static int sr_mdio_read(struct net_device *net, int phy_id, int loc) 336 { 337 struct usbnet *dev = netdev_priv(net); 338 __le16 res = 0; 339 340 mutex_lock(&dev->phy_mutex); 341 sr_set_sw_mii(dev); 342 sr_read_cmd(dev, SR_CMD_READ_MII_REG, phy_id, (__u16)loc, 2, &res); 343 sr_set_hw_mii(dev); 344 mutex_unlock(&dev->phy_mutex); 345 346 netdev_dbg(dev->net, 347 "%s : phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n", __func__, 348 phy_id, loc, le16_to_cpu(res)); 349 350 return le16_to_cpu(res); 351 } 352 353 static void 354 sr_mdio_write(struct net_device *net, int phy_id, int loc, int val) 355 { 356 struct usbnet *dev = netdev_priv(net); 357 __le16 res = cpu_to_le16(val); 358 359 netdev_dbg(dev->net, 360 "%s : phy_id=0x%02x, loc=0x%02x, val=0x%04x\n", __func__, 361 phy_id, loc, val); 362 mutex_lock(&dev->phy_mutex); 363 sr_set_sw_mii(dev); 364 sr_write_cmd(dev, SR_CMD_WRITE_MII_REG, phy_id, (__u16)loc, 2, &res); 365 sr_set_hw_mii(dev); 366 mutex_unlock(&dev->phy_mutex); 367 } 368 369 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */ 370 static u32 sr_get_phyid(struct usbnet *dev) 371 { 372 int phy_reg; 373 u32 phy_id; 374 int i; 375 376 /* Poll for the rare case the FW or phy isn't ready yet. */ 377 for (i = 0; i < 100; i++) { 378 phy_reg = sr_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1); 379 if (phy_reg != 0 && phy_reg != 0xFFFF) 380 break; 381 mdelay(1); 382 } 383 384 if (phy_reg <= 0 || phy_reg == 0xFFFF) 385 return 0; 386 387 phy_id = (phy_reg & 0xffff) << 16; 388 389 phy_reg = sr_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2); 390 if (phy_reg < 0) 391 return 0; 392 393 phy_id |= (phy_reg & 0xffff); 394 395 return phy_id; 396 } 397 398 static void 399 sr_get_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 400 { 401 struct usbnet *dev = netdev_priv(net); 402 u8 opt; 403 404 if (sr_read_cmd(dev, SR_CMD_READ_MONITOR_MODE, 0, 0, 1, &opt) < 0) { 405 wolinfo->supported = 0; 406 wolinfo->wolopts = 0; 407 return; 408 } 409 wolinfo->supported = WAKE_PHY | WAKE_MAGIC; 410 wolinfo->wolopts = 0; 411 if (opt & SR_MONITOR_LINK) 412 wolinfo->wolopts |= WAKE_PHY; 413 if (opt & SR_MONITOR_MAGIC) 414 wolinfo->wolopts |= WAKE_MAGIC; 415 } 416 417 static int 418 sr_set_wol(struct net_device *net, struct ethtool_wolinfo *wolinfo) 419 { 420 struct usbnet *dev = netdev_priv(net); 421 u8 opt = 0; 422 423 if (wolinfo->wolopts & ~(WAKE_PHY | WAKE_MAGIC)) 424 return -EINVAL; 425 426 if (wolinfo->wolopts & WAKE_PHY) 427 opt |= SR_MONITOR_LINK; 428 if (wolinfo->wolopts & WAKE_MAGIC) 429 opt |= SR_MONITOR_MAGIC; 430 431 if (sr_write_cmd(dev, SR_CMD_WRITE_MONITOR_MODE, 432 opt, 0, 0, NULL) < 0) 433 return -EINVAL; 434 435 return 0; 436 } 437 438 static int sr_get_eeprom_len(struct net_device *net) 439 { 440 struct usbnet *dev = netdev_priv(net); 441 struct sr_data *data = (struct sr_data *)&dev->data; 442 443 return data->eeprom_len; 444 } 445 446 static int sr_get_eeprom(struct net_device *net, 447 struct ethtool_eeprom *eeprom, u8 *data) 448 { 449 struct usbnet *dev = netdev_priv(net); 450 __le16 *ebuf = (__le16 *)data; 451 int ret; 452 int i; 453 454 /* Crude hack to ensure that we don't overwrite memory 455 * if an odd length is supplied 456 */ 457 if (eeprom->len % 2) 458 return -EINVAL; 459 460 eeprom->magic = SR_EEPROM_MAGIC; 461 462 /* sr9800 returns 2 bytes from eeprom on read */ 463 for (i = 0; i < eeprom->len / 2; i++) { 464 ret = sr_read_cmd(dev, SR_CMD_READ_EEPROM, eeprom->offset + i, 465 0, 2, &ebuf[i]); 466 if (ret < 0) 467 return -EINVAL; 468 } 469 return 0; 470 } 471 472 static int sr_set_mac_address(struct net_device *net, void *p) 473 { 474 struct usbnet *dev = netdev_priv(net); 475 struct sr_data *data = (struct sr_data *)&dev->data; 476 struct sockaddr *addr = p; 477 478 if (netif_running(net)) 479 return -EBUSY; 480 if (!is_valid_ether_addr(addr->sa_data)) 481 return -EADDRNOTAVAIL; 482 483 eth_hw_addr_set(net, addr->sa_data); 484 485 /* We use the 20 byte dev->data 486 * for our 6 byte mac buffer 487 * to avoid allocating memory that 488 * is tricky to free later 489 */ 490 memcpy(data->mac_addr, addr->sa_data, ETH_ALEN); 491 sr_write_cmd_async(dev, SR_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 492 data->mac_addr); 493 494 return 0; 495 } 496 497 static const struct ethtool_ops sr9800_ethtool_ops = { 498 .get_drvinfo = usbnet_get_drvinfo, 499 .get_link = usbnet_get_link, 500 .get_msglevel = usbnet_get_msglevel, 501 .set_msglevel = usbnet_set_msglevel, 502 .get_wol = sr_get_wol, 503 .set_wol = sr_set_wol, 504 .get_eeprom_len = sr_get_eeprom_len, 505 .get_eeprom = sr_get_eeprom, 506 .nway_reset = usbnet_nway_reset, 507 .get_link_ksettings = usbnet_get_link_ksettings_mii, 508 .set_link_ksettings = usbnet_set_link_ksettings_mii, 509 }; 510 511 static int sr9800_link_reset(struct usbnet *dev) 512 { 513 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET }; 514 u16 mode; 515 516 mii_check_media(&dev->mii, 1, 1); 517 mii_ethtool_gset(&dev->mii, &ecmd); 518 mode = SR9800_MEDIUM_DEFAULT; 519 520 if (ethtool_cmd_speed(&ecmd) != SPEED_100) 521 mode &= ~SR_MEDIUM_PS; 522 523 if (ecmd.duplex != DUPLEX_FULL) 524 mode &= ~SR_MEDIUM_FD; 525 526 netdev_dbg(dev->net, "%s : speed: %u duplex: %d mode: 0x%04x\n", 527 __func__, ethtool_cmd_speed(&ecmd), ecmd.duplex, mode); 528 529 sr_write_medium_mode(dev, mode); 530 531 return 0; 532 } 533 534 535 static int sr9800_set_default_mode(struct usbnet *dev) 536 { 537 u16 rx_ctl; 538 int ret; 539 540 sr_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, BMCR_RESET); 541 sr_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE, 542 ADVERTISE_ALL | ADVERTISE_CSMA); 543 mii_nway_restart(&dev->mii); 544 545 ret = sr_write_medium_mode(dev, SR9800_MEDIUM_DEFAULT); 546 if (ret < 0) 547 goto out; 548 549 ret = sr_write_cmd(dev, SR_CMD_WRITE_IPG012, 550 SR9800_IPG0_DEFAULT | SR9800_IPG1_DEFAULT, 551 SR9800_IPG2_DEFAULT, 0, NULL); 552 if (ret < 0) { 553 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret); 554 goto out; 555 } 556 557 /* Set RX_CTL to default values with 2k buffer, and enable cactus */ 558 ret = sr_write_rx_ctl(dev, SR_DEFAULT_RX_CTL); 559 if (ret < 0) 560 goto out; 561 562 rx_ctl = sr_read_rx_ctl(dev); 563 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n", 564 rx_ctl); 565 566 rx_ctl = sr_read_medium_status(dev); 567 netdev_dbg(dev->net, "Medium Status:0x%04x after all initializations\n", 568 rx_ctl); 569 570 return 0; 571 out: 572 return ret; 573 } 574 575 static int sr9800_reset(struct usbnet *dev) 576 { 577 struct sr_data *data = (struct sr_data *)&dev->data; 578 int ret, embd_phy; 579 u16 rx_ctl; 580 581 ret = sr_write_gpio(dev, 582 SR_GPIO_RSE | SR_GPIO_GPO_2 | SR_GPIO_GPO2EN, 5); 583 if (ret < 0) 584 goto out; 585 586 embd_phy = ((sr_get_phy_addr(dev) & 0x1f) == 0x10 ? 1 : 0); 587 588 ret = sr_write_cmd(dev, SR_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL); 589 if (ret < 0) { 590 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 591 goto out; 592 } 593 594 ret = sr_sw_reset(dev, SR_SWRESET_IPPD | SR_SWRESET_PRL); 595 if (ret < 0) 596 goto out; 597 598 msleep(150); 599 600 ret = sr_sw_reset(dev, SR_SWRESET_CLEAR); 601 if (ret < 0) 602 goto out; 603 604 msleep(150); 605 606 if (embd_phy) { 607 ret = sr_sw_reset(dev, SR_SWRESET_IPRL); 608 if (ret < 0) 609 goto out; 610 } else { 611 ret = sr_sw_reset(dev, SR_SWRESET_PRTE); 612 if (ret < 0) 613 goto out; 614 } 615 616 msleep(150); 617 rx_ctl = sr_read_rx_ctl(dev); 618 netdev_dbg(dev->net, "RX_CTL is 0x%04x after software reset\n", rx_ctl); 619 ret = sr_write_rx_ctl(dev, 0x0000); 620 if (ret < 0) 621 goto out; 622 623 rx_ctl = sr_read_rx_ctl(dev); 624 netdev_dbg(dev->net, "RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl); 625 626 ret = sr_sw_reset(dev, SR_SWRESET_PRL); 627 if (ret < 0) 628 goto out; 629 630 msleep(150); 631 632 ret = sr_sw_reset(dev, SR_SWRESET_IPRL | SR_SWRESET_PRL); 633 if (ret < 0) 634 goto out; 635 636 msleep(150); 637 638 ret = sr9800_set_default_mode(dev); 639 if (ret < 0) 640 goto out; 641 642 /* Rewrite MAC address */ 643 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN); 644 ret = sr_write_cmd(dev, SR_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN, 645 data->mac_addr); 646 if (ret < 0) 647 goto out; 648 649 return 0; 650 651 out: 652 return ret; 653 } 654 655 static const struct net_device_ops sr9800_netdev_ops = { 656 .ndo_open = usbnet_open, 657 .ndo_stop = usbnet_stop, 658 .ndo_start_xmit = usbnet_start_xmit, 659 .ndo_tx_timeout = usbnet_tx_timeout, 660 .ndo_change_mtu = usbnet_change_mtu, 661 .ndo_get_stats64 = dev_get_tstats64, 662 .ndo_set_mac_address = sr_set_mac_address, 663 .ndo_validate_addr = eth_validate_addr, 664 .ndo_eth_ioctl = usbnet_mii_ioctl, 665 .ndo_set_rx_mode = sr_set_multicast, 666 }; 667 668 static int sr9800_phy_powerup(struct usbnet *dev) 669 { 670 int ret; 671 672 /* set the embedded Ethernet PHY in power-down state */ 673 ret = sr_sw_reset(dev, SR_SWRESET_IPPD | SR_SWRESET_IPRL); 674 if (ret < 0) { 675 netdev_err(dev->net, "Failed to power down PHY : %d\n", ret); 676 return ret; 677 } 678 msleep(20); 679 680 /* set the embedded Ethernet PHY in power-up state */ 681 ret = sr_sw_reset(dev, SR_SWRESET_IPRL); 682 if (ret < 0) { 683 netdev_err(dev->net, "Failed to reset PHY: %d\n", ret); 684 return ret; 685 } 686 msleep(600); 687 688 /* set the embedded Ethernet PHY in reset state */ 689 ret = sr_sw_reset(dev, SR_SWRESET_CLEAR); 690 if (ret < 0) { 691 netdev_err(dev->net, "Failed to power up PHY: %d\n", ret); 692 return ret; 693 } 694 msleep(20); 695 696 /* set the embedded Ethernet PHY in power-up state */ 697 ret = sr_sw_reset(dev, SR_SWRESET_IPRL); 698 if (ret < 0) { 699 netdev_err(dev->net, "Failed to reset PHY: %d\n", ret); 700 return ret; 701 } 702 703 return 0; 704 } 705 706 static int sr9800_bind(struct usbnet *dev, struct usb_interface *intf) 707 { 708 struct sr_data *data = (struct sr_data *)&dev->data; 709 u16 led01_mux, led23_mux; 710 int ret, embd_phy; 711 u8 addr[ETH_ALEN]; 712 u32 phyid; 713 u16 rx_ctl; 714 715 data->eeprom_len = SR9800_EEPROM_LEN; 716 717 ret = usbnet_get_endpoints(dev, intf); 718 if (ret) 719 goto out; 720 721 /* LED Setting Rule : 722 * AABB:CCDD 723 * AA : MFA0(LED0) 724 * BB : MFA1(LED1) 725 * CC : MFA2(LED2), Reserved for SR9800 726 * DD : MFA3(LED3), Reserved for SR9800 727 */ 728 led01_mux = (SR_LED_MUX_LINK_ACTIVE << 8) | SR_LED_MUX_LINK; 729 led23_mux = (SR_LED_MUX_LINK_ACTIVE << 8) | SR_LED_MUX_TX_ACTIVE; 730 ret = sr_write_cmd(dev, SR_CMD_LED_MUX, led01_mux, led23_mux, 0, NULL); 731 if (ret < 0) { 732 netdev_err(dev->net, "set LINK LED failed : %d\n", ret); 733 goto out; 734 } 735 736 /* Get the MAC address */ 737 ret = sr_read_cmd(dev, SR_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, addr); 738 if (ret < 0) { 739 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret); 740 return ret; 741 } 742 eth_hw_addr_set(dev->net, addr); 743 netdev_dbg(dev->net, "mac addr : %pM\n", dev->net->dev_addr); 744 745 /* Initialize MII structure */ 746 dev->mii.dev = dev->net; 747 dev->mii.mdio_read = sr_mdio_read; 748 dev->mii.mdio_write = sr_mdio_write; 749 dev->mii.phy_id_mask = 0x1f; 750 dev->mii.reg_num_mask = 0x1f; 751 dev->mii.phy_id = sr_get_phy_addr(dev); 752 753 dev->net->netdev_ops = &sr9800_netdev_ops; 754 dev->net->ethtool_ops = &sr9800_ethtool_ops; 755 756 embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0); 757 /* Reset the PHY to normal operation mode */ 758 ret = sr_write_cmd(dev, SR_CMD_SW_PHY_SELECT, embd_phy, 0, 0, NULL); 759 if (ret < 0) { 760 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret); 761 return ret; 762 } 763 764 /* Init PHY routine */ 765 ret = sr9800_phy_powerup(dev); 766 if (ret < 0) 767 goto out; 768 769 rx_ctl = sr_read_rx_ctl(dev); 770 netdev_dbg(dev->net, "RX_CTL is 0x%04x after software reset\n", rx_ctl); 771 ret = sr_write_rx_ctl(dev, 0x0000); 772 if (ret < 0) 773 goto out; 774 775 rx_ctl = sr_read_rx_ctl(dev); 776 netdev_dbg(dev->net, "RX_CTL is 0x%04x setting to 0x0000\n", rx_ctl); 777 778 /* Read PHYID register *AFTER* the PHY was reset properly */ 779 phyid = sr_get_phyid(dev); 780 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid); 781 782 /* medium mode setting */ 783 ret = sr9800_set_default_mode(dev); 784 if (ret < 0) 785 goto out; 786 787 if (dev->udev->speed == USB_SPEED_HIGH) { 788 ret = sr_write_cmd(dev, SR_CMD_BULKIN_SIZE, 789 SR9800_BULKIN_SIZE[SR9800_MAX_BULKIN_4K].byte_cnt, 790 SR9800_BULKIN_SIZE[SR9800_MAX_BULKIN_4K].threshold, 791 0, NULL); 792 if (ret < 0) { 793 netdev_err(dev->net, "Reset RX_CTL failed: %d\n", ret); 794 goto out; 795 } 796 dev->rx_urb_size = 797 SR9800_BULKIN_SIZE[SR9800_MAX_BULKIN_4K].size; 798 } else { 799 ret = sr_write_cmd(dev, SR_CMD_BULKIN_SIZE, 800 SR9800_BULKIN_SIZE[SR9800_MAX_BULKIN_2K].byte_cnt, 801 SR9800_BULKIN_SIZE[SR9800_MAX_BULKIN_2K].threshold, 802 0, NULL); 803 if (ret < 0) { 804 netdev_err(dev->net, "Reset RX_CTL failed: %d\n", ret); 805 goto out; 806 } 807 dev->rx_urb_size = 808 SR9800_BULKIN_SIZE[SR9800_MAX_BULKIN_2K].size; 809 } 810 netdev_dbg(dev->net, "%s : setting rx_urb_size with : %zu\n", __func__, 811 dev->rx_urb_size); 812 return 0; 813 814 out: 815 return ret; 816 } 817 818 static const struct driver_info sr9800_driver_info = { 819 .description = "CoreChip SR9800 USB 2.0 Ethernet", 820 .bind = sr9800_bind, 821 .status = sr_status, 822 .link_reset = sr9800_link_reset, 823 .reset = sr9800_reset, 824 .flags = DRIVER_FLAG, 825 .rx_fixup = sr_rx_fixup, 826 .tx_fixup = sr_tx_fixup, 827 }; 828 829 static const struct usb_device_id products[] = { 830 { 831 USB_DEVICE(0x0fe6, 0x9800), /* SR9800 Device */ 832 .driver_info = (unsigned long) &sr9800_driver_info, 833 }, 834 {}, /* END */ 835 }; 836 837 MODULE_DEVICE_TABLE(usb, products); 838 839 static struct usb_driver sr_driver = { 840 .name = DRIVER_NAME, 841 .id_table = products, 842 .probe = usbnet_probe, 843 .suspend = usbnet_suspend, 844 .resume = usbnet_resume, 845 .disconnect = usbnet_disconnect, 846 .supports_autosuspend = 1, 847 }; 848 849 module_usb_driver(sr_driver); 850 851 MODULE_AUTHOR("Liu Junliang <liujunliang_ljl@163.com"); 852 MODULE_DESCRIPTION("SR9800 USB 2.0 USB2NET Dev : http://www.corechip-sz.com"); 853 MODULE_LICENSE("GPL"); 854