1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 Spreadtrum Communications Inc.
4 * Copyright (C) 2018 Linaro Ltd.
5 */
6
7 #include <linux/bitops.h>
8 #include <linux/gpio/driver.h>
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/spinlock.h>
13
14 /* GPIO registers definition */
15 #define SPRD_GPIO_DATA 0x0
16 #define SPRD_GPIO_DMSK 0x4
17 #define SPRD_GPIO_DIR 0x8
18 #define SPRD_GPIO_IS 0xc
19 #define SPRD_GPIO_IBE 0x10
20 #define SPRD_GPIO_IEV 0x14
21 #define SPRD_GPIO_IE 0x18
22 #define SPRD_GPIO_RIS 0x1c
23 #define SPRD_GPIO_MIS 0x20
24 #define SPRD_GPIO_IC 0x24
25 #define SPRD_GPIO_INEN 0x28
26
27 /* We have 16 banks GPIOs and each bank contain 16 GPIOs */
28 #define SPRD_GPIO_BANK_NR 16
29 #define SPRD_GPIO_NR 256
30 #define SPRD_GPIO_BANK_SIZE 0x80
31 #define SPRD_GPIO_BANK_MASK GENMASK(15, 0)
32 #define SPRD_GPIO_BIT(x) ((x) & (SPRD_GPIO_BANK_NR - 1))
33
34 struct sprd_gpio {
35 struct gpio_chip chip;
36 void __iomem *base;
37 raw_spinlock_t lock;
38 int irq;
39 };
40
sprd_gpio_bank_base(struct sprd_gpio * sprd_gpio,unsigned int bank)41 static inline void __iomem *sprd_gpio_bank_base(struct sprd_gpio *sprd_gpio,
42 unsigned int bank)
43 {
44 return sprd_gpio->base + SPRD_GPIO_BANK_SIZE * bank;
45 }
46
sprd_gpio_update(struct gpio_chip * chip,unsigned int offset,u16 reg,int val)47 static void sprd_gpio_update(struct gpio_chip *chip, unsigned int offset,
48 u16 reg, int val)
49 {
50 struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
51 void __iomem *base = sprd_gpio_bank_base(sprd_gpio,
52 offset / SPRD_GPIO_BANK_NR);
53 unsigned long flags;
54 u32 tmp;
55
56 raw_spin_lock_irqsave(&sprd_gpio->lock, flags);
57 tmp = readl_relaxed(base + reg);
58
59 if (val)
60 tmp |= BIT(SPRD_GPIO_BIT(offset));
61 else
62 tmp &= ~BIT(SPRD_GPIO_BIT(offset));
63
64 writel_relaxed(tmp, base + reg);
65 raw_spin_unlock_irqrestore(&sprd_gpio->lock, flags);
66 }
67
sprd_gpio_read(struct gpio_chip * chip,unsigned int offset,u16 reg)68 static int sprd_gpio_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
69 {
70 struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
71 void __iomem *base = sprd_gpio_bank_base(sprd_gpio,
72 offset / SPRD_GPIO_BANK_NR);
73
74 return !!(readl_relaxed(base + reg) & BIT(SPRD_GPIO_BIT(offset)));
75 }
76
sprd_gpio_request(struct gpio_chip * chip,unsigned int offset)77 static int sprd_gpio_request(struct gpio_chip *chip, unsigned int offset)
78 {
79 sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 1);
80 return 0;
81 }
82
sprd_gpio_free(struct gpio_chip * chip,unsigned int offset)83 static void sprd_gpio_free(struct gpio_chip *chip, unsigned int offset)
84 {
85 sprd_gpio_update(chip, offset, SPRD_GPIO_DMSK, 0);
86 }
87
sprd_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)88 static int sprd_gpio_direction_input(struct gpio_chip *chip,
89 unsigned int offset)
90 {
91 sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 0);
92 sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 1);
93 return 0;
94 }
95
sprd_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)96 static int sprd_gpio_direction_output(struct gpio_chip *chip,
97 unsigned int offset, int value)
98 {
99 sprd_gpio_update(chip, offset, SPRD_GPIO_DIR, 1);
100 sprd_gpio_update(chip, offset, SPRD_GPIO_INEN, 0);
101 sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
102 return 0;
103 }
104
sprd_gpio_get(struct gpio_chip * chip,unsigned int offset)105 static int sprd_gpio_get(struct gpio_chip *chip, unsigned int offset)
106 {
107 return sprd_gpio_read(chip, offset, SPRD_GPIO_DATA);
108 }
109
sprd_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)110 static int sprd_gpio_set(struct gpio_chip *chip, unsigned int offset,
111 int value)
112 {
113 sprd_gpio_update(chip, offset, SPRD_GPIO_DATA, value);
114
115 return 0;
116 }
117
sprd_gpio_irq_mask(struct irq_data * data)118 static void sprd_gpio_irq_mask(struct irq_data *data)
119 {
120 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
121 u32 offset = irqd_to_hwirq(data);
122
123 sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 0);
124 gpiochip_disable_irq(chip, offset);
125 }
126
sprd_gpio_irq_ack(struct irq_data * data)127 static void sprd_gpio_irq_ack(struct irq_data *data)
128 {
129 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
130 u32 offset = irqd_to_hwirq(data);
131
132 sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
133 }
134
sprd_gpio_irq_unmask(struct irq_data * data)135 static void sprd_gpio_irq_unmask(struct irq_data *data)
136 {
137 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
138 u32 offset = irqd_to_hwirq(data);
139
140 sprd_gpio_update(chip, offset, SPRD_GPIO_IE, 1);
141 gpiochip_enable_irq(chip, offset);
142 }
143
sprd_gpio_irq_set_type(struct irq_data * data,unsigned int flow_type)144 static int sprd_gpio_irq_set_type(struct irq_data *data,
145 unsigned int flow_type)
146 {
147 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
148 u32 offset = irqd_to_hwirq(data);
149
150 switch (flow_type) {
151 case IRQ_TYPE_EDGE_RISING:
152 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
153 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
154 sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
155 sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
156 irq_set_handler_locked(data, handle_edge_irq);
157 break;
158 case IRQ_TYPE_EDGE_FALLING:
159 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
160 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
161 sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
162 sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
163 irq_set_handler_locked(data, handle_edge_irq);
164 break;
165 case IRQ_TYPE_EDGE_BOTH:
166 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 0);
167 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 1);
168 sprd_gpio_update(chip, offset, SPRD_GPIO_IC, 1);
169 irq_set_handler_locked(data, handle_edge_irq);
170 break;
171 case IRQ_TYPE_LEVEL_HIGH:
172 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1);
173 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
174 sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 1);
175 irq_set_handler_locked(data, handle_level_irq);
176 break;
177 case IRQ_TYPE_LEVEL_LOW:
178 sprd_gpio_update(chip, offset, SPRD_GPIO_IS, 1);
179 sprd_gpio_update(chip, offset, SPRD_GPIO_IBE, 0);
180 sprd_gpio_update(chip, offset, SPRD_GPIO_IEV, 0);
181 irq_set_handler_locked(data, handle_level_irq);
182 break;
183 default:
184 return -EINVAL;
185 }
186
187 return 0;
188 }
189
sprd_gpio_irq_handler(struct irq_desc * desc)190 static void sprd_gpio_irq_handler(struct irq_desc *desc)
191 {
192 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
193 struct irq_chip *ic = irq_desc_get_chip(desc);
194 struct sprd_gpio *sprd_gpio = gpiochip_get_data(chip);
195 u32 bank, n;
196
197 chained_irq_enter(ic, desc);
198
199 for (bank = 0; bank * SPRD_GPIO_BANK_NR < chip->ngpio; bank++) {
200 void __iomem *base = sprd_gpio_bank_base(sprd_gpio, bank);
201 unsigned long reg = readl_relaxed(base + SPRD_GPIO_MIS) &
202 SPRD_GPIO_BANK_MASK;
203
204 for_each_set_bit(n, ®, SPRD_GPIO_BANK_NR)
205 generic_handle_domain_irq(chip->irq.domain,
206 bank * SPRD_GPIO_BANK_NR + n);
207 }
208 chained_irq_exit(ic, desc);
209 }
210
211 static const struct irq_chip sprd_gpio_irqchip = {
212 .name = "sprd-gpio",
213 .irq_ack = sprd_gpio_irq_ack,
214 .irq_mask = sprd_gpio_irq_mask,
215 .irq_unmask = sprd_gpio_irq_unmask,
216 .irq_set_type = sprd_gpio_irq_set_type,
217 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
218 GPIOCHIP_IRQ_RESOURCE_HELPERS,
219 };
220
sprd_gpio_probe(struct platform_device * pdev)221 static int sprd_gpio_probe(struct platform_device *pdev)
222 {
223 struct gpio_irq_chip *irq;
224 struct sprd_gpio *sprd_gpio;
225
226 sprd_gpio = devm_kzalloc(&pdev->dev, sizeof(*sprd_gpio), GFP_KERNEL);
227 if (!sprd_gpio)
228 return -ENOMEM;
229
230 sprd_gpio->irq = platform_get_irq(pdev, 0);
231 if (sprd_gpio->irq < 0)
232 return sprd_gpio->irq;
233
234 sprd_gpio->base = devm_platform_ioremap_resource(pdev, 0);
235 if (IS_ERR(sprd_gpio->base))
236 return PTR_ERR(sprd_gpio->base);
237
238 raw_spin_lock_init(&sprd_gpio->lock);
239
240 sprd_gpio->chip.label = dev_name(&pdev->dev);
241 sprd_gpio->chip.ngpio = SPRD_GPIO_NR;
242 sprd_gpio->chip.base = -1;
243 sprd_gpio->chip.parent = &pdev->dev;
244 sprd_gpio->chip.request = sprd_gpio_request;
245 sprd_gpio->chip.free = sprd_gpio_free;
246 sprd_gpio->chip.get = sprd_gpio_get;
247 sprd_gpio->chip.set = sprd_gpio_set;
248 sprd_gpio->chip.direction_input = sprd_gpio_direction_input;
249 sprd_gpio->chip.direction_output = sprd_gpio_direction_output;
250
251 irq = &sprd_gpio->chip.irq;
252 gpio_irq_chip_set_chip(irq, &sprd_gpio_irqchip);
253 irq->handler = handle_bad_irq;
254 irq->default_type = IRQ_TYPE_NONE;
255 irq->parent_handler = sprd_gpio_irq_handler;
256 irq->parent_handler_data = sprd_gpio;
257 irq->num_parents = 1;
258 irq->parents = &sprd_gpio->irq;
259
260 return devm_gpiochip_add_data(&pdev->dev, &sprd_gpio->chip, sprd_gpio);
261 }
262
263 static const struct of_device_id sprd_gpio_of_match[] = {
264 { .compatible = "sprd,sc9860-gpio", },
265 { /* end of list */ }
266 };
267 MODULE_DEVICE_TABLE(of, sprd_gpio_of_match);
268
269 static struct platform_driver sprd_gpio_driver = {
270 .probe = sprd_gpio_probe,
271 .driver = {
272 .name = "sprd-gpio",
273 .of_match_table = sprd_gpio_of_match,
274 },
275 };
276
277 module_platform_driver_probe(sprd_gpio_driver, sprd_gpio_probe);
278
279 MODULE_DESCRIPTION("Spreadtrum GPIO driver");
280 MODULE_LICENSE("GPL v2");
281